Diff: STM32H747I-Discovery/stm32h747i_discovery_qspi.h

Revision:

0:146cf26a9bbb

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/STM32H747I-Discovery/stm32h747i_discovery_qspi.h	Wed Sep 25 13:37:39 2019 +0200
@@ -0,0 +1,174 @@
+/**
+  ******************************************************************************
+  * @file    stm32h747i_discovery_qspi.h
+  * @author  MCD Application Team
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32h747i_discovery_qspi.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32H747I_DISCOVERY
+  * @{
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H747I_DISCOVERY_QSPI_H
+#define __STM32H747I_DISCOVERY_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+#include "../Components/mt25tl01g/mt25tl01g.h"
+
+/** @addtogroup STM32H747I_DISCOVERY_QSPI
+  * @{
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup STM32H747I_DISCOVERY_QSPI_Exported_Constants Exported Constants
+  * @{
+  */
+/* QSPI Error codes */
+#define QSPI_OK            ((uint8_t)0x00)
+#define QSPI_ERROR         ((uint8_t)0x01)
+#define QSPI_BUSY          ((uint8_t)0x02)
+#define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
+#define QSPI_SUSPENDED     ((uint8_t)0x08)
+#define QSPI_PROTECTED     ((uint8_t)0x10)
+
+/* Definition for QSPI clock resources */
+#define QSPI_CLK_ENABLE()              __HAL_RCC_QSPI_CLK_ENABLE()
+#define QSPI_CLK_DISABLE()             __HAL_RCC_QSPI_CLK_DISABLE()
+#define QSPI_CLK_GPIO_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
+#define QSPI_BK1_CS_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
+#define QSPI_BK1_D0_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOD_CLK_ENABLE()
+#define QSPI_BK1_D1_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
+#define QSPI_BK1_D2_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
+#define QSPI_BK1_D3_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOF_CLK_ENABLE()
+#define QSPI_BK2_CS_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
+#define QSPI_BK2_D0_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOH_CLK_ENABLE()
+#define QSPI_BK2_D1_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOH_CLK_ENABLE()
+#define QSPI_BK2_D2_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
+#define QSPI_BK2_D3_GPIO_CLK_ENABLE()  __HAL_RCC_GPIOG_CLK_ENABLE()
+
+
+#define QSPI_FORCE_RESET()         __HAL_RCC_QSPI_FORCE_RESET()
+#define QSPI_RELEASE_RESET()       __HAL_RCC_QSPI_RELEASE_RESET()
+
+/* Definition for QSPI Pins */
+#define QSPI_CLK_PIN               GPIO_PIN_2
+#define QSPI_CLK_GPIO_PORT         GPIOB
+/* Bank 1 */
+#define QSPI_BK1_CS_PIN            GPIO_PIN_6
+#define QSPI_BK1_CS_GPIO_PORT      GPIOG
+#define QSPI_BK1_D0_PIN            GPIO_PIN_11
+#define QSPI_BK1_D0_GPIO_PORT      GPIOD
+#define QSPI_BK1_D1_PIN            GPIO_PIN_9
+#define QSPI_BK1_D1_GPIO_PORT      GPIOF
+#define QSPI_BK1_D2_PIN            GPIO_PIN_7
+#define QSPI_BK1_D2_GPIO_PORT      GPIOF
+#define QSPI_BK1_D3_PIN            GPIO_PIN_6
+#define QSPI_BK1_D3_GPIO_PORT      GPIOF
+
+/* Bank 2 */
+#define QSPI_BK2_CS_PIN            GPIO_PIN_6
+#define QSPI_BK2_CS_GPIO_PORT      GPIOG
+#define QSPI_BK2_D0_PIN            GPIO_PIN_2
+#define QSPI_BK2_D0_GPIO_PORT      GPIOH
+#define QSPI_BK2_D1_PIN            GPIO_PIN_3
+#define QSPI_BK2_D1_GPIO_PORT      GPIOH
+#define QSPI_BK2_D2_PIN            GPIO_PIN_9
+#define QSPI_BK2_D2_GPIO_PORT      GPIOG
+#define QSPI_BK2_D3_PIN            GPIO_PIN_14
+#define QSPI_BK2_D3_GPIO_PORT      GPIOG
+
+
+/* MT25TL01G Micron memory */
+/* Size of the flash */
+#define QSPI_FLASH_SIZE            26     /* Address bus width to access whole memory space */
+#define QSPI_PAGE_SIZE             256
+
+/* QSPI Base Address */
+#define QSPI_BASE_ADDRESS          0x90000000
+
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup STM32H747I_DISCOVERY_QSPI_Exported_Types Exported Types
+  * @{
+  */
+/* QSPI Info */
+typedef struct {
+  uint32_t FlashSize;          /*!< Size of the flash */
+  uint32_t EraseSectorSize;    /*!< Size of sectors for the erase operation */
+  uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
+  uint32_t ProgPageSize;       /*!< Size of pages for the program operation */
+  uint32_t ProgPagesNumber;    /*!< Number of pages for the program operation */
+} QSPI_Info;
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup STM32H747I_DISCOVERY_QSPI_Exported_Functions
+  * @{
+  */
+uint8_t BSP_QSPI_Init       (void);
+uint8_t BSP_QSPI_DeInit     (void);
+uint8_t BSP_QSPI_Read       (uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
+uint8_t BSP_QSPI_Write      (uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
+uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);
+uint8_t BSP_QSPI_Erase_Chip (void);
+uint8_t BSP_QSPI_GetStatus  (void);
+uint8_t BSP_QSPI_GetInfo    (QSPI_Info* pInfo);
+uint8_t BSP_QSPI_EnableMemoryMappedMode(void);
+
+/* These functions can be modified in case the current settings
+   need to be changed for specific application needs */
+void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params);
+void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H747I_DISCOVERY_QSPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/