ST / BSP_DISCO_H747I

BSP files for STM32H747I-Discovery Copy from ST Cube delivery

Dependents:   DISCO_H747I_LCD_demo DISCO_H747I_AUDIO_demo

STM32H747I-Discovery/stm32h747i_discovery_qspi.c@0:146cf26a9bbb, 2019-09-25 (annotated)

Committer:
Jerome Coutant
Date:
Wed Sep 25 13:37:39 2019 +0200
Revision:
0:146cf26a9bbb
STM32Cube_FW_H7_V1.5.0 BSP STM32H747I-DISCO

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jerome Coutant 0:146cf26a9bbb 1 /**
Jerome Coutant 0:146cf26a9bbb 2 ******************************************************************************
Jerome Coutant 0:146cf26a9bbb 3 * @file stm32h747i_discovery_qspi.c
Jerome Coutant 0:146cf26a9bbb 4 * @author MCD Application Team
Jerome Coutant 0:146cf26a9bbb 5 * @brief This file includes a standard driver for the MT25TL01G QSPI
Jerome Coutant 0:146cf26a9bbb 6 * memory mounted on STM32H747I-DISCOVERY board.
Jerome Coutant 0:146cf26a9bbb 7 @verbatim
Jerome Coutant 0:146cf26a9bbb 8 ==============================================================================
Jerome Coutant 0:146cf26a9bbb 9 ##### How to use this driver #####
Jerome Coutant 0:146cf26a9bbb 10 ==============================================================================
Jerome Coutant 0:146cf26a9bbb 11 [..]
Jerome Coutant 0:146cf26a9bbb 12 (#) This driver is used to drive the MT25TL01G QSPI external
Jerome Coutant 0:146cf26a9bbb 13 memory mounted on STM32H747I-DISCOVERY board.
Jerome Coutant 0:146cf26a9bbb 14
Jerome Coutant 0:146cf26a9bbb 15 (#) This driver need a specific component driver (MT25TL01G) to be included with.
Jerome Coutant 0:146cf26a9bbb 16
Jerome Coutant 0:146cf26a9bbb 17 (#) Initialization steps:
Jerome Coutant 0:146cf26a9bbb 18 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
Jerome Coutant 0:146cf26a9bbb 19 function includes the MSP layer hardware resources initialization and the
Jerome Coutant 0:146cf26a9bbb 20 QSPI interface with the external memory.
Jerome Coutant 0:146cf26a9bbb 21
Jerome Coutant 0:146cf26a9bbb 22 (#) QSPI memory operations
Jerome Coutant 0:146cf26a9bbb 23 (++) QSPI memory can be accessed with read/write operations once it is
Jerome Coutant 0:146cf26a9bbb 24 initialized.
Jerome Coutant 0:146cf26a9bbb 25 Read/write operation can be performed with AHB access using the functions
Jerome Coutant 0:146cf26a9bbb 26 BSP_QSPI_Read()/BSP_QSPI_Write().
Jerome Coutant 0:146cf26a9bbb 27 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 28 (see the QSPI memory data sheet)
Jerome Coutant 0:146cf26a9bbb 29 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
Jerome Coutant 0:146cf26a9bbb 30 specifying the block address. You can perform an erase operation of the whole
Jerome Coutant 0:146cf26a9bbb 31 chip by calling the function BSP_QSPI_Erase_Chip().
Jerome Coutant 0:146cf26a9bbb 32 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 33 (see the QSPI memory data sheet)
Jerome Coutant 0:146cf26a9bbb 34 @endverbatim
Jerome Coutant 0:146cf26a9bbb 35 ******************************************************************************
Jerome Coutant 0:146cf26a9bbb 36 * @attention
Jerome Coutant 0:146cf26a9bbb 37 *
Jerome Coutant 0:146cf26a9bbb 38 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
Jerome Coutant 0:146cf26a9bbb 39 * All rights reserved.</center></h2>
Jerome Coutant 0:146cf26a9bbb 40 *
Jerome Coutant 0:146cf26a9bbb 41 * This software component is licensed by ST under BSD 3-Clause license,
Jerome Coutant 0:146cf26a9bbb 42 * the "License"; You may not use this file except in compliance with the
Jerome Coutant 0:146cf26a9bbb 43 * License. You may obtain a copy of the License at:
Jerome Coutant 0:146cf26a9bbb 44 * opensource.org/licenses/BSD-3-Clause
Jerome Coutant 0:146cf26a9bbb 45 *
Jerome Coutant 0:146cf26a9bbb 46 ******************************************************************************
Jerome Coutant 0:146cf26a9bbb 47 */
Jerome Coutant 0:146cf26a9bbb 48
Jerome Coutant 0:146cf26a9bbb 49 /* Includes ------------------------------------------------------------------*/
Jerome Coutant 0:146cf26a9bbb 50 #include "stm32h747i_discovery_qspi.h"
Jerome Coutant 0:146cf26a9bbb 51
Jerome Coutant 0:146cf26a9bbb 52 /** @addtogroup BSP
Jerome Coutant 0:146cf26a9bbb 53 * @{
Jerome Coutant 0:146cf26a9bbb 54 */
Jerome Coutant 0:146cf26a9bbb 55
Jerome Coutant 0:146cf26a9bbb 56 /** @addtogroup STM32H747I_DISCOVERY
Jerome Coutant 0:146cf26a9bbb 57 * @{
Jerome Coutant 0:146cf26a9bbb 58 */
Jerome Coutant 0:146cf26a9bbb 59
Jerome Coutant 0:146cf26a9bbb 60 /** @defgroup STM32H747I_DISCOVERY_QSPI STM32H747I_DISCOVERY_QSPI
Jerome Coutant 0:146cf26a9bbb 61 * @{
Jerome Coutant 0:146cf26a9bbb 62 */
Jerome Coutant 0:146cf26a9bbb 63
Jerome Coutant 0:146cf26a9bbb 64
Jerome Coutant 0:146cf26a9bbb 65 /* Private variables ---------------------------------------------------------*/
Jerome Coutant 0:146cf26a9bbb 66
Jerome Coutant 0:146cf26a9bbb 67 /** @defgroup STM32H747I_DISCOVERY_QSPI_Private_Variables Private Variables
Jerome Coutant 0:146cf26a9bbb 68 * @{
Jerome Coutant 0:146cf26a9bbb 69 */
Jerome Coutant 0:146cf26a9bbb 70 QSPI_HandleTypeDef QSPIHandle;
Jerome Coutant 0:146cf26a9bbb 71
Jerome Coutant 0:146cf26a9bbb 72 /**
Jerome Coutant 0:146cf26a9bbb 73 * @}
Jerome Coutant 0:146cf26a9bbb 74 */
Jerome Coutant 0:146cf26a9bbb 75
Jerome Coutant 0:146cf26a9bbb 76 /* Private functions ---------------------------------------------------------*/
Jerome Coutant 0:146cf26a9bbb 77
Jerome Coutant 0:146cf26a9bbb 78 /** @defgroup STM32H747I_DISCOVERY_QSPI_Private_Functions Private Functions
Jerome Coutant 0:146cf26a9bbb 79 * @{
Jerome Coutant 0:146cf26a9bbb 80 */
Jerome Coutant 0:146cf26a9bbb 81 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
Jerome Coutant 0:146cf26a9bbb 82 static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi);
Jerome Coutant 0:146cf26a9bbb 83 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
Jerome Coutant 0:146cf26a9bbb 84 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
Jerome Coutant 0:146cf26a9bbb 85 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
Jerome Coutant 0:146cf26a9bbb 86 static uint8_t QSPI_EnterQPI(QSPI_HandleTypeDef *hqspi);
Jerome Coutant 0:146cf26a9bbb 87 /**
Jerome Coutant 0:146cf26a9bbb 88 * @}
Jerome Coutant 0:146cf26a9bbb 89 */
Jerome Coutant 0:146cf26a9bbb 90
Jerome Coutant 0:146cf26a9bbb 91 /** @defgroup STM32H747I_DISCOVERY_QSPI_Exported_Functions Exported Functions
Jerome Coutant 0:146cf26a9bbb 92 * @{
Jerome Coutant 0:146cf26a9bbb 93 */
Jerome Coutant 0:146cf26a9bbb 94
Jerome Coutant 0:146cf26a9bbb 95 /**
Jerome Coutant 0:146cf26a9bbb 96 * @brief Initializes the QSPI interface.
Jerome Coutant 0:146cf26a9bbb 97 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 98 */
Jerome Coutant 0:146cf26a9bbb 99 uint8_t BSP_QSPI_Init(void)
Jerome Coutant 0:146cf26a9bbb 100 {
Jerome Coutant 0:146cf26a9bbb 101 QSPIHandle.Instance = QUADSPI;
Jerome Coutant 0:146cf26a9bbb 102
Jerome Coutant 0:146cf26a9bbb 103 /* Call the DeInit function to reset the driver */
Jerome Coutant 0:146cf26a9bbb 104 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 105 {
Jerome Coutant 0:146cf26a9bbb 106 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 107 }
Jerome Coutant 0:146cf26a9bbb 108
Jerome Coutant 0:146cf26a9bbb 109 /* System level initialization */
Jerome Coutant 0:146cf26a9bbb 110 BSP_QSPI_MspInit(&QSPIHandle, NULL);
Jerome Coutant 0:146cf26a9bbb 111
Jerome Coutant 0:146cf26a9bbb 112 /* QSPI initialization */
Jerome Coutant 0:146cf26a9bbb 113 /* ClockPrescaler set to 1, so QSPI clock = 200MHz / (1+3) = 50MHz */
Jerome Coutant 0:146cf26a9bbb 114 QSPIHandle.Init.ClockPrescaler = 3;
Jerome Coutant 0:146cf26a9bbb 115 QSPIHandle.Init.FifoThreshold = 1;
Jerome Coutant 0:146cf26a9bbb 116 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
Jerome Coutant 0:146cf26a9bbb 117 QSPIHandle.Init.FlashSize = POSITION_VAL(MT25TL01G_FLASH_SIZE) - 1;
Jerome Coutant 0:146cf26a9bbb 118 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE;
Jerome Coutant 0:146cf26a9bbb 119 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
Jerome Coutant 0:146cf26a9bbb 120 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_2;
Jerome Coutant 0:146cf26a9bbb 121 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_ENABLE;
Jerome Coutant 0:146cf26a9bbb 122
Jerome Coutant 0:146cf26a9bbb 123 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 124 {
Jerome Coutant 0:146cf26a9bbb 125 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 126 }
Jerome Coutant 0:146cf26a9bbb 127
Jerome Coutant 0:146cf26a9bbb 128 /* QSPI memory reset */
Jerome Coutant 0:146cf26a9bbb 129 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 130 {
Jerome Coutant 0:146cf26a9bbb 131 return QSPI_NOT_SUPPORTED;
Jerome Coutant 0:146cf26a9bbb 132 }
Jerome Coutant 0:146cf26a9bbb 133
Jerome Coutant 0:146cf26a9bbb 134 /* Set the QSPI memory in 4-bytes address mode */
Jerome Coutant 0:146cf26a9bbb 135 if (QSPI_EnterFourBytesAddress(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 136 {
Jerome Coutant 0:146cf26a9bbb 137 return QSPI_NOT_SUPPORTED;
Jerome Coutant 0:146cf26a9bbb 138 }
Jerome Coutant 0:146cf26a9bbb 139
Jerome Coutant 0:146cf26a9bbb 140 /* Configuration of the dummy cycles on QSPI memory side */
Jerome Coutant 0:146cf26a9bbb 141 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 142 {
Jerome Coutant 0:146cf26a9bbb 143 return QSPI_NOT_SUPPORTED;
Jerome Coutant 0:146cf26a9bbb 144 }
Jerome Coutant 0:146cf26a9bbb 145
Jerome Coutant 0:146cf26a9bbb 146 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 147 }
Jerome Coutant 0:146cf26a9bbb 148
Jerome Coutant 0:146cf26a9bbb 149 /**
Jerome Coutant 0:146cf26a9bbb 150 * @brief De-Initializes the QSPI interface.
Jerome Coutant 0:146cf26a9bbb 151 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 152 */
Jerome Coutant 0:146cf26a9bbb 153 uint8_t BSP_QSPI_DeInit(void)
Jerome Coutant 0:146cf26a9bbb 154 {
Jerome Coutant 0:146cf26a9bbb 155 QSPIHandle.Instance = QUADSPI;
Jerome Coutant 0:146cf26a9bbb 156
Jerome Coutant 0:146cf26a9bbb 157 /* Call the DeInit function to reset the driver */
Jerome Coutant 0:146cf26a9bbb 158 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 159 {
Jerome Coutant 0:146cf26a9bbb 160 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 161 }
Jerome Coutant 0:146cf26a9bbb 162
Jerome Coutant 0:146cf26a9bbb 163 /* System level De-initialization */
Jerome Coutant 0:146cf26a9bbb 164 BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
Jerome Coutant 0:146cf26a9bbb 165
Jerome Coutant 0:146cf26a9bbb 166 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 167 }
Jerome Coutant 0:146cf26a9bbb 168
Jerome Coutant 0:146cf26a9bbb 169 /**
Jerome Coutant 0:146cf26a9bbb 170 * @brief Reads an amount of data from the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 171 * @param pData: Pointer to data to be read
Jerome Coutant 0:146cf26a9bbb 172 * @param ReadAddr: Read start address
Jerome Coutant 0:146cf26a9bbb 173 * @param Size: Size of data to read
Jerome Coutant 0:146cf26a9bbb 174 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 175 */
Jerome Coutant 0:146cf26a9bbb 176 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
Jerome Coutant 0:146cf26a9bbb 177 {
Jerome Coutant 0:146cf26a9bbb 178 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 179
Jerome Coutant 0:146cf26a9bbb 180 /* Initialize the read command */
Jerome Coutant 0:146cf26a9bbb 181 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 182 s_command.Instruction = QUAD_INOUT_FAST_READ_DTR_CMD; /* DTR QUAD INPUT/OUTPUT FAST READ and 4-BYTE DTR FAST READ commands */
Jerome Coutant 0:146cf26a9bbb 183 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
Jerome Coutant 0:146cf26a9bbb 184 s_command.AddressSize = QSPI_ADDRESS_32_BITS;
Jerome Coutant 0:146cf26a9bbb 185 s_command.Address = ReadAddr;
Jerome Coutant 0:146cf26a9bbb 186 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 187 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 188 s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;
Jerome Coutant 0:146cf26a9bbb 189 s_command.NbData = Size;
Jerome Coutant 0:146cf26a9bbb 190 s_command.DdrMode = QSPI_DDR_MODE_ENABLE;
Jerome Coutant 0:146cf26a9bbb 191 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_HALF_CLK_DELAY;
Jerome Coutant 0:146cf26a9bbb 192 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 193
Jerome Coutant 0:146cf26a9bbb 194 /* Configure the command */
Jerome Coutant 0:146cf26a9bbb 195 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 196 {
Jerome Coutant 0:146cf26a9bbb 197 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 198 }
Jerome Coutant 0:146cf26a9bbb 199
Jerome Coutant 0:146cf26a9bbb 200 /* Reception of the data */
Jerome Coutant 0:146cf26a9bbb 201 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 202 {
Jerome Coutant 0:146cf26a9bbb 203 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 204 }
Jerome Coutant 0:146cf26a9bbb 205
Jerome Coutant 0:146cf26a9bbb 206 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 207 }
Jerome Coutant 0:146cf26a9bbb 208
Jerome Coutant 0:146cf26a9bbb 209 /**
Jerome Coutant 0:146cf26a9bbb 210 * @brief Writes an amount of data to the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 211 * @param pData: Pointer to data to be written
Jerome Coutant 0:146cf26a9bbb 212 * @param WriteAddr: Write start address
Jerome Coutant 0:146cf26a9bbb 213 * @param Size: Size of data to write
Jerome Coutant 0:146cf26a9bbb 214 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 215 */
Jerome Coutant 0:146cf26a9bbb 216 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
Jerome Coutant 0:146cf26a9bbb 217 {
Jerome Coutant 0:146cf26a9bbb 218 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 219 uint32_t end_addr, current_size, current_addr;
Jerome Coutant 0:146cf26a9bbb 220
Jerome Coutant 0:146cf26a9bbb 221 /* Calculation of the size between the write address and the end of the page */
Jerome Coutant 0:146cf26a9bbb 222 current_size = MT25TL01G_PAGE_SIZE - (WriteAddr % MT25TL01G_PAGE_SIZE);
Jerome Coutant 0:146cf26a9bbb 223
Jerome Coutant 0:146cf26a9bbb 224 /* Check if the size of the data is less than the remaining place in the page */
Jerome Coutant 0:146cf26a9bbb 225 if (current_size > Size)
Jerome Coutant 0:146cf26a9bbb 226 {
Jerome Coutant 0:146cf26a9bbb 227 current_size = Size;
Jerome Coutant 0:146cf26a9bbb 228 }
Jerome Coutant 0:146cf26a9bbb 229
Jerome Coutant 0:146cf26a9bbb 230 /* Initialize the address variables */
Jerome Coutant 0:146cf26a9bbb 231 current_addr = WriteAddr;
Jerome Coutant 0:146cf26a9bbb 232 end_addr = WriteAddr + Size;
Jerome Coutant 0:146cf26a9bbb 233
Jerome Coutant 0:146cf26a9bbb 234 /* Initialize the program command */
Jerome Coutant 0:146cf26a9bbb 235 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 236 s_command.Instruction = QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD;
Jerome Coutant 0:146cf26a9bbb 237 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
Jerome Coutant 0:146cf26a9bbb 238 s_command.AddressSize = QSPI_ADDRESS_32_BITS;
Jerome Coutant 0:146cf26a9bbb 239 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 240 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 241 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 242 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 243 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 244 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 245
Jerome Coutant 0:146cf26a9bbb 246 /* Perform the write page by page */
Jerome Coutant 0:146cf26a9bbb 247 do
Jerome Coutant 0:146cf26a9bbb 248 {
Jerome Coutant 0:146cf26a9bbb 249 s_command.Address = current_addr;
Jerome Coutant 0:146cf26a9bbb 250 s_command.NbData = current_size;
Jerome Coutant 0:146cf26a9bbb 251
Jerome Coutant 0:146cf26a9bbb 252 /* Enable write operations */
Jerome Coutant 0:146cf26a9bbb 253 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 254 {
Jerome Coutant 0:146cf26a9bbb 255 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 256 }
Jerome Coutant 0:146cf26a9bbb 257
Jerome Coutant 0:146cf26a9bbb 258 /* Configure the command */
Jerome Coutant 0:146cf26a9bbb 259 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 260 {
Jerome Coutant 0:146cf26a9bbb 261 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 262 }
Jerome Coutant 0:146cf26a9bbb 263
Jerome Coutant 0:146cf26a9bbb 264 /* Transmission of the data */
Jerome Coutant 0:146cf26a9bbb 265 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 266 {
Jerome Coutant 0:146cf26a9bbb 267 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 268 }
Jerome Coutant 0:146cf26a9bbb 269
Jerome Coutant 0:146cf26a9bbb 270 /* Configure automatic polling mode to wait for end of program */
Jerome Coutant 0:146cf26a9bbb 271 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 272 {
Jerome Coutant 0:146cf26a9bbb 273 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 274 }
Jerome Coutant 0:146cf26a9bbb 275
Jerome Coutant 0:146cf26a9bbb 276 /* Update the address and size variables for next page programming */
Jerome Coutant 0:146cf26a9bbb 277 current_addr += current_size;
Jerome Coutant 0:146cf26a9bbb 278 pData += current_size;
Jerome Coutant 0:146cf26a9bbb 279 current_size = ((current_addr + MT25TL01G_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MT25TL01G_PAGE_SIZE;
Jerome Coutant 0:146cf26a9bbb 280 } while (current_addr < end_addr);
Jerome Coutant 0:146cf26a9bbb 281
Jerome Coutant 0:146cf26a9bbb 282 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 283 }
Jerome Coutant 0:146cf26a9bbb 284
Jerome Coutant 0:146cf26a9bbb 285 /**
Jerome Coutant 0:146cf26a9bbb 286 * @brief Erases the specified block of the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 287 * @param BlockAddress: Block address to erase
Jerome Coutant 0:146cf26a9bbb 288 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 289 */
Jerome Coutant 0:146cf26a9bbb 290 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
Jerome Coutant 0:146cf26a9bbb 291 {
Jerome Coutant 0:146cf26a9bbb 292 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 293
Jerome Coutant 0:146cf26a9bbb 294 /* Initialize the erase command */
Jerome Coutant 0:146cf26a9bbb 295 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 296 s_command.Instruction = SUBSECTOR_ERASE_4_BYTE_ADDR_CMD;
Jerome Coutant 0:146cf26a9bbb 297 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
Jerome Coutant 0:146cf26a9bbb 298 s_command.AddressSize = QSPI_ADDRESS_32_BITS;
Jerome Coutant 0:146cf26a9bbb 299 s_command.Address = BlockAddress;
Jerome Coutant 0:146cf26a9bbb 300 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 301 s_command.DataMode = QSPI_DATA_NONE;
Jerome Coutant 0:146cf26a9bbb 302 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 303 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 304 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 305 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 306
Jerome Coutant 0:146cf26a9bbb 307 /* Enable write operations */
Jerome Coutant 0:146cf26a9bbb 308 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 309 {
Jerome Coutant 0:146cf26a9bbb 310 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 311 }
Jerome Coutant 0:146cf26a9bbb 312
Jerome Coutant 0:146cf26a9bbb 313 /* Send the command */
Jerome Coutant 0:146cf26a9bbb 314 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 315 {
Jerome Coutant 0:146cf26a9bbb 316 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 317 }
Jerome Coutant 0:146cf26a9bbb 318
Jerome Coutant 0:146cf26a9bbb 319 /* Configure automatic polling mode to wait for end of erase */
Jerome Coutant 0:146cf26a9bbb 320 if (QSPI_AutoPollingMemReady(&QSPIHandle, MT25TL01G_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 321 {
Jerome Coutant 0:146cf26a9bbb 322 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 323 }
Jerome Coutant 0:146cf26a9bbb 324
Jerome Coutant 0:146cf26a9bbb 325 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 326 }
Jerome Coutant 0:146cf26a9bbb 327
Jerome Coutant 0:146cf26a9bbb 328 /**
Jerome Coutant 0:146cf26a9bbb 329 * @brief Erases the entire QSPI memory.
Jerome Coutant 0:146cf26a9bbb 330 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 331 */
Jerome Coutant 0:146cf26a9bbb 332 uint8_t BSP_QSPI_Erase_Chip(void)
Jerome Coutant 0:146cf26a9bbb 333 {
Jerome Coutant 0:146cf26a9bbb 334 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 335
Jerome Coutant 0:146cf26a9bbb 336 /* Initialize the erase command */
Jerome Coutant 0:146cf26a9bbb 337 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 338 s_command.Instruction = DIE_ERASE_CMD;
Jerome Coutant 0:146cf26a9bbb 339 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 340 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 341 s_command.DataMode = QSPI_DATA_NONE;
Jerome Coutant 0:146cf26a9bbb 342 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 343 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 344 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 345 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 346
Jerome Coutant 0:146cf26a9bbb 347 /* Enable write operations */
Jerome Coutant 0:146cf26a9bbb 348 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 349 {
Jerome Coutant 0:146cf26a9bbb 350 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 351 }
Jerome Coutant 0:146cf26a9bbb 352
Jerome Coutant 0:146cf26a9bbb 353 /* Send the command */
Jerome Coutant 0:146cf26a9bbb 354 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 355 {
Jerome Coutant 0:146cf26a9bbb 356 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 357 }
Jerome Coutant 0:146cf26a9bbb 358
Jerome Coutant 0:146cf26a9bbb 359 /* Configure automatic polling mode to wait for end of erase */
Jerome Coutant 0:146cf26a9bbb 360 if (QSPI_AutoPollingMemReady(&QSPIHandle, MT25TL01G_DIE_ERASE_MAX_TIME) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 361 {
Jerome Coutant 0:146cf26a9bbb 362 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 363 }
Jerome Coutant 0:146cf26a9bbb 364
Jerome Coutant 0:146cf26a9bbb 365 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 366 }
Jerome Coutant 0:146cf26a9bbb 367
Jerome Coutant 0:146cf26a9bbb 368 /**
Jerome Coutant 0:146cf26a9bbb 369 * @brief Reads current status of the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 370 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 371 */
Jerome Coutant 0:146cf26a9bbb 372 uint8_t BSP_QSPI_GetStatus(void)
Jerome Coutant 0:146cf26a9bbb 373 {
Jerome Coutant 0:146cf26a9bbb 374 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 375 uint16_t reg;
Jerome Coutant 0:146cf26a9bbb 376
Jerome Coutant 0:146cf26a9bbb 377 /* Initialize the read flag status register command */
Jerome Coutant 0:146cf26a9bbb 378 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 379 s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
Jerome Coutant 0:146cf26a9bbb 380 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 381 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 382 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 383 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 384 s_command.NbData = 1;
Jerome Coutant 0:146cf26a9bbb 385 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 386 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 387 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 388
Jerome Coutant 0:146cf26a9bbb 389 /* Configure the command */
Jerome Coutant 0:146cf26a9bbb 390 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 391 {
Jerome Coutant 0:146cf26a9bbb 392 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 393 }
Jerome Coutant 0:146cf26a9bbb 394
Jerome Coutant 0:146cf26a9bbb 395 /* Reception of the data */
Jerome Coutant 0:146cf26a9bbb 396 if (HAL_QSPI_Receive(&QSPIHandle, (uint8_t*)(&reg), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 397 {
Jerome Coutant 0:146cf26a9bbb 398 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 399 }
Jerome Coutant 0:146cf26a9bbb 400
Jerome Coutant 0:146cf26a9bbb 401 /* Check the value of the register */
Jerome Coutant 0:146cf26a9bbb 402 if ((reg & (MT25TL01G_FSR_PRERR | MT25TL01G_FSR_PGERR | MT25TL01G_FSR_ERERR)) != 0)
Jerome Coutant 0:146cf26a9bbb 403 {
Jerome Coutant 0:146cf26a9bbb 404 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 405 }
Jerome Coutant 0:146cf26a9bbb 406 else if ((reg & (MT25TL01G_FSR_PGSUS | MT25TL01G_FSR_ERSUS)) != 0)
Jerome Coutant 0:146cf26a9bbb 407 {
Jerome Coutant 0:146cf26a9bbb 408 return QSPI_SUSPENDED;
Jerome Coutant 0:146cf26a9bbb 409 }
Jerome Coutant 0:146cf26a9bbb 410 else if ((reg & MT25TL01G_FSR_READY) != 0)
Jerome Coutant 0:146cf26a9bbb 411 {
Jerome Coutant 0:146cf26a9bbb 412 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 413 }
Jerome Coutant 0:146cf26a9bbb 414 else
Jerome Coutant 0:146cf26a9bbb 415 {
Jerome Coutant 0:146cf26a9bbb 416 return QSPI_BUSY;
Jerome Coutant 0:146cf26a9bbb 417 }
Jerome Coutant 0:146cf26a9bbb 418 }
Jerome Coutant 0:146cf26a9bbb 419
Jerome Coutant 0:146cf26a9bbb 420 /**
Jerome Coutant 0:146cf26a9bbb 421 * @brief Return the configuration of the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 422 * @param pInfo: pointer on the configuration structure
Jerome Coutant 0:146cf26a9bbb 423 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 424 */
Jerome Coutant 0:146cf26a9bbb 425 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
Jerome Coutant 0:146cf26a9bbb 426 {
Jerome Coutant 0:146cf26a9bbb 427 /* Configure the structure with the memory configuration */
Jerome Coutant 0:146cf26a9bbb 428 pInfo->FlashSize = MT25TL01G_FLASH_SIZE;
Jerome Coutant 0:146cf26a9bbb 429 pInfo->EraseSectorSize = (2 * MT25TL01G_SUBSECTOR_SIZE);
Jerome Coutant 0:146cf26a9bbb 430 pInfo->ProgPageSize = MT25TL01G_PAGE_SIZE;
Jerome Coutant 0:146cf26a9bbb 431 pInfo->EraseSectorsNumber = (MT25TL01G_FLASH_SIZE/pInfo->EraseSectorSize);
Jerome Coutant 0:146cf26a9bbb 432 pInfo->ProgPagesNumber = (MT25TL01G_FLASH_SIZE/pInfo->ProgPageSize);
Jerome Coutant 0:146cf26a9bbb 433
Jerome Coutant 0:146cf26a9bbb 434 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 435 }
Jerome Coutant 0:146cf26a9bbb 436
Jerome Coutant 0:146cf26a9bbb 437 /**
Jerome Coutant 0:146cf26a9bbb 438 * @brief Configure the QSPI in memory-mapped mode
Jerome Coutant 0:146cf26a9bbb 439 * @retval QSPI memory status
Jerome Coutant 0:146cf26a9bbb 440 */
Jerome Coutant 0:146cf26a9bbb 441 uint8_t BSP_QSPI_EnableMemoryMappedMode(void)
Jerome Coutant 0:146cf26a9bbb 442 {
Jerome Coutant 0:146cf26a9bbb 443 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 444 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
Jerome Coutant 0:146cf26a9bbb 445
Jerome Coutant 0:146cf26a9bbb 446 /* Configure the command for the read instruction */
Jerome Coutant 0:146cf26a9bbb 447 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 448 s_command.Instruction = QUAD_INOUT_FAST_READ_DTR_CMD; /* DTR QUAD INPUT/OUTPUT FAST READ and 4-BYTE DTR FAST READ commands */
Jerome Coutant 0:146cf26a9bbb 449 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
Jerome Coutant 0:146cf26a9bbb 450 s_command.AddressSize = QSPI_ADDRESS_32_BITS;
Jerome Coutant 0:146cf26a9bbb 451 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 452 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 453 s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;
Jerome Coutant 0:146cf26a9bbb 454
Jerome Coutant 0:146cf26a9bbb 455 s_command.DdrMode = QSPI_DDR_MODE_ENABLE;
Jerome Coutant 0:146cf26a9bbb 456 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_HALF_CLK_DELAY;
Jerome Coutant 0:146cf26a9bbb 457 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 458
Jerome Coutant 0:146cf26a9bbb 459 /* Configure the memory mapped mode */
Jerome Coutant 0:146cf26a9bbb 460 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
Jerome Coutant 0:146cf26a9bbb 461 s_mem_mapped_cfg.TimeOutPeriod = 0;
Jerome Coutant 0:146cf26a9bbb 462
Jerome Coutant 0:146cf26a9bbb 463 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 464 {
Jerome Coutant 0:146cf26a9bbb 465 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 466 }
Jerome Coutant 0:146cf26a9bbb 467
Jerome Coutant 0:146cf26a9bbb 468 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 469 }
Jerome Coutant 0:146cf26a9bbb 470
Jerome Coutant 0:146cf26a9bbb 471 /**
Jerome Coutant 0:146cf26a9bbb 472 * @brief QSPI MSP Initialization
Jerome Coutant 0:146cf26a9bbb 473 * This function configures the hardware resources used in this example:
Jerome Coutant 0:146cf26a9bbb 474 * - Peripheral's clock enable
Jerome Coutant 0:146cf26a9bbb 475 * - Peripheral's GPIO Configuration
Jerome Coutant 0:146cf26a9bbb 476 * - NVIC configuration for QSPI interrupt
Jerome Coutant 0:146cf26a9bbb 477 * @retval None
Jerome Coutant 0:146cf26a9bbb 478 */
Jerome Coutant 0:146cf26a9bbb 479 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
Jerome Coutant 0:146cf26a9bbb 480 {
Jerome Coutant 0:146cf26a9bbb 481 GPIO_InitTypeDef gpio_init_structure;
Jerome Coutant 0:146cf26a9bbb 482
Jerome Coutant 0:146cf26a9bbb 483 /*##-1- Enable peripherals and GPIO Clocks #################################*/
Jerome Coutant 0:146cf26a9bbb 484 /* Enable the QuadSPI memory interface clock */
Jerome Coutant 0:146cf26a9bbb 485 QSPI_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 486 /* Reset the QuadSPI memory interface */
Jerome Coutant 0:146cf26a9bbb 487 QSPI_FORCE_RESET();
Jerome Coutant 0:146cf26a9bbb 488 QSPI_RELEASE_RESET();
Jerome Coutant 0:146cf26a9bbb 489 /* Enable GPIO clocks */
Jerome Coutant 0:146cf26a9bbb 490 QSPI_CLK_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 491 QSPI_BK1_CS_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 492 QSPI_BK1_D0_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 493 QSPI_BK1_D1_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 494 QSPI_BK1_D2_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 495 QSPI_BK1_D3_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 496
Jerome Coutant 0:146cf26a9bbb 497 QSPI_BK2_CS_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 498 QSPI_BK2_D0_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 499 QSPI_BK2_D1_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 500 QSPI_BK2_D2_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 501 QSPI_BK2_D3_GPIO_CLK_ENABLE();
Jerome Coutant 0:146cf26a9bbb 502
Jerome Coutant 0:146cf26a9bbb 503 /*##-2- Configure peripheral GPIO ##########################################*/
Jerome Coutant 0:146cf26a9bbb 504 /* QSPI CLK GPIO pin configuration */
Jerome Coutant 0:146cf26a9bbb 505 gpio_init_structure.Pin = QSPI_CLK_PIN;
Jerome Coutant 0:146cf26a9bbb 506 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
Jerome Coutant 0:146cf26a9bbb 507 gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
Jerome Coutant 0:146cf26a9bbb 508 gpio_init_structure.Pull = GPIO_NOPULL;
Jerome Coutant 0:146cf26a9bbb 509 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 510 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 511
Jerome Coutant 0:146cf26a9bbb 512 /* QSPI CS GPIO pin configuration */
Jerome Coutant 0:146cf26a9bbb 513 gpio_init_structure.Pin = QSPI_BK1_CS_PIN;
Jerome Coutant 0:146cf26a9bbb 514 gpio_init_structure.Pull = GPIO_PULLUP;
Jerome Coutant 0:146cf26a9bbb 515 gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 516 HAL_GPIO_Init(QSPI_BK1_CS_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 517
Jerome Coutant 0:146cf26a9bbb 518 /* QSPI D0 GPIO pin configuration */
Jerome Coutant 0:146cf26a9bbb 519 gpio_init_structure.Pin = QSPI_BK1_D0_PIN;
Jerome Coutant 0:146cf26a9bbb 520 gpio_init_structure.Pull = GPIO_NOPULL;
Jerome Coutant 0:146cf26a9bbb 521 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 522 HAL_GPIO_Init(QSPI_BK1_D0_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 523
Jerome Coutant 0:146cf26a9bbb 524 gpio_init_structure.Pin = QSPI_BK2_D0_PIN;
Jerome Coutant 0:146cf26a9bbb 525 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 526 HAL_GPIO_Init(QSPI_BK2_D0_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 527
Jerome Coutant 0:146cf26a9bbb 528 /* QSPI D1 GPIO pin configuration */
Jerome Coutant 0:146cf26a9bbb 529 gpio_init_structure.Pin = QSPI_BK1_D1_PIN;
Jerome Coutant 0:146cf26a9bbb 530 gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 531 HAL_GPIO_Init(QSPI_BK1_D1_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 532
Jerome Coutant 0:146cf26a9bbb 533 gpio_init_structure.Pin = QSPI_BK2_D1_PIN;
Jerome Coutant 0:146cf26a9bbb 534 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 535 HAL_GPIO_Init(QSPI_BK2_D1_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 536
Jerome Coutant 0:146cf26a9bbb 537 /* QSPI D2 GPIO pin configuration */
Jerome Coutant 0:146cf26a9bbb 538 gpio_init_structure.Pin = QSPI_BK1_D2_PIN;
Jerome Coutant 0:146cf26a9bbb 539 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
Jerome Coutant 0:146cf26a9bbb 540 HAL_GPIO_Init(QSPI_BK1_D2_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 541
Jerome Coutant 0:146cf26a9bbb 542 gpio_init_structure.Pin = QSPI_BK2_D2_PIN;
Jerome Coutant 0:146cf26a9bbb 543 HAL_GPIO_Init(QSPI_BK2_D2_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 544
Jerome Coutant 0:146cf26a9bbb 545 /* QSPI D3 GPIO pin configuration */
Jerome Coutant 0:146cf26a9bbb 546 gpio_init_structure.Pin = QSPI_BK1_D3_PIN;
Jerome Coutant 0:146cf26a9bbb 547 HAL_GPIO_Init(QSPI_BK1_D3_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 548
Jerome Coutant 0:146cf26a9bbb 549 gpio_init_structure.Pin = QSPI_BK2_D3_PIN;
Jerome Coutant 0:146cf26a9bbb 550 HAL_GPIO_Init(QSPI_BK2_D3_GPIO_PORT, &gpio_init_structure);
Jerome Coutant 0:146cf26a9bbb 551
Jerome Coutant 0:146cf26a9bbb 552 /*##-3- Configure the NVIC for QSPI #########################################*/
Jerome Coutant 0:146cf26a9bbb 553 /* NVIC configuration for QSPI interrupt */
Jerome Coutant 0:146cf26a9bbb 554 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
Jerome Coutant 0:146cf26a9bbb 555 HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
Jerome Coutant 0:146cf26a9bbb 556
Jerome Coutant 0:146cf26a9bbb 557 }
Jerome Coutant 0:146cf26a9bbb 558
Jerome Coutant 0:146cf26a9bbb 559 /**
Jerome Coutant 0:146cf26a9bbb 560 * @brief QSPI MSP De-Initialization
Jerome Coutant 0:146cf26a9bbb 561 * This function frees the hardware resources used in this example:
Jerome Coutant 0:146cf26a9bbb 562 * - Disable the Peripheral's clock
Jerome Coutant 0:146cf26a9bbb 563 * - Revert GPIO and NVIC configuration to their default state
Jerome Coutant 0:146cf26a9bbb 564 * @retval None
Jerome Coutant 0:146cf26a9bbb 565 */
Jerome Coutant 0:146cf26a9bbb 566 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
Jerome Coutant 0:146cf26a9bbb 567 {
Jerome Coutant 0:146cf26a9bbb 568 /*##-1- Disable the NVIC for QSPI ###########################################*/
Jerome Coutant 0:146cf26a9bbb 569 HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
Jerome Coutant 0:146cf26a9bbb 570
Jerome Coutant 0:146cf26a9bbb 571 /*##-2- Disable peripherals and GPIO Clocks ################################*/
Jerome Coutant 0:146cf26a9bbb 572 /* De-Configure QSPI pins */
Jerome Coutant 0:146cf26a9bbb 573 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
Jerome Coutant 0:146cf26a9bbb 574 HAL_GPIO_DeInit(QSPI_BK1_CS_GPIO_PORT, QSPI_BK1_CS_PIN);
Jerome Coutant 0:146cf26a9bbb 575 HAL_GPIO_DeInit(QSPI_BK1_D0_GPIO_PORT, QSPI_BK1_D0_PIN);
Jerome Coutant 0:146cf26a9bbb 576 HAL_GPIO_DeInit(QSPI_BK1_D1_GPIO_PORT, QSPI_BK1_D1_PIN);
Jerome Coutant 0:146cf26a9bbb 577 HAL_GPIO_DeInit(QSPI_BK1_D2_GPIO_PORT, QSPI_BK1_D2_PIN);
Jerome Coutant 0:146cf26a9bbb 578 HAL_GPIO_DeInit(QSPI_BK1_D3_GPIO_PORT, QSPI_BK1_D3_PIN);
Jerome Coutant 0:146cf26a9bbb 579
Jerome Coutant 0:146cf26a9bbb 580 HAL_GPIO_DeInit(QSPI_BK2_CS_GPIO_PORT, QSPI_BK2_CS_PIN);
Jerome Coutant 0:146cf26a9bbb 581 HAL_GPIO_DeInit(QSPI_BK2_D0_GPIO_PORT, QSPI_BK2_D0_PIN);
Jerome Coutant 0:146cf26a9bbb 582 HAL_GPIO_DeInit(QSPI_BK2_D1_GPIO_PORT, QSPI_BK2_D1_PIN);
Jerome Coutant 0:146cf26a9bbb 583 HAL_GPIO_DeInit(QSPI_BK2_D2_GPIO_PORT, QSPI_BK2_D2_PIN);
Jerome Coutant 0:146cf26a9bbb 584 HAL_GPIO_DeInit(QSPI_BK2_D3_GPIO_PORT, QSPI_BK2_D3_PIN);
Jerome Coutant 0:146cf26a9bbb 585
Jerome Coutant 0:146cf26a9bbb 586 /*##-3- Reset peripherals ##################################################*/
Jerome Coutant 0:146cf26a9bbb 587 /* Reset the QuadSPI memory interface */
Jerome Coutant 0:146cf26a9bbb 588 QSPI_FORCE_RESET();
Jerome Coutant 0:146cf26a9bbb 589 QSPI_RELEASE_RESET();
Jerome Coutant 0:146cf26a9bbb 590
Jerome Coutant 0:146cf26a9bbb 591 /* Disable the QuadSPI memory interface clock */
Jerome Coutant 0:146cf26a9bbb 592 QSPI_CLK_DISABLE();
Jerome Coutant 0:146cf26a9bbb 593 }
Jerome Coutant 0:146cf26a9bbb 594
Jerome Coutant 0:146cf26a9bbb 595 /**
Jerome Coutant 0:146cf26a9bbb 596 * @}
Jerome Coutant 0:146cf26a9bbb 597 */
Jerome Coutant 0:146cf26a9bbb 598
Jerome Coutant 0:146cf26a9bbb 599 /** @defgroup STM32H747I_DISCOVERY_QSPI_Private_Functions Private Functions
Jerome Coutant 0:146cf26a9bbb 600 * @{
Jerome Coutant 0:146cf26a9bbb 601 */
Jerome Coutant 0:146cf26a9bbb 602
Jerome Coutant 0:146cf26a9bbb 603 /**
Jerome Coutant 0:146cf26a9bbb 604 * @brief This function reset the QSPI memory.
Jerome Coutant 0:146cf26a9bbb 605 * @param hqspi: QSPI handle
Jerome Coutant 0:146cf26a9bbb 606 * @retval None
Jerome Coutant 0:146cf26a9bbb 607 */
Jerome Coutant 0:146cf26a9bbb 608 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
Jerome Coutant 0:146cf26a9bbb 609 {
Jerome Coutant 0:146cf26a9bbb 610 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 611
Jerome Coutant 0:146cf26a9bbb 612 /* Initialize the reset enable command */
Jerome Coutant 0:146cf26a9bbb 613 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
Jerome Coutant 0:146cf26a9bbb 614 s_command.Instruction = RESET_ENABLE_CMD;
Jerome Coutant 0:146cf26a9bbb 615 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 616 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 617 s_command.DataMode = QSPI_DATA_NONE;
Jerome Coutant 0:146cf26a9bbb 618 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 619 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 620 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 621 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 622
Jerome Coutant 0:146cf26a9bbb 623 /* Send the command */
Jerome Coutant 0:146cf26a9bbb 624 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 625 {
Jerome Coutant 0:146cf26a9bbb 626 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 627 }
Jerome Coutant 0:146cf26a9bbb 628
Jerome Coutant 0:146cf26a9bbb 629 /* Send the reset memory command */
Jerome Coutant 0:146cf26a9bbb 630 s_command.Instruction = RESET_MEMORY_CMD;
Jerome Coutant 0:146cf26a9bbb 631 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 632 {
Jerome Coutant 0:146cf26a9bbb 633 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 634 }
Jerome Coutant 0:146cf26a9bbb 635
Jerome Coutant 0:146cf26a9bbb 636 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 637 s_command.Instruction = RESET_ENABLE_CMD;
Jerome Coutant 0:146cf26a9bbb 638 /* Send the command */
Jerome Coutant 0:146cf26a9bbb 639 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 640 {
Jerome Coutant 0:146cf26a9bbb 641 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 642 }
Jerome Coutant 0:146cf26a9bbb 643
Jerome Coutant 0:146cf26a9bbb 644 /* Send the reset memory command */
Jerome Coutant 0:146cf26a9bbb 645 s_command.Instruction = RESET_MEMORY_CMD;
Jerome Coutant 0:146cf26a9bbb 646 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 647 {
Jerome Coutant 0:146cf26a9bbb 648 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 649 }
Jerome Coutant 0:146cf26a9bbb 650
Jerome Coutant 0:146cf26a9bbb 651 /* Enter QSPI memory in QPI mode */
Jerome Coutant 0:146cf26a9bbb 652 if(QSPI_EnterQPI(&QSPIHandle) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 653 {
Jerome Coutant 0:146cf26a9bbb 654 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 655 }
Jerome Coutant 0:146cf26a9bbb 656
Jerome Coutant 0:146cf26a9bbb 657 /* Configure automatic polling mode to wait the memory is ready */
Jerome Coutant 0:146cf26a9bbb 658 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 659 {
Jerome Coutant 0:146cf26a9bbb 660 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 661 }
Jerome Coutant 0:146cf26a9bbb 662
Jerome Coutant 0:146cf26a9bbb 663 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 664 }
Jerome Coutant 0:146cf26a9bbb 665
Jerome Coutant 0:146cf26a9bbb 666 /**
Jerome Coutant 0:146cf26a9bbb 667 * @brief This function set the QSPI memory in 4-byte address mode
Jerome Coutant 0:146cf26a9bbb 668 * @param hqspi: QSPI handle
Jerome Coutant 0:146cf26a9bbb 669 * @retval None
Jerome Coutant 0:146cf26a9bbb 670 */
Jerome Coutant 0:146cf26a9bbb 671 static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi)
Jerome Coutant 0:146cf26a9bbb 672 {
Jerome Coutant 0:146cf26a9bbb 673 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 674
Jerome Coutant 0:146cf26a9bbb 675 /* Initialize the command */
Jerome Coutant 0:146cf26a9bbb 676 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 677 s_command.Instruction = ENTER_4_BYTE_ADDR_MODE_CMD;
Jerome Coutant 0:146cf26a9bbb 678 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 679 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 680 s_command.DataMode = QSPI_DATA_NONE;
Jerome Coutant 0:146cf26a9bbb 681 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 682 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 683 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 684 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 685
Jerome Coutant 0:146cf26a9bbb 686 /* Enable write operations */
Jerome Coutant 0:146cf26a9bbb 687 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 688 {
Jerome Coutant 0:146cf26a9bbb 689 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 690 }
Jerome Coutant 0:146cf26a9bbb 691
Jerome Coutant 0:146cf26a9bbb 692 /* Send the command */
Jerome Coutant 0:146cf26a9bbb 693 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 694 {
Jerome Coutant 0:146cf26a9bbb 695 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 696 }
Jerome Coutant 0:146cf26a9bbb 697
Jerome Coutant 0:146cf26a9bbb 698 /* Configure automatic polling mode to wait the memory is ready */
Jerome Coutant 0:146cf26a9bbb 699 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 700 {
Jerome Coutant 0:146cf26a9bbb 701 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 702 }
Jerome Coutant 0:146cf26a9bbb 703
Jerome Coutant 0:146cf26a9bbb 704 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 705 }
Jerome Coutant 0:146cf26a9bbb 706
Jerome Coutant 0:146cf26a9bbb 707 /**
Jerome Coutant 0:146cf26a9bbb 708 * @brief This function configure the dummy cycles on memory side.
Jerome Coutant 0:146cf26a9bbb 709 * @param hqspi: QSPI handle
Jerome Coutant 0:146cf26a9bbb 710 * @retval None
Jerome Coutant 0:146cf26a9bbb 711 */
Jerome Coutant 0:146cf26a9bbb 712 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
Jerome Coutant 0:146cf26a9bbb 713 {
Jerome Coutant 0:146cf26a9bbb 714 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 715 uint16_t reg = 0;
Jerome Coutant 0:146cf26a9bbb 716
Jerome Coutant 0:146cf26a9bbb 717 /* Initialize the read volatile configuration register command */
Jerome Coutant 0:146cf26a9bbb 718 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 719 s_command.Instruction = READ_VOL_CFG_REG_CMD;
Jerome Coutant 0:146cf26a9bbb 720 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 721 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 722 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 723 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 724 s_command.NbData = 2;
Jerome Coutant 0:146cf26a9bbb 725 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 726 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 727 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 728
Jerome Coutant 0:146cf26a9bbb 729 /* Configure the command */
Jerome Coutant 0:146cf26a9bbb 730 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 731 {
Jerome Coutant 0:146cf26a9bbb 732 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 733 }
Jerome Coutant 0:146cf26a9bbb 734
Jerome Coutant 0:146cf26a9bbb 735 /* Reception of the data */
Jerome Coutant 0:146cf26a9bbb 736 if (HAL_QSPI_Receive(hqspi, (uint8_t *)(&reg), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 737 {
Jerome Coutant 0:146cf26a9bbb 738 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 739 }
Jerome Coutant 0:146cf26a9bbb 740
Jerome Coutant 0:146cf26a9bbb 741 /* Enable write operations */
Jerome Coutant 0:146cf26a9bbb 742 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
Jerome Coutant 0:146cf26a9bbb 743 {
Jerome Coutant 0:146cf26a9bbb 744 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 745 }
Jerome Coutant 0:146cf26a9bbb 746
Jerome Coutant 0:146cf26a9bbb 747 /* Update volatile configuration register (with new dummy cycles) */
Jerome Coutant 0:146cf26a9bbb 748 s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
Jerome Coutant 0:146cf26a9bbb 749 MODIFY_REG(reg, 0xF0F0, ((MT25TL01G_DUMMY_CYCLES_READ_QUAD << 4) |
Jerome Coutant 0:146cf26a9bbb 750 (MT25TL01G_DUMMY_CYCLES_READ_QUAD << 12)));
Jerome Coutant 0:146cf26a9bbb 751
Jerome Coutant 0:146cf26a9bbb 752 /* Configure the write volatile configuration register command */
Jerome Coutant 0:146cf26a9bbb 753 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 754 {
Jerome Coutant 0:146cf26a9bbb 755 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 756 }
Jerome Coutant 0:146cf26a9bbb 757
Jerome Coutant 0:146cf26a9bbb 758 /* Transmission of the data */
Jerome Coutant 0:146cf26a9bbb 759 if (HAL_QSPI_Transmit(hqspi, (uint8_t *)(&reg), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 760 {
Jerome Coutant 0:146cf26a9bbb 761 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 762 }
Jerome Coutant 0:146cf26a9bbb 763
Jerome Coutant 0:146cf26a9bbb 764 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 765 }
Jerome Coutant 0:146cf26a9bbb 766
Jerome Coutant 0:146cf26a9bbb 767 /**
Jerome Coutant 0:146cf26a9bbb 768 * @brief This function send a Write Enable and wait it is effective.
Jerome Coutant 0:146cf26a9bbb 769 * @param hqspi: QSPI handle
Jerome Coutant 0:146cf26a9bbb 770 * @retval None
Jerome Coutant 0:146cf26a9bbb 771 */
Jerome Coutant 0:146cf26a9bbb 772 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
Jerome Coutant 0:146cf26a9bbb 773 {
Jerome Coutant 0:146cf26a9bbb 774 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 775 QSPI_AutoPollingTypeDef s_config;
Jerome Coutant 0:146cf26a9bbb 776
Jerome Coutant 0:146cf26a9bbb 777 /* Enable write operations */
Jerome Coutant 0:146cf26a9bbb 778 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 779 s_command.Instruction = WRITE_ENABLE_CMD;
Jerome Coutant 0:146cf26a9bbb 780 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 781 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 782 s_command.DataMode = QSPI_DATA_NONE;
Jerome Coutant 0:146cf26a9bbb 783 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 784 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 785 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 786 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 787
Jerome Coutant 0:146cf26a9bbb 788 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 789 {
Jerome Coutant 0:146cf26a9bbb 790 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 791 }
Jerome Coutant 0:146cf26a9bbb 792
Jerome Coutant 0:146cf26a9bbb 793 /* Configure automatic polling mode to wait for write enabling */
Jerome Coutant 0:146cf26a9bbb 794 s_config.Match = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);
Jerome Coutant 0:146cf26a9bbb 795 s_config.Mask = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);
Jerome Coutant 0:146cf26a9bbb 796 s_config.MatchMode = QSPI_MATCH_MODE_AND;
Jerome Coutant 0:146cf26a9bbb 797 s_config.StatusBytesSize = 2;
Jerome Coutant 0:146cf26a9bbb 798 s_config.Interval = 0x10;
Jerome Coutant 0:146cf26a9bbb 799 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
Jerome Coutant 0:146cf26a9bbb 800
Jerome Coutant 0:146cf26a9bbb 801 s_command.Instruction = READ_STATUS_REG_CMD;
Jerome Coutant 0:146cf26a9bbb 802 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 803
Jerome Coutant 0:146cf26a9bbb 804 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 805 {
Jerome Coutant 0:146cf26a9bbb 806 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 807 }
Jerome Coutant 0:146cf26a9bbb 808
Jerome Coutant 0:146cf26a9bbb 809 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 810 }
Jerome Coutant 0:146cf26a9bbb 811
Jerome Coutant 0:146cf26a9bbb 812 /**
Jerome Coutant 0:146cf26a9bbb 813 * @brief This function read the SR of the memory and wait the EOP.
Jerome Coutant 0:146cf26a9bbb 814 * @param hqspi: QSPI handle
Jerome Coutant 0:146cf26a9bbb 815 * @param Timeout: timeout in ms
Jerome Coutant 0:146cf26a9bbb 816 * @retval None
Jerome Coutant 0:146cf26a9bbb 817 */
Jerome Coutant 0:146cf26a9bbb 818 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Jerome Coutant 0:146cf26a9bbb 819 {
Jerome Coutant 0:146cf26a9bbb 820 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 821 QSPI_AutoPollingTypeDef s_config;
Jerome Coutant 0:146cf26a9bbb 822
Jerome Coutant 0:146cf26a9bbb 823 /* Configure automatic polling mode to wait for memory ready */
Jerome Coutant 0:146cf26a9bbb 824 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
Jerome Coutant 0:146cf26a9bbb 825 s_command.Instruction = READ_STATUS_REG_CMD;
Jerome Coutant 0:146cf26a9bbb 826 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 827 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 828 s_command.DataMode = QSPI_DATA_4_LINES;
Jerome Coutant 0:146cf26a9bbb 829 s_command.DummyCycles = 2;
Jerome Coutant 0:146cf26a9bbb 830 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 831 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 832 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 833
Jerome Coutant 0:146cf26a9bbb 834 s_config.Match = 0;
Jerome Coutant 0:146cf26a9bbb 835 s_config.MatchMode = QSPI_MATCH_MODE_AND;
Jerome Coutant 0:146cf26a9bbb 836 s_config.Interval = 0x10;
Jerome Coutant 0:146cf26a9bbb 837 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
Jerome Coutant 0:146cf26a9bbb 838 s_config.Mask = MT25TL01G_SR_WIP | (MT25TL01G_SR_WIP <<8);
Jerome Coutant 0:146cf26a9bbb 839 s_config.StatusBytesSize = 2;
Jerome Coutant 0:146cf26a9bbb 840
Jerome Coutant 0:146cf26a9bbb 841 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 842 {
Jerome Coutant 0:146cf26a9bbb 843 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 844 }
Jerome Coutant 0:146cf26a9bbb 845
Jerome Coutant 0:146cf26a9bbb 846 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 847 }
Jerome Coutant 0:146cf26a9bbb 848
Jerome Coutant 0:146cf26a9bbb 849 /**
Jerome Coutant 0:146cf26a9bbb 850 * @brief This function enter the QPSI memory in QPI mode
Jerome Coutant 0:146cf26a9bbb 851 * @param hqspi QSPI handle
Jerome Coutant 0:146cf26a9bbb 852 * @retval QSPI status
Jerome Coutant 0:146cf26a9bbb 853 */
Jerome Coutant 0:146cf26a9bbb 854 static uint8_t QSPI_EnterQPI(QSPI_HandleTypeDef *hqspi)
Jerome Coutant 0:146cf26a9bbb 855 {
Jerome Coutant 0:146cf26a9bbb 856 QSPI_CommandTypeDef s_command;
Jerome Coutant 0:146cf26a9bbb 857
Jerome Coutant 0:146cf26a9bbb 858 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
Jerome Coutant 0:146cf26a9bbb 859 s_command.Instruction = ENTER_QUAD_CMD;
Jerome Coutant 0:146cf26a9bbb 860 s_command.AddressMode = QSPI_ADDRESS_NONE;
Jerome Coutant 0:146cf26a9bbb 861 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
Jerome Coutant 0:146cf26a9bbb 862 s_command.DataMode = QSPI_DATA_NONE;
Jerome Coutant 0:146cf26a9bbb 863 s_command.DummyCycles = 0;
Jerome Coutant 0:146cf26a9bbb 864 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
Jerome Coutant 0:146cf26a9bbb 865 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
Jerome Coutant 0:146cf26a9bbb 866 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
Jerome Coutant 0:146cf26a9bbb 867
Jerome Coutant 0:146cf26a9bbb 868 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
Jerome Coutant 0:146cf26a9bbb 869 {
Jerome Coutant 0:146cf26a9bbb 870 return QSPI_ERROR;
Jerome Coutant 0:146cf26a9bbb 871 }
Jerome Coutant 0:146cf26a9bbb 872
Jerome Coutant 0:146cf26a9bbb 873 return QSPI_OK;
Jerome Coutant 0:146cf26a9bbb 874 }
Jerome Coutant 0:146cf26a9bbb 875
Jerome Coutant 0:146cf26a9bbb 876 /**
Jerome Coutant 0:146cf26a9bbb 877 * @}
Jerome Coutant 0:146cf26a9bbb 878 */
Jerome Coutant 0:146cf26a9bbb 879
Jerome Coutant 0:146cf26a9bbb 880 /**
Jerome Coutant 0:146cf26a9bbb 881 * @}
Jerome Coutant 0:146cf26a9bbb 882 */
Jerome Coutant 0:146cf26a9bbb 883
Jerome Coutant 0:146cf26a9bbb 884 /**
Jerome Coutant 0:146cf26a9bbb 885 * @}
Jerome Coutant 0:146cf26a9bbb 886 */
Jerome Coutant 0:146cf26a9bbb 887
Jerome Coutant 0:146cf26a9bbb 888 /**
Jerome Coutant 0:146cf26a9bbb 889 * @}
Jerome Coutant 0:146cf26a9bbb 890 */
Jerome Coutant 0:146cf26a9bbb 891
Jerome Coutant 0:146cf26a9bbb 892 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Jerome Coutant 0:146cf26a9bbb 893