ST / BSP_DISCO_F769NI

STM32Cube BSP FW for STM32F769I-Discovery

Dependents:   mbed-os-example-blinky-5 DISCO-F769NI_TOUCHSCREEN_demo_custom_1 Datarecorder2 DISCO-F769NI_TOUCHSCREEN_demo ... more

Drivers/BSP/STM32F769I-Discovery/stm32f769i_discovery_sdram.c@6:05b81d60cdae, 2019-11-12 (annotated)

Committer:
Jerome Coutant
Date:
Tue Nov 12 11:24:02 2019 +0100
Revision:
6:05b81d60cdae
Parent:
3:145e714557cf 
STM32Cube_FW_F7_V1.15.0 BSP_DISCO_F769NI

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jerome Coutant 0:c0f3bbab73d2 1 /**
Jerome Coutant 0:c0f3bbab73d2 2 ******************************************************************************
Jerome Coutant 0:c0f3bbab73d2 3 * @file stm32f769i_discovery_sdram.c
Jerome Coutant 0:c0f3bbab73d2 4 * @author MCD Application Team
Jerome Coutant 0:c0f3bbab73d2 5 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-6A memory
Jerome Coutant 0:c0f3bbab73d2 6 * device mounted on STM32F769I-DISCOVERY boards.
Jerome Coutant 0:c0f3bbab73d2 7 @verbatim
Jerome Coutant 0:c0f3bbab73d2 8 How To use this driver:
Jerome Coutant 0:c0f3bbab73d2 9 -----------------------
Jerome Coutant 0:c0f3bbab73d2 10 - This driver is used to drive the MT48LC4M32B2B5-6A SDRAM external memory mounted
Jerome Coutant 0:c0f3bbab73d2 11 on STM32F769I-DISCOVERY board.
Jerome Coutant 0:c0f3bbab73d2 12 - This driver does not need a specific component driver for the SDRAM device
Jerome Coutant 0:c0f3bbab73d2 13 to be included with.
Jerome Coutant 0:c0f3bbab73d2 14
Jerome Coutant 0:c0f3bbab73d2 15 Driver description:
Jerome Coutant 0:c0f3bbab73d2 16 ------------------
Jerome Coutant 0:c0f3bbab73d2 17 + Initialization steps:
Jerome Coutant 0:c0f3bbab73d2 18 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
Jerome Coutant 0:c0f3bbab73d2 19 function includes the MSP layer hardware resources initialization and the
Jerome Coutant 0:c0f3bbab73d2 20 FMC controller configuration to interface with the external SDRAM memory.
Jerome Coutant 0:c0f3bbab73d2 21 o It contains the SDRAM initialization sequence to program the SDRAM external
Jerome Coutant 0:c0f3bbab73d2 22 device using the function BSP_SDRAM_Initialization_sequence(). Note that this
Jerome Coutant 0:c0f3bbab73d2 23 sequence is standard for all SDRAM devices, but can include some differences
Jerome Coutant 0:c0f3bbab73d2 24 from a device to another. If it is the case, the right sequence should be
Jerome Coutant 0:c0f3bbab73d2 25 implemented separately.
Jerome Coutant 0:c0f3bbab73d2 26
Jerome Coutant 0:c0f3bbab73d2 27 + SDRAM read/write operations
Jerome Coutant 0:c0f3bbab73d2 28 o SDRAM external memory can be accessed with read/write operations once it is
Jerome Coutant 0:c0f3bbab73d2 29 initialized.
Jerome Coutant 0:c0f3bbab73d2 30 Read/write operation can be performed with AHB access using the functions
Jerome Coutant 0:c0f3bbab73d2 31 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
Jerome Coutant 0:c0f3bbab73d2 32 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
Jerome Coutant 0:c0f3bbab73d2 33 o The AHB access is performed with 32-bit width transaction, the DMA transfer
Jerome Coutant 0:c0f3bbab73d2 34 configuration is fixed at single (no burst) word transfer (see the
Jerome Coutant 0:c0f3bbab73d2 35 SDRAM_MspInit() static function).
Jerome Coutant 0:c0f3bbab73d2 36 o User can implement his own functions for read/write access with his desired
Jerome Coutant 0:c0f3bbab73d2 37 configurations.
Jerome Coutant 0:c0f3bbab73d2 38 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
Jerome Coutant 0:c0f3bbab73d2 39 is called in IRQ handler file, to serve the generated interrupt once the DMA
Jerome Coutant 0:c0f3bbab73d2 40 transfer is complete.
Jerome Coutant 0:c0f3bbab73d2 41 o You can send a command to the SDRAM device in runtime using the function
Jerome Coutant 0:c0f3bbab73d2 42 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
Jerome Coutant 0:c0f3bbab73d2 43 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
Jerome Coutant 0:c0f3bbab73d2 44 @endverbatim
Jerome Coutant 0:c0f3bbab73d2 45 ******************************************************************************
Jerome Coutant 0:c0f3bbab73d2 46 * @attention
Jerome Coutant 0:c0f3bbab73d2 47 *
Jerome Coutant 0:c0f3bbab73d2 48 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Jerome Coutant 0:c0f3bbab73d2 49 *
Jerome Coutant 0:c0f3bbab73d2 50 * Redistribution and use in source and binary forms, with or without modification,
Jerome Coutant 0:c0f3bbab73d2 51 * are permitted provided that the following conditions are met:
Jerome Coutant 0:c0f3bbab73d2 52 * 1. Redistributions of source code must retain the above copyright notice,
Jerome Coutant 0:c0f3bbab73d2 53 * this list of conditions and the following disclaimer.
Jerome Coutant 0:c0f3bbab73d2 54 * 2. Redistributions in binary form must reproduce the above copyright notice,
Jerome Coutant 0:c0f3bbab73d2 55 * this list of conditions and the following disclaimer in the documentation
Jerome Coutant 0:c0f3bbab73d2 56 * and/or other materials provided with the distribution.
Jerome Coutant 0:c0f3bbab73d2 57 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Jerome Coutant 0:c0f3bbab73d2 58 * may be used to endorse or promote products derived from this software
Jerome Coutant 0:c0f3bbab73d2 59 * without specific prior written permission.
Jerome Coutant 0:c0f3bbab73d2 60 *
Jerome Coutant 0:c0f3bbab73d2 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Jerome Coutant 0:c0f3bbab73d2 62 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Jerome Coutant 0:c0f3bbab73d2 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jerome Coutant 0:c0f3bbab73d2 64 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Jerome Coutant 0:c0f3bbab73d2 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Jerome Coutant 0:c0f3bbab73d2 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Jerome Coutant 0:c0f3bbab73d2 67 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Jerome Coutant 0:c0f3bbab73d2 68 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Jerome Coutant 0:c0f3bbab73d2 69 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Jerome Coutant 0:c0f3bbab73d2 70 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jerome Coutant 0:c0f3bbab73d2 71 *
Jerome Coutant 0:c0f3bbab73d2 72 ******************************************************************************
Jerome Coutant 0:c0f3bbab73d2 73 */
Jerome Coutant 0:c0f3bbab73d2 74
Jerome Coutant 6:05b81d60cdae 75 /* Dependencies
Jerome Coutant 6:05b81d60cdae 76 - stm32f7xx_hal_sdram.c
Jerome Coutant 6:05b81d60cdae 77 - stm32f7xx_ll_fmc.c
Jerome Coutant 6:05b81d60cdae 78 - stm32f7xx_hal_dma.c
Jerome Coutant 6:05b81d60cdae 79 - stm32f7xx_hal_gpio.c
Jerome Coutant 6:05b81d60cdae 80 - stm32f7xx_hal_cortex.c
Jerome Coutant 6:05b81d60cdae 81 - stm32f7xx_hal_rcc_ex.h
Jerome Coutant 6:05b81d60cdae 82 EndDependencies */
Jerome Coutant 6:05b81d60cdae 83
Jerome Coutant 0:c0f3bbab73d2 84 /* Includes ------------------------------------------------------------------*/
Jerome Coutant 0:c0f3bbab73d2 85 #include "stm32f769i_discovery_sdram.h"
Jerome Coutant 0:c0f3bbab73d2 86
Jerome Coutant 0:c0f3bbab73d2 87 /** @addtogroup BSP
Jerome Coutant 0:c0f3bbab73d2 88 * @{
Jerome Coutant 0:c0f3bbab73d2 89 */
Jerome Coutant 0:c0f3bbab73d2 90
Jerome Coutant 0:c0f3bbab73d2 91 /** @addtogroup STM32F769I_DISCOVERY
Jerome Coutant 0:c0f3bbab73d2 92 * @{
Jerome Coutant 0:c0f3bbab73d2 93 */
Jerome Coutant 0:c0f3bbab73d2 94
Jerome Coutant 1:3e58f8a39705 95 /** @defgroup STM32F769I_DISCOVERY_SDRAM STM32F769I_DISCOVERY SDRAM
Jerome Coutant 0:c0f3bbab73d2 96 * @{
Jerome Coutant 0:c0f3bbab73d2 97 */
Jerome Coutant 0:c0f3bbab73d2 98
Jerome Coutant 1:3e58f8a39705 99 /** @defgroup STM32F769I_DISCOVERY_SDRAM_Private_Types_Definitions SDRAM Private Types Definitions
Jerome Coutant 0:c0f3bbab73d2 100 * @{
Jerome Coutant 0:c0f3bbab73d2 101 */
Jerome Coutant 0:c0f3bbab73d2 102 /**
Jerome Coutant 0:c0f3bbab73d2 103 * @}
Jerome Coutant 0:c0f3bbab73d2 104 */
Jerome Coutant 0:c0f3bbab73d2 105
Jerome Coutant 1:3e58f8a39705 106 /** @defgroup STM32F769I_DISCOVERY_SDRAM_Private_Defines SDRAM Private Defines
Jerome Coutant 0:c0f3bbab73d2 107 * @{
Jerome Coutant 0:c0f3bbab73d2 108 */
Jerome Coutant 0:c0f3bbab73d2 109 /**
Jerome Coutant 0:c0f3bbab73d2 110 * @}
Jerome Coutant 0:c0f3bbab73d2 111 */
Jerome Coutant 0:c0f3bbab73d2 112
Jerome Coutant 1:3e58f8a39705 113 /** @defgroup STM32F769I_DISCOVERY_SDRAM_Private_Macros SDRAM Private Macros
Jerome Coutant 0:c0f3bbab73d2 114 * @{
Jerome Coutant 0:c0f3bbab73d2 115 */
Jerome Coutant 0:c0f3bbab73d2 116 /**
Jerome Coutant 0:c0f3bbab73d2 117 * @}
Jerome Coutant 0:c0f3bbab73d2 118 */
Jerome Coutant 0:c0f3bbab73d2 119
Jerome Coutant 1:3e58f8a39705 120 /** @defgroup STM32F769I_DISCOVERY_SDRAM_Private_Variables SDRAM Private Variables
Jerome Coutant 0:c0f3bbab73d2 121 * @{
Jerome Coutant 0:c0f3bbab73d2 122 */
Jerome Coutant 0:c0f3bbab73d2 123 SDRAM_HandleTypeDef sdramHandle;
Jerome Coutant 0:c0f3bbab73d2 124 static FMC_SDRAM_TimingTypeDef Timing;
Jerome Coutant 0:c0f3bbab73d2 125 static FMC_SDRAM_CommandTypeDef Command;
Jerome Coutant 0:c0f3bbab73d2 126 /**
Jerome Coutant 0:c0f3bbab73d2 127 * @}
Jerome Coutant 0:c0f3bbab73d2 128 */
Jerome Coutant 0:c0f3bbab73d2 129
Jerome Coutant 1:3e58f8a39705 130 /** @defgroup STM32F769I_DISCOVERY_SDRAM_Private_Function_Prototypes SDRAM Private Function Prototypes
Jerome Coutant 0:c0f3bbab73d2 131 * @{
Jerome Coutant 0:c0f3bbab73d2 132 */
Jerome Coutant 0:c0f3bbab73d2 133 /**
Jerome Coutant 0:c0f3bbab73d2 134 * @}
Jerome Coutant 0:c0f3bbab73d2 135 */
Jerome Coutant 0:c0f3bbab73d2 136
Jerome Coutant 1:3e58f8a39705 137 /** @defgroup STM32F769I_DISCOVERY_SDRAM_Private_Functions SDRAM Private Functions
Jerome Coutant 0:c0f3bbab73d2 138 * @{
Jerome Coutant 0:c0f3bbab73d2 139 */
Jerome Coutant 0:c0f3bbab73d2 140
Jerome Coutant 0:c0f3bbab73d2 141 /**
Jerome Coutant 0:c0f3bbab73d2 142 * @brief Initializes the SDRAM device.
Jerome Coutant 0:c0f3bbab73d2 143 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 144 */
Jerome Coutant 0:c0f3bbab73d2 145 uint8_t BSP_SDRAM_Init(void)
Jerome Coutant 0:c0f3bbab73d2 146 {
Jerome Coutant 0:c0f3bbab73d2 147 static uint8_t sdramstatus = SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 148 /* SDRAM device configuration */
Jerome Coutant 0:c0f3bbab73d2 149 sdramHandle.Instance = FMC_SDRAM_DEVICE;
Jerome Coutant 0:c0f3bbab73d2 150
Jerome Coutant 0:c0f3bbab73d2 151 /* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */
Jerome Coutant 0:c0f3bbab73d2 152 Timing.LoadToActiveDelay = 2;
Jerome Coutant 0:c0f3bbab73d2 153 Timing.ExitSelfRefreshDelay = 7;
Jerome Coutant 0:c0f3bbab73d2 154 Timing.SelfRefreshTime = 4;
Jerome Coutant 0:c0f3bbab73d2 155 Timing.RowCycleDelay = 7;
Jerome Coutant 0:c0f3bbab73d2 156 Timing.WriteRecoveryTime = 2;
Jerome Coutant 0:c0f3bbab73d2 157 Timing.RPDelay = 2;
Jerome Coutant 0:c0f3bbab73d2 158 Timing.RCDDelay = 2;
Jerome Coutant 0:c0f3bbab73d2 159
Jerome Coutant 0:c0f3bbab73d2 160 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
Jerome Coutant 0:c0f3bbab73d2 161 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
Jerome Coutant 0:c0f3bbab73d2 162 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
Jerome Coutant 0:c0f3bbab73d2 163 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
Jerome Coutant 0:c0f3bbab73d2 164 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
Jerome Coutant 0:c0f3bbab73d2 165 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
Jerome Coutant 0:c0f3bbab73d2 166 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
Jerome Coutant 0:c0f3bbab73d2 167 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
Jerome Coutant 0:c0f3bbab73d2 168 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
Jerome Coutant 0:c0f3bbab73d2 169 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
Jerome Coutant 0:c0f3bbab73d2 170
Jerome Coutant 0:c0f3bbab73d2 171 /* SDRAM controller initialization */
Jerome Coutant 0:c0f3bbab73d2 172
Jerome Coutant 0:c0f3bbab73d2 173 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
Jerome Coutant 0:c0f3bbab73d2 174
Jerome Coutant 0:c0f3bbab73d2 175 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 176 {
Jerome Coutant 0:c0f3bbab73d2 177 sdramstatus = SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 178 }
Jerome Coutant 0:c0f3bbab73d2 179 else
Jerome Coutant 0:c0f3bbab73d2 180 {
Jerome Coutant 0:c0f3bbab73d2 181 sdramstatus = SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 182 }
Jerome Coutant 0:c0f3bbab73d2 183
Jerome Coutant 0:c0f3bbab73d2 184 /* SDRAM initialization sequence */
Jerome Coutant 0:c0f3bbab73d2 185 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
Jerome Coutant 0:c0f3bbab73d2 186
Jerome Coutant 0:c0f3bbab73d2 187 return sdramstatus;
Jerome Coutant 0:c0f3bbab73d2 188 }
Jerome Coutant 0:c0f3bbab73d2 189
Jerome Coutant 0:c0f3bbab73d2 190 /**
Jerome Coutant 0:c0f3bbab73d2 191 * @brief DeInitializes the SDRAM device.
Jerome Coutant 0:c0f3bbab73d2 192 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 193 */
Jerome Coutant 0:c0f3bbab73d2 194 uint8_t BSP_SDRAM_DeInit(void)
Jerome Coutant 0:c0f3bbab73d2 195 {
Jerome Coutant 0:c0f3bbab73d2 196 static uint8_t sdramstatus = SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 197 /* SDRAM device de-initialization */
Jerome Coutant 0:c0f3bbab73d2 198 sdramHandle.Instance = FMC_SDRAM_DEVICE;
Jerome Coutant 0:c0f3bbab73d2 199
Jerome Coutant 0:c0f3bbab73d2 200 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 201 {
Jerome Coutant 0:c0f3bbab73d2 202 sdramstatus = SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 203 }
Jerome Coutant 0:c0f3bbab73d2 204 else
Jerome Coutant 0:c0f3bbab73d2 205 {
Jerome Coutant 0:c0f3bbab73d2 206 sdramstatus = SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 207 }
Jerome Coutant 0:c0f3bbab73d2 208
Jerome Coutant 0:c0f3bbab73d2 209 /* SDRAM controller de-initialization */
Jerome Coutant 0:c0f3bbab73d2 210 BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
Jerome Coutant 0:c0f3bbab73d2 211
Jerome Coutant 0:c0f3bbab73d2 212 return sdramstatus;
Jerome Coutant 0:c0f3bbab73d2 213 }
Jerome Coutant 0:c0f3bbab73d2 214
Jerome Coutant 0:c0f3bbab73d2 215 /**
Jerome Coutant 0:c0f3bbab73d2 216 * @brief Programs the SDRAM device.
Jerome Coutant 0:c0f3bbab73d2 217 * @param RefreshCount: SDRAM refresh counter value
Jerome Coutant 0:c0f3bbab73d2 218 * @retval None
Jerome Coutant 0:c0f3bbab73d2 219 */
Jerome Coutant 0:c0f3bbab73d2 220 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
Jerome Coutant 0:c0f3bbab73d2 221 {
Jerome Coutant 0:c0f3bbab73d2 222 __IO uint32_t tmpmrd = 0;
Jerome Coutant 0:c0f3bbab73d2 223
Jerome Coutant 0:c0f3bbab73d2 224 /* Step 1: Configure a clock configuration enable command */
Jerome Coutant 0:c0f3bbab73d2 225 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
Jerome Coutant 0:c0f3bbab73d2 226 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Jerome Coutant 0:c0f3bbab73d2 227 Command.AutoRefreshNumber = 1;
Jerome Coutant 0:c0f3bbab73d2 228 Command.ModeRegisterDefinition = 0;
Jerome Coutant 0:c0f3bbab73d2 229
Jerome Coutant 0:c0f3bbab73d2 230 /* Send the command */
Jerome Coutant 0:c0f3bbab73d2 231 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
Jerome Coutant 0:c0f3bbab73d2 232
Jerome Coutant 0:c0f3bbab73d2 233 /* Step 2: Insert 100 us minimum delay */
Jerome Coutant 0:c0f3bbab73d2 234 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
Jerome Coutant 6:05b81d60cdae 235 HAL_Delay(1);
Jerome Coutant 0:c0f3bbab73d2 236
Jerome Coutant 0:c0f3bbab73d2 237 /* Step 3: Configure a PALL (precharge all) command */
Jerome Coutant 0:c0f3bbab73d2 238 Command.CommandMode = FMC_SDRAM_CMD_PALL;
Jerome Coutant 0:c0f3bbab73d2 239 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Jerome Coutant 0:c0f3bbab73d2 240 Command.AutoRefreshNumber = 1;
Jerome Coutant 0:c0f3bbab73d2 241 Command.ModeRegisterDefinition = 0;
Jerome Coutant 0:c0f3bbab73d2 242
Jerome Coutant 0:c0f3bbab73d2 243 /* Send the command */
Jerome Coutant 0:c0f3bbab73d2 244 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
Jerome Coutant 0:c0f3bbab73d2 245
Jerome Coutant 0:c0f3bbab73d2 246 /* Step 4: Configure an Auto Refresh command */
Jerome Coutant 0:c0f3bbab73d2 247 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
Jerome Coutant 0:c0f3bbab73d2 248 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Jerome Coutant 0:c0f3bbab73d2 249 Command.AutoRefreshNumber = 8;
Jerome Coutant 0:c0f3bbab73d2 250 Command.ModeRegisterDefinition = 0;
Jerome Coutant 0:c0f3bbab73d2 251
Jerome Coutant 0:c0f3bbab73d2 252 /* Send the command */
Jerome Coutant 0:c0f3bbab73d2 253 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
Jerome Coutant 0:c0f3bbab73d2 254
Jerome Coutant 0:c0f3bbab73d2 255 /* Step 5: Program the external memory mode register */
Jerome Coutant 0:c0f3bbab73d2 256 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
Jerome Coutant 0:c0f3bbab73d2 257 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
Jerome Coutant 0:c0f3bbab73d2 258 SDRAM_MODEREG_CAS_LATENCY_3 |\
Jerome Coutant 0:c0f3bbab73d2 259 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
Jerome Coutant 0:c0f3bbab73d2 260 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Jerome Coutant 0:c0f3bbab73d2 261
Jerome Coutant 0:c0f3bbab73d2 262 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Jerome Coutant 0:c0f3bbab73d2 263 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Jerome Coutant 0:c0f3bbab73d2 264 Command.AutoRefreshNumber = 1;
Jerome Coutant 0:c0f3bbab73d2 265 Command.ModeRegisterDefinition = tmpmrd;
Jerome Coutant 0:c0f3bbab73d2 266
Jerome Coutant 0:c0f3bbab73d2 267 /* Send the command */
Jerome Coutant 0:c0f3bbab73d2 268 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
Jerome Coutant 0:c0f3bbab73d2 269
Jerome Coutant 0:c0f3bbab73d2 270 /* Step 6: Set the refresh rate counter */
Jerome Coutant 0:c0f3bbab73d2 271 /* Set the device refresh rate */
Jerome Coutant 0:c0f3bbab73d2 272 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
Jerome Coutant 0:c0f3bbab73d2 273 }
Jerome Coutant 0:c0f3bbab73d2 274
Jerome Coutant 0:c0f3bbab73d2 275 /**
Jerome Coutant 0:c0f3bbab73d2 276 * @brief Reads an amount of data from the SDRAM memory in polling mode.
Jerome Coutant 0:c0f3bbab73d2 277 * @param uwStartAddress: Read start address
Jerome Coutant 0:c0f3bbab73d2 278 * @param pData: Pointer to data to be read
Jerome Coutant 0:c0f3bbab73d2 279 * @param uwDataSize: Size of read data from the memory
Jerome Coutant 0:c0f3bbab73d2 280 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 281 */
Jerome Coutant 0:c0f3bbab73d2 282 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
Jerome Coutant 0:c0f3bbab73d2 283 {
Jerome Coutant 0:c0f3bbab73d2 284 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 285 {
Jerome Coutant 0:c0f3bbab73d2 286 return SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 287 }
Jerome Coutant 0:c0f3bbab73d2 288 else
Jerome Coutant 0:c0f3bbab73d2 289 {
Jerome Coutant 0:c0f3bbab73d2 290 return SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 291 }
Jerome Coutant 0:c0f3bbab73d2 292 }
Jerome Coutant 0:c0f3bbab73d2 293
Jerome Coutant 0:c0f3bbab73d2 294 /**
Jerome Coutant 0:c0f3bbab73d2 295 * @brief Reads an amount of data from the SDRAM memory in DMA mode.
Jerome Coutant 0:c0f3bbab73d2 296 * @param uwStartAddress: Read start address
Jerome Coutant 0:c0f3bbab73d2 297 * @param pData: Pointer to data to be read
Jerome Coutant 0:c0f3bbab73d2 298 * @param uwDataSize: Size of read data from the memory
Jerome Coutant 0:c0f3bbab73d2 299 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 300 */
Jerome Coutant 0:c0f3bbab73d2 301 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
Jerome Coutant 0:c0f3bbab73d2 302 {
Jerome Coutant 0:c0f3bbab73d2 303 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 304 {
Jerome Coutant 0:c0f3bbab73d2 305 return SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 306 }
Jerome Coutant 0:c0f3bbab73d2 307 else
Jerome Coutant 0:c0f3bbab73d2 308 {
Jerome Coutant 0:c0f3bbab73d2 309 return SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 310 }
Jerome Coutant 0:c0f3bbab73d2 311 }
Jerome Coutant 0:c0f3bbab73d2 312
Jerome Coutant 0:c0f3bbab73d2 313 /**
Jerome Coutant 0:c0f3bbab73d2 314 * @brief Writes an amount of data to the SDRAM memory in polling mode.
Jerome Coutant 0:c0f3bbab73d2 315 * @param uwStartAddress: Write start address
Jerome Coutant 0:c0f3bbab73d2 316 * @param pData: Pointer to data to be written
Jerome Coutant 0:c0f3bbab73d2 317 * @param uwDataSize: Size of written data from the memory
Jerome Coutant 0:c0f3bbab73d2 318 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 319 */
Jerome Coutant 0:c0f3bbab73d2 320 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
Jerome Coutant 0:c0f3bbab73d2 321 {
Jerome Coutant 0:c0f3bbab73d2 322 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 323 {
Jerome Coutant 0:c0f3bbab73d2 324 return SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 325 }
Jerome Coutant 0:c0f3bbab73d2 326 else
Jerome Coutant 0:c0f3bbab73d2 327 {
Jerome Coutant 0:c0f3bbab73d2 328 return SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 329 }
Jerome Coutant 0:c0f3bbab73d2 330 }
Jerome Coutant 0:c0f3bbab73d2 331
Jerome Coutant 0:c0f3bbab73d2 332 /**
Jerome Coutant 0:c0f3bbab73d2 333 * @brief Writes an amount of data to the SDRAM memory in DMA mode.
Jerome Coutant 0:c0f3bbab73d2 334 * @param uwStartAddress: Write start address
Jerome Coutant 0:c0f3bbab73d2 335 * @param pData: Pointer to data to be written
Jerome Coutant 0:c0f3bbab73d2 336 * @param uwDataSize: Size of written data from the memory
Jerome Coutant 0:c0f3bbab73d2 337 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 338 */
Jerome Coutant 0:c0f3bbab73d2 339 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
Jerome Coutant 0:c0f3bbab73d2 340 {
Jerome Coutant 0:c0f3bbab73d2 341 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 342 {
Jerome Coutant 0:c0f3bbab73d2 343 return SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 344 }
Jerome Coutant 0:c0f3bbab73d2 345 else
Jerome Coutant 0:c0f3bbab73d2 346 {
Jerome Coutant 0:c0f3bbab73d2 347 return SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 348 }
Jerome Coutant 0:c0f3bbab73d2 349 }
Jerome Coutant 0:c0f3bbab73d2 350
Jerome Coutant 0:c0f3bbab73d2 351 /**
Jerome Coutant 0:c0f3bbab73d2 352 * @brief Sends command to the SDRAM bank.
Jerome Coutant 0:c0f3bbab73d2 353 * @param SdramCmd: Pointer to SDRAM command structure
Jerome Coutant 0:c0f3bbab73d2 354 * @retval SDRAM status
Jerome Coutant 0:c0f3bbab73d2 355 */
Jerome Coutant 0:c0f3bbab73d2 356 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
Jerome Coutant 0:c0f3bbab73d2 357 {
Jerome Coutant 0:c0f3bbab73d2 358 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
Jerome Coutant 0:c0f3bbab73d2 359 {
Jerome Coutant 0:c0f3bbab73d2 360 return SDRAM_ERROR;
Jerome Coutant 0:c0f3bbab73d2 361 }
Jerome Coutant 0:c0f3bbab73d2 362 else
Jerome Coutant 0:c0f3bbab73d2 363 {
Jerome Coutant 0:c0f3bbab73d2 364 return SDRAM_OK;
Jerome Coutant 0:c0f3bbab73d2 365 }
Jerome Coutant 0:c0f3bbab73d2 366 }
Jerome Coutant 0:c0f3bbab73d2 367
Jerome Coutant 0:c0f3bbab73d2 368 /**
Jerome Coutant 0:c0f3bbab73d2 369 * @brief Initializes SDRAM MSP.
Jerome Coutant 0:c0f3bbab73d2 370 * @param hsdram: SDRAM handle
Jerome Coutant 1:3e58f8a39705 371 * @param Params
Jerome Coutant 0:c0f3bbab73d2 372 * @retval None
Jerome Coutant 0:c0f3bbab73d2 373 */
Jerome Coutant 0:c0f3bbab73d2 374 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
Jerome Coutant 0:c0f3bbab73d2 375 {
Jerome Coutant 0:c0f3bbab73d2 376 static DMA_HandleTypeDef dma_handle;
Jerome Coutant 0:c0f3bbab73d2 377 GPIO_InitTypeDef gpio_init_structure;
Jerome Coutant 0:c0f3bbab73d2 378
Jerome Coutant 0:c0f3bbab73d2 379 /* Enable FMC clock */
Jerome Coutant 0:c0f3bbab73d2 380 __HAL_RCC_FMC_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 381
Jerome Coutant 0:c0f3bbab73d2 382 /* Enable chosen DMAx clock */
Jerome Coutant 0:c0f3bbab73d2 383 __DMAx_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 384
Jerome Coutant 0:c0f3bbab73d2 385 /* Enable GPIOs clock */
Jerome Coutant 0:c0f3bbab73d2 386 __HAL_RCC_GPIOD_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 387 __HAL_RCC_GPIOE_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 388 __HAL_RCC_GPIOF_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 389 __HAL_RCC_GPIOG_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 390 __HAL_RCC_GPIOH_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 391 __HAL_RCC_GPIOI_CLK_ENABLE();
Jerome Coutant 0:c0f3bbab73d2 392
Jerome Coutant 0:c0f3bbab73d2 393 /* Common GPIO configuration */
Jerome Coutant 0:c0f3bbab73d2 394 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
Jerome Coutant 0:c0f3bbab73d2 395 gpio_init_structure.Pull = GPIO_PULLUP;
Jerome Coutant 0:c0f3bbab73d2 396 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
Jerome Coutant 0:c0f3bbab73d2 397 gpio_init_structure.Alternate = GPIO_AF12_FMC;
Jerome Coutant 0:c0f3bbab73d2 398
Jerome Coutant 0:c0f3bbab73d2 399 /* GPIOD configuration */
Jerome Coutant 0:c0f3bbab73d2 400 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
Jerome Coutant 0:c0f3bbab73d2 401 GPIO_PIN_14 | GPIO_PIN_15;
Jerome Coutant 0:c0f3bbab73d2 402
Jerome Coutant 0:c0f3bbab73d2 403
Jerome Coutant 0:c0f3bbab73d2 404 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
Jerome Coutant 0:c0f3bbab73d2 405
Jerome Coutant 0:c0f3bbab73d2 406 /* GPIOE configuration */
Jerome Coutant 0:c0f3bbab73d2 407 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
Jerome Coutant 0:c0f3bbab73d2 408 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
Jerome Coutant 0:c0f3bbab73d2 409 GPIO_PIN_15;
Jerome Coutant 0:c0f3bbab73d2 410
Jerome Coutant 0:c0f3bbab73d2 411 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
Jerome Coutant 0:c0f3bbab73d2 412
Jerome Coutant 0:c0f3bbab73d2 413 /* GPIOF configuration */
Jerome Coutant 0:c0f3bbab73d2 414 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
Jerome Coutant 0:c0f3bbab73d2 415 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
Jerome Coutant 0:c0f3bbab73d2 416 GPIO_PIN_15;
Jerome Coutant 0:c0f3bbab73d2 417
Jerome Coutant 0:c0f3bbab73d2 418 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
Jerome Coutant 0:c0f3bbab73d2 419
Jerome Coutant 0:c0f3bbab73d2 420 /* GPIOG configuration */
Jerome Coutant 0:c0f3bbab73d2 421 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4|\
Jerome Coutant 0:c0f3bbab73d2 422 GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
Jerome Coutant 0:c0f3bbab73d2 423 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
Jerome Coutant 0:c0f3bbab73d2 424
Jerome Coutant 0:c0f3bbab73d2 425 /* GPIOH configuration */
Jerome Coutant 0:c0f3bbab73d2 426 gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\
Jerome Coutant 0:c0f3bbab73d2 427 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
Jerome Coutant 0:c0f3bbab73d2 428 GPIO_PIN_15;
Jerome Coutant 0:c0f3bbab73d2 429 HAL_GPIO_Init(GPIOH, &gpio_init_structure);
Jerome Coutant 0:c0f3bbab73d2 430
Jerome Coutant 0:c0f3bbab73d2 431 /* GPIOI configuration */
Jerome Coutant 0:c0f3bbab73d2 432 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
Jerome Coutant 0:c0f3bbab73d2 433 GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
Jerome Coutant 0:c0f3bbab73d2 434 HAL_GPIO_Init(GPIOI, &gpio_init_structure);
Jerome Coutant 0:c0f3bbab73d2 435
Jerome Coutant 0:c0f3bbab73d2 436 /* Configure common DMA parameters */
Jerome Coutant 0:c0f3bbab73d2 437 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
Jerome Coutant 0:c0f3bbab73d2 438 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
Jerome Coutant 0:c0f3bbab73d2 439 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
Jerome Coutant 0:c0f3bbab73d2 440 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
Jerome Coutant 0:c0f3bbab73d2 441 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
Jerome Coutant 0:c0f3bbab73d2 442 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
Jerome Coutant 0:c0f3bbab73d2 443 dma_handle.Init.Mode = DMA_NORMAL;
Jerome Coutant 0:c0f3bbab73d2 444 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
Jerome Coutant 0:c0f3bbab73d2 445 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
Jerome Coutant 0:c0f3bbab73d2 446 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
Jerome Coutant 0:c0f3bbab73d2 447 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
Jerome Coutant 0:c0f3bbab73d2 448 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
Jerome Coutant 0:c0f3bbab73d2 449
Jerome Coutant 0:c0f3bbab73d2 450 dma_handle.Instance = SDRAM_DMAx_STREAM;
Jerome Coutant 0:c0f3bbab73d2 451
Jerome Coutant 0:c0f3bbab73d2 452 /* Associate the DMA handle */
Jerome Coutant 0:c0f3bbab73d2 453 __HAL_LINKDMA(hsdram, hdma, dma_handle);
Jerome Coutant 0:c0f3bbab73d2 454
Jerome Coutant 0:c0f3bbab73d2 455 /* Deinitialize the stream for new transfer */
Jerome Coutant 0:c0f3bbab73d2 456 HAL_DMA_DeInit(&dma_handle);
Jerome Coutant 0:c0f3bbab73d2 457
Jerome Coutant 0:c0f3bbab73d2 458 /* Configure the DMA stream */
Jerome Coutant 0:c0f3bbab73d2 459 HAL_DMA_Init(&dma_handle);
Jerome Coutant 0:c0f3bbab73d2 460
Jerome Coutant 0:c0f3bbab73d2 461 /* NVIC configuration for DMA transfer complete interrupt */
Jerome Coutant 0:c0f3bbab73d2 462 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
Jerome Coutant 0:c0f3bbab73d2 463 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
Jerome Coutant 0:c0f3bbab73d2 464 }
Jerome Coutant 0:c0f3bbab73d2 465
Jerome Coutant 0:c0f3bbab73d2 466 /**
Jerome Coutant 0:c0f3bbab73d2 467 * @brief DeInitializes SDRAM MSP.
Jerome Coutant 0:c0f3bbab73d2 468 * @param hsdram: SDRAM handle
Jerome Coutant 1:3e58f8a39705 469 * @param Params
Jerome Coutant 0:c0f3bbab73d2 470 * @retval None
Jerome Coutant 0:c0f3bbab73d2 471 */
Jerome Coutant 0:c0f3bbab73d2 472 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
Jerome Coutant 0:c0f3bbab73d2 473 {
Jerome Coutant 0:c0f3bbab73d2 474 static DMA_HandleTypeDef dma_handle;
Jerome Coutant 0:c0f3bbab73d2 475
Jerome Coutant 0:c0f3bbab73d2 476 /* Disable NVIC configuration for DMA interrupt */
Jerome Coutant 0:c0f3bbab73d2 477 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
Jerome Coutant 0:c0f3bbab73d2 478
Jerome Coutant 0:c0f3bbab73d2 479 /* Deinitialize the stream for new transfer */
Jerome Coutant 0:c0f3bbab73d2 480 dma_handle.Instance = SDRAM_DMAx_STREAM;
Jerome Coutant 0:c0f3bbab73d2 481 HAL_DMA_DeInit(&dma_handle);
Jerome Coutant 0:c0f3bbab73d2 482
Jerome Coutant 0:c0f3bbab73d2 483 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
Jerome Coutant 0:c0f3bbab73d2 484 by surcharging this __weak function */
Jerome Coutant 0:c0f3bbab73d2 485 }
Jerome Coutant 0:c0f3bbab73d2 486
Jerome Coutant 0:c0f3bbab73d2 487 /**
Jerome Coutant 0:c0f3bbab73d2 488 * @}
Jerome Coutant 0:c0f3bbab73d2 489 */
Jerome Coutant 0:c0f3bbab73d2 490
Jerome Coutant 0:c0f3bbab73d2 491 /**
Jerome Coutant 0:c0f3bbab73d2 492 * @}
Jerome Coutant 0:c0f3bbab73d2 493 */
Jerome Coutant 0:c0f3bbab73d2 494
Jerome Coutant 0:c0f3bbab73d2 495 /**
Jerome Coutant 0:c0f3bbab73d2 496 * @}
Jerome Coutant 0:c0f3bbab73d2 497 */
Jerome Coutant 0:c0f3bbab73d2 498
Jerome Coutant 0:c0f3bbab73d2 499 /**
Jerome Coutant 0:c0f3bbab73d2 500 * @}
Jerome Coutant 0:c0f3bbab73d2 501 */
Jerome Coutant 0:c0f3bbab73d2 502
Jerome Coutant 0:c0f3bbab73d2 503 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/