n25q128a.h

00001 /**
00002   ******************************************************************************
00003   * @file    n25q128a.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the description of the N25Q128A QSPI memory.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */ 
00035 
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __N25Q128A_H
00038 #define __N25Q128A_H
00039 
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif 
00043 
00044 /* Includes ------------------------------------------------------------------*/
00045 
00046 /** @addtogroup BSP
00047   * @{
00048   */ 
00049 
00050 /** @addtogroup Components
00051   * @{
00052   */ 
00053   
00054 /** @addtogroup n25q128a
00055   * @{
00056   */
00057 
00058 /** @defgroup N25Q128A_Exported_Types
00059   * @{
00060   */
00061    
00062 /**
00063   * @}
00064   */ 
00065 
00066 /** @defgroup N25Q128A_Exported_Constants
00067   * @{
00068   */
00069    
00070 /** 
00071   * @brief  N25Q128A Configuration  
00072   */  
00073 #define N25Q128A_FLASH_SIZE                  0x1000000 /* 128 MBits => 16MBytes */
00074 #define N25Q128A_SECTOR_SIZE                 0x10000   /* 256 sectors of 64KBytes */
00075 #define N25Q128A_SUBSECTOR_SIZE              0x1000    /* 4096 subsectors of 4kBytes */
00076 #define N25Q128A_PAGE_SIZE                   0x100     /* 65536 pages of 256 bytes */
00077 
00078 #define N25Q128A_DUMMY_CYCLES_READ           8
00079 #define N25Q128A_DUMMY_CYCLES_READ_QUAD      10
00080 
00081 #define N25Q128A_BULK_ERASE_MAX_TIME         250000
00082 #define N25Q128A_SECTOR_ERASE_MAX_TIME       3000
00083 #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME    800
00084 
00085 /** 
00086   * @brief  N25Q128A Commands  
00087   */  
00088 /* Reset Operations */
00089 #define RESET_ENABLE_CMD                     0x66
00090 #define RESET_MEMORY_CMD                     0x99
00091 
00092 /* Identification Operations */
00093 #define READ_ID_CMD                          0x9E
00094 #define READ_ID_CMD2                         0x9F
00095 #define MULTIPLE_IO_READ_ID_CMD              0xAF
00096 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD    0x5A
00097 
00098 /* Read Operations */
00099 #define READ_CMD                             0x03
00100 #define FAST_READ_CMD                        0x0B
00101 #define DUAL_OUT_FAST_READ_CMD               0x3B
00102 #define DUAL_INOUT_FAST_READ_CMD             0xBB
00103 #define QUAD_OUT_FAST_READ_CMD               0x6B
00104 #define QUAD_INOUT_FAST_READ_CMD             0xEB
00105 
00106 /* Write Operations */
00107 #define WRITE_ENABLE_CMD                     0x06
00108 #define WRITE_DISABLE_CMD                    0x04
00109 
00110 /* Register Operations */
00111 #define READ_STATUS_REG_CMD                  0x05
00112 #define WRITE_STATUS_REG_CMD                 0x01
00113 
00114 #define READ_LOCK_REG_CMD                    0xE8
00115 #define WRITE_LOCK_REG_CMD                   0xE5
00116 
00117 #define READ_FLAG_STATUS_REG_CMD             0x70
00118 #define CLEAR_FLAG_STATUS_REG_CMD            0x50
00119 
00120 #define READ_NONVOL_CFG_REG_CMD              0xB5
00121 #define WRITE_NONVOL_CFG_REG_CMD             0xB1
00122 
00123 #define READ_VOL_CFG_REG_CMD                 0x85
00124 #define WRITE_VOL_CFG_REG_CMD                0x81
00125 
00126 #define READ_ENHANCED_VOL_CFG_REG_CMD        0x65
00127 #define WRITE_ENHANCED_VOL_CFG_REG_CMD       0x61
00128 
00129 /* Program Operations */
00130 #define PAGE_PROG_CMD                        0x02
00131 #define DUAL_IN_FAST_PROG_CMD                0xA2
00132 #define EXT_DUAL_IN_FAST_PROG_CMD            0xD2
00133 #define QUAD_IN_FAST_PROG_CMD                0x32
00134 #define EXT_QUAD_IN_FAST_PROG_CMD            0x12
00135 
00136 /* Erase Operations */
00137 #define SUBSECTOR_ERASE_CMD                  0x20
00138 #define SECTOR_ERASE_CMD                     0xD8
00139 #define BULK_ERASE_CMD                       0xC7
00140 
00141 #define PROG_ERASE_RESUME_CMD                0x7A
00142 #define PROG_ERASE_SUSPEND_CMD               0x75
00143 
00144 /* One-Time Programmable Operations */
00145 #define READ_OTP_ARRAY_CMD                   0x4B
00146 #define PROG_OTP_ARRAY_CMD                   0x42
00147 
00148 /** 
00149   * @brief  N25Q128A Registers  
00150   */ 
00151 /* Status Register */
00152 #define N25Q128A_SR_WIP                      ((uint8_t)0x01)    /*!< Write in progress */
00153 #define N25Q128A_SR_WREN                     ((uint8_t)0x02)    /*!< Write enable latch */
00154 #define N25Q128A_SR_BLOCKPR                  ((uint8_t)0x5C)    /*!< Block protected against program and erase operations */
00155 #define N25Q128A_SR_PRBOTTOM                 ((uint8_t)0x20)    /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
00156 #define N25Q128A_SR_SRWREN                   ((uint8_t)0x80)    /*!< Status register write enable/disable */
00157 
00158 /* Nonvolatile Configuration Register */
00159 #define N25Q128A_NVCR_LOCK                   ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */
00160 #define N25Q128A_NVCR_DUAL                   ((uint16_t)0x0004) /*!< Dual I/O protocol */
00161 #define N25Q128A_NVCR_QUAB                   ((uint16_t)0x0008) /*!< Quad I/O protocol */
00162 #define N25Q128A_NVCR_RH                     ((uint16_t)0x0010) /*!< Reset/hold */
00163 #define N25Q128A_NVCR_ODS                    ((uint16_t)0x01C0) /*!< Output driver strength */
00164 #define N25Q128A_NVCR_XIP                    ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
00165 #define N25Q128A_NVCR_NB_DUMMY               ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
00166 
00167 /* Volatile Configuration Register */
00168 #define N25Q128A_VCR_WRAP                    ((uint8_t)0x03)    /*!< Wrap */
00169 #define N25Q128A_VCR_XIP                     ((uint8_t)0x08)    /*!< XIP */
00170 #define N25Q128A_VCR_NB_DUMMY                ((uint8_t)0xF0)    /*!< Number of dummy clock cycles */
00171 
00172 /* Enhanced Volatile Configuration Register */
00173 #define N25Q128A_EVCR_ODS                    ((uint8_t)0x07)    /*!< Output driver strength */
00174 #define N25Q128A_EVCR_VPPA                   ((uint8_t)0x08)    /*!< Vpp accelerator */
00175 #define N25Q128A_EVCR_RH                     ((uint8_t)0x10)    /*!< Reset/hold */
00176 #define N25Q128A_EVCR_DUAL                   ((uint8_t)0x40)    /*!< Dual I/O protocol */
00177 #define N25Q128A_EVCR_QUAD                   ((uint8_t)0x80)    /*!< Quad I/O protocol */
00178 
00179 /* Flag Status Register */
00180 #define N25Q128A_FSR_PRERR                   ((uint8_t)0x02)    /*!< Protection error */
00181 #define N25Q128A_FSR_PGSUS                   ((uint8_t)0x04)    /*!< Program operation suspended */
00182 #define N25Q128A_FSR_VPPERR                  ((uint8_t)0x08)    /*!< Invalid voltage during program or erase */
00183 #define N25Q128A_FSR_PGERR                   ((uint8_t)0x10)    /*!< Program error */
00184 #define N25Q128A_FSR_ERERR                   ((uint8_t)0x20)    /*!< Erase error */
00185 #define N25Q128A_FSR_ERSUS                   ((uint8_t)0x40)    /*!< Erase operation suspended */
00186 #define N25Q128A_FSR_READY                   ((uint8_t)0x80)    /*!< Ready or command in progress */
00187 
00188 /**
00189   * @}
00190   */
00191   
00192 /** @defgroup N25Q128A_Exported_Functions
00193   * @{
00194   */ 
00195 /**
00196   * @}
00197   */ 
00198       
00199 /**
00200   * @}
00201   */ 
00202 
00203 /**
00204   * @}
00205   */ 
00206 
00207 /**
00208   * @}
00209   */
00210   
00211 #ifdef __cplusplus
00212 }
00213 #endif
00214 
00215 #endif /* __N25Q128A_H */
00216 
00217 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/