ST Expansion SW Team / X_NUCLEO_COMMON_SPI3W

Including SPI 3-wires class

Fork of X_NUCLEO_COMMON_SPI3W by Licio Mapelli

DevSPI3W/SPI3W.h@25:e4f6488865d1, 2017-08-31 (annotated)

Committer:
mapellil
Date:
Thu Aug 31 11:24:35 2017 +0200
Revision:
25:e4f6488865d1
Parent:
22:62b662a23496 
Modifications to support mbed-os pull req https://github.com/ARMmbed/mbed-os/pull/4975

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mapellil 22:62b662a23496 1 /* mbed Microcontroller Library
mapellil 22:62b662a23496 2 * Copyright (c) 2006-2015 ARM Limited
mapellil 22:62b662a23496 3 *
mapellil 22:62b662a23496 4 * Licensed under the Apache License, Version 2.0 (the "License");
mapellil 22:62b662a23496 5 * you may not use this file except in compliance with the License.
mapellil 22:62b662a23496 6 * You may obtain a copy of the License at
mapellil 22:62b662a23496 7 *
mapellil 22:62b662a23496 8 * http://www.apache.org/licenses/LICENSE-2.0
mapellil 22:62b662a23496 9 *
mapellil 22:62b662a23496 10 * Unless required by applicable law or agreed to in writing, software
mapellil 22:62b662a23496 11 * distributed under the License is distributed on an "AS IS" BASIS,
mapellil 22:62b662a23496 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mapellil 22:62b662a23496 13 * See the License for the specific language governing permissions and
mapellil 22:62b662a23496 14 * limitations under the License.
mapellil 22:62b662a23496 15 */
mapellil 22:62b662a23496 16 #ifndef MBED_SPI3W_H
mapellil 22:62b662a23496 17 #define MBED_SPI3W_H
mapellil 22:62b662a23496 18
mapellil 22:62b662a23496 19 #include "mbed.h"
mapellil 22:62b662a23496 20 #include "Component.h"
mapellil 22:62b662a23496 21 #include "SPI.h"
mapellil 22:62b662a23496 22
mapellil 22:62b662a23496 23 /** A SPI3W Master, used for communicating with SPI3W slave devices
mapellil 22:62b662a23496 24 *
mapellil 22:62b662a23496 25 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
mapellil 22:62b662a23496 26 *
mapellil 22:62b662a23496 27 * Most SPI devices will also require Chip Select and Reset signals. These
mapellil 22:62b662a23496 28 * can be controlled using <DigitalOut> pins
mapellil 22:62b662a23496 29 *
mapellil 22:62b662a23496 30 * @Note Synchronization level: Thread safe
mapellil 22:62b662a23496 31 *
mapellil 22:62b662a23496 32 * Example:
mapellil 22:62b662a23496 33 * @code
mapellil 22:62b662a23496 34 * // Send a byte to a SPI slave, and record the response
mapellil 22:62b662a23496 35 *
mapellil 22:62b662a23496 36 * #include "mbed.h"
mapellil 22:62b662a23496 37 *
mapellil 22:62b662a23496 38 * // hardware ssel (where applicable)
mapellil 22:62b662a23496 39 * //SPI device(p5, p7, p8); // mosi, sclk, ssel
mapellil 22:62b662a23496 40 *
mapellil 22:62b662a23496 41 * // software ssel
mapellil 22:62b662a23496 42 * SPI3W device(p5, p7); // mosi, sclk
mapellil 22:62b662a23496 43 * DigitalOut cs(p8); // ssel
mapellil 22:62b662a23496 44 *
mapellil 22:62b662a23496 45 * int main() {
mapellil 22:62b662a23496 46 * // hardware ssel (where applicable)
mapellil 22:62b662a23496 47 * //int response = device.write(0xFF);
mapellil 22:62b662a23496 48 *
mapellil 22:62b662a23496 49 * device.lock();
mapellil 22:62b662a23496 50 * // software ssel
mapellil 22:62b662a23496 51 * cs = 0;
mapellil 22:62b662a23496 52 * int response = device.spi3w_write(0xFF);
mapellil 22:62b662a23496 53 * cs = 1;
mapellil 22:62b662a23496 54 * device.unlock();
mapellil 22:62b662a23496 55 *
mapellil 22:62b662a23496 56 * }
mapellil 22:62b662a23496 57 * @endcode
mapellil 22:62b662a23496 58 */
mapellil 22:62b662a23496 59
mapellil 22:62b662a23496 60 class SPI3W : public SPI {
mapellil 22:62b662a23496 61
mapellil 22:62b662a23496 62 public:
mapellil 22:62b662a23496 63 SPI3W (PinName spi_sda, PinName spi_sdi, PinName spi_clk);
mapellil 22:62b662a23496 64
mapellil 22:62b662a23496 65 uint8_t spi3w_read (uint8_t * pBuffer, DigitalOut * _cs_pin, uint8_t RegisterAddr, uint16_t NumByteToRead);
mapellil 22:62b662a23496 66 uint8_t spi3w_write(uint8_t * pBuffer, DigitalOut * _cs_pin, uint8_t RegisterAddr, uint16_t NumByteToWrite);
mapellil 22:62b662a23496 67
mapellil 22:62b662a23496 68 private:
mapellil 22:62b662a23496 69 uint8_t Sensor_IO_Read( DigitalOut * _cs_pin, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead );
mapellil 22:62b662a23496 70 uint8_t Sensor_IO_SPI_Read( DigitalOut * _cs_pin, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead );
mapellil 22:62b662a23496 71
mapellil 22:62b662a23496 72 uint8_t Sensor_IO_Write( DigitalOut * _cs_pin, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite );
mapellil 22:62b662a23496 73 uint8_t Sensor_IO_SPI_Write( DigitalOut * _cs_pin, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite );
mapellil 22:62b662a23496 74
mapellil 22:62b662a23496 75 uint8_t Sensor_IO_SPI_CS_Disable(DigitalOut * _cs_pin);
mapellil 22:62b662a23496 76 uint8_t Sensor_IO_SPI_CS_Enable(DigitalOut * _cs_pin);
mapellil 22:62b662a23496 77
mapellil 22:62b662a23496 78 public:
mapellil 22:62b662a23496 79 virtual ~SPI3W() {
mapellil 22:62b662a23496 80 }
mapellil 22:62b662a23496 81
mapellil 22:62b662a23496 82 };
mapellil 22:62b662a23496 83
mapellil 22:62b662a23496 84 #endif
mapellil 22:62b662a23496 85
mapellil 22:62b662a23496 86 /** @}*/