ST Expansion SW Team / X_NUCLEO_COMMON_SPI3W

Including SPI 3-wires class

Fork of X_NUCLEO_COMMON_SPI3W by Licio Mapelli

DevSPI/DevSPI.h@10:da29b5403ca1, 2015-10-16 (annotated)

Committer:
davide.aliprandi@st.com
Date:
Fri Oct 16 14:13:27 2015 +0200
Revision:
10:da29b5403ca1
Parent:
9:1f35e8bf427b
Child:
11:165bd6bc00ea
Description of "DevSPI" class updated.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
davide aliprandi <> 9:1f35e8bf427b 1 /**
davide aliprandi <> 9:1f35e8bf427b 2 ******************************************************************************
davide aliprandi <> 9:1f35e8bf427b 3 * @file DevSPI.h
davide aliprandi <> 9:1f35e8bf427b 4 * @author AST / Software Platforms and Cloud
davide aliprandi <> 9:1f35e8bf427b 5 * @version V0.0.1
davide aliprandi <> 9:1f35e8bf427b 6 * @date September 24th, 2015
davide aliprandi <> 9:1f35e8bf427b 7 * @brief Header file for a special SPI class DevSPI which provides some
davide aliprandi <> 9:1f35e8bf427b 8 * helper function for on-board communication.
davide aliprandi <> 9:1f35e8bf427b 9 ******************************************************************************
davide aliprandi <> 9:1f35e8bf427b 10 * @attention
davide aliprandi <> 9:1f35e8bf427b 11 *
davide aliprandi <> 9:1f35e8bf427b 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
davide aliprandi <> 9:1f35e8bf427b 13 *
davide aliprandi <> 9:1f35e8bf427b 14 * Redistribution and use in source and binary forms, with or without modification,
davide aliprandi <> 9:1f35e8bf427b 15 * are permitted provided that the following conditions are met:
davide aliprandi <> 9:1f35e8bf427b 16 * 1. Redistributions of source code must retain the above copyright notice,
davide aliprandi <> 9:1f35e8bf427b 17 * this list of conditions and the following disclaimer.
davide aliprandi <> 9:1f35e8bf427b 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
davide aliprandi <> 9:1f35e8bf427b 19 * this list of conditions and the following disclaimer in the documentation
davide aliprandi <> 9:1f35e8bf427b 20 * and/or other materials provided with the distribution.
davide aliprandi <> 9:1f35e8bf427b 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
davide aliprandi <> 9:1f35e8bf427b 22 * may be used to endorse or promote products derived from this software
davide aliprandi <> 9:1f35e8bf427b 23 * without specific prior written permission.
davide aliprandi <> 9:1f35e8bf427b 24 *
davide aliprandi <> 9:1f35e8bf427b 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
davide aliprandi <> 9:1f35e8bf427b 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
davide aliprandi <> 9:1f35e8bf427b 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
davide aliprandi <> 9:1f35e8bf427b 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
davide aliprandi <> 9:1f35e8bf427b 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
davide aliprandi <> 9:1f35e8bf427b 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
davide aliprandi <> 9:1f35e8bf427b 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
davide aliprandi <> 9:1f35e8bf427b 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
davide aliprandi <> 9:1f35e8bf427b 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
davide aliprandi <> 9:1f35e8bf427b 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
davide aliprandi <> 9:1f35e8bf427b 35 *
davide aliprandi <> 9:1f35e8bf427b 36 ******************************************************************************
davide aliprandi <> 9:1f35e8bf427b 37 */
davide aliprandi <> 9:1f35e8bf427b 38
davide aliprandi <> 9:1f35e8bf427b 39 /* Define to prevent from recursive inclusion --------------------------------*/
davide aliprandi <> 9:1f35e8bf427b 40 #ifndef __DEV_SPI_H
davide aliprandi <> 9:1f35e8bf427b 41 #define __DEV_SPI_H
davide aliprandi <> 9:1f35e8bf427b 42
davide aliprandi <> 9:1f35e8bf427b 43 /* Includes ------------------------------------------------------------------*/
davide aliprandi <> 9:1f35e8bf427b 44 #include "mbed.h"
davide aliprandi <> 9:1f35e8bf427b 45
davide aliprandi <> 9:1f35e8bf427b 46 /* Classes -------------------------------------------------------------------*/
davide.aliprandi@st.com 10:da29b5403ca1 47 /** Helper class DevSPI providing functions for SPI communication common for a
davide.aliprandi@st.com 10:da29b5403ca1 48 * series of SPI devices.
davide aliprandi <> 9:1f35e8bf427b 49 */
davide aliprandi <> 9:1f35e8bf427b 50 class DevSPI : public SPI
davide aliprandi <> 9:1f35e8bf427b 51 {
davide aliprandi <> 9:1f35e8bf427b 52 public:
davide aliprandi <> 9:1f35e8bf427b 53 /*
davide aliprandi <> 9:1f35e8bf427b 54 * Create a DevSPI interface.
davide aliprandi <> 9:1f35e8bf427b 55 * @param mosi pin name of the MOSI pin of the SPI device to be used for communication.
davide aliprandi <> 9:1f35e8bf427b 56 * @param miso pin name of the MISO pin of the SPI device to be used for communication.
davide aliprandi <> 9:1f35e8bf427b 57 * @param sclk pin name of the SCLK pin of the SPI device to be used for communication.
davide aliprandi <> 9:1f35e8bf427b 58 */
davide aliprandi <> 9:1f35e8bf427b 59 DevSPI(PinName mosi, PinName miso, PinName sclk) : SPI(mosi, miso, sclk)
davide aliprandi <> 9:1f35e8bf427b 60 {
davide aliprandi <> 9:1f35e8bf427b 61 bits = 9;
davide aliprandi <> 9:1f35e8bf427b 62 mode = 0;
davide aliprandi <> 9:1f35e8bf427b 63 frequency_hz = 1E6;
davide aliprandi <> 9:1f35e8bf427b 64 setup_done = false;
davide aliprandi <> 9:1f35e8bf427b 65 }
davide aliprandi <> 9:1f35e8bf427b 66
davide aliprandi <> 9:1f35e8bf427b 67 /*
davide aliprandi <> 9:1f35e8bf427b 68 * Setup the spi.
davide aliprandi <> 9:1f35e8bf427b 69 * Typically:
davide aliprandi <> 9:1f35e8bf427b 70 * + 8 bit data;
davide aliprandi <> 9:1f35e8bf427b 71 * + high steady state clock;
davide aliprandi <> 9:1f35e8bf427b 72 * + second edge capture;
davide aliprandi <> 9:1f35e8bf427b 73 * + 1MHz clock rate.
davide aliprandi <> 9:1f35e8bf427b 74 *
davide aliprandi <> 9:1f35e8bf427b 75 * @param bits Number of bits per SPI frame (4 - 16)
davide aliprandi <> 9:1f35e8bf427b 76 * @param mode Clock polarity and phase mode (0 - 3)
davide aliprandi <> 9:1f35e8bf427b 77 * @param frequency_hz SCLK frequency in hz (default = 1MHz)
davide aliprandi <> 9:1f35e8bf427b 78 *
davide aliprandi <> 9:1f35e8bf427b 79 * @code
davide aliprandi <> 9:1f35e8bf427b 80 * mode | POL PHA
davide aliprandi <> 9:1f35e8bf427b 81 * -----+--------
davide aliprandi <> 9:1f35e8bf427b 82 * 0 | 0 0
davide aliprandi <> 9:1f35e8bf427b 83 * 1 | 0 1
davide aliprandi <> 9:1f35e8bf427b 84 * 2 | 1 0
davide aliprandi <> 9:1f35e8bf427b 85 * 3 | 1 1
davide aliprandi <> 9:1f35e8bf427b 86 * @endcode
davide aliprandi <> 9:1f35e8bf427b 87 */
davide aliprandi <> 9:1f35e8bf427b 88 void setup(int bits, int mode = 0, int frequency_hz = 1E6)
davide aliprandi <> 9:1f35e8bf427b 89 {
davide aliprandi <> 9:1f35e8bf427b 90 format(bits, mode);
davide aliprandi <> 9:1f35e8bf427b 91 frequency(frequency_hz);
davide aliprandi <> 9:1f35e8bf427b 92 setup_done = true;
davide aliprandi <> 9:1f35e8bf427b 93 }
davide aliprandi <> 9:1f35e8bf427b 94
davide aliprandi <> 9:1f35e8bf427b 95 /**
davide aliprandi <> 9:1f35e8bf427b 96 * @brief Writes a buffer to the SPI peripheral device.
davide aliprandi <> 9:1f35e8bf427b 97 * @param[in] pBuffer pointer to the buffer of data to send.
davide aliprandi <> 9:1f35e8bf427b 98 * @param[in] ssel GPIO of the SSEL pin of the SPI device to be used for communication.
davide aliprandi <> 9:1f35e8bf427b 99 * @param[in] NumBytesToWrite number of bytes to write.
davide aliprandi <> 9:1f35e8bf427b 100 * @retval 0 if ok.
davide aliprandi <> 9:1f35e8bf427b 101 * @note When using the SPI in Interrupt-mode, remember to disable interrupts
davide aliprandi <> 9:1f35e8bf427b 102 * before calling this function and to enable them again after.
davide aliprandi <> 9:1f35e8bf427b 103 */
davide aliprandi <> 9:1f35e8bf427b 104 int spi_write(uint8_t* pBuffer, DigitalOut ssel, uint16_t NumBytesToWrite)
davide aliprandi <> 9:1f35e8bf427b 105 {
davide aliprandi <> 9:1f35e8bf427b 106 /* Setup. */
davide aliprandi <> 9:1f35e8bf427b 107 if (!setup_done)
davide aliprandi <> 9:1f35e8bf427b 108 {
davide aliprandi <> 9:1f35e8bf427b 109 ssel = 1;
davide aliprandi <> 9:1f35e8bf427b 110 setup(8, 3, 1E6);
davide aliprandi <> 9:1f35e8bf427b 111 setup_done = true;
davide aliprandi <> 9:1f35e8bf427b 112 }
davide aliprandi <> 9:1f35e8bf427b 113
davide aliprandi <> 9:1f35e8bf427b 114 /* Select the chip. */
davide aliprandi <> 9:1f35e8bf427b 115 ssel = 0;
davide aliprandi <> 9:1f35e8bf427b 116
davide aliprandi <> 9:1f35e8bf427b 117 /* Write data. */
davide aliprandi <> 9:1f35e8bf427b 118 for (int i = 0; i < NumBytesToWrite; i++)
davide aliprandi <> 9:1f35e8bf427b 119 write(pBuffer[i]);
davide aliprandi <> 9:1f35e8bf427b 120
davide aliprandi <> 9:1f35e8bf427b 121 /* Unselect the chip. */
davide aliprandi <> 9:1f35e8bf427b 122 ssel = 1;
davide aliprandi <> 9:1f35e8bf427b 123
davide aliprandi <> 9:1f35e8bf427b 124 return 0;
davide aliprandi <> 9:1f35e8bf427b 125 }
davide aliprandi <> 9:1f35e8bf427b 126
davide aliprandi <> 9:1f35e8bf427b 127 /**
davide aliprandi <> 9:1f35e8bf427b 128 * @brief Reads a buffer from the SPI peripheral device.
davide aliprandi <> 9:1f35e8bf427b 129 * @param[out] pBuffer pointer to the buffer to read data into.
davide aliprandi <> 9:1f35e8bf427b 130 * @param[in] ssel GPIO of the SSEL pin of the SPI device to be used for communication.
davide aliprandi <> 9:1f35e8bf427b 131 * @param[in] NumBytesToRead number of bytes to read.
davide aliprandi <> 9:1f35e8bf427b 132 * @retval 0 if ok.
davide aliprandi <> 9:1f35e8bf427b 133 * @note When using the SPI in Interrupt-mode, remember to disable interrupts
davide aliprandi <> 9:1f35e8bf427b 134 * before calling this function and to enable them again after.
davide aliprandi <> 9:1f35e8bf427b 135 */
davide aliprandi <> 9:1f35e8bf427b 136 int spi_read(uint8_t* pBuffer, DigitalOut ssel, uint16_t NumBytesToRead)
davide aliprandi <> 9:1f35e8bf427b 137 {
davide aliprandi <> 9:1f35e8bf427b 138 /* Setup. */
davide aliprandi <> 9:1f35e8bf427b 139 if (!setup_done)
davide aliprandi <> 9:1f35e8bf427b 140 {
davide aliprandi <> 9:1f35e8bf427b 141 ssel = 1;
davide aliprandi <> 9:1f35e8bf427b 142 setup(8, 3, 1E6);
davide aliprandi <> 9:1f35e8bf427b 143 setup_done = true;
davide aliprandi <> 9:1f35e8bf427b 144 }
davide aliprandi <> 9:1f35e8bf427b 145
davide aliprandi <> 9:1f35e8bf427b 146 /* Select the chip. */
davide aliprandi <> 9:1f35e8bf427b 147 ssel = 0;
davide aliprandi <> 9:1f35e8bf427b 148
davide aliprandi <> 9:1f35e8bf427b 149 /* Read data. */
davide aliprandi <> 9:1f35e8bf427b 150 for (int i = 0; i < NumBytesToRead; i++)
davide aliprandi <> 9:1f35e8bf427b 151 pBuffer[i] = write(0x00);
davide aliprandi <> 9:1f35e8bf427b 152
davide aliprandi <> 9:1f35e8bf427b 153 /* Unselect the chip. */
davide aliprandi <> 9:1f35e8bf427b 154 ssel = 1;
davide aliprandi <> 9:1f35e8bf427b 155
davide aliprandi <> 9:1f35e8bf427b 156 return 0;
davide aliprandi <> 9:1f35e8bf427b 157 }
davide aliprandi <> 9:1f35e8bf427b 158
davide aliprandi <> 9:1f35e8bf427b 159 /**
davide aliprandi <> 9:1f35e8bf427b 160 * @brief Reads and write a buffer from/to the SPI peripheral device at the same time.
davide aliprandi <> 9:1f35e8bf427b 161 * @param[out] pBufferToRead pointer to the buffer to read data into.
davide aliprandi <> 9:1f35e8bf427b 162 * @param[in] pBufferToWrite pointer to the buffer of data to send.
davide aliprandi <> 9:1f35e8bf427b 163 * @param[in] ssel GPIO of the SSEL pin of the SPI device to be used for communication.
davide aliprandi <> 9:1f35e8bf427b 164 * @param[in] NumBytes number of bytes to read and write.
davide aliprandi <> 9:1f35e8bf427b 165 * @retval 0 if ok.
davide aliprandi <> 9:1f35e8bf427b 166 * @note When using the SPI in Interrupt-mode, remember to disable interrupts
davide aliprandi <> 9:1f35e8bf427b 167 * before calling this function and to enable them again after.
davide aliprandi <> 9:1f35e8bf427b 168 */
davide aliprandi <> 9:1f35e8bf427b 169 int spi_read_write(uint8_t* pBufferToRead, uint8_t* pBufferToWrite, DigitalOut ssel, uint16_t NumBytes)
davide aliprandi <> 9:1f35e8bf427b 170 {
davide aliprandi <> 9:1f35e8bf427b 171 /* Setup. */
davide aliprandi <> 9:1f35e8bf427b 172 if (!setup_done)
davide aliprandi <> 9:1f35e8bf427b 173 {
davide aliprandi <> 9:1f35e8bf427b 174 ssel = 1;
davide aliprandi <> 9:1f35e8bf427b 175 setup(8, 3, 1E6);
davide aliprandi <> 9:1f35e8bf427b 176 setup_done = true;
davide aliprandi <> 9:1f35e8bf427b 177 }
davide aliprandi <> 9:1f35e8bf427b 178
davide aliprandi <> 9:1f35e8bf427b 179 /* Select the chip. */
davide aliprandi <> 9:1f35e8bf427b 180 ssel = 0;
davide aliprandi <> 9:1f35e8bf427b 181
davide aliprandi <> 9:1f35e8bf427b 182 /* Read and write data at the same time. */
davide aliprandi <> 9:1f35e8bf427b 183 for (int i = 0; i < NumBytes; i++)
davide aliprandi <> 9:1f35e8bf427b 184 pBufferToRead[i] = write(pBufferToWrite[i]);
davide aliprandi <> 9:1f35e8bf427b 185
davide aliprandi <> 9:1f35e8bf427b 186 /* Unselect the chip. */
davide aliprandi <> 9:1f35e8bf427b 187 ssel = 1;
davide aliprandi <> 9:1f35e8bf427b 188
davide aliprandi <> 9:1f35e8bf427b 189 return 0;
davide aliprandi <> 9:1f35e8bf427b 190 }
davide aliprandi <> 9:1f35e8bf427b 191
davide aliprandi <> 9:1f35e8bf427b 192 protected:
davide aliprandi <> 9:1f35e8bf427b 193 bool setup_done;
davide aliprandi <> 9:1f35e8bf427b 194 int bits;
davide aliprandi <> 9:1f35e8bf427b 195 int mode;
davide aliprandi <> 9:1f35e8bf427b 196 int frequency_hz;
davide aliprandi <> 9:1f35e8bf427b 197 };
davide aliprandi <> 9:1f35e8bf427b 198
davide aliprandi <> 9:1f35e8bf427b 199 #endif /* __DEV_SPI_H */