ST Expansion SW Team / VL53L1CB

The VL53L1CB proximity sensor, based on ST’s FlightSense™, Time-of-Flight technology.

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Dependents:   VL53L1CB_noshield_1sensor_polls_auton VL53L1CB_noshield_1sensor_interrupt_auton X_NUCLEO_53L1A2

Based on VL53L1 library, this is a library for the VL53L1CB ToF chip.

inc/vl53l1_ll_def.h@0:3ac96e360672, 2020-11-06 (annotated)

Committer:
charlesmn
Date:
Fri Nov 06 10:06:37 2020 +0000
Revision:
0:3ac96e360672
Child:
7:1add29d51e72
Library for ST Vl53L1A1 time of flight sensor.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
charlesmn 0:3ac96e360672 1
charlesmn 0:3ac96e360672 2 /*******************************************************************************
charlesmn 0:3ac96e360672 3 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
charlesmn 0:3ac96e360672 4
charlesmn 0:3ac96e360672 5 This file is part of VL53L1 Core and is dual licensed,
charlesmn 0:3ac96e360672 6 either 'STMicroelectronics
charlesmn 0:3ac96e360672 7 Proprietary license'
charlesmn 0:3ac96e360672 8 or 'BSD 3-clause "New" or "Revised" License' , at your option.
charlesmn 0:3ac96e360672 9
charlesmn 0:3ac96e360672 10 ********************************************************************************
charlesmn 0:3ac96e360672 11
charlesmn 0:3ac96e360672 12 'STMicroelectronics Proprietary license'
charlesmn 0:3ac96e360672 13
charlesmn 0:3ac96e360672 14 ********************************************************************************
charlesmn 0:3ac96e360672 15
charlesmn 0:3ac96e360672 16 License terms: STMicroelectronics Proprietary in accordance with licensing
charlesmn 0:3ac96e360672 17 terms at www.st.com/sla0081
charlesmn 0:3ac96e360672 18
charlesmn 0:3ac96e360672 19 STMicroelectronics confidential
charlesmn 0:3ac96e360672 20 Reproduction and Communication of this document is strictly prohibited unless
charlesmn 0:3ac96e360672 21 specifically authorized in writing by STMicroelectronics.
charlesmn 0:3ac96e360672 22
charlesmn 0:3ac96e360672 23
charlesmn 0:3ac96e360672 24 ********************************************************************************
charlesmn 0:3ac96e360672 25
charlesmn 0:3ac96e360672 26 Alternatively, VL53L1 Core may be distributed under the terms of
charlesmn 0:3ac96e360672 27 'BSD 3-clause "New" or "Revised" License', in which case the following
charlesmn 0:3ac96e360672 28 provisions apply instead of the ones
charlesmn 0:3ac96e360672 29 mentioned above :
charlesmn 0:3ac96e360672 30
charlesmn 0:3ac96e360672 31 ********************************************************************************
charlesmn 0:3ac96e360672 32
charlesmn 0:3ac96e360672 33 License terms: BSD 3-clause "New" or "Revised" License.
charlesmn 0:3ac96e360672 34
charlesmn 0:3ac96e360672 35 Redistribution and use in source and binary forms, with or without
charlesmn 0:3ac96e360672 36 modification, are permitted provided that the following conditions are met:
charlesmn 0:3ac96e360672 37
charlesmn 0:3ac96e360672 38 1. Redistributions of source code must retain the above copyright notice, this
charlesmn 0:3ac96e360672 39 list of conditions and the following disclaimer.
charlesmn 0:3ac96e360672 40
charlesmn 0:3ac96e360672 41 2. Redistributions in binary form must reproduce the above copyright notice,
charlesmn 0:3ac96e360672 42 this list of conditions and the following disclaimer in the documentation
charlesmn 0:3ac96e360672 43 and/or other materials provided with the distribution.
charlesmn 0:3ac96e360672 44
charlesmn 0:3ac96e360672 45 3. Neither the name of the copyright holder nor the names of its contributors
charlesmn 0:3ac96e360672 46 may be used to endorse or promote products derived from this software
charlesmn 0:3ac96e360672 47 without specific prior written permission.
charlesmn 0:3ac96e360672 48
charlesmn 0:3ac96e360672 49 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
charlesmn 0:3ac96e360672 50 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
charlesmn 0:3ac96e360672 51 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
charlesmn 0:3ac96e360672 52 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
charlesmn 0:3ac96e360672 53 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
charlesmn 0:3ac96e360672 54 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
charlesmn 0:3ac96e360672 55 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
charlesmn 0:3ac96e360672 56 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
charlesmn 0:3ac96e360672 57 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
charlesmn 0:3ac96e360672 58 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
charlesmn 0:3ac96e360672 59
charlesmn 0:3ac96e360672 60
charlesmn 0:3ac96e360672 61 ********************************************************************************
charlesmn 0:3ac96e360672 62
charlesmn 0:3ac96e360672 63 */
charlesmn 0:3ac96e360672 64
charlesmn 0:3ac96e360672 65
charlesmn 0:3ac96e360672 66
charlesmn 0:3ac96e360672 67
charlesmn 0:3ac96e360672 68
charlesmn 0:3ac96e360672 69 #ifndef _VL53L1_LL_DEF_H_
charlesmn 0:3ac96e360672 70 #define _VL53L1_LL_DEF_H_
charlesmn 0:3ac96e360672 71
charlesmn 0:3ac96e360672 72 #include "vl53l1_error_codes.h"
charlesmn 0:3ac96e360672 73 #include "vl53l1_register_structs.h"
charlesmn 0:3ac96e360672 74 #include "vl53l1_platform_user_config.h"
charlesmn 0:3ac96e360672 75 #include "vl53l1_platform_user_defines.h"
charlesmn 0:3ac96e360672 76 #include "vl53l1_hist_structs.h"
charlesmn 0:3ac96e360672 77 #include "vl53l1_dmax_structs.h"
charlesmn 0:3ac96e360672 78 #include "vl53l1_error_exceptions.h"
charlesmn 0:3ac96e360672 79
charlesmn 0:3ac96e360672 80 #ifdef __cplusplus
charlesmn 0:3ac96e360672 81 extern "C" {
charlesmn 0:3ac96e360672 82 #endif
charlesmn 0:3ac96e360672 83
charlesmn 0:3ac96e360672 84
charlesmn 0:3ac96e360672 85
charlesmn 0:3ac96e360672 86
charlesmn 0:3ac96e360672 87 #define VL53L1_LL_API_IMPLEMENTATION_VER_MAJOR 1
charlesmn 0:3ac96e360672 88
charlesmn 0:3ac96e360672 89 #define VL53L1_LL_API_IMPLEMENTATION_VER_MINOR 1
charlesmn 0:3ac96e360672 90
charlesmn 0:3ac96e360672 91 #define VL53L1_LL_API_IMPLEMENTATION_VER_SUB 48
charlesmn 0:3ac96e360672 92
charlesmn 0:3ac96e360672 93 #define VL53L1_LL_API_IMPLEMENTATION_VER_REVISION 12224
charlesmn 0:3ac96e360672 94
charlesmn 0:3ac96e360672 95 #define VL53L1_LL_API_IMPLEMENTATION_VER_STRING "1.1.48.12224"
charlesmn 0:3ac96e360672 96
charlesmn 0:3ac96e360672 97
charlesmn 0:3ac96e360672 98 #define VL53L1_FIRMWARE_VER_MINIMUM 398
charlesmn 0:3ac96e360672 99 #define VL53L1_FIRMWARE_VER_MAXIMUM 400
charlesmn 0:3ac96e360672 100
charlesmn 0:3ac96e360672 101
charlesmn 0:3ac96e360672 102
charlesmn 0:3ac96e360672 103
charlesmn 0:3ac96e360672 104 #define VL53L1_LL_CALIBRATION_DATA_STRUCT_VERSION 0xECAB0102
charlesmn 0:3ac96e360672 105
charlesmn 0:3ac96e360672 106
charlesmn 0:3ac96e360672 107
charlesmn 0:3ac96e360672 108
charlesmn 0:3ac96e360672 109 #define VL53L1_LL_ZONE_CALIBRATION_DATA_STRUCT_VERSION 0xECAE0101
charlesmn 0:3ac96e360672 110
charlesmn 0:3ac96e360672 111
charlesmn 0:3ac96e360672 112
charlesmn 0:3ac96e360672 113
charlesmn 0:3ac96e360672 114
charlesmn 0:3ac96e360672 115 #define VL53L1_BIN_REC_SIZE 6
charlesmn 0:3ac96e360672 116
charlesmn 0:3ac96e360672 117 #define VL53L1_TIMING_CONF_A_B_SIZE 2
charlesmn 0:3ac96e360672 118
charlesmn 0:3ac96e360672 119 #define VL53L1_FRAME_WAIT_EVENT 6
charlesmn 0:3ac96e360672 120
charlesmn 0:3ac96e360672 121
charlesmn 0:3ac96e360672 122
charlesmn 0:3ac96e360672 123 #define VL53L1_MAX_XTALK_RANGE_RESULTS 5
charlesmn 0:3ac96e360672 124
charlesmn 0:3ac96e360672 125
charlesmn 0:3ac96e360672 126 #define VL53L1_MAX_OFFSET_RANGE_RESULTS 3
charlesmn 0:3ac96e360672 127
charlesmn 0:3ac96e360672 128
charlesmn 0:3ac96e360672 129 #define VL53L1_NVM_MAX_FMT_RANGE_DATA 4
charlesmn 0:3ac96e360672 130
charlesmn 0:3ac96e360672 131
charlesmn 0:3ac96e360672 132 #define VL53L1_NVM_PEAK_RATE_MAP_SAMPLES 25
charlesmn 0:3ac96e360672 133
charlesmn 0:3ac96e360672 134 #define VL53L1_NVM_PEAK_RATE_MAP_WIDTH 5
charlesmn 0:3ac96e360672 135
charlesmn 0:3ac96e360672 136 #define VL53L1_NVM_PEAK_RATE_MAP_HEIGHT 5
charlesmn 0:3ac96e360672 137
charlesmn 0:3ac96e360672 138
charlesmn 0:3ac96e360672 139
charlesmn 0:3ac96e360672 140
charlesmn 0:3ac96e360672 141 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_OLD ((VL53L1_Error) - 80)
charlesmn 0:3ac96e360672 142
charlesmn 0:3ac96e360672 143 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_NEW ((VL53L1_Error) - 85)
charlesmn 0:3ac96e360672 144
charlesmn 0:3ac96e360672 145 #define VL53L1_ERROR_UNIT_TEST_FAIL ((VL53L1_Error) - 90)
charlesmn 0:3ac96e360672 146
charlesmn 0:3ac96e360672 147 #define VL53L1_ERROR_FILE_READ_FAIL ((VL53L1_Error) - 95)
charlesmn 0:3ac96e360672 148
charlesmn 0:3ac96e360672 149 #define VL53L1_ERROR_FILE_WRITE_FAIL ((VL53L1_Error) - 96)
charlesmn 0:3ac96e360672 150
charlesmn 0:3ac96e360672 151
charlesmn 0:3ac96e360672 152
charlesmn 0:3ac96e360672 153
charlesmn 0:3ac96e360672 154
charlesmn 0:3ac96e360672 155
charlesmn 0:3ac96e360672 156 typedef struct {
charlesmn 0:3ac96e360672 157 uint32_t ll_revision;
charlesmn 0:3ac96e360672 158 uint8_t ll_major;
charlesmn 0:3ac96e360672 159 uint8_t ll_minor;
charlesmn 0:3ac96e360672 160 uint8_t ll_build;
charlesmn 0:3ac96e360672 161 } VL53L1_ll_version_t;
charlesmn 0:3ac96e360672 162
charlesmn 0:3ac96e360672 163
charlesmn 0:3ac96e360672 164
charlesmn 0:3ac96e360672 165
charlesmn 0:3ac96e360672 166 typedef struct {
charlesmn 0:3ac96e360672 167
charlesmn 0:3ac96e360672 168 uint8_t device_test_mode;
charlesmn 0:3ac96e360672 169 uint8_t VL53L1_p_009;
charlesmn 0:3ac96e360672 170 uint32_t timeout_us;
charlesmn 0:3ac96e360672 171 uint16_t target_count_rate_mcps;
charlesmn 0:3ac96e360672 172
charlesmn 0:3ac96e360672 173 uint16_t min_count_rate_limit_mcps;
charlesmn 0:3ac96e360672 174
charlesmn 0:3ac96e360672 175 uint16_t max_count_rate_limit_mcps;
charlesmn 0:3ac96e360672 176
charlesmn 0:3ac96e360672 177
charlesmn 0:3ac96e360672 178 } VL53L1_refspadchar_config_t;
charlesmn 0:3ac96e360672 179
charlesmn 0:3ac96e360672 180
charlesmn 0:3ac96e360672 181
charlesmn 0:3ac96e360672 182
charlesmn 0:3ac96e360672 183 typedef struct {
charlesmn 0:3ac96e360672 184
charlesmn 0:3ac96e360672 185 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 186
charlesmn 0:3ac96e360672 187 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 188
charlesmn 0:3ac96e360672 189 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 190
charlesmn 0:3ac96e360672 191 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 192
charlesmn 0:3ac96e360672 193 uint8_t num_of_samples;
charlesmn 0:3ac96e360672 194
charlesmn 0:3ac96e360672 195 int16_t algo__crosstalk_extract_min_valid_range_mm;
charlesmn 0:3ac96e360672 196
charlesmn 0:3ac96e360672 197 int16_t algo__crosstalk_extract_max_valid_range_mm;
charlesmn 0:3ac96e360672 198
charlesmn 0:3ac96e360672 199 uint16_t algo__crosstalk_extract_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 200
charlesmn 0:3ac96e360672 201 uint16_t algo__crosstalk_extract_max_sigma_mm;
charlesmn 0:3ac96e360672 202
charlesmn 0:3ac96e360672 203
charlesmn 0:3ac96e360672 204 } VL53L1_xtalkextract_config_t;
charlesmn 0:3ac96e360672 205
charlesmn 0:3ac96e360672 206
charlesmn 0:3ac96e360672 207
charlesmn 0:3ac96e360672 208
charlesmn 0:3ac96e360672 209 typedef struct {
charlesmn 0:3ac96e360672 210
charlesmn 0:3ac96e360672 211 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 212
charlesmn 0:3ac96e360672 213 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 214
charlesmn 0:3ac96e360672 215 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 216
charlesmn 0:3ac96e360672 217 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 218
charlesmn 0:3ac96e360672 219 uint8_t pre_num_of_samples;
charlesmn 0:3ac96e360672 220
charlesmn 0:3ac96e360672 221 uint8_t mm1_num_of_samples;
charlesmn 0:3ac96e360672 222
charlesmn 0:3ac96e360672 223 uint8_t mm2_num_of_samples;
charlesmn 0:3ac96e360672 224
charlesmn 0:3ac96e360672 225
charlesmn 0:3ac96e360672 226 } VL53L1_offsetcal_config_t;
charlesmn 0:3ac96e360672 227
charlesmn 0:3ac96e360672 228
charlesmn 0:3ac96e360672 229
charlesmn 0:3ac96e360672 230
charlesmn 0:3ac96e360672 231 typedef struct {
charlesmn 0:3ac96e360672 232
charlesmn 0:3ac96e360672 233 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 234
charlesmn 0:3ac96e360672 235 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 236
charlesmn 0:3ac96e360672 237 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 238
charlesmn 0:3ac96e360672 239 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 240
charlesmn 0:3ac96e360672 241 uint16_t phasecal_num_of_samples;
charlesmn 0:3ac96e360672 242
charlesmn 0:3ac96e360672 243 uint16_t zone_num_of_samples;
charlesmn 0:3ac96e360672 244
charlesmn 0:3ac96e360672 245
charlesmn 0:3ac96e360672 246 } VL53L1_zonecal_config_t;
charlesmn 0:3ac96e360672 247
charlesmn 0:3ac96e360672 248
charlesmn 0:3ac96e360672 249
charlesmn 0:3ac96e360672 250
charlesmn 0:3ac96e360672 251
charlesmn 0:3ac96e360672 252 typedef struct {
charlesmn 0:3ac96e360672 253
charlesmn 0:3ac96e360672 254 VL53L1_DeviceSscArray array_select;
charlesmn 0:3ac96e360672 255
charlesmn 0:3ac96e360672 256 uint8_t VL53L1_p_009;
charlesmn 0:3ac96e360672 257
charlesmn 0:3ac96e360672 258 uint8_t vcsel_start;
charlesmn 0:3ac96e360672 259
charlesmn 0:3ac96e360672 260 uint8_t vcsel_width;
charlesmn 0:3ac96e360672 261
charlesmn 0:3ac96e360672 262 uint32_t timeout_us;
charlesmn 0:3ac96e360672 263
charlesmn 0:3ac96e360672 264 uint16_t rate_limit_mcps;
charlesmn 0:3ac96e360672 265
charlesmn 0:3ac96e360672 266
charlesmn 0:3ac96e360672 267 } VL53L1_ssc_config_t;
charlesmn 0:3ac96e360672 268
charlesmn 0:3ac96e360672 269
charlesmn 0:3ac96e360672 270
charlesmn 0:3ac96e360672 271
charlesmn 0:3ac96e360672 272 typedef struct {
charlesmn 0:3ac96e360672 273
charlesmn 0:3ac96e360672 274
charlesmn 0:3ac96e360672 275 uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 276
charlesmn 0:3ac96e360672 277 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 278
charlesmn 0:3ac96e360672 279 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 280
charlesmn 0:3ac96e360672 281 uint32_t nvm_default__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 282
charlesmn 0:3ac96e360672 283 int16_t nvm_default__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 284
charlesmn 0:3ac96e360672 285 int16_t nvm_default__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 286
charlesmn 0:3ac96e360672 287 uint8_t global_crosstalk_compensation_enable;
charlesmn 0:3ac96e360672 288
charlesmn 0:3ac96e360672 289 int16_t histogram_mode_crosstalk_margin_kcps;
charlesmn 0:3ac96e360672 290
charlesmn 0:3ac96e360672 291 int16_t lite_mode_crosstalk_margin_kcps;
charlesmn 0:3ac96e360672 292
charlesmn 0:3ac96e360672 293 uint8_t crosstalk_range_ignore_threshold_mult;
charlesmn 0:3ac96e360672 294
charlesmn 0:3ac96e360672 295 uint16_t crosstalk_range_ignore_threshold_rate_mcps;
charlesmn 0:3ac96e360672 296
charlesmn 0:3ac96e360672 297 int16_t algo__crosstalk_detect_min_valid_range_mm;
charlesmn 0:3ac96e360672 298
charlesmn 0:3ac96e360672 299 int16_t algo__crosstalk_detect_max_valid_range_mm;
charlesmn 0:3ac96e360672 300
charlesmn 0:3ac96e360672 301 uint16_t algo__crosstalk_detect_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 302
charlesmn 0:3ac96e360672 303 uint16_t algo__crosstalk_detect_max_sigma_mm;
charlesmn 0:3ac96e360672 304
charlesmn 0:3ac96e360672 305
charlesmn 0:3ac96e360672 306
charlesmn 0:3ac96e360672 307 } VL53L1_xtalk_config_t;
charlesmn 0:3ac96e360672 308
charlesmn 0:3ac96e360672 309
charlesmn 0:3ac96e360672 310
charlesmn 0:3ac96e360672 311
charlesmn 0:3ac96e360672 312 typedef struct {
charlesmn 0:3ac96e360672 313
charlesmn 0:3ac96e360672 314
charlesmn 0:3ac96e360672 315 uint16_t tp_tuning_parm_version;
charlesmn 0:3ac96e360672 316
charlesmn 0:3ac96e360672 317 uint16_t tp_tuning_parm_key_table_version;
charlesmn 0:3ac96e360672 318
charlesmn 0:3ac96e360672 319 uint16_t tp_tuning_parm_lld_version;
charlesmn 0:3ac96e360672 320
charlesmn 0:3ac96e360672 321 uint8_t tp_init_phase_rtn_lite_long;
charlesmn 0:3ac96e360672 322
charlesmn 0:3ac96e360672 323 uint8_t tp_init_phase_rtn_lite_med;
charlesmn 0:3ac96e360672 324
charlesmn 0:3ac96e360672 325 uint8_t tp_init_phase_rtn_lite_short;
charlesmn 0:3ac96e360672 326
charlesmn 0:3ac96e360672 327 uint8_t tp_init_phase_ref_lite_long;
charlesmn 0:3ac96e360672 328
charlesmn 0:3ac96e360672 329 uint8_t tp_init_phase_ref_lite_med;
charlesmn 0:3ac96e360672 330
charlesmn 0:3ac96e360672 331 uint8_t tp_init_phase_ref_lite_short;
charlesmn 0:3ac96e360672 332
charlesmn 0:3ac96e360672 333
charlesmn 0:3ac96e360672 334 uint8_t tp_init_phase_rtn_hist_long;
charlesmn 0:3ac96e360672 335
charlesmn 0:3ac96e360672 336 uint8_t tp_init_phase_rtn_hist_med;
charlesmn 0:3ac96e360672 337
charlesmn 0:3ac96e360672 338 uint8_t tp_init_phase_rtn_hist_short;
charlesmn 0:3ac96e360672 339
charlesmn 0:3ac96e360672 340 uint8_t tp_init_phase_ref_hist_long;
charlesmn 0:3ac96e360672 341
charlesmn 0:3ac96e360672 342 uint8_t tp_init_phase_ref_hist_med;
charlesmn 0:3ac96e360672 343
charlesmn 0:3ac96e360672 344 uint8_t tp_init_phase_ref_hist_short;
charlesmn 0:3ac96e360672 345
charlesmn 0:3ac96e360672 346
charlesmn 0:3ac96e360672 347 uint8_t tp_consistency_lite_phase_tolerance;
charlesmn 0:3ac96e360672 348
charlesmn 0:3ac96e360672 349 uint8_t tp_phasecal_target;
charlesmn 0:3ac96e360672 350
charlesmn 0:3ac96e360672 351 uint16_t tp_cal_repeat_rate;
charlesmn 0:3ac96e360672 352
charlesmn 0:3ac96e360672 353 uint8_t tp_lite_min_clip;
charlesmn 0:3ac96e360672 354
charlesmn 0:3ac96e360672 355
charlesmn 0:3ac96e360672 356 uint16_t tp_lite_long_sigma_thresh_mm;
charlesmn 0:3ac96e360672 357
charlesmn 0:3ac96e360672 358 uint16_t tp_lite_med_sigma_thresh_mm;
charlesmn 0:3ac96e360672 359
charlesmn 0:3ac96e360672 360 uint16_t tp_lite_short_sigma_thresh_mm;
charlesmn 0:3ac96e360672 361
charlesmn 0:3ac96e360672 362
charlesmn 0:3ac96e360672 363 uint16_t tp_lite_long_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 364
charlesmn 0:3ac96e360672 365 uint16_t tp_lite_med_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 366
charlesmn 0:3ac96e360672 367 uint16_t tp_lite_short_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 368
charlesmn 0:3ac96e360672 369
charlesmn 0:3ac96e360672 370 uint8_t tp_lite_sigma_est_pulse_width_ns;
charlesmn 0:3ac96e360672 371
charlesmn 0:3ac96e360672 372 uint8_t tp_lite_sigma_est_amb_width_ns;
charlesmn 0:3ac96e360672 373
charlesmn 0:3ac96e360672 374 uint8_t tp_lite_sigma_ref_mm;
charlesmn 0:3ac96e360672 375
charlesmn 0:3ac96e360672 376 uint8_t tp_lite_seed_cfg;
charlesmn 0:3ac96e360672 377
charlesmn 0:3ac96e360672 378 uint8_t tp_timed_seed_cfg;
charlesmn 0:3ac96e360672 379
charlesmn 0:3ac96e360672 380
charlesmn 0:3ac96e360672 381 uint8_t tp_lite_quantifier;
charlesmn 0:3ac96e360672 382
charlesmn 0:3ac96e360672 383 uint8_t tp_lite_first_order_select;
charlesmn 0:3ac96e360672 384
charlesmn 0:3ac96e360672 385
charlesmn 0:3ac96e360672 386 uint16_t tp_dss_target_lite_mcps;
charlesmn 0:3ac96e360672 387
charlesmn 0:3ac96e360672 388 uint16_t tp_dss_target_histo_mcps;
charlesmn 0:3ac96e360672 389
charlesmn 0:3ac96e360672 390 uint16_t tp_dss_target_histo_mz_mcps;
charlesmn 0:3ac96e360672 391
charlesmn 0:3ac96e360672 392 uint16_t tp_dss_target_timed_mcps;
charlesmn 0:3ac96e360672 393
charlesmn 0:3ac96e360672 394 uint16_t tp_dss_target_very_short_mcps;
charlesmn 0:3ac96e360672 395
charlesmn 0:3ac96e360672 396
charlesmn 0:3ac96e360672 397 uint32_t tp_phasecal_timeout_lite_us;
charlesmn 0:3ac96e360672 398
charlesmn 0:3ac96e360672 399 uint32_t tp_phasecal_timeout_hist_long_us;
charlesmn 0:3ac96e360672 400
charlesmn 0:3ac96e360672 401 uint32_t tp_phasecal_timeout_hist_med_us;
charlesmn 0:3ac96e360672 402
charlesmn 0:3ac96e360672 403 uint32_t tp_phasecal_timeout_hist_short_us;
charlesmn 0:3ac96e360672 404
charlesmn 0:3ac96e360672 405
charlesmn 0:3ac96e360672 406 uint32_t tp_phasecal_timeout_mz_long_us;
charlesmn 0:3ac96e360672 407
charlesmn 0:3ac96e360672 408 uint32_t tp_phasecal_timeout_mz_med_us;
charlesmn 0:3ac96e360672 409
charlesmn 0:3ac96e360672 410 uint32_t tp_phasecal_timeout_mz_short_us;
charlesmn 0:3ac96e360672 411
charlesmn 0:3ac96e360672 412 uint32_t tp_phasecal_timeout_timed_us;
charlesmn 0:3ac96e360672 413
charlesmn 0:3ac96e360672 414
charlesmn 0:3ac96e360672 415 uint32_t tp_mm_timeout_lite_us;
charlesmn 0:3ac96e360672 416
charlesmn 0:3ac96e360672 417 uint32_t tp_mm_timeout_histo_us;
charlesmn 0:3ac96e360672 418
charlesmn 0:3ac96e360672 419 uint32_t tp_mm_timeout_mz_us;
charlesmn 0:3ac96e360672 420
charlesmn 0:3ac96e360672 421 uint32_t tp_mm_timeout_timed_us;
charlesmn 0:3ac96e360672 422
charlesmn 0:3ac96e360672 423 uint32_t tp_mm_timeout_lpa_us;
charlesmn 0:3ac96e360672 424
charlesmn 0:3ac96e360672 425
charlesmn 0:3ac96e360672 426 uint32_t tp_range_timeout_lite_us;
charlesmn 0:3ac96e360672 427
charlesmn 0:3ac96e360672 428 uint32_t tp_range_timeout_histo_us;
charlesmn 0:3ac96e360672 429
charlesmn 0:3ac96e360672 430 uint32_t tp_range_timeout_mz_us;
charlesmn 0:3ac96e360672 431
charlesmn 0:3ac96e360672 432 uint32_t tp_range_timeout_timed_us;
charlesmn 0:3ac96e360672 433
charlesmn 0:3ac96e360672 434 uint32_t tp_range_timeout_lpa_us;
charlesmn 0:3ac96e360672 435
charlesmn 0:3ac96e360672 436 uint32_t tp_phasecal_patch_power;
charlesmn 0:3ac96e360672 437
charlesmn 0:3ac96e360672 438 uint8_t tp_hist_merge;
charlesmn 0:3ac96e360672 439
charlesmn 0:3ac96e360672 440 uint32_t tp_reset_merge_threshold;
charlesmn 0:3ac96e360672 441
charlesmn 0:3ac96e360672 442 uint8_t tp_hist_merge_max_size;
charlesmn 0:3ac96e360672 443
charlesmn 0:3ac96e360672 444 uint8_t tp_uwr_enable;
charlesmn 0:3ac96e360672 445 int16_t tp_uwr_med_z_1_min;
charlesmn 0:3ac96e360672 446 int16_t tp_uwr_med_z_1_max;
charlesmn 0:3ac96e360672 447 int16_t tp_uwr_med_z_2_min;
charlesmn 0:3ac96e360672 448 int16_t tp_uwr_med_z_2_max;
charlesmn 0:3ac96e360672 449 int16_t tp_uwr_med_z_3_min;
charlesmn 0:3ac96e360672 450 int16_t tp_uwr_med_z_3_max;
charlesmn 0:3ac96e360672 451 int16_t tp_uwr_med_z_4_min;
charlesmn 0:3ac96e360672 452 int16_t tp_uwr_med_z_4_max;
charlesmn 0:3ac96e360672 453 int16_t tp_uwr_med_z_5_min;
charlesmn 0:3ac96e360672 454 int16_t tp_uwr_med_z_5_max;
charlesmn 0:3ac96e360672 455 int16_t tp_uwr_med_z_6_min;
charlesmn 0:3ac96e360672 456 int16_t tp_uwr_med_z_6_max;
charlesmn 0:3ac96e360672 457 int16_t tp_uwr_med_corr_z_1_rangea;
charlesmn 0:3ac96e360672 458 int16_t tp_uwr_med_corr_z_1_rangeb;
charlesmn 0:3ac96e360672 459 int16_t tp_uwr_med_corr_z_2_rangea;
charlesmn 0:3ac96e360672 460 int16_t tp_uwr_med_corr_z_2_rangeb;
charlesmn 0:3ac96e360672 461 int16_t tp_uwr_med_corr_z_3_rangea;
charlesmn 0:3ac96e360672 462 int16_t tp_uwr_med_corr_z_3_rangeb;
charlesmn 0:3ac96e360672 463 int16_t tp_uwr_med_corr_z_4_rangea;
charlesmn 0:3ac96e360672 464 int16_t tp_uwr_med_corr_z_4_rangeb;
charlesmn 0:3ac96e360672 465 int16_t tp_uwr_med_corr_z_5_rangea;
charlesmn 0:3ac96e360672 466 int16_t tp_uwr_med_corr_z_5_rangeb;
charlesmn 0:3ac96e360672 467 int16_t tp_uwr_med_corr_z_6_rangea;
charlesmn 0:3ac96e360672 468 int16_t tp_uwr_med_corr_z_6_rangeb;
charlesmn 0:3ac96e360672 469 int16_t tp_uwr_lng_z_1_min;
charlesmn 0:3ac96e360672 470 int16_t tp_uwr_lng_z_1_max;
charlesmn 0:3ac96e360672 471 int16_t tp_uwr_lng_z_2_min;
charlesmn 0:3ac96e360672 472 int16_t tp_uwr_lng_z_2_max;
charlesmn 0:3ac96e360672 473 int16_t tp_uwr_lng_z_3_min;
charlesmn 0:3ac96e360672 474 int16_t tp_uwr_lng_z_3_max;
charlesmn 0:3ac96e360672 475 int16_t tp_uwr_lng_z_4_min;
charlesmn 0:3ac96e360672 476 int16_t tp_uwr_lng_z_4_max;
charlesmn 0:3ac96e360672 477 int16_t tp_uwr_lng_z_5_min;
charlesmn 0:3ac96e360672 478 int16_t tp_uwr_lng_z_5_max;
charlesmn 0:3ac96e360672 479 int16_t tp_uwr_lng_corr_z_1_rangea;
charlesmn 0:3ac96e360672 480 int16_t tp_uwr_lng_corr_z_1_rangeb;
charlesmn 0:3ac96e360672 481 int16_t tp_uwr_lng_corr_z_2_rangea;
charlesmn 0:3ac96e360672 482 int16_t tp_uwr_lng_corr_z_2_rangeb;
charlesmn 0:3ac96e360672 483 int16_t tp_uwr_lng_corr_z_3_rangea;
charlesmn 0:3ac96e360672 484 int16_t tp_uwr_lng_corr_z_3_rangeb;
charlesmn 0:3ac96e360672 485 int16_t tp_uwr_lng_corr_z_4_rangea;
charlesmn 0:3ac96e360672 486 int16_t tp_uwr_lng_corr_z_4_rangeb;
charlesmn 0:3ac96e360672 487 int16_t tp_uwr_lng_corr_z_5_rangea;
charlesmn 0:3ac96e360672 488 int16_t tp_uwr_lng_corr_z_5_rangeb;
charlesmn 0:3ac96e360672 489
charlesmn 0:3ac96e360672 490 } VL53L1_tuning_parm_storage_t;
charlesmn 0:3ac96e360672 491
charlesmn 0:3ac96e360672 492
charlesmn 0:3ac96e360672 493
charlesmn 0:3ac96e360672 494
charlesmn 0:3ac96e360672 495
charlesmn 0:3ac96e360672 496 typedef struct {
charlesmn 0:3ac96e360672 497
charlesmn 0:3ac96e360672 498 uint8_t x_centre;
charlesmn 0:3ac96e360672 499 uint8_t y_centre;
charlesmn 0:3ac96e360672 500
charlesmn 0:3ac96e360672 501 } VL53L1_optical_centre_t;
charlesmn 0:3ac96e360672 502
charlesmn 0:3ac96e360672 503
charlesmn 0:3ac96e360672 504
charlesmn 0:3ac96e360672 505
charlesmn 0:3ac96e360672 506 typedef struct {
charlesmn 0:3ac96e360672 507
charlesmn 0:3ac96e360672 508 uint8_t x_centre;
charlesmn 0:3ac96e360672 509 uint8_t y_centre;
charlesmn 0:3ac96e360672 510 uint8_t width;
charlesmn 0:3ac96e360672 511 uint8_t height;
charlesmn 0:3ac96e360672 512
charlesmn 0:3ac96e360672 513 } VL53L1_user_zone_t;
charlesmn 0:3ac96e360672 514
charlesmn 0:3ac96e360672 515
charlesmn 0:3ac96e360672 516
charlesmn 0:3ac96e360672 517
charlesmn 0:3ac96e360672 518 typedef struct {
charlesmn 0:3ac96e360672 519
charlesmn 0:3ac96e360672 520 uint8_t max_zones;
charlesmn 0:3ac96e360672 521 uint8_t active_zones;
charlesmn 0:3ac96e360672 522
charlesmn 0:3ac96e360672 523
charlesmn 0:3ac96e360672 524
charlesmn 0:3ac96e360672 525 VL53L1_histogram_config_t multizone_hist_cfg;
charlesmn 0:3ac96e360672 526
charlesmn 0:3ac96e360672 527 VL53L1_user_zone_t user_zones[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 528
charlesmn 0:3ac96e360672 529
charlesmn 0:3ac96e360672 530 uint8_t bin_config[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 531
charlesmn 0:3ac96e360672 532
charlesmn 0:3ac96e360672 533 } VL53L1_zone_config_t;
charlesmn 0:3ac96e360672 534
charlesmn 0:3ac96e360672 535
charlesmn 0:3ac96e360672 536
charlesmn 0:3ac96e360672 537 typedef struct {
charlesmn 0:3ac96e360672 538
charlesmn 0:3ac96e360672 539
charlesmn 0:3ac96e360672 540 VL53L1_GPIO_Interrupt_Mode intr_mode_distance;
charlesmn 0:3ac96e360672 541
charlesmn 0:3ac96e360672 542
charlesmn 0:3ac96e360672 543 VL53L1_GPIO_Interrupt_Mode intr_mode_rate;
charlesmn 0:3ac96e360672 544
charlesmn 0:3ac96e360672 545
charlesmn 0:3ac96e360672 546 uint8_t intr_new_measure_ready;
charlesmn 0:3ac96e360672 547
charlesmn 0:3ac96e360672 548
charlesmn 0:3ac96e360672 549 uint8_t intr_no_target;
charlesmn 0:3ac96e360672 550
charlesmn 0:3ac96e360672 551
charlesmn 0:3ac96e360672 552 uint8_t intr_combined_mode;
charlesmn 0:3ac96e360672 553
charlesmn 0:3ac96e360672 554
charlesmn 0:3ac96e360672 555
charlesmn 0:3ac96e360672 556
charlesmn 0:3ac96e360672 557
charlesmn 0:3ac96e360672 558 uint16_t threshold_distance_high;
charlesmn 0:3ac96e360672 559
charlesmn 0:3ac96e360672 560
charlesmn 0:3ac96e360672 561 uint16_t threshold_distance_low;
charlesmn 0:3ac96e360672 562
charlesmn 0:3ac96e360672 563
charlesmn 0:3ac96e360672 564 uint16_t threshold_rate_high;
charlesmn 0:3ac96e360672 565
charlesmn 0:3ac96e360672 566
charlesmn 0:3ac96e360672 567 uint16_t threshold_rate_low;
charlesmn 0:3ac96e360672 568
charlesmn 0:3ac96e360672 569 } VL53L1_GPIO_interrupt_config_t;
charlesmn 0:3ac96e360672 570
charlesmn 0:3ac96e360672 571
charlesmn 0:3ac96e360672 572
charlesmn 0:3ac96e360672 573
charlesmn 0:3ac96e360672 574 typedef struct {
charlesmn 0:3ac96e360672 575
charlesmn 0:3ac96e360672 576
charlesmn 0:3ac96e360672 577 uint8_t vhv_loop_bound;
charlesmn 0:3ac96e360672 578
charlesmn 0:3ac96e360672 579
charlesmn 0:3ac96e360672 580 uint8_t is_low_power_auto_mode;
charlesmn 0:3ac96e360672 581
charlesmn 0:3ac96e360672 582
charlesmn 0:3ac96e360672 583 uint8_t low_power_auto_range_count;
charlesmn 0:3ac96e360672 584
charlesmn 0:3ac96e360672 585
charlesmn 0:3ac96e360672 586 uint8_t saved_interrupt_config;
charlesmn 0:3ac96e360672 587
charlesmn 0:3ac96e360672 588
charlesmn 0:3ac96e360672 589 uint8_t saved_vhv_init;
charlesmn 0:3ac96e360672 590
charlesmn 0:3ac96e360672 591
charlesmn 0:3ac96e360672 592 uint8_t saved_vhv_timeout;
charlesmn 0:3ac96e360672 593
charlesmn 0:3ac96e360672 594
charlesmn 0:3ac96e360672 595 uint8_t first_run_phasecal_result;
charlesmn 0:3ac96e360672 596
charlesmn 0:3ac96e360672 597
charlesmn 0:3ac96e360672 598 uint32_t dss__total_rate_per_spad_mcps;
charlesmn 0:3ac96e360672 599
charlesmn 0:3ac96e360672 600
charlesmn 0:3ac96e360672 601 uint16_t dss__required_spads;
charlesmn 0:3ac96e360672 602
charlesmn 0:3ac96e360672 603 } VL53L1_low_power_auto_data_t;
charlesmn 0:3ac96e360672 604
charlesmn 0:3ac96e360672 605
charlesmn 0:3ac96e360672 606
charlesmn 0:3ac96e360672 607
charlesmn 0:3ac96e360672 608
charlesmn 0:3ac96e360672 609
charlesmn 0:3ac96e360672 610
charlesmn 0:3ac96e360672 611 typedef struct {
charlesmn 0:3ac96e360672 612
charlesmn 0:3ac96e360672 613
charlesmn 0:3ac96e360672 614 uint8_t smudge_corr_enabled;
charlesmn 0:3ac96e360672 615
charlesmn 0:3ac96e360672 616
charlesmn 0:3ac96e360672 617 uint8_t smudge_corr_apply_enabled;
charlesmn 0:3ac96e360672 618
charlesmn 0:3ac96e360672 619
charlesmn 0:3ac96e360672 620 uint8_t smudge_corr_single_apply;
charlesmn 0:3ac96e360672 621
charlesmn 0:3ac96e360672 622
charlesmn 0:3ac96e360672 623
charlesmn 0:3ac96e360672 624
charlesmn 0:3ac96e360672 625 uint16_t smudge_margin;
charlesmn 0:3ac96e360672 626
charlesmn 0:3ac96e360672 627
charlesmn 0:3ac96e360672 628 uint32_t noise_margin;
charlesmn 0:3ac96e360672 629
charlesmn 0:3ac96e360672 630
charlesmn 0:3ac96e360672 631 uint32_t user_xtalk_offset_limit;
charlesmn 0:3ac96e360672 632
charlesmn 0:3ac96e360672 633
charlesmn 0:3ac96e360672 634 uint8_t user_xtalk_offset_limit_hi;
charlesmn 0:3ac96e360672 635
charlesmn 0:3ac96e360672 636
charlesmn 0:3ac96e360672 637 uint32_t sample_limit;
charlesmn 0:3ac96e360672 638
charlesmn 0:3ac96e360672 639
charlesmn 0:3ac96e360672 640 uint32_t single_xtalk_delta;
charlesmn 0:3ac96e360672 641
charlesmn 0:3ac96e360672 642
charlesmn 0:3ac96e360672 643 uint32_t averaged_xtalk_delta;
charlesmn 0:3ac96e360672 644
charlesmn 0:3ac96e360672 645
charlesmn 0:3ac96e360672 646 uint32_t smudge_corr_clip_limit;
charlesmn 0:3ac96e360672 647
charlesmn 0:3ac96e360672 648
charlesmn 0:3ac96e360672 649 uint32_t smudge_corr_ambient_threshold;
charlesmn 0:3ac96e360672 650
charlesmn 0:3ac96e360672 651
charlesmn 0:3ac96e360672 652 uint8_t scaler_calc_method;
charlesmn 0:3ac96e360672 653
charlesmn 0:3ac96e360672 654
charlesmn 0:3ac96e360672 655 int16_t x_gradient_scaler;
charlesmn 0:3ac96e360672 656
charlesmn 0:3ac96e360672 657
charlesmn 0:3ac96e360672 658 int16_t y_gradient_scaler;
charlesmn 0:3ac96e360672 659
charlesmn 0:3ac96e360672 660
charlesmn 0:3ac96e360672 661 uint8_t user_scaler_set;
charlesmn 0:3ac96e360672 662
charlesmn 0:3ac96e360672 663
charlesmn 0:3ac96e360672 664 uint32_t nodetect_ambient_threshold;
charlesmn 0:3ac96e360672 665
charlesmn 0:3ac96e360672 666
charlesmn 0:3ac96e360672 667 uint32_t nodetect_sample_limit;
charlesmn 0:3ac96e360672 668
charlesmn 0:3ac96e360672 669
charlesmn 0:3ac96e360672 670 uint32_t nodetect_xtalk_offset;
charlesmn 0:3ac96e360672 671
charlesmn 0:3ac96e360672 672
charlesmn 0:3ac96e360672 673 uint16_t nodetect_min_range_mm;
charlesmn 0:3ac96e360672 674
charlesmn 0:3ac96e360672 675
charlesmn 0:3ac96e360672 676 uint32_t max_smudge_factor;
charlesmn 0:3ac96e360672 677
charlesmn 0:3ac96e360672 678 } VL53L1_smudge_corrector_config_t;
charlesmn 0:3ac96e360672 679
charlesmn 0:3ac96e360672 680
charlesmn 0:3ac96e360672 681
charlesmn 0:3ac96e360672 682 typedef struct {
charlesmn 0:3ac96e360672 683
charlesmn 0:3ac96e360672 684
charlesmn 0:3ac96e360672 685 uint32_t current_samples;
charlesmn 0:3ac96e360672 686
charlesmn 0:3ac96e360672 687
charlesmn 0:3ac96e360672 688 uint32_t required_samples;
charlesmn 0:3ac96e360672 689
charlesmn 0:3ac96e360672 690
charlesmn 0:3ac96e360672 691 uint64_t accumulator;
charlesmn 0:3ac96e360672 692
charlesmn 0:3ac96e360672 693
charlesmn 0:3ac96e360672 694 uint32_t nodetect_counter;
charlesmn 0:3ac96e360672 695
charlesmn 0:3ac96e360672 696 } VL53L1_smudge_corrector_internals_t;
charlesmn 0:3ac96e360672 697
charlesmn 0:3ac96e360672 698
charlesmn 0:3ac96e360672 699
charlesmn 0:3ac96e360672 700 typedef struct {
charlesmn 0:3ac96e360672 701
charlesmn 0:3ac96e360672 702
charlesmn 0:3ac96e360672 703 uint8_t smudge_corr_valid;
charlesmn 0:3ac96e360672 704
charlesmn 0:3ac96e360672 705
charlesmn 0:3ac96e360672 706 uint8_t smudge_corr_clipped;
charlesmn 0:3ac96e360672 707
charlesmn 0:3ac96e360672 708
charlesmn 0:3ac96e360672 709 uint8_t single_xtalk_delta_flag;
charlesmn 0:3ac96e360672 710
charlesmn 0:3ac96e360672 711
charlesmn 0:3ac96e360672 712 uint8_t averaged_xtalk_delta_flag;
charlesmn 0:3ac96e360672 713
charlesmn 0:3ac96e360672 714
charlesmn 0:3ac96e360672 715 uint8_t sample_limit_exceeded_flag;
charlesmn 0:3ac96e360672 716
charlesmn 0:3ac96e360672 717
charlesmn 0:3ac96e360672 718 uint8_t gradient_zero_flag;
charlesmn 0:3ac96e360672 719
charlesmn 0:3ac96e360672 720
charlesmn 0:3ac96e360672 721 uint8_t new_xtalk_applied_flag;
charlesmn 0:3ac96e360672 722
charlesmn 0:3ac96e360672 723
charlesmn 0:3ac96e360672 724 uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 725
charlesmn 0:3ac96e360672 726
charlesmn 0:3ac96e360672 727 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 728
charlesmn 0:3ac96e360672 729
charlesmn 0:3ac96e360672 730 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 731
charlesmn 0:3ac96e360672 732
charlesmn 0:3ac96e360672 733 } VL53L1_smudge_corrector_data_t;
charlesmn 0:3ac96e360672 734
charlesmn 0:3ac96e360672 735
charlesmn 0:3ac96e360672 736
charlesmn 0:3ac96e360672 737
charlesmn 0:3ac96e360672 738
charlesmn 0:3ac96e360672 739 typedef struct {
charlesmn 0:3ac96e360672 740
charlesmn 0:3ac96e360672 741
charlesmn 0:3ac96e360672 742
charlesmn 0:3ac96e360672 743 uint8_t range_id;
charlesmn 0:3ac96e360672 744
charlesmn 0:3ac96e360672 745 uint32_t time_stamp;
charlesmn 0:3ac96e360672 746
charlesmn 0:3ac96e360672 747 uint8_t VL53L1_p_015;
charlesmn 0:3ac96e360672 748
charlesmn 0:3ac96e360672 749 uint8_t VL53L1_p_022;
charlesmn 0:3ac96e360672 750
charlesmn 0:3ac96e360672 751 uint8_t VL53L1_p_025;
charlesmn 0:3ac96e360672 752
charlesmn 0:3ac96e360672 753 uint8_t VL53L1_p_026;
charlesmn 0:3ac96e360672 754
charlesmn 0:3ac96e360672 755 uint8_t VL53L1_p_016;
charlesmn 0:3ac96e360672 756
charlesmn 0:3ac96e360672 757 uint8_t VL53L1_p_027;
charlesmn 0:3ac96e360672 758
charlesmn 0:3ac96e360672 759
charlesmn 0:3ac96e360672 760 uint16_t width;
charlesmn 0:3ac96e360672 761
charlesmn 0:3ac96e360672 762 uint8_t VL53L1_p_030;
charlesmn 0:3ac96e360672 763
charlesmn 0:3ac96e360672 764
charlesmn 0:3ac96e360672 765 uint16_t fast_osc_frequency;
charlesmn 0:3ac96e360672 766
charlesmn 0:3ac96e360672 767 uint16_t zero_distance_phase;
charlesmn 0:3ac96e360672 768
charlesmn 0:3ac96e360672 769 uint16_t VL53L1_p_006;
charlesmn 0:3ac96e360672 770
charlesmn 0:3ac96e360672 771
charlesmn 0:3ac96e360672 772 uint32_t total_periods_elapsed;
charlesmn 0:3ac96e360672 773
charlesmn 0:3ac96e360672 774
charlesmn 0:3ac96e360672 775 uint32_t peak_duration_us;
charlesmn 0:3ac96e360672 776
charlesmn 0:3ac96e360672 777
charlesmn 0:3ac96e360672 778 uint32_t woi_duration_us;
charlesmn 0:3ac96e360672 779
charlesmn 0:3ac96e360672 780
charlesmn 0:3ac96e360672 781
charlesmn 0:3ac96e360672 782
charlesmn 0:3ac96e360672 783
charlesmn 0:3ac96e360672 784 uint32_t VL53L1_p_020;
charlesmn 0:3ac96e360672 785
charlesmn 0:3ac96e360672 786 uint32_t VL53L1_p_021;
charlesmn 0:3ac96e360672 787
charlesmn 0:3ac96e360672 788 int32_t VL53L1_p_013;
charlesmn 0:3ac96e360672 789
charlesmn 0:3ac96e360672 790
charlesmn 0:3ac96e360672 791
charlesmn 0:3ac96e360672 792
charlesmn 0:3ac96e360672 793 uint16_t peak_signal_count_rate_mcps;
charlesmn 0:3ac96e360672 794
charlesmn 0:3ac96e360672 795 uint16_t avg_signal_count_rate_mcps;
charlesmn 0:3ac96e360672 796
charlesmn 0:3ac96e360672 797 uint16_t ambient_count_rate_mcps;
charlesmn 0:3ac96e360672 798
charlesmn 0:3ac96e360672 799 uint16_t total_rate_per_spad_mcps;
charlesmn 0:3ac96e360672 800
charlesmn 0:3ac96e360672 801 uint32_t VL53L1_p_012;
charlesmn 0:3ac96e360672 802
charlesmn 0:3ac96e360672 803
charlesmn 0:3ac96e360672 804
charlesmn 0:3ac96e360672 805
charlesmn 0:3ac96e360672 806 uint16_t VL53L1_p_005;
charlesmn 0:3ac96e360672 807
charlesmn 0:3ac96e360672 808
charlesmn 0:3ac96e360672 809
charlesmn 0:3ac96e360672 810
charlesmn 0:3ac96e360672 811 uint16_t VL53L1_p_028;
charlesmn 0:3ac96e360672 812
charlesmn 0:3ac96e360672 813 uint16_t VL53L1_p_014;
charlesmn 0:3ac96e360672 814
charlesmn 0:3ac96e360672 815 uint16_t VL53L1_p_029;
charlesmn 0:3ac96e360672 816
charlesmn 0:3ac96e360672 817
charlesmn 0:3ac96e360672 818
charlesmn 0:3ac96e360672 819
charlesmn 0:3ac96e360672 820 int16_t min_range_mm;
charlesmn 0:3ac96e360672 821
charlesmn 0:3ac96e360672 822 int16_t median_range_mm;
charlesmn 0:3ac96e360672 823
charlesmn 0:3ac96e360672 824 int16_t max_range_mm;
charlesmn 0:3ac96e360672 825
charlesmn 0:3ac96e360672 826
charlesmn 0:3ac96e360672 827
charlesmn 0:3ac96e360672 828
charlesmn 0:3ac96e360672 829 uint8_t range_status;
charlesmn 0:3ac96e360672 830
charlesmn 0:3ac96e360672 831 } VL53L1_range_data_t;
charlesmn 0:3ac96e360672 832
charlesmn 0:3ac96e360672 833
charlesmn 0:3ac96e360672 834
charlesmn 0:3ac96e360672 835
charlesmn 0:3ac96e360672 836 typedef struct {
charlesmn 0:3ac96e360672 837
charlesmn 0:3ac96e360672 838 VL53L1_DeviceState cfg_device_state;
charlesmn 0:3ac96e360672 839
charlesmn 0:3ac96e360672 840 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 841
charlesmn 0:3ac96e360672 842 uint8_t zone_id;
charlesmn 0:3ac96e360672 843
charlesmn 0:3ac96e360672 844 uint8_t stream_count;
charlesmn 0:3ac96e360672 845
charlesmn 0:3ac96e360672 846
charlesmn 0:3ac96e360672 847 int16_t VL53L1_p_007[VL53L1_MAX_AMBIENT_DMAX_VALUES];
charlesmn 0:3ac96e360672 848
charlesmn 0:3ac96e360672 849 int16_t wrap_dmax_mm;
charlesmn 0:3ac96e360672 850
charlesmn 0:3ac96e360672 851
charlesmn 0:3ac96e360672 852 uint8_t device_status;
charlesmn 0:3ac96e360672 853
charlesmn 0:3ac96e360672 854
charlesmn 0:3ac96e360672 855 uint8_t max_results;
charlesmn 0:3ac96e360672 856
charlesmn 0:3ac96e360672 857 uint8_t active_results;
charlesmn 0:3ac96e360672 858
charlesmn 0:3ac96e360672 859 VL53L1_range_data_t VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 860
charlesmn 0:3ac96e360672 861 VL53L1_range_data_t xmonitor;
charlesmn 0:3ac96e360672 862
charlesmn 0:3ac96e360672 863 VL53L1_smudge_corrector_data_t smudge_corrector_data;
charlesmn 0:3ac96e360672 864
charlesmn 0:3ac96e360672 865
charlesmn 0:3ac96e360672 866
charlesmn 0:3ac96e360672 867 } VL53L1_range_results_t;
charlesmn 0:3ac96e360672 868
charlesmn 0:3ac96e360672 869
charlesmn 0:3ac96e360672 870
charlesmn 0:3ac96e360672 871
charlesmn 0:3ac96e360672 872 typedef struct {
charlesmn 0:3ac96e360672 873
charlesmn 0:3ac96e360672 874 uint8_t no_of_samples;
charlesmn 0:3ac96e360672 875
charlesmn 0:3ac96e360672 876 uint32_t rate_per_spad_kcps_sum;
charlesmn 0:3ac96e360672 877
charlesmn 0:3ac96e360672 878 uint32_t rate_per_spad_kcps_avg;
charlesmn 0:3ac96e360672 879
charlesmn 0:3ac96e360672 880 int32_t signal_total_events_sum;
charlesmn 0:3ac96e360672 881
charlesmn 0:3ac96e360672 882 int32_t signal_total_events_avg;
charlesmn 0:3ac96e360672 883
charlesmn 0:3ac96e360672 884 uint32_t sigma_mm_sum;
charlesmn 0:3ac96e360672 885
charlesmn 0:3ac96e360672 886 uint32_t sigma_mm_avg;
charlesmn 0:3ac96e360672 887
charlesmn 0:3ac96e360672 888 uint32_t median_phase_sum;
charlesmn 0:3ac96e360672 889
charlesmn 0:3ac96e360672 890 uint32_t median_phase_avg;
charlesmn 0:3ac96e360672 891
charlesmn 0:3ac96e360672 892
charlesmn 0:3ac96e360672 893 } VL53L1_xtalk_range_data_t;
charlesmn 0:3ac96e360672 894
charlesmn 0:3ac96e360672 895
charlesmn 0:3ac96e360672 896
charlesmn 0:3ac96e360672 897
charlesmn 0:3ac96e360672 898 typedef struct {
charlesmn 0:3ac96e360672 899
charlesmn 0:3ac96e360672 900 VL53L1_Error cal_status;
charlesmn 0:3ac96e360672 901
charlesmn 0:3ac96e360672 902 uint8_t num_of_samples_status;
charlesmn 0:3ac96e360672 903
charlesmn 0:3ac96e360672 904 uint8_t zero_samples_status;
charlesmn 0:3ac96e360672 905
charlesmn 0:3ac96e360672 906 uint8_t max_sigma_status;
charlesmn 0:3ac96e360672 907
charlesmn 0:3ac96e360672 908 uint8_t max_results;
charlesmn 0:3ac96e360672 909
charlesmn 0:3ac96e360672 910 uint8_t active_results;
charlesmn 0:3ac96e360672 911
charlesmn 0:3ac96e360672 912
charlesmn 0:3ac96e360672 913 VL53L1_xtalk_range_data_t
charlesmn 0:3ac96e360672 914 VL53L1_p_002[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 915
charlesmn 0:3ac96e360672 916 VL53L1_histogram_bin_data_t central_histogram_sum;
charlesmn 0:3ac96e360672 917
charlesmn 0:3ac96e360672 918 VL53L1_histogram_bin_data_t central_histogram_avg;
charlesmn 0:3ac96e360672 919
charlesmn 0:3ac96e360672 920 uint8_t central_histogram__window_start;
charlesmn 0:3ac96e360672 921
charlesmn 0:3ac96e360672 922 uint8_t central_histogram__window_end;
charlesmn 0:3ac96e360672 923
charlesmn 0:3ac96e360672 924 VL53L1_histogram_bin_data_t
charlesmn 0:3ac96e360672 925 histogram_avg_1[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 926
charlesmn 0:3ac96e360672 927 VL53L1_histogram_bin_data_t
charlesmn 0:3ac96e360672 928 histogram_avg_2[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 929
charlesmn 0:3ac96e360672 930 VL53L1_histogram_bin_data_t
charlesmn 0:3ac96e360672 931 xtalk_avg[VL53L1_MAX_XTALK_RANGE_RESULTS];
charlesmn 0:3ac96e360672 932
charlesmn 0:3ac96e360672 933
charlesmn 0:3ac96e360672 934 } VL53L1_xtalk_range_results_t;
charlesmn 0:3ac96e360672 935
charlesmn 0:3ac96e360672 936
charlesmn 0:3ac96e360672 937
charlesmn 0:3ac96e360672 938
charlesmn 0:3ac96e360672 939 typedef struct {
charlesmn 0:3ac96e360672 940
charlesmn 0:3ac96e360672 941 uint8_t preset_mode;
charlesmn 0:3ac96e360672 942
charlesmn 0:3ac96e360672 943 uint8_t dss_config__roi_mode_control;
charlesmn 0:3ac96e360672 944
charlesmn 0:3ac96e360672 945 uint16_t dss_config__manual_effective_spads_select;
charlesmn 0:3ac96e360672 946
charlesmn 0:3ac96e360672 947 uint8_t no_of_samples;
charlesmn 0:3ac96e360672 948
charlesmn 0:3ac96e360672 949 uint32_t effective_spads;
charlesmn 0:3ac96e360672 950
charlesmn 0:3ac96e360672 951 uint32_t peak_rate_mcps;
charlesmn 0:3ac96e360672 952
charlesmn 0:3ac96e360672 953 uint32_t VL53L1_p_005;
charlesmn 0:3ac96e360672 954
charlesmn 0:3ac96e360672 955 int32_t median_range_mm;
charlesmn 0:3ac96e360672 956
charlesmn 0:3ac96e360672 957 int32_t range_mm_offset;
charlesmn 0:3ac96e360672 958
charlesmn 0:3ac96e360672 959
charlesmn 0:3ac96e360672 960 } VL53L1_offset_range_data_t;
charlesmn 0:3ac96e360672 961
charlesmn 0:3ac96e360672 962
charlesmn 0:3ac96e360672 963
charlesmn 0:3ac96e360672 964
charlesmn 0:3ac96e360672 965 typedef struct {
charlesmn 0:3ac96e360672 966
charlesmn 0:3ac96e360672 967 int16_t cal_distance_mm;
charlesmn 0:3ac96e360672 968
charlesmn 0:3ac96e360672 969 uint16_t cal_reflectance_pc;
charlesmn 0:3ac96e360672 970
charlesmn 0:3ac96e360672 971 VL53L1_Error cal_status;
charlesmn 0:3ac96e360672 972
charlesmn 0:3ac96e360672 973 uint8_t cal_report;
charlesmn 0:3ac96e360672 974
charlesmn 0:3ac96e360672 975 uint8_t max_results;
charlesmn 0:3ac96e360672 976
charlesmn 0:3ac96e360672 977 uint8_t active_results;
charlesmn 0:3ac96e360672 978
charlesmn 0:3ac96e360672 979 VL53L1_offset_range_data_t
charlesmn 0:3ac96e360672 980 VL53L1_p_002[VL53L1_MAX_OFFSET_RANGE_RESULTS];
charlesmn 0:3ac96e360672 981
charlesmn 0:3ac96e360672 982
charlesmn 0:3ac96e360672 983 } VL53L1_offset_range_results_t;
charlesmn 0:3ac96e360672 984
charlesmn 0:3ac96e360672 985
charlesmn 0:3ac96e360672 986
charlesmn 0:3ac96e360672 987
charlesmn 0:3ac96e360672 988 typedef struct {
charlesmn 0:3ac96e360672 989
charlesmn 0:3ac96e360672 990 uint16_t result__mm_inner_actual_effective_spads;
charlesmn 0:3ac96e360672 991
charlesmn 0:3ac96e360672 992 uint16_t result__mm_outer_actual_effective_spads;
charlesmn 0:3ac96e360672 993
charlesmn 0:3ac96e360672 994 uint16_t result__mm_inner_peak_signal_count_rtn_mcps;
charlesmn 0:3ac96e360672 995
charlesmn 0:3ac96e360672 996 uint16_t result__mm_outer_peak_signal_count_rtn_mcps;
charlesmn 0:3ac96e360672 997
charlesmn 0:3ac96e360672 998
charlesmn 0:3ac96e360672 999 } VL53L1_additional_offset_cal_data_t;
charlesmn 0:3ac96e360672 1000
charlesmn 0:3ac96e360672 1001
charlesmn 0:3ac96e360672 1002
charlesmn 0:3ac96e360672 1003 typedef struct {
charlesmn 0:3ac96e360672 1004 int16_t short_a_offset_mm;
charlesmn 0:3ac96e360672 1005 int16_t short_b_offset_mm;
charlesmn 0:3ac96e360672 1006 int16_t medium_a_offset_mm;
charlesmn 0:3ac96e360672 1007 int16_t medium_b_offset_mm;
charlesmn 0:3ac96e360672 1008 int16_t long_a_offset_mm;
charlesmn 0:3ac96e360672 1009 int16_t long_b_offset_mm;
charlesmn 0:3ac96e360672 1010 } VL53L1_per_vcsel_period_offset_cal_data_t;
charlesmn 0:3ac96e360672 1011
charlesmn 0:3ac96e360672 1012
charlesmn 0:3ac96e360672 1013
charlesmn 0:3ac96e360672 1014
charlesmn 0:3ac96e360672 1015
charlesmn 0:3ac96e360672 1016 typedef struct {
charlesmn 0:3ac96e360672 1017
charlesmn 0:3ac96e360672 1018 uint32_t VL53L1_p_020;
charlesmn 0:3ac96e360672 1019
charlesmn 0:3ac96e360672 1020 uint32_t VL53L1_p_021;
charlesmn 0:3ac96e360672 1021
charlesmn 0:3ac96e360672 1022 uint16_t VL53L1_p_014;
charlesmn 0:3ac96e360672 1023
charlesmn 0:3ac96e360672 1024 uint8_t range_status;
charlesmn 0:3ac96e360672 1025
charlesmn 0:3ac96e360672 1026
charlesmn 0:3ac96e360672 1027 } VL53L1_object_data_t;
charlesmn 0:3ac96e360672 1028
charlesmn 0:3ac96e360672 1029
charlesmn 0:3ac96e360672 1030
charlesmn 0:3ac96e360672 1031
charlesmn 0:3ac96e360672 1032 typedef struct {
charlesmn 0:3ac96e360672 1033
charlesmn 0:3ac96e360672 1034 VL53L1_DeviceState cfg_device_state;
charlesmn 0:3ac96e360672 1035
charlesmn 0:3ac96e360672 1036 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 1037
charlesmn 0:3ac96e360672 1038 uint8_t zone_id;
charlesmn 0:3ac96e360672 1039
charlesmn 0:3ac96e360672 1040 uint8_t stream_count;
charlesmn 0:3ac96e360672 1041
charlesmn 0:3ac96e360672 1042 uint8_t max_objects;
charlesmn 0:3ac96e360672 1043
charlesmn 0:3ac96e360672 1044 uint8_t active_objects;
charlesmn 0:3ac96e360672 1045
charlesmn 0:3ac96e360672 1046 VL53L1_object_data_t VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1047
charlesmn 0:3ac96e360672 1048
charlesmn 0:3ac96e360672 1049 VL53L1_object_data_t xmonitor;
charlesmn 0:3ac96e360672 1050
charlesmn 0:3ac96e360672 1051
charlesmn 0:3ac96e360672 1052 } VL53L1_zone_objects_t;
charlesmn 0:3ac96e360672 1053
charlesmn 0:3ac96e360672 1054
charlesmn 0:3ac96e360672 1055
charlesmn 0:3ac96e360672 1056
charlesmn 0:3ac96e360672 1057
charlesmn 0:3ac96e360672 1058
charlesmn 0:3ac96e360672 1059 typedef struct {
charlesmn 0:3ac96e360672 1060
charlesmn 0:3ac96e360672 1061 uint8_t max_zones;
charlesmn 0:3ac96e360672 1062
charlesmn 0:3ac96e360672 1063 uint8_t active_zones;
charlesmn 0:3ac96e360672 1064
charlesmn 0:3ac96e360672 1065 VL53L1_zone_objects_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1066
charlesmn 0:3ac96e360672 1067
charlesmn 0:3ac96e360672 1068 } VL53L1_zone_results_t;
charlesmn 0:3ac96e360672 1069
charlesmn 0:3ac96e360672 1070
charlesmn 0:3ac96e360672 1071
charlesmn 0:3ac96e360672 1072
charlesmn 0:3ac96e360672 1073 typedef struct {
charlesmn 0:3ac96e360672 1074
charlesmn 0:3ac96e360672 1075 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 1076
charlesmn 0:3ac96e360672 1077
charlesmn 0:3ac96e360672 1078 uint8_t number_of_ambient_bins;
charlesmn 0:3ac96e360672 1079
charlesmn 0:3ac96e360672 1080
charlesmn 0:3ac96e360672 1081 uint16_t result__dss_actual_effective_spads;
charlesmn 0:3ac96e360672 1082
charlesmn 0:3ac96e360672 1083 uint8_t VL53L1_p_009;
charlesmn 0:3ac96e360672 1084
charlesmn 0:3ac96e360672 1085 uint32_t total_periods_elapsed;
charlesmn 0:3ac96e360672 1086
charlesmn 0:3ac96e360672 1087
charlesmn 0:3ac96e360672 1088 int32_t ambient_events_sum;
charlesmn 0:3ac96e360672 1089
charlesmn 0:3ac96e360672 1090
charlesmn 0:3ac96e360672 1091 } VL53L1_zone_hist_info_t;
charlesmn 0:3ac96e360672 1092
charlesmn 0:3ac96e360672 1093
charlesmn 0:3ac96e360672 1094
charlesmn 0:3ac96e360672 1095
charlesmn 0:3ac96e360672 1096 typedef struct {
charlesmn 0:3ac96e360672 1097
charlesmn 0:3ac96e360672 1098 uint8_t max_zones;
charlesmn 0:3ac96e360672 1099
charlesmn 0:3ac96e360672 1100 uint8_t active_zones;
charlesmn 0:3ac96e360672 1101
charlesmn 0:3ac96e360672 1102 VL53L1_zone_hist_info_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1103
charlesmn 0:3ac96e360672 1104
charlesmn 0:3ac96e360672 1105 } VL53L1_zone_histograms_t;
charlesmn 0:3ac96e360672 1106
charlesmn 0:3ac96e360672 1107
charlesmn 0:3ac96e360672 1108
charlesmn 0:3ac96e360672 1109
charlesmn 0:3ac96e360672 1110 typedef struct {
charlesmn 0:3ac96e360672 1111
charlesmn 0:3ac96e360672 1112 uint32_t no_of_samples;
charlesmn 0:3ac96e360672 1113
charlesmn 0:3ac96e360672 1114 uint32_t effective_spads;
charlesmn 0:3ac96e360672 1115
charlesmn 0:3ac96e360672 1116 uint32_t peak_rate_mcps;
charlesmn 0:3ac96e360672 1117
charlesmn 0:3ac96e360672 1118 uint32_t VL53L1_p_014;
charlesmn 0:3ac96e360672 1119
charlesmn 0:3ac96e360672 1120 uint32_t VL53L1_p_005;
charlesmn 0:3ac96e360672 1121
charlesmn 0:3ac96e360672 1122 int32_t median_range_mm;
charlesmn 0:3ac96e360672 1123
charlesmn 0:3ac96e360672 1124 int32_t range_mm_offset;
charlesmn 0:3ac96e360672 1125
charlesmn 0:3ac96e360672 1126
charlesmn 0:3ac96e360672 1127 } VL53L1_zone_calibration_data_t;
charlesmn 0:3ac96e360672 1128
charlesmn 0:3ac96e360672 1129
charlesmn 0:3ac96e360672 1130
charlesmn 0:3ac96e360672 1131
charlesmn 0:3ac96e360672 1132
charlesmn 0:3ac96e360672 1133
charlesmn 0:3ac96e360672 1134 typedef struct {
charlesmn 0:3ac96e360672 1135
charlesmn 0:3ac96e360672 1136 uint32_t struct_version;
charlesmn 0:3ac96e360672 1137
charlesmn 0:3ac96e360672 1138 VL53L1_DevicePresetModes preset_mode;
charlesmn 0:3ac96e360672 1139
charlesmn 0:3ac96e360672 1140 VL53L1_DeviceZonePreset zone_preset;
charlesmn 0:3ac96e360672 1141
charlesmn 0:3ac96e360672 1142 int16_t cal_distance_mm;
charlesmn 0:3ac96e360672 1143
charlesmn 0:3ac96e360672 1144 uint16_t cal_reflectance_pc;
charlesmn 0:3ac96e360672 1145
charlesmn 0:3ac96e360672 1146 uint16_t phasecal_result__reference_phase;
charlesmn 0:3ac96e360672 1147
charlesmn 0:3ac96e360672 1148 uint16_t zero_distance_phase;
charlesmn 0:3ac96e360672 1149
charlesmn 0:3ac96e360672 1150 VL53L1_Error cal_status;
charlesmn 0:3ac96e360672 1151
charlesmn 0:3ac96e360672 1152 uint8_t max_zones;
charlesmn 0:3ac96e360672 1153
charlesmn 0:3ac96e360672 1154 uint8_t active_zones;
charlesmn 0:3ac96e360672 1155
charlesmn 0:3ac96e360672 1156 VL53L1_zone_calibration_data_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1157
charlesmn 0:3ac96e360672 1158
charlesmn 0:3ac96e360672 1159 } VL53L1_zone_calibration_results_t;
charlesmn 0:3ac96e360672 1160
charlesmn 0:3ac96e360672 1161
charlesmn 0:3ac96e360672 1162
charlesmn 0:3ac96e360672 1163
charlesmn 0:3ac96e360672 1164
charlesmn 0:3ac96e360672 1165 typedef struct {
charlesmn 0:3ac96e360672 1166
charlesmn 0:3ac96e360672 1167 int16_t cal_distance_mm;
charlesmn 0:3ac96e360672 1168
charlesmn 0:3ac96e360672 1169 uint16_t cal_reflectance_pc;
charlesmn 0:3ac96e360672 1170
charlesmn 0:3ac96e360672 1171 uint16_t max_samples;
charlesmn 0:3ac96e360672 1172
charlesmn 0:3ac96e360672 1173 uint16_t width;
charlesmn 0:3ac96e360672 1174
charlesmn 0:3ac96e360672 1175 uint16_t height;
charlesmn 0:3ac96e360672 1176
charlesmn 0:3ac96e360672 1177 uint16_t peak_rate_mcps[VL53L1_NVM_PEAK_RATE_MAP_SAMPLES];
charlesmn 0:3ac96e360672 1178
charlesmn 0:3ac96e360672 1179
charlesmn 0:3ac96e360672 1180 } VL53L1_cal_peak_rate_map_t;
charlesmn 0:3ac96e360672 1181
charlesmn 0:3ac96e360672 1182
charlesmn 0:3ac96e360672 1183
charlesmn 0:3ac96e360672 1184
charlesmn 0:3ac96e360672 1185 typedef struct {
charlesmn 0:3ac96e360672 1186
charlesmn 0:3ac96e360672 1187 uint8_t expected_stream_count;
charlesmn 0:3ac96e360672 1188
charlesmn 0:3ac96e360672 1189 uint8_t expected_gph_id;
charlesmn 0:3ac96e360672 1190
charlesmn 0:3ac96e360672 1191 uint8_t dss_mode;
charlesmn 0:3ac96e360672 1192
charlesmn 0:3ac96e360672 1193 uint16_t dss_requested_effective_spad_count;
charlesmn 0:3ac96e360672 1194
charlesmn 0:3ac96e360672 1195 uint8_t seed_cfg;
charlesmn 0:3ac96e360672 1196
charlesmn 0:3ac96e360672 1197 uint8_t initial_phase_seed;
charlesmn 0:3ac96e360672 1198
charlesmn 0:3ac96e360672 1199
charlesmn 0:3ac96e360672 1200 uint8_t roi_config__user_roi_centre_spad;
charlesmn 0:3ac96e360672 1201
charlesmn 0:3ac96e360672 1202 uint8_t roi_config__user_roi_requested_global_xy_size;
charlesmn 0:3ac96e360672 1203
charlesmn 0:3ac96e360672 1204
charlesmn 0:3ac96e360672 1205 } VL53L1_zone_private_dyn_cfg_t;
charlesmn 0:3ac96e360672 1206
charlesmn 0:3ac96e360672 1207
charlesmn 0:3ac96e360672 1208
charlesmn 0:3ac96e360672 1209
charlesmn 0:3ac96e360672 1210 typedef struct {
charlesmn 0:3ac96e360672 1211
charlesmn 0:3ac96e360672 1212 uint8_t max_zones;
charlesmn 0:3ac96e360672 1213
charlesmn 0:3ac96e360672 1214 uint8_t active_zones;
charlesmn 0:3ac96e360672 1215
charlesmn 0:3ac96e360672 1216 VL53L1_zone_private_dyn_cfg_t VL53L1_p_002[VL53L1_MAX_USER_ZONES];
charlesmn 0:3ac96e360672 1217
charlesmn 0:3ac96e360672 1218
charlesmn 0:3ac96e360672 1219 } VL53L1_zone_private_dyn_cfgs_t;
charlesmn 0:3ac96e360672 1220
charlesmn 0:3ac96e360672 1221
charlesmn 0:3ac96e360672 1222
charlesmn 0:3ac96e360672 1223 typedef struct {
charlesmn 0:3ac96e360672 1224
charlesmn 0:3ac96e360672 1225 uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn 0:3ac96e360672 1226
charlesmn 0:3ac96e360672 1227 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn 0:3ac96e360672 1228
charlesmn 0:3ac96e360672 1229 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn 0:3ac96e360672 1230
charlesmn 0:3ac96e360672 1231 uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53L1_BIN_REC_SIZE];
charlesmn 0:3ac96e360672 1232
charlesmn 0:3ac96e360672 1233
charlesmn 0:3ac96e360672 1234 } VL53L1_xtalk_calibration_results_t;
charlesmn 0:3ac96e360672 1235
charlesmn 0:3ac96e360672 1236
charlesmn 0:3ac96e360672 1237
charlesmn 0:3ac96e360672 1238
charlesmn 0:3ac96e360672 1239 typedef struct {
charlesmn 0:3ac96e360672 1240
charlesmn 0:3ac96e360672 1241
charlesmn 0:3ac96e360672 1242 uint32_t sample_count;
charlesmn 0:3ac96e360672 1243
charlesmn 0:3ac96e360672 1244
charlesmn 0:3ac96e360672 1245 uint32_t pll_period_mm;
charlesmn 0:3ac96e360672 1246
charlesmn 0:3ac96e360672 1247
charlesmn 0:3ac96e360672 1248 uint32_t peak_duration_us_sum;
charlesmn 0:3ac96e360672 1249
charlesmn 0:3ac96e360672 1250
charlesmn 0:3ac96e360672 1251 uint32_t effective_spad_count_sum;
charlesmn 0:3ac96e360672 1252
charlesmn 0:3ac96e360672 1253
charlesmn 0:3ac96e360672 1254 uint32_t zero_distance_phase_sum;
charlesmn 0:3ac96e360672 1255
charlesmn 0:3ac96e360672 1256
charlesmn 0:3ac96e360672 1257 uint32_t zero_distance_phase_avg;
charlesmn 0:3ac96e360672 1258
charlesmn 0:3ac96e360672 1259
charlesmn 0:3ac96e360672 1260 int32_t event_scaler_sum;
charlesmn 0:3ac96e360672 1261
charlesmn 0:3ac96e360672 1262
charlesmn 0:3ac96e360672 1263 int32_t event_scaler_avg;
charlesmn 0:3ac96e360672 1264
charlesmn 0:3ac96e360672 1265
charlesmn 0:3ac96e360672 1266 int32_t signal_events_sum;
charlesmn 0:3ac96e360672 1267
charlesmn 0:3ac96e360672 1268
charlesmn 0:3ac96e360672 1269 uint32_t xtalk_rate_kcps_per_spad;
charlesmn 0:3ac96e360672 1270
charlesmn 0:3ac96e360672 1271
charlesmn 0:3ac96e360672 1272 int32_t xtalk_start_phase;
charlesmn 0:3ac96e360672 1273
charlesmn 0:3ac96e360672 1274
charlesmn 0:3ac96e360672 1275 int32_t xtalk_end_phase;
charlesmn 0:3ac96e360672 1276
charlesmn 0:3ac96e360672 1277
charlesmn 0:3ac96e360672 1278 int32_t xtalk_width_phase;
charlesmn 0:3ac96e360672 1279
charlesmn 0:3ac96e360672 1280
charlesmn 0:3ac96e360672 1281 int32_t target_start_phase;
charlesmn 0:3ac96e360672 1282
charlesmn 0:3ac96e360672 1283
charlesmn 0:3ac96e360672 1284 int32_t target_end_phase;
charlesmn 0:3ac96e360672 1285
charlesmn 0:3ac96e360672 1286
charlesmn 0:3ac96e360672 1287 int32_t target_width_phase;
charlesmn 0:3ac96e360672 1288
charlesmn 0:3ac96e360672 1289
charlesmn 0:3ac96e360672 1290 int32_t effective_width;
charlesmn 0:3ac96e360672 1291
charlesmn 0:3ac96e360672 1292
charlesmn 0:3ac96e360672 1293 int32_t event_scaler;
charlesmn 0:3ac96e360672 1294
charlesmn 0:3ac96e360672 1295
charlesmn 0:3ac96e360672 1296 uint8_t VL53L1_p_015;
charlesmn 0:3ac96e360672 1297
charlesmn 0:3ac96e360672 1298
charlesmn 0:3ac96e360672 1299 uint8_t VL53L1_p_016;
charlesmn 0:3ac96e360672 1300
charlesmn 0:3ac96e360672 1301
charlesmn 0:3ac96e360672 1302 uint8_t target_start;
charlesmn 0:3ac96e360672 1303
charlesmn 0:3ac96e360672 1304
charlesmn 0:3ac96e360672 1305 int32_t max_shape_value;
charlesmn 0:3ac96e360672 1306
charlesmn 0:3ac96e360672 1307
charlesmn 0:3ac96e360672 1308 int32_t bin_data_sums[VL53L1_XTALK_HISTO_BINS];
charlesmn 0:3ac96e360672 1309
charlesmn 0:3ac96e360672 1310 } VL53L1_hist_xtalk_extract_data_t;
charlesmn 0:3ac96e360672 1311
charlesmn 0:3ac96e360672 1312
charlesmn 0:3ac96e360672 1313
charlesmn 0:3ac96e360672 1314
charlesmn 0:3ac96e360672 1315 typedef struct {
charlesmn 0:3ac96e360672 1316
charlesmn 0:3ac96e360672 1317 uint16_t standard_ranging_gain_factor;
charlesmn 0:3ac96e360672 1318
charlesmn 0:3ac96e360672 1319 uint16_t histogram_ranging_gain_factor;
charlesmn 0:3ac96e360672 1320
charlesmn 0:3ac96e360672 1321
charlesmn 0:3ac96e360672 1322 } VL53L1_gain_calibration_data_t;
charlesmn 0:3ac96e360672 1323
charlesmn 0:3ac96e360672 1324
charlesmn 0:3ac96e360672 1325
charlesmn 0:3ac96e360672 1326
charlesmn 0:3ac96e360672 1327 typedef struct {
charlesmn 0:3ac96e360672 1328
charlesmn 0:3ac96e360672 1329 VL53L1_DeviceState cfg_device_state;
charlesmn 0:3ac96e360672 1330
charlesmn 0:3ac96e360672 1331 uint8_t cfg_stream_count;
charlesmn 0:3ac96e360672 1332
charlesmn 0:3ac96e360672 1333 uint8_t cfg_internal_stream_count;
charlesmn 0:3ac96e360672 1334
charlesmn 0:3ac96e360672 1335 uint8_t cfg_internal_stream_count_val;
charlesmn 0:3ac96e360672 1336
charlesmn 0:3ac96e360672 1337 uint8_t cfg_gph_id;
charlesmn 0:3ac96e360672 1338
charlesmn 0:3ac96e360672 1339 uint8_t cfg_timing_status;
charlesmn 0:3ac96e360672 1340
charlesmn 0:3ac96e360672 1341 uint8_t cfg_zone_id;
charlesmn 0:3ac96e360672 1342
charlesmn 0:3ac96e360672 1343
charlesmn 0:3ac96e360672 1344 VL53L1_DeviceState rd_device_state;
charlesmn 0:3ac96e360672 1345
charlesmn 0:3ac96e360672 1346 uint8_t rd_stream_count;
charlesmn 0:3ac96e360672 1347
charlesmn 0:3ac96e360672 1348 uint8_t rd_internal_stream_count;
charlesmn 0:3ac96e360672 1349
charlesmn 0:3ac96e360672 1350 uint8_t rd_internal_stream_count_val;
charlesmn 0:3ac96e360672 1351
charlesmn 0:3ac96e360672 1352 uint8_t rd_gph_id;
charlesmn 0:3ac96e360672 1353
charlesmn 0:3ac96e360672 1354 uint8_t rd_timing_status;
charlesmn 0:3ac96e360672 1355
charlesmn 0:3ac96e360672 1356 uint8_t rd_zone_id;
charlesmn 0:3ac96e360672 1357
charlesmn 0:3ac96e360672 1358
charlesmn 0:3ac96e360672 1359 } VL53L1_ll_driver_state_t;
charlesmn 0:3ac96e360672 1360
charlesmn 0:3ac96e360672 1361
charlesmn 0:3ac96e360672 1362
charlesmn 0:3ac96e360672 1363
charlesmn 0:3ac96e360672 1364 typedef struct {
charlesmn 0:3ac96e360672 1365
charlesmn 0:3ac96e360672 1366 uint8_t wait_method;
charlesmn 0:3ac96e360672 1367
charlesmn 0:3ac96e360672 1368 VL53L1_DevicePresetModes preset_mode;
charlesmn 0:3ac96e360672 1369
charlesmn 0:3ac96e360672 1370 VL53L1_DeviceZonePreset zone_preset;
charlesmn 0:3ac96e360672 1371
charlesmn 0:3ac96e360672 1372 VL53L1_DeviceMeasurementModes measurement_mode;
charlesmn 0:3ac96e360672 1373
charlesmn 0:3ac96e360672 1374 VL53L1_OffsetCalibrationMode offset_calibration_mode;
charlesmn 0:3ac96e360672 1375
charlesmn 0:3ac96e360672 1376 VL53L1_OffsetCorrectionMode offset_correction_mode;
charlesmn 0:3ac96e360672 1377
charlesmn 0:3ac96e360672 1378 VL53L1_DeviceDmaxMode dmax_mode;
charlesmn 0:3ac96e360672 1379
charlesmn 0:3ac96e360672 1380 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1381
charlesmn 0:3ac96e360672 1382 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 1383
charlesmn 0:3ac96e360672 1384 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 1385
charlesmn 0:3ac96e360672 1386 uint32_t inter_measurement_period_ms;
charlesmn 0:3ac96e360672 1387
charlesmn 0:3ac96e360672 1388 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 1389
charlesmn 0:3ac96e360672 1390 uint32_t fw_ready_poll_duration_ms;
charlesmn 0:3ac96e360672 1391
charlesmn 0:3ac96e360672 1392 uint8_t fw_ready;
charlesmn 0:3ac96e360672 1393
charlesmn 0:3ac96e360672 1394 uint8_t debug_mode;
charlesmn 0:3ac96e360672 1395
charlesmn 0:3ac96e360672 1396
charlesmn 0:3ac96e360672 1397
charlesmn 0:3ac96e360672 1398 VL53L1_ll_version_t version;
charlesmn 0:3ac96e360672 1399
charlesmn 0:3ac96e360672 1400
charlesmn 0:3ac96e360672 1401 VL53L1_ll_driver_state_t ll_state;
charlesmn 0:3ac96e360672 1402
charlesmn 0:3ac96e360672 1403
charlesmn 0:3ac96e360672 1404 VL53L1_GPIO_interrupt_config_t gpio_interrupt_config;
charlesmn 0:3ac96e360672 1405
charlesmn 0:3ac96e360672 1406
charlesmn 0:3ac96e360672 1407 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1408 VL53L1_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn 0:3ac96e360672 1409 VL53L1_additional_offset_cal_data_t add_off_cal_data;
charlesmn 0:3ac96e360672 1410 VL53L1_dmax_calibration_data_t fmt_dmax_cal;
charlesmn 0:3ac96e360672 1411 VL53L1_dmax_calibration_data_t cust_dmax_cal;
charlesmn 0:3ac96e360672 1412 VL53L1_gain_calibration_data_t gain_cal;
charlesmn 0:3ac96e360672 1413 VL53L1_user_zone_t mm_roi;
charlesmn 0:3ac96e360672 1414 VL53L1_optical_centre_t optical_centre;
charlesmn 0:3ac96e360672 1415 VL53L1_zone_config_t zone_cfg;
charlesmn 0:3ac96e360672 1416
charlesmn 0:3ac96e360672 1417
charlesmn 0:3ac96e360672 1418 VL53L1_tuning_parm_storage_t tuning_parms;
charlesmn 0:3ac96e360672 1419
charlesmn 0:3ac96e360672 1420
charlesmn 0:3ac96e360672 1421 uint8_t rtn_good_spads[VL53L1_RTN_SPAD_BUFFER_SIZE];
charlesmn 0:3ac96e360672 1422
charlesmn 0:3ac96e360672 1423
charlesmn 0:3ac96e360672 1424 VL53L1_refspadchar_config_t refspadchar;
charlesmn 0:3ac96e360672 1425 VL53L1_ssc_config_t ssc_cfg;
charlesmn 0:3ac96e360672 1426 VL53L1_hist_post_process_config_t histpostprocess;
charlesmn 0:3ac96e360672 1427 VL53L1_hist_gen3_dmax_config_t dmax_cfg;
charlesmn 0:3ac96e360672 1428 VL53L1_xtalkextract_config_t xtalk_extract_cfg;
charlesmn 0:3ac96e360672 1429 VL53L1_xtalk_config_t xtalk_cfg;
charlesmn 0:3ac96e360672 1430 VL53L1_offsetcal_config_t offsetcal_cfg;
charlesmn 0:3ac96e360672 1431 VL53L1_zonecal_config_t zonecal_cfg;
charlesmn 0:3ac96e360672 1432
charlesmn 0:3ac96e360672 1433
charlesmn 0:3ac96e360672 1434 VL53L1_static_nvm_managed_t stat_nvm;
charlesmn 0:3ac96e360672 1435 VL53L1_histogram_config_t hist_cfg;
charlesmn 0:3ac96e360672 1436 VL53L1_static_config_t stat_cfg;
charlesmn 0:3ac96e360672 1437 VL53L1_general_config_t gen_cfg;
charlesmn 0:3ac96e360672 1438 VL53L1_timing_config_t tim_cfg;
charlesmn 0:3ac96e360672 1439 VL53L1_dynamic_config_t dyn_cfg;
charlesmn 0:3ac96e360672 1440 VL53L1_system_control_t sys_ctrl;
charlesmn 0:3ac96e360672 1441 VL53L1_system_results_t sys_results;
charlesmn 0:3ac96e360672 1442 VL53L1_nvm_copy_data_t nvm_copy_data;
charlesmn 0:3ac96e360672 1443
charlesmn 0:3ac96e360672 1444
charlesmn 0:3ac96e360672 1445 VL53L1_histogram_bin_data_t hist_data;
charlesmn 0:3ac96e360672 1446 VL53L1_histogram_bin_data_t hist_xtalk;
charlesmn 0:3ac96e360672 1447
charlesmn 0:3ac96e360672 1448
charlesmn 0:3ac96e360672 1449 VL53L1_xtalk_histogram_data_t xtalk_shapes;
charlesmn 0:3ac96e360672 1450 VL53L1_xtalk_range_results_t xtalk_results;
charlesmn 0:3ac96e360672 1451 VL53L1_xtalk_calibration_results_t xtalk_cal;
charlesmn 0:3ac96e360672 1452 VL53L1_hist_xtalk_extract_data_t xtalk_extract;
charlesmn 0:3ac96e360672 1453
charlesmn 0:3ac96e360672 1454
charlesmn 0:3ac96e360672 1455 VL53L1_offset_range_results_t offset_results;
charlesmn 0:3ac96e360672 1456
charlesmn 0:3ac96e360672 1457
charlesmn 0:3ac96e360672 1458 VL53L1_core_results_t core_results;
charlesmn 0:3ac96e360672 1459 VL53L1_debug_results_t dbg_results;
charlesmn 0:3ac96e360672 1460
charlesmn 0:3ac96e360672 1461 VL53L1_smudge_corrector_config_t smudge_correct_config;
charlesmn 0:3ac96e360672 1462
charlesmn 0:3ac96e360672 1463 VL53L1_smudge_corrector_internals_t smudge_corrector_internals;
charlesmn 0:3ac96e360672 1464
charlesmn 0:3ac96e360672 1465
charlesmn 0:3ac96e360672 1466
charlesmn 0:3ac96e360672 1467
charlesmn 0:3ac96e360672 1468 VL53L1_low_power_auto_data_t low_power_auto_data;
charlesmn 0:3ac96e360672 1469
charlesmn 0:3ac96e360672 1470
charlesmn 0:3ac96e360672 1471 #ifdef PAL_EXTENDED
charlesmn 0:3ac96e360672 1472
charlesmn 0:3ac96e360672 1473 VL53L1_patch_results_t patch_results;
charlesmn 0:3ac96e360672 1474 VL53L1_shadow_core_results_t shadow_core_results;
charlesmn 0:3ac96e360672 1475 VL53L1_shadow_system_results_t shadow_sys_results;
charlesmn 0:3ac96e360672 1476 VL53L1_prev_shadow_core_results_t prev_shadow_core_results;
charlesmn 0:3ac96e360672 1477 VL53L1_prev_shadow_system_results_t prev_shadow_sys_results;
charlesmn 0:3ac96e360672 1478 #endif
charlesmn 0:3ac96e360672 1479 uint8_t wArea1[1536];
charlesmn 0:3ac96e360672 1480 uint8_t wArea2[512];
charlesmn 0:3ac96e360672 1481 VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn 0:3ac96e360672 1482
charlesmn 0:3ac96e360672 1483 uint8_t bin_rec_pos;
charlesmn 0:3ac96e360672 1484
charlesmn 0:3ac96e360672 1485 uint8_t pos_before_next_recom;
charlesmn 0:3ac96e360672 1486
charlesmn 0:3ac96e360672 1487 int32_t multi_bins_rec[VL53L1_BIN_REC_SIZE]
charlesmn 0:3ac96e360672 1488 [VL53L1_TIMING_CONF_A_B_SIZE][VL53L1_HISTOGRAM_BUFFER_SIZE];
charlesmn 0:3ac96e360672 1489
charlesmn 0:3ac96e360672 1490 int16_t PreviousRangeMilliMeter[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1491 uint8_t PreviousRangeStatus[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1492 uint8_t PreviousExtendedRange[VL53L1_MAX_RANGE_RESULTS];
charlesmn 0:3ac96e360672 1493 uint8_t PreviousStreamCount;
charlesmn 0:3ac96e360672 1494
charlesmn 0:3ac96e360672 1495 } VL53L1_LLDriverData_t;
charlesmn 0:3ac96e360672 1496
charlesmn 0:3ac96e360672 1497
charlesmn 0:3ac96e360672 1498
charlesmn 0:3ac96e360672 1499
charlesmn 0:3ac96e360672 1500 typedef struct {
charlesmn 0:3ac96e360672 1501
charlesmn 0:3ac96e360672 1502
charlesmn 0:3ac96e360672 1503 VL53L1_range_results_t range_results;
charlesmn 0:3ac96e360672 1504
charlesmn 0:3ac96e360672 1505
charlesmn 0:3ac96e360672 1506 VL53L1_zone_private_dyn_cfgs_t zone_dyn_cfgs;
charlesmn 0:3ac96e360672 1507
charlesmn 0:3ac96e360672 1508
charlesmn 0:3ac96e360672 1509 VL53L1_zone_results_t zone_results;
charlesmn 0:3ac96e360672 1510 VL53L1_zone_histograms_t zone_hists;
charlesmn 0:3ac96e360672 1511 VL53L1_zone_calibration_results_t zone_cal;
charlesmn 0:3ac96e360672 1512
charlesmn 0:3ac96e360672 1513 } VL53L1_LLDriverResults_t;
charlesmn 0:3ac96e360672 1514
charlesmn 0:3ac96e360672 1515
charlesmn 0:3ac96e360672 1516
charlesmn 0:3ac96e360672 1517
charlesmn 0:3ac96e360672 1518 typedef struct {
charlesmn 0:3ac96e360672 1519
charlesmn 0:3ac96e360672 1520 uint32_t struct_version;
charlesmn 0:3ac96e360672 1521 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1522 VL53L1_dmax_calibration_data_t fmt_dmax_cal;
charlesmn 0:3ac96e360672 1523 VL53L1_dmax_calibration_data_t cust_dmax_cal;
charlesmn 0:3ac96e360672 1524 VL53L1_additional_offset_cal_data_t add_off_cal_data;
charlesmn 0:3ac96e360672 1525 VL53L1_optical_centre_t optical_centre;
charlesmn 0:3ac96e360672 1526 VL53L1_xtalk_histogram_data_t xtalkhisto;
charlesmn 0:3ac96e360672 1527 VL53L1_gain_calibration_data_t gain_cal;
charlesmn 0:3ac96e360672 1528 VL53L1_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn 0:3ac96e360672 1529 VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn 0:3ac96e360672 1530
charlesmn 0:3ac96e360672 1531 } VL53L1_calibration_data_t;
charlesmn 0:3ac96e360672 1532
charlesmn 0:3ac96e360672 1533
charlesmn 0:3ac96e360672 1534
charlesmn 0:3ac96e360672 1535
charlesmn 0:3ac96e360672 1536 typedef struct {
charlesmn 0:3ac96e360672 1537
charlesmn 0:3ac96e360672 1538 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1539 VL53L1_xtalkextract_config_t xtalk_extract_cfg;
charlesmn 0:3ac96e360672 1540 VL53L1_xtalk_config_t xtalk_cfg;
charlesmn 0:3ac96e360672 1541 VL53L1_histogram_bin_data_t hist_data;
charlesmn 0:3ac96e360672 1542 VL53L1_xtalk_histogram_data_t xtalk_shapes;
charlesmn 0:3ac96e360672 1543 VL53L1_xtalk_range_results_t xtalk_results;
charlesmn 0:3ac96e360672 1544
charlesmn 0:3ac96e360672 1545 } VL53L1_xtalk_debug_data_t;
charlesmn 0:3ac96e360672 1546
charlesmn 0:3ac96e360672 1547
charlesmn 0:3ac96e360672 1548
charlesmn 0:3ac96e360672 1549
charlesmn 0:3ac96e360672 1550 typedef struct {
charlesmn 0:3ac96e360672 1551
charlesmn 0:3ac96e360672 1552 VL53L1_customer_nvm_managed_t customer;
charlesmn 0:3ac96e360672 1553 VL53L1_dmax_calibration_data_t fmt_dmax_cal;
charlesmn 0:3ac96e360672 1554 VL53L1_dmax_calibration_data_t cust_dmax_cal;
charlesmn 0:3ac96e360672 1555 VL53L1_additional_offset_cal_data_t add_off_cal_data;
charlesmn 0:3ac96e360672 1556 VL53L1_offset_range_results_t offset_results;
charlesmn 0:3ac96e360672 1557
charlesmn 0:3ac96e360672 1558 } VL53L1_offset_debug_data_t;
charlesmn 0:3ac96e360672 1559
charlesmn 0:3ac96e360672 1560
charlesmn 0:3ac96e360672 1561
charlesmn 0:3ac96e360672 1562
charlesmn 0:3ac96e360672 1563 typedef struct {
charlesmn 0:3ac96e360672 1564 uint16_t vl53l1_tuningparm_version;
charlesmn 0:3ac96e360672 1565 uint16_t vl53l1_tuningparm_key_table_version;
charlesmn 0:3ac96e360672 1566 uint16_t vl53l1_tuningparm_lld_version;
charlesmn 0:3ac96e360672 1567 uint8_t vl53l1_tuningparm_hist_algo_select;
charlesmn 0:3ac96e360672 1568 uint8_t vl53l1_tuningparm_hist_target_order;
charlesmn 0:3ac96e360672 1569 uint8_t vl53l1_tuningparm_hist_filter_woi_0;
charlesmn 0:3ac96e360672 1570 uint8_t vl53l1_tuningparm_hist_filter_woi_1;
charlesmn 0:3ac96e360672 1571 uint8_t vl53l1_tuningparm_hist_amb_est_method;
charlesmn 0:3ac96e360672 1572 uint8_t vl53l1_tuningparm_hist_amb_thresh_sigma_0;
charlesmn 0:3ac96e360672 1573 uint8_t vl53l1_tuningparm_hist_amb_thresh_sigma_1;
charlesmn 0:3ac96e360672 1574 int32_t vl53l1_tuningparm_hist_min_amb_thresh_events;
charlesmn 0:3ac96e360672 1575 uint16_t vl53l1_tuningparm_hist_amb_events_scaler;
charlesmn 0:3ac96e360672 1576 uint16_t vl53l1_tuningparm_hist_noise_threshold;
charlesmn 0:3ac96e360672 1577 int32_t vl53l1_tuningparm_hist_signal_total_events_limit;
charlesmn 0:3ac96e360672 1578 uint8_t vl53l1_tuningparm_hist_sigma_est_ref_mm;
charlesmn 0:3ac96e360672 1579 uint16_t vl53l1_tuningparm_hist_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1580 uint16_t vl53l1_tuningparm_hist_gain_factor;
charlesmn 0:3ac96e360672 1581 uint8_t vl53l1_tuningparm_consistency_hist_phase_tolerance;
charlesmn 0:3ac96e360672 1582 uint16_t vl53l1_tuningparm_consistency_hist_min_max_tolerance_mm;
charlesmn 0:3ac96e360672 1583 uint8_t vl53l1_tuningparm_consistency_hist_event_sigma;
charlesmn 0:3ac96e360672 1584 uint16_t vl53l1_tuningparm_consistency_hist_event_sigma_min_spad_limit;
charlesmn 0:3ac96e360672 1585 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_long_range;
charlesmn 0:3ac96e360672 1586 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_med_range;
charlesmn 0:3ac96e360672 1587 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_short_range;
charlesmn 0:3ac96e360672 1588 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_long_range;
charlesmn 0:3ac96e360672 1589 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_med_range;
charlesmn 0:3ac96e360672 1590 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_short_range;
charlesmn 0:3ac96e360672 1591 int16_t vl53l1_tuningparm_xtalk_detect_min_valid_range_mm;
charlesmn 0:3ac96e360672 1592 int16_t vl53l1_tuningparm_xtalk_detect_max_valid_range_mm;
charlesmn 0:3ac96e360672 1593 uint16_t vl53l1_tuningparm_xtalk_detect_max_sigma_mm;
charlesmn 0:3ac96e360672 1594 uint16_t vl53l1_tuningparm_xtalk_detect_min_max_tolerance;
charlesmn 0:3ac96e360672 1595 uint16_t vl53l1_tuningparm_xtalk_detect_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 1596 uint8_t vl53l1_tuningparm_xtalk_detect_event_sigma;
charlesmn 0:3ac96e360672 1597 int16_t vl53l1_tuningparm_hist_xtalk_margin_kcps;
charlesmn 0:3ac96e360672 1598 uint8_t vl53l1_tuningparm_consistency_lite_phase_tolerance;
charlesmn 0:3ac96e360672 1599 uint8_t vl53l1_tuningparm_phasecal_target;
charlesmn 0:3ac96e360672 1600 uint16_t vl53l1_tuningparm_lite_cal_repeat_rate;
charlesmn 0:3ac96e360672 1601 uint16_t vl53l1_tuningparm_lite_ranging_gain_factor;
charlesmn 0:3ac96e360672 1602 uint8_t vl53l1_tuningparm_lite_min_clip_mm;
charlesmn 0:3ac96e360672 1603 uint16_t vl53l1_tuningparm_lite_long_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1604 uint16_t vl53l1_tuningparm_lite_med_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1605 uint16_t vl53l1_tuningparm_lite_short_sigma_thresh_mm;
charlesmn 0:3ac96e360672 1606 uint16_t vl53l1_tuningparm_lite_long_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 1607 uint16_t vl53l1_tuningparm_lite_med_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 1608 uint16_t vl53l1_tuningparm_lite_short_min_count_rate_rtn_mcps;
charlesmn 0:3ac96e360672 1609 uint8_t vl53l1_tuningparm_lite_sigma_est_pulse_width;
charlesmn 0:3ac96e360672 1610 uint8_t vl53l1_tuningparm_lite_sigma_est_amb_width_ns;
charlesmn 0:3ac96e360672 1611 uint8_t vl53l1_tuningparm_lite_sigma_ref_mm;
charlesmn 0:3ac96e360672 1612 uint8_t vl53l1_tuningparm_lite_rit_mult;
charlesmn 0:3ac96e360672 1613 uint8_t vl53l1_tuningparm_lite_seed_config;
charlesmn 0:3ac96e360672 1614 uint8_t vl53l1_tuningparm_lite_quantifier;
charlesmn 0:3ac96e360672 1615 uint8_t vl53l1_tuningparm_lite_first_order_select;
charlesmn 0:3ac96e360672 1616 int16_t vl53l1_tuningparm_lite_xtalk_margin_kcps;
charlesmn 0:3ac96e360672 1617 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_long_range;
charlesmn 0:3ac96e360672 1618 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_med_range;
charlesmn 0:3ac96e360672 1619 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_short_range;
charlesmn 0:3ac96e360672 1620 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_long_range;
charlesmn 0:3ac96e360672 1621 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_med_range;
charlesmn 0:3ac96e360672 1622 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_short_range;
charlesmn 0:3ac96e360672 1623 uint8_t vl53l1_tuningparm_timed_seed_config;
charlesmn 0:3ac96e360672 1624 uint8_t vl53l1_tuningparm_dmax_cfg_signal_thresh_sigma;
charlesmn 0:3ac96e360672 1625 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_0;
charlesmn 0:3ac96e360672 1626 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_1;
charlesmn 0:3ac96e360672 1627 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_2;
charlesmn 0:3ac96e360672 1628 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_3;
charlesmn 0:3ac96e360672 1629 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_4;
charlesmn 0:3ac96e360672 1630 uint8_t vl53l1_tuningparm_vhv_loopbound;
charlesmn 0:3ac96e360672 1631 uint8_t vl53l1_tuningparm_refspadchar_device_test_mode;
charlesmn 0:3ac96e360672 1632 uint8_t vl53l1_tuningparm_refspadchar_vcsel_period;
charlesmn 0:3ac96e360672 1633 uint32_t vl53l1_tuningparm_refspadchar_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1634 uint16_t vl53l1_tuningparm_refspadchar_target_count_rate_mcps;
charlesmn 0:3ac96e360672 1635 uint16_t vl53l1_tuningparm_refspadchar_min_countrate_limit_mcps;
charlesmn 0:3ac96e360672 1636 uint16_t vl53l1_tuningparm_refspadchar_max_countrate_limit_mcps;
charlesmn 0:3ac96e360672 1637 uint8_t vl53l1_tuningparm_xtalk_extract_num_of_samples;
charlesmn 0:3ac96e360672 1638 int16_t vl53l1_tuningparm_xtalk_extract_min_filter_thresh_mm;
charlesmn 0:3ac96e360672 1639 int16_t vl53l1_tuningparm_xtalk_extract_max_filter_thresh_mm;
charlesmn 0:3ac96e360672 1640 uint16_t vl53l1_tuningparm_xtalk_extract_dss_rate_mcps;
charlesmn 0:3ac96e360672 1641 uint32_t vl53l1_tuningparm_xtalk_extract_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1642 uint16_t vl53l1_tuningparm_xtalk_extract_max_valid_rate_kcps;
charlesmn 0:3ac96e360672 1643 uint16_t vl53l1_tuningparm_xtalk_extract_sigma_threshold_mm;
charlesmn 0:3ac96e360672 1644 uint32_t vl53l1_tuningparm_xtalk_extract_dss_timeout_us;
charlesmn 0:3ac96e360672 1645 uint32_t vl53l1_tuningparm_xtalk_extract_bin_timeout_us;
charlesmn 0:3ac96e360672 1646 uint16_t vl53l1_tuningparm_offset_cal_dss_rate_mcps;
charlesmn 0:3ac96e360672 1647 uint32_t vl53l1_tuningparm_offset_cal_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1648 uint32_t vl53l1_tuningparm_offset_cal_mm_timeout_us;
charlesmn 0:3ac96e360672 1649 uint32_t vl53l1_tuningparm_offset_cal_range_timeout_us;
charlesmn 0:3ac96e360672 1650 uint8_t vl53l1_tuningparm_offset_cal_pre_samples;
charlesmn 0:3ac96e360672 1651 uint8_t vl53l1_tuningparm_offset_cal_mm1_samples;
charlesmn 0:3ac96e360672 1652 uint8_t vl53l1_tuningparm_offset_cal_mm2_samples;
charlesmn 0:3ac96e360672 1653 uint16_t vl53l1_tuningparm_zone_cal_dss_rate_mcps;
charlesmn 0:3ac96e360672 1654 uint32_t vl53l1_tuningparm_zone_cal_phasecal_timeout_us;
charlesmn 0:3ac96e360672 1655 uint32_t vl53l1_tuningparm_zone_cal_dss_timeout_us;
charlesmn 0:3ac96e360672 1656 uint16_t vl53l1_tuningparm_zone_cal_phasecal_num_samples;
charlesmn 0:3ac96e360672 1657 uint32_t vl53l1_tuningparm_zone_cal_range_timeout_us;
charlesmn 0:3ac96e360672 1658 uint16_t vl53l1_tuningparm_zone_cal_zone_num_samples;
charlesmn 0:3ac96e360672 1659 uint8_t vl53l1_tuningparm_spadmap_vcsel_period;
charlesmn 0:3ac96e360672 1660 uint8_t vl53l1_tuningparm_spadmap_vcsel_start;
charlesmn 0:3ac96e360672 1661 uint16_t vl53l1_tuningparm_spadmap_rate_limit_mcps;
charlesmn 0:3ac96e360672 1662 uint16_t vl53l1_tuningparm_lite_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1663 uint16_t vl53l1_tuningparm_ranging_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1664 uint16_t vl53l1_tuningparm_mz_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1665 uint16_t vl53l1_tuningparm_timed_dss_config_target_total_rate_mcps;
charlesmn 0:3ac96e360672 1666 uint32_t vl53l1_tuningparm_lite_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1667 uint32_t vl53l1_tuningparm_ranging_long_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1668 uint32_t vl53l1_tuningparm_ranging_med_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1669 uint32_t vl53l1_tuningparm_ranging_short_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1670 uint32_t vl53l1_tuningparm_mz_long_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1671 uint32_t vl53l1_tuningparm_mz_med_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1672 uint32_t vl53l1_tuningparm_mz_short_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1673 uint32_t vl53l1_tuningparm_timed_phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1674 uint32_t vl53l1_tuningparm_lite_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1675 uint32_t vl53l1_tuningparm_ranging_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1676 uint32_t vl53l1_tuningparm_mz_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1677 uint32_t vl53l1_tuningparm_timed_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1678 uint32_t vl53l1_tuningparm_lite_range_config_timeout_us;
charlesmn 0:3ac96e360672 1679 uint32_t vl53l1_tuningparm_ranging_range_config_timeout_us;
charlesmn 0:3ac96e360672 1680 uint32_t vl53l1_tuningparm_mz_range_config_timeout_us;
charlesmn 0:3ac96e360672 1681 uint32_t vl53l1_tuningparm_timed_range_config_timeout_us;
charlesmn 0:3ac96e360672 1682 uint16_t vl53l1_tuningparm_dynxtalk_smudge_margin;
charlesmn 0:3ac96e360672 1683 uint32_t vl53l1_tuningparm_dynxtalk_noise_margin;
charlesmn 0:3ac96e360672 1684 uint32_t vl53l1_tuningparm_dynxtalk_xtalk_offset_limit;
charlesmn 0:3ac96e360672 1685 uint8_t vl53l1_tuningparm_dynxtalk_xtalk_offset_limit_hi;
charlesmn 0:3ac96e360672 1686 uint32_t vl53l1_tuningparm_dynxtalk_sample_limit;
charlesmn 0:3ac96e360672 1687 uint32_t vl53l1_tuningparm_dynxtalk_single_xtalk_delta;
charlesmn 0:3ac96e360672 1688 uint32_t vl53l1_tuningparm_dynxtalk_averaged_xtalk_delta;
charlesmn 0:3ac96e360672 1689 uint32_t vl53l1_tuningparm_dynxtalk_clip_limit;
charlesmn 0:3ac96e360672 1690 uint8_t vl53l1_tuningparm_dynxtalk_scaler_calc_method;
charlesmn 0:3ac96e360672 1691 int16_t vl53l1_tuningparm_dynxtalk_xgradient_scaler;
charlesmn 0:3ac96e360672 1692 int16_t vl53l1_tuningparm_dynxtalk_ygradient_scaler;
charlesmn 0:3ac96e360672 1693 uint8_t vl53l1_tuningparm_dynxtalk_user_scaler_set;
charlesmn 0:3ac96e360672 1694 uint8_t vl53l1_tuningparm_dynxtalk_smudge_cor_single_apply;
charlesmn 0:3ac96e360672 1695 uint32_t vl53l1_tuningparm_dynxtalk_xtalk_amb_threshold;
charlesmn 0:3ac96e360672 1696 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_amb_threshold_kcps;
charlesmn 0:3ac96e360672 1697 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_sample_limit;
charlesmn 0:3ac96e360672 1698 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_xtalk_offset_kcps;
charlesmn 0:3ac96e360672 1699 uint16_t vl53l1_tuningparm_dynxtalk_nodetect_min_range_mm;
charlesmn 0:3ac96e360672 1700 uint8_t vl53l1_tuningparm_lowpowerauto_vhv_loop_bound;
charlesmn 0:3ac96e360672 1701 uint32_t vl53l1_tuningparm_lowpowerauto_mm_config_timeout_us;
charlesmn 0:3ac96e360672 1702 uint32_t vl53l1_tuningparm_lowpowerauto_range_config_timeout_us;
charlesmn 0:3ac96e360672 1703 uint16_t vl53l1_tuningparm_very_short_dss_rate_mcps;
charlesmn 0:3ac96e360672 1704 uint32_t vl53l1_tuningparm_phasecal_patch_power;
charlesmn 0:3ac96e360672 1705 } VL53L1_tuning_parameters_t;
charlesmn 0:3ac96e360672 1706
charlesmn 0:3ac96e360672 1707
charlesmn 0:3ac96e360672 1708
charlesmn 0:3ac96e360672 1709
charlesmn 0:3ac96e360672 1710
charlesmn 0:3ac96e360672 1711 typedef struct {
charlesmn 0:3ac96e360672 1712
charlesmn 0:3ac96e360672 1713 uint16_t target_reflectance_for_dmax[VL53L1_MAX_AMBIENT_DMAX_VALUES];
charlesmn 0:3ac96e360672 1714
charlesmn 0:3ac96e360672 1715 } VL53L1_dmax_reflectance_array_t;
charlesmn 0:3ac96e360672 1716
charlesmn 0:3ac96e360672 1717
charlesmn 0:3ac96e360672 1718
charlesmn 0:3ac96e360672 1719
charlesmn 0:3ac96e360672 1720 typedef struct {
charlesmn 0:3ac96e360672 1721
charlesmn 0:3ac96e360672 1722 uint8_t spad_type;
charlesmn 0:3ac96e360672 1723
charlesmn 0:3ac96e360672 1724 uint16_t VL53L1_p_023;
charlesmn 0:3ac96e360672 1725
charlesmn 0:3ac96e360672 1726 uint16_t rate_data[VL53L1_NO_OF_SPAD_ENABLES];
charlesmn 0:3ac96e360672 1727
charlesmn 0:3ac96e360672 1728 uint16_t no_of_values;
charlesmn 0:3ac96e360672 1729
charlesmn 0:3ac96e360672 1730 uint8_t fractional_bits;
charlesmn 0:3ac96e360672 1731
charlesmn 0:3ac96e360672 1732 uint8_t error_status;
charlesmn 0:3ac96e360672 1733
charlesmn 0:3ac96e360672 1734
charlesmn 0:3ac96e360672 1735 } VL53L1_spad_rate_data_t;
charlesmn 0:3ac96e360672 1736
charlesmn 0:3ac96e360672 1737
charlesmn 0:3ac96e360672 1738
charlesmn 0:3ac96e360672 1739
charlesmn 0:3ac96e360672 1740
charlesmn 0:3ac96e360672 1741
charlesmn 0:3ac96e360672 1742 typedef struct {
charlesmn 0:3ac96e360672 1743
charlesmn 0:3ac96e360672 1744 VL53L1_DevicePresetModes preset_mode;
charlesmn 0:3ac96e360672 1745
charlesmn 0:3ac96e360672 1746 VL53L1_DeviceZonePreset zone_preset;
charlesmn 0:3ac96e360672 1747
charlesmn 0:3ac96e360672 1748 VL53L1_DeviceMeasurementModes measurement_mode;
charlesmn 0:3ac96e360672 1749
charlesmn 0:3ac96e360672 1750 VL53L1_OffsetCalibrationMode offset_calibration_mode;
charlesmn 0:3ac96e360672 1751
charlesmn 0:3ac96e360672 1752 VL53L1_OffsetCorrectionMode offset_correction_mode;
charlesmn 0:3ac96e360672 1753
charlesmn 0:3ac96e360672 1754 VL53L1_DeviceDmaxMode dmax_mode;
charlesmn 0:3ac96e360672 1755
charlesmn 0:3ac96e360672 1756
charlesmn 0:3ac96e360672 1757 uint32_t phasecal_config_timeout_us;
charlesmn 0:3ac96e360672 1758
charlesmn 0:3ac96e360672 1759 uint32_t mm_config_timeout_us;
charlesmn 0:3ac96e360672 1760
charlesmn 0:3ac96e360672 1761 uint32_t range_config_timeout_us;
charlesmn 0:3ac96e360672 1762
charlesmn 0:3ac96e360672 1763 uint32_t inter_measurement_period_ms;
charlesmn 0:3ac96e360672 1764
charlesmn 0:3ac96e360672 1765 uint16_t dss_config__target_total_rate_mcps;
charlesmn 0:3ac96e360672 1766
charlesmn 0:3ac96e360672 1767
charlesmn 0:3ac96e360672 1768 VL53L1_histogram_bin_data_t VL53L1_p_010;
charlesmn 0:3ac96e360672 1769
charlesmn 0:3ac96e360672 1770
charlesmn 0:3ac96e360672 1771 } VL53L1_additional_data_t;
charlesmn 0:3ac96e360672 1772
charlesmn 0:3ac96e360672 1773
charlesmn 0:3ac96e360672 1774
charlesmn 0:3ac96e360672 1775
charlesmn 0:3ac96e360672 1776
charlesmn 0:3ac96e360672 1777
charlesmn 0:3ac96e360672 1778
charlesmn 0:3ac96e360672 1779
charlesmn 0:3ac96e360672 1780 #define SUPPRESS_UNUSED_WARNING(x) \
charlesmn 0:3ac96e360672 1781 ((void) (x))
charlesmn 0:3ac96e360672 1782
charlesmn 0:3ac96e360672 1783
charlesmn 0:3ac96e360672 1784 #define IGNORE_STATUS(__FUNCTION_ID__, __ERROR_STATUS_CHECK__, __STATUS__) \
charlesmn 0:3ac96e360672 1785 do { \
charlesmn 0:3ac96e360672 1786 DISABLE_WARNINGS(); \
charlesmn 0:3ac96e360672 1787 if (__FUNCTION_ID__) { \
charlesmn 0:3ac96e360672 1788 if (__STATUS__ == __ERROR_STATUS_CHECK__) { \
charlesmn 0:3ac96e360672 1789 __STATUS__ = VL53L1_ERROR_NONE; \
charlesmn 0:3ac96e360672 1790 WARN_OVERRIDE_STATUS(__FUNCTION_ID__); \
charlesmn 0:3ac96e360672 1791 } \
charlesmn 0:3ac96e360672 1792 } \
charlesmn 0:3ac96e360672 1793 ENABLE_WARNINGS(); \
charlesmn 0:3ac96e360672 1794 } \
charlesmn 0:3ac96e360672 1795 while (0)
charlesmn 0:3ac96e360672 1796
charlesmn 0:3ac96e360672 1797 #define VL53L1_COPYSTRING(str, ...) \
charlesmn 0:3ac96e360672 1798 (strncpy(str, ##__VA_ARGS__, VL53L1_MAX_STRING_LENGTH-1))
charlesmn 0:3ac96e360672 1799
charlesmn 0:3ac96e360672 1800 #ifdef __cplusplus
charlesmn 0:3ac96e360672 1801 }
charlesmn 0:3ac96e360672 1802 #endif
charlesmn 0:3ac96e360672 1803
charlesmn 0:3ac96e360672 1804 #endif
charlesmn 0:3ac96e360672 1805
charlesmn 0:3ac96e360672 1806
charlesmn 0:3ac96e360672 1807
charlesmn 0:3ac96e360672 1808