VL53L1CB - The VL53L1CB proximity sensor, based on ST’s Flig…

ST Expansion SW Team » Code » VL53L1CB

ST Expansion SW Team / VL53L1CB

The VL53L1CB proximity sensor, based on ST’s FlightSense™, Time-of-Flight technology.

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

Dependents: VL53L1CB_noshield_1sensor_polls_auton VL53L1CB_noshield_1sensor_interrupt_auton X_NUCLEO_53L1A2

Based on VL53L1 library, this is a library for the VL53L1CB ToF chip.

src/vl53l1_core.c@0:3ac96e360672, 2020-11-06 (annotated)

Committer:: charlesmn
Date:: Fri Nov 06 10:06:37 2020 +0000
Revision:: 0:3ac96e360672
Child:: 7:1add29d51e72

Library for ST Vl53L1A1 time of flight sensor.

Who changed what in which revision?

User	Revision	Line number	New contents of line
charlesmn	0:3ac96e360672	1
charlesmn	0:3ac96e360672	2	/*******************************************************************************
charlesmn	0:3ac96e360672	3	* Copyright (c) 2020, STMicroelectronics - All Rights Reserved
charlesmn	0:3ac96e360672	4
charlesmn	0:3ac96e360672	5	This file is part of VL53L1 Core and is dual licensed,
charlesmn	0:3ac96e360672	6	either 'STMicroelectronics
charlesmn	0:3ac96e360672	7	Proprietary license'
charlesmn	0:3ac96e360672	8	or 'BSD 3-clause "New" or "Revised" License' , at your option.
charlesmn	0:3ac96e360672	9
charlesmn	0:3ac96e360672	10	********************************************************************************
charlesmn	0:3ac96e360672	11
charlesmn	0:3ac96e360672	12	'STMicroelectronics Proprietary license'
charlesmn	0:3ac96e360672	13
charlesmn	0:3ac96e360672	14	********************************************************************************
charlesmn	0:3ac96e360672	15
charlesmn	0:3ac96e360672	16	License terms: STMicroelectronics Proprietary in accordance with licensing
charlesmn	0:3ac96e360672	17	terms at www.st.com/sla0081
charlesmn	0:3ac96e360672	18
charlesmn	0:3ac96e360672	19	STMicroelectronics confidential
charlesmn	0:3ac96e360672	20	Reproduction and Communication of this document is strictly prohibited unless
charlesmn	0:3ac96e360672	21	specifically authorized in writing by STMicroelectronics.
charlesmn	0:3ac96e360672	22
charlesmn	0:3ac96e360672	23
charlesmn	0:3ac96e360672	24	********************************************************************************
charlesmn	0:3ac96e360672	25
charlesmn	0:3ac96e360672	26	Alternatively, VL53L1 Core may be distributed under the terms of
charlesmn	0:3ac96e360672	27	'BSD 3-clause "New" or "Revised" License', in which case the following
charlesmn	0:3ac96e360672	28	provisions apply instead of the ones
charlesmn	0:3ac96e360672	29	mentioned above :
charlesmn	0:3ac96e360672	30
charlesmn	0:3ac96e360672	31	********************************************************************************
charlesmn	0:3ac96e360672	32
charlesmn	0:3ac96e360672	33	License terms: BSD 3-clause "New" or "Revised" License.
charlesmn	0:3ac96e360672	34
charlesmn	0:3ac96e360672	35	Redistribution and use in source and binary forms, with or without
charlesmn	0:3ac96e360672	36	modification, are permitted provided that the following conditions are met:
charlesmn	0:3ac96e360672	37
charlesmn	0:3ac96e360672	38	1. Redistributions of source code must retain the above copyright notice, this
charlesmn	0:3ac96e360672	39	list of conditions and the following disclaimer.
charlesmn	0:3ac96e360672	40
charlesmn	0:3ac96e360672	41	2. Redistributions in binary form must reproduce the above copyright notice,
charlesmn	0:3ac96e360672	42	this list of conditions and the following disclaimer in the documentation
charlesmn	0:3ac96e360672	43	and/or other materials provided with the distribution.
charlesmn	0:3ac96e360672	44
charlesmn	0:3ac96e360672	45	3. Neither the name of the copyright holder nor the names of its contributors
charlesmn	0:3ac96e360672	46	may be used to endorse or promote products derived from this software
charlesmn	0:3ac96e360672	47	without specific prior written permission.
charlesmn	0:3ac96e360672	48
charlesmn	0:3ac96e360672	49	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
charlesmn	0:3ac96e360672	50	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
charlesmn	0:3ac96e360672	51	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
charlesmn	0:3ac96e360672	52	DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
charlesmn	0:3ac96e360672	53	FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
charlesmn	0:3ac96e360672	54	DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
charlesmn	0:3ac96e360672	55	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
charlesmn	0:3ac96e360672	56	CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
charlesmn	0:3ac96e360672	57	OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
charlesmn	0:3ac96e360672	58	OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
charlesmn	0:3ac96e360672	59
charlesmn	0:3ac96e360672	60
charlesmn	0:3ac96e360672	61	********************************************************************************
charlesmn	0:3ac96e360672	62
charlesmn	0:3ac96e360672	63	*/
charlesmn	0:3ac96e360672	64
charlesmn	0:3ac96e360672	65
charlesmn	0:3ac96e360672	66
charlesmn	0:3ac96e360672	67
charlesmn	0:3ac96e360672	68	#include "vl53l1_ll_def.h"
charlesmn	0:3ac96e360672	69	#include "vl53l1_ll_device.h"
charlesmn	0:3ac96e360672	70	#include "vl53l1_platform.h"
charlesmn	0:3ac96e360672	71	#include "vl53l1_register_map.h"
charlesmn	0:3ac96e360672	72	#include "vl53l1_register_funcs.h"
charlesmn	0:3ac96e360672	73	#include "vl53l1_register_settings.h"
charlesmn	0:3ac96e360672	74	#include "vl53l1_hist_structs.h"
charlesmn	0:3ac96e360672	75	#include "vl53l1_api_preset_modes.h"
charlesmn	0:3ac96e360672	76	#include "vl53l1_core.h"
charlesmn	0:3ac96e360672	77	#include "vl53l1_tuning_parm_defaults.h"
charlesmn	0:3ac96e360672	78
charlesmn	0:3ac96e360672	79
charlesmn	0:3ac96e360672	80
charlesmn	0:3ac96e360672	81	#define LOG_FUNCTION_START(fmt, ...) \
charlesmn	0:3ac96e360672	82	_LOG_FUNCTION_START(VL53L1_TRACE_MODULE_CORE, fmt, ##__VA_ARGS__)
charlesmn	0:3ac96e360672	83	#define LOG_FUNCTION_END(status, ...) \
charlesmn	0:3ac96e360672	84	_LOG_FUNCTION_END(VL53L1_TRACE_MODULE_CORE, status, ##__VA_ARGS__)
charlesmn	0:3ac96e360672	85	#define LOG_FUNCTION_END_FMT(status, fmt, ...) \
charlesmn	0:3ac96e360672	86	_LOG_FUNCTION_END_FMT(VL53L1_TRACE_MODULE_CORE, \
charlesmn	0:3ac96e360672	87	status, fmt, ##__VA_ARGS__)
charlesmn	0:3ac96e360672	88
charlesmn	0:3ac96e360672	89	#define trace_print(level, ...) \
charlesmn	0:3ac96e360672	90	_LOG_TRACE_PRINT(VL53L1_TRACE_MODULE_CORE, \
charlesmn	0:3ac96e360672	91	level, VL53L1_TRACE_FUNCTION_NONE, ##__VA_ARGS__)
charlesmn	0:3ac96e360672	92
charlesmn	0:3ac96e360672	93
charlesmn	0:3ac96e360672	94	void VL53L1_init_version(
charlesmn	0:3ac96e360672	95	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	96	{
charlesmn	0:3ac96e360672	97
charlesmn	0:3ac96e360672	98
charlesmn	0:3ac96e360672	99	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	100
charlesmn	0:3ac96e360672	101	pdev->version.ll_major = VL53L1_LL_API_IMPLEMENTATION_VER_MAJOR;
charlesmn	0:3ac96e360672	102	pdev->version.ll_minor = VL53L1_LL_API_IMPLEMENTATION_VER_MINOR;
charlesmn	0:3ac96e360672	103	pdev->version.ll_build = VL53L1_LL_API_IMPLEMENTATION_VER_SUB;
charlesmn	0:3ac96e360672	104	pdev->version.ll_revision = VL53L1_LL_API_IMPLEMENTATION_VER_REVISION;
charlesmn	0:3ac96e360672	105	}
charlesmn	0:3ac96e360672	106
charlesmn	0:3ac96e360672	107
charlesmn	0:3ac96e360672	108	void VL53L1_init_ll_driver_state(
charlesmn	0:3ac96e360672	109	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	110	VL53L1_DeviceState device_state)
charlesmn	0:3ac96e360672	111	{
charlesmn	0:3ac96e360672	112
charlesmn	0:3ac96e360672	113
charlesmn	0:3ac96e360672	114	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	115	VL53L1_ll_driver_state_t *pstate = &(pdev->ll_state);
charlesmn	0:3ac96e360672	116
charlesmn	0:3ac96e360672	117	pstate->cfg_device_state = device_state;
charlesmn	0:3ac96e360672	118	pstate->cfg_stream_count = 0;
charlesmn	0:3ac96e360672	119	pstate->cfg_gph_id = VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	120	pstate->cfg_timing_status = 0;
charlesmn	0:3ac96e360672	121	pstate->cfg_zone_id = 0;
charlesmn	0:3ac96e360672	122
charlesmn	0:3ac96e360672	123	pstate->rd_device_state = device_state;
charlesmn	0:3ac96e360672	124	pstate->rd_stream_count = 0;
charlesmn	0:3ac96e360672	125	pstate->rd_gph_id = VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	126	pstate->rd_timing_status = 0;
charlesmn	0:3ac96e360672	127	pstate->rd_zone_id = 0;
charlesmn	0:3ac96e360672	128
charlesmn	0:3ac96e360672	129	}
charlesmn	0:3ac96e360672	130
charlesmn	0:3ac96e360672	131
charlesmn	0:3ac96e360672	132	VL53L1_Error VL53L1_update_ll_driver_rd_state(
charlesmn	0:3ac96e360672	133	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	134	{
charlesmn	0:3ac96e360672	135
charlesmn	0:3ac96e360672	136
charlesmn	0:3ac96e360672	137	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	138	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	139	VL53L1_ll_driver_state_t *pstate = &(pdev->ll_state);
charlesmn	0:3ac96e360672	140
charlesmn	0:3ac96e360672	141
charlesmn	0:3ac96e360672	142
charlesmn	0:3ac96e360672	143	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	144
charlesmn	0:3ac96e360672	145
charlesmn	0:3ac96e360672	146
charlesmn	0:3ac96e360672	147	if ((pdev->sys_ctrl.system__mode_start &
charlesmn	0:3ac96e360672	148	VL53L1_DEVICEMEASUREMENTMODE_MODE_MASK) == 0x00) {
charlesmn	0:3ac96e360672	149
charlesmn	0:3ac96e360672	150	pstate->rd_device_state = VL53L1_DEVICESTATE_SW_STANDBY;
charlesmn	0:3ac96e360672	151	pstate->rd_stream_count = 0;
charlesmn	0:3ac96e360672	152	pstate->rd_internal_stream_count = 0;
charlesmn	0:3ac96e360672	153	pstate->rd_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	154	pstate->rd_gph_id = VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	155	pstate->rd_timing_status = 0;
charlesmn	0:3ac96e360672	156	pstate->rd_zone_id = 0;
charlesmn	0:3ac96e360672	157
charlesmn	0:3ac96e360672	158	} else {
charlesmn	0:3ac96e360672	159
charlesmn	0:3ac96e360672	160
charlesmn	0:3ac96e360672	161
charlesmn	0:3ac96e360672	162	if (pstate->rd_stream_count == 0xFF)
charlesmn	0:3ac96e360672	163	pstate->rd_stream_count = 0x80;
charlesmn	0:3ac96e360672	164	else
charlesmn	0:3ac96e360672	165	pstate->rd_stream_count++;
charlesmn	0:3ac96e360672	166
charlesmn	0:3ac96e360672	167
charlesmn	0:3ac96e360672	168	status = VL53L1_update_internal_stream_counters(Dev,
charlesmn	0:3ac96e360672	169	pstate->rd_stream_count,
charlesmn	0:3ac96e360672	170	&(pstate->rd_internal_stream_count),
charlesmn	0:3ac96e360672	171	&(pstate->rd_internal_stream_count_val));
charlesmn	0:3ac96e360672	172
charlesmn	0:3ac96e360672	173
charlesmn	0:3ac96e360672	174
charlesmn	0:3ac96e360672	175	pstate->rd_gph_id ^= VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	176
charlesmn	0:3ac96e360672	177
charlesmn	0:3ac96e360672	178
charlesmn	0:3ac96e360672	179	switch (pstate->rd_device_state) {
charlesmn	0:3ac96e360672	180
charlesmn	0:3ac96e360672	181	case VL53L1_DEVICESTATE_SW_STANDBY:
charlesmn	0:3ac96e360672	182
charlesmn	0:3ac96e360672	183	if ((pdev->dyn_cfg.system__grouped_parameter_hold &
charlesmn	0:3ac96e360672	184	VL53L1_GROUPEDPARAMETERHOLD_ID_MASK) > 0) {
charlesmn	0:3ac96e360672	185	pstate->rd_device_state =
charlesmn	0:3ac96e360672	186	VL53L1_DEVICESTATE_RANGING_WAIT_GPH_SYNC;
charlesmn	0:3ac96e360672	187	} else {
charlesmn	0:3ac96e360672	188	if (pstate->rd_zone_id >=
charlesmn	0:3ac96e360672	189	pdev->zone_cfg.active_zones)
charlesmn	0:3ac96e360672	190	pstate->rd_device_state =
charlesmn	0:3ac96e360672	191	VL53L1_DEVICESTATE_RANGING_OUTPUT_DATA;
charlesmn	0:3ac96e360672	192	else
charlesmn	0:3ac96e360672	193	pstate->rd_device_state =
charlesmn	0:3ac96e360672	194	VL53L1_DEVICESTATE_RANGING_GATHER_DATA;
charlesmn	0:3ac96e360672	195	}
charlesmn	0:3ac96e360672	196
charlesmn	0:3ac96e360672	197	pstate->rd_stream_count = 0;
charlesmn	0:3ac96e360672	198	pstate->rd_internal_stream_count = 0;
charlesmn	0:3ac96e360672	199	pstate->rd_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	200	pstate->rd_timing_status = 0;
charlesmn	0:3ac96e360672	201	pstate->rd_zone_id = 0;
charlesmn	0:3ac96e360672	202
charlesmn	0:3ac96e360672	203	break;
charlesmn	0:3ac96e360672	204
charlesmn	0:3ac96e360672	205	case VL53L1_DEVICESTATE_RANGING_WAIT_GPH_SYNC:
charlesmn	0:3ac96e360672	206	pstate->rd_stream_count = 0;
charlesmn	0:3ac96e360672	207	pstate->rd_internal_stream_count = 0;
charlesmn	0:3ac96e360672	208	pstate->rd_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	209	pstate->rd_zone_id = 0;
charlesmn	0:3ac96e360672	210	if (pstate->rd_zone_id >=
charlesmn	0:3ac96e360672	211	pdev->zone_cfg.active_zones)
charlesmn	0:3ac96e360672	212	pstate->rd_device_state =
charlesmn	0:3ac96e360672	213	VL53L1_DEVICESTATE_RANGING_OUTPUT_DATA;
charlesmn	0:3ac96e360672	214	else
charlesmn	0:3ac96e360672	215	pstate->rd_device_state =
charlesmn	0:3ac96e360672	216	VL53L1_DEVICESTATE_RANGING_GATHER_DATA;
charlesmn	0:3ac96e360672	217
charlesmn	0:3ac96e360672	218	break;
charlesmn	0:3ac96e360672	219
charlesmn	0:3ac96e360672	220	case VL53L1_DEVICESTATE_RANGING_GATHER_DATA:
charlesmn	0:3ac96e360672	221	pstate->rd_zone_id++;
charlesmn	0:3ac96e360672	222	if (pstate->rd_zone_id >=
charlesmn	0:3ac96e360672	223	pdev->zone_cfg.active_zones)
charlesmn	0:3ac96e360672	224	pstate->rd_device_state =
charlesmn	0:3ac96e360672	225	VL53L1_DEVICESTATE_RANGING_OUTPUT_DATA;
charlesmn	0:3ac96e360672	226	else
charlesmn	0:3ac96e360672	227	pstate->rd_device_state =
charlesmn	0:3ac96e360672	228	VL53L1_DEVICESTATE_RANGING_GATHER_DATA;
charlesmn	0:3ac96e360672	229
charlesmn	0:3ac96e360672	230	break;
charlesmn	0:3ac96e360672	231
charlesmn	0:3ac96e360672	232	case VL53L1_DEVICESTATE_RANGING_OUTPUT_DATA:
charlesmn	0:3ac96e360672	233	pstate->rd_zone_id = 0;
charlesmn	0:3ac96e360672	234	pstate->rd_timing_status ^= 0x01;
charlesmn	0:3ac96e360672	235
charlesmn	0:3ac96e360672	236	if (pstate->rd_zone_id >=
charlesmn	0:3ac96e360672	237	pdev->zone_cfg.active_zones)
charlesmn	0:3ac96e360672	238	pstate->rd_device_state =
charlesmn	0:3ac96e360672	239	VL53L1_DEVICESTATE_RANGING_OUTPUT_DATA;
charlesmn	0:3ac96e360672	240	else
charlesmn	0:3ac96e360672	241	pstate->rd_device_state =
charlesmn	0:3ac96e360672	242	VL53L1_DEVICESTATE_RANGING_GATHER_DATA;
charlesmn	0:3ac96e360672	243	break;
charlesmn	0:3ac96e360672	244
charlesmn	0:3ac96e360672	245	default:
charlesmn	0:3ac96e360672	246	pstate->rd_device_state =
charlesmn	0:3ac96e360672	247	VL53L1_DEVICESTATE_SW_STANDBY;
charlesmn	0:3ac96e360672	248	pstate->rd_stream_count = 0;
charlesmn	0:3ac96e360672	249	pstate->rd_internal_stream_count = 0;
charlesmn	0:3ac96e360672	250	pstate->rd_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	251	pstate->rd_gph_id = VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	252	pstate->rd_timing_status = 0;
charlesmn	0:3ac96e360672	253	pstate->rd_zone_id = 0;
charlesmn	0:3ac96e360672	254	break;
charlesmn	0:3ac96e360672	255	}
charlesmn	0:3ac96e360672	256	}
charlesmn	0:3ac96e360672	257
charlesmn	0:3ac96e360672	258
charlesmn	0:3ac96e360672	259
charlesmn	0:3ac96e360672	260	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	261
charlesmn	0:3ac96e360672	262	return status;
charlesmn	0:3ac96e360672	263	}
charlesmn	0:3ac96e360672	264
charlesmn	0:3ac96e360672	265
charlesmn	0:3ac96e360672	266	VL53L1_Error VL53L1_check_ll_driver_rd_state(
charlesmn	0:3ac96e360672	267	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	268	{
charlesmn	0:3ac96e360672	269
charlesmn	0:3ac96e360672	270
charlesmn	0:3ac96e360672	271	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	272	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	273	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	274	VL53L1_LLDriverResults_t *pres =
charlesmn	0:3ac96e360672	275	VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	276
charlesmn	0:3ac96e360672	277	VL53L1_ll_driver_state_t *pstate = &(pdev->ll_state);
charlesmn	0:3ac96e360672	278	VL53L1_system_results_t *psys_results = &(pdev->sys_results);
charlesmn	0:3ac96e360672	279	VL53L1_histogram_bin_data_t *phist_data = &(pdev->hist_data);
charlesmn	0:3ac96e360672	280	VL53L1_zone_private_dyn_cfgs_t *pZ = &(pres->zone_dyn_cfgs);
charlesmn	0:3ac96e360672	281
charlesmn	0:3ac96e360672	282	uint8_t device_range_status = 0;
charlesmn	0:3ac96e360672	283	uint8_t device_stream_count = 0;
charlesmn	0:3ac96e360672	284	uint8_t device_gph_id = 0;
charlesmn	0:3ac96e360672	285	uint8_t histogram_mode = 0;
charlesmn	0:3ac96e360672	286	uint8_t expected_stream_count = 0;
charlesmn	0:3ac96e360672	287	uint8_t expected_gph_id = 0;
charlesmn	0:3ac96e360672	288
charlesmn	0:3ac96e360672	289	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	290
charlesmn	0:3ac96e360672	291
charlesmn	0:3ac96e360672	292
charlesmn	0:3ac96e360672	293	device_range_status =
charlesmn	0:3ac96e360672	294	psys_results->result__range_status &
charlesmn	0:3ac96e360672	295	VL53L1_RANGE_STATUS__RANGE_STATUS_MASK;
charlesmn	0:3ac96e360672	296
charlesmn	0:3ac96e360672	297	device_stream_count = psys_results->result__stream_count;
charlesmn	0:3ac96e360672	298
charlesmn	0:3ac96e360672	299
charlesmn	0:3ac96e360672	300
charlesmn	0:3ac96e360672	301	histogram_mode =
charlesmn	0:3ac96e360672	302	(pdev->sys_ctrl.system__mode_start &
charlesmn	0:3ac96e360672	303	VL53L1_DEVICESCHEDULERMODE_HISTOGRAM) ==
charlesmn	0:3ac96e360672	304	VL53L1_DEVICESCHEDULERMODE_HISTOGRAM;
charlesmn	0:3ac96e360672	305
charlesmn	0:3ac96e360672	306
charlesmn	0:3ac96e360672	307	device_gph_id = (psys_results->result__interrupt_status &
charlesmn	0:3ac96e360672	308	VL53L1_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK) >> 4;
charlesmn	0:3ac96e360672	309
charlesmn	0:3ac96e360672	310	if (histogram_mode)
charlesmn	0:3ac96e360672	311	device_gph_id = (phist_data->result__interrupt_status &
charlesmn	0:3ac96e360672	312	VL53L1_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK) >> 4;
charlesmn	0:3ac96e360672	313
charlesmn	0:3ac96e360672	314
charlesmn	0:3ac96e360672	315
charlesmn	0:3ac96e360672	316	if (!((pdev->sys_ctrl.system__mode_start &
charlesmn	0:3ac96e360672	317	VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK) ==
charlesmn	0:3ac96e360672	318	VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK))
charlesmn	0:3ac96e360672	319	goto ENDFUNC;
charlesmn	0:3ac96e360672	320
charlesmn	0:3ac96e360672	321
charlesmn	0:3ac96e360672	322
charlesmn	0:3ac96e360672	323	if (pstate->rd_device_state ==
charlesmn	0:3ac96e360672	324	VL53L1_DEVICESTATE_RANGING_WAIT_GPH_SYNC) {
charlesmn	0:3ac96e360672	325
charlesmn	0:3ac96e360672	326	if (histogram_mode == 0) {
charlesmn	0:3ac96e360672	327	if (device_range_status !=
charlesmn	0:3ac96e360672	328	VL53L1_DEVICEERROR_GPHSTREAMCOUNT0READY)
charlesmn	0:3ac96e360672	329	status =
charlesmn	0:3ac96e360672	330	VL53L1_ERROR_GPH_SYNC_CHECK_FAIL;
charlesmn	0:3ac96e360672	331
charlesmn	0:3ac96e360672	332	}
charlesmn	0:3ac96e360672	333	} else {
charlesmn	0:3ac96e360672	334	if (pstate->rd_stream_count != device_stream_count)
charlesmn	0:3ac96e360672	335	status = VL53L1_ERROR_STREAM_COUNT_CHECK_FAIL;
charlesmn	0:3ac96e360672	336
charlesmn	0:3ac96e360672	337
charlesmn	0:3ac96e360672	338	if (pstate->rd_gph_id != device_gph_id)
charlesmn	0:3ac96e360672	339	status = VL53L1_ERROR_GPH_ID_CHECK_FAIL;
charlesmn	0:3ac96e360672	340
charlesmn	0:3ac96e360672	341
charlesmn	0:3ac96e360672	342
charlesmn	0:3ac96e360672	343
charlesmn	0:3ac96e360672	344	expected_stream_count =
charlesmn	0:3ac96e360672	345	pZ->VL53L1_p_002[pstate->rd_zone_id].expected_stream_count;
charlesmn	0:3ac96e360672	346	expected_gph_id =
charlesmn	0:3ac96e360672	347	pZ->VL53L1_p_002[pstate->rd_zone_id].expected_gph_id;
charlesmn	0:3ac96e360672	348
charlesmn	0:3ac96e360672	349
charlesmn	0:3ac96e360672	350
charlesmn	0:3ac96e360672	351	if (expected_stream_count != device_stream_count) {
charlesmn	0:3ac96e360672	352
charlesmn	0:3ac96e360672	353
charlesmn	0:3ac96e360672	354	if (!((pdev->zone_cfg.active_zones == 0) &&
charlesmn	0:3ac96e360672	355	(device_stream_count == 255)))
charlesmn	0:3ac96e360672	356	status =
charlesmn	0:3ac96e360672	357	VL53L1_ERROR_ZONE_STREAM_COUNT_CHECK_FAIL;
charlesmn	0:3ac96e360672	358
charlesmn	0:3ac96e360672	359
charlesmn	0:3ac96e360672	360	}
charlesmn	0:3ac96e360672	361
charlesmn	0:3ac96e360672	362
charlesmn	0:3ac96e360672	363
charlesmn	0:3ac96e360672	364	if (expected_gph_id != device_gph_id)
charlesmn	0:3ac96e360672	365	status = VL53L1_ERROR_ZONE_GPH_ID_CHECK_FAIL;
charlesmn	0:3ac96e360672	366
charlesmn	0:3ac96e360672	367	}
charlesmn	0:3ac96e360672	368
charlesmn	0:3ac96e360672	369
charlesmn	0:3ac96e360672	370
charlesmn	0:3ac96e360672	371	ENDFUNC:
charlesmn	0:3ac96e360672	372	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	373	return status;
charlesmn	0:3ac96e360672	374	}
charlesmn	0:3ac96e360672	375
charlesmn	0:3ac96e360672	376
charlesmn	0:3ac96e360672	377	VL53L1_Error VL53L1_update_ll_driver_cfg_state(
charlesmn	0:3ac96e360672	378	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	379	{
charlesmn	0:3ac96e360672	380
charlesmn	0:3ac96e360672	381
charlesmn	0:3ac96e360672	382	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	383	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	384	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	385	VL53L1_LLDriverResults_t *pres =
charlesmn	0:3ac96e360672	386	VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	387
charlesmn	0:3ac96e360672	388	VL53L1_ll_driver_state_t *pstate = &(pdev->ll_state);
charlesmn	0:3ac96e360672	389	VL53L1_zone_private_dyn_cfgs_t *pZ = &(pres->zone_dyn_cfgs);
charlesmn	0:3ac96e360672	390
charlesmn	0:3ac96e360672	391	uint8_t prev_cfg_zone_id;
charlesmn	0:3ac96e360672	392	uint8_t prev_cfg_gph_id;
charlesmn	0:3ac96e360672	393	uint8_t prev_cfg_stream_count;
charlesmn	0:3ac96e360672	394
charlesmn	0:3ac96e360672	395	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	396
charlesmn	0:3ac96e360672	397
charlesmn	0:3ac96e360672	398
charlesmn	0:3ac96e360672	399
charlesmn	0:3ac96e360672	400
charlesmn	0:3ac96e360672	401	if ((pdev->sys_ctrl.system__mode_start &
charlesmn	0:3ac96e360672	402	VL53L1_DEVICEMEASUREMENTMODE_MODE_MASK) == 0x00) {
charlesmn	0:3ac96e360672	403
charlesmn	0:3ac96e360672	404	pstate->cfg_device_state = VL53L1_DEVICESTATE_SW_STANDBY;
charlesmn	0:3ac96e360672	405	pstate->cfg_stream_count = 0;
charlesmn	0:3ac96e360672	406	pstate->cfg_internal_stream_count = 0;
charlesmn	0:3ac96e360672	407	pstate->cfg_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	408	pstate->cfg_gph_id = VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	409	pstate->cfg_timing_status = 0;
charlesmn	0:3ac96e360672	410	pstate->cfg_zone_id = 0;
charlesmn	0:3ac96e360672	411	prev_cfg_zone_id = 0;
charlesmn	0:3ac96e360672	412	prev_cfg_gph_id = 0;
charlesmn	0:3ac96e360672	413	prev_cfg_stream_count = 0;
charlesmn	0:3ac96e360672	414
charlesmn	0:3ac96e360672	415	} else {
charlesmn	0:3ac96e360672	416
charlesmn	0:3ac96e360672	417	prev_cfg_gph_id = pstate->cfg_gph_id;
charlesmn	0:3ac96e360672	418	prev_cfg_zone_id = pstate->cfg_zone_id;
charlesmn	0:3ac96e360672	419	prev_cfg_stream_count = pstate->cfg_stream_count;
charlesmn	0:3ac96e360672	420
charlesmn	0:3ac96e360672	421
charlesmn	0:3ac96e360672	422
charlesmn	0:3ac96e360672	423	if (pstate->cfg_stream_count == 0xFF)
charlesmn	0:3ac96e360672	424	pstate->cfg_stream_count = 0x80;
charlesmn	0:3ac96e360672	425	else
charlesmn	0:3ac96e360672	426	pstate->cfg_stream_count++;
charlesmn	0:3ac96e360672	427
charlesmn	0:3ac96e360672	428
charlesmn	0:3ac96e360672	429	status = VL53L1_update_internal_stream_counters(
charlesmn	0:3ac96e360672	430	Dev,
charlesmn	0:3ac96e360672	431	pstate->cfg_stream_count,
charlesmn	0:3ac96e360672	432	&(pstate->cfg_internal_stream_count),
charlesmn	0:3ac96e360672	433	&(pstate->cfg_internal_stream_count_val));
charlesmn	0:3ac96e360672	434
charlesmn	0:3ac96e360672	435
charlesmn	0:3ac96e360672	436
charlesmn	0:3ac96e360672	437	pstate->cfg_gph_id ^= VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	438
charlesmn	0:3ac96e360672	439
charlesmn	0:3ac96e360672	440
charlesmn	0:3ac96e360672	441	switch (pstate->cfg_device_state) {
charlesmn	0:3ac96e360672	442
charlesmn	0:3ac96e360672	443	case VL53L1_DEVICESTATE_SW_STANDBY:
charlesmn	0:3ac96e360672	444	pstate->cfg_zone_id = 1;
charlesmn	0:3ac96e360672	445	if (pstate->cfg_zone_id >
charlesmn	0:3ac96e360672	446	pdev->zone_cfg.active_zones) {
charlesmn	0:3ac96e360672	447	pstate->cfg_zone_id = 0;
charlesmn	0:3ac96e360672	448	pstate->cfg_timing_status ^= 0x01;
charlesmn	0:3ac96e360672	449	}
charlesmn	0:3ac96e360672	450	pstate->cfg_stream_count = 1;
charlesmn	0:3ac96e360672	451
charlesmn	0:3ac96e360672	452	if (pdev->gen_cfg.global_config__stream_divider == 0) {
charlesmn	0:3ac96e360672	453	pstate->cfg_internal_stream_count = 1;
charlesmn	0:3ac96e360672	454	pstate->cfg_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	455	} else {
charlesmn	0:3ac96e360672	456	pstate->cfg_internal_stream_count = 0;
charlesmn	0:3ac96e360672	457	pstate->cfg_internal_stream_count_val = 1;
charlesmn	0:3ac96e360672	458	}
charlesmn	0:3ac96e360672	459	pstate->cfg_device_state =
charlesmn	0:3ac96e360672	460	VL53L1_DEVICESTATE_RANGING_DSS_AUTO;
charlesmn	0:3ac96e360672	461	break;
charlesmn	0:3ac96e360672	462
charlesmn	0:3ac96e360672	463	case VL53L1_DEVICESTATE_RANGING_DSS_AUTO:
charlesmn	0:3ac96e360672	464	pstate->cfg_zone_id++;
charlesmn	0:3ac96e360672	465	if (pstate->cfg_zone_id >
charlesmn	0:3ac96e360672	466	pdev->zone_cfg.active_zones) {
charlesmn	0:3ac96e360672	467
charlesmn	0:3ac96e360672	468	pstate->cfg_zone_id = 0;
charlesmn	0:3ac96e360672	469	pstate->cfg_timing_status ^= 0x01;
charlesmn	0:3ac96e360672	470
charlesmn	0:3ac96e360672	471
charlesmn	0:3ac96e360672	472
charlesmn	0:3ac96e360672	473
charlesmn	0:3ac96e360672	474	if (pdev->zone_cfg.active_zones > 0) {
charlesmn	0:3ac96e360672	475	pstate->cfg_device_state =
charlesmn	0:3ac96e360672	476	VL53L1_DEVICESTATE_RANGING_DSS_MANUAL;
charlesmn	0:3ac96e360672	477	}
charlesmn	0:3ac96e360672	478	}
charlesmn	0:3ac96e360672	479	break;
charlesmn	0:3ac96e360672	480
charlesmn	0:3ac96e360672	481	case VL53L1_DEVICESTATE_RANGING_DSS_MANUAL:
charlesmn	0:3ac96e360672	482	pstate->cfg_zone_id++;
charlesmn	0:3ac96e360672	483	if (pstate->cfg_zone_id >
charlesmn	0:3ac96e360672	484	pdev->zone_cfg.active_zones) {
charlesmn	0:3ac96e360672	485	pstate->cfg_zone_id = 0;
charlesmn	0:3ac96e360672	486	pstate->cfg_timing_status ^= 0x01;
charlesmn	0:3ac96e360672	487	}
charlesmn	0:3ac96e360672	488	break;
charlesmn	0:3ac96e360672	489
charlesmn	0:3ac96e360672	490	default:
charlesmn	0:3ac96e360672	491	pstate->cfg_device_state =
charlesmn	0:3ac96e360672	492	VL53L1_DEVICESTATE_SW_STANDBY;
charlesmn	0:3ac96e360672	493	pstate->cfg_stream_count = 0;
charlesmn	0:3ac96e360672	494	pstate->cfg_internal_stream_count = 0;
charlesmn	0:3ac96e360672	495	pstate->cfg_internal_stream_count_val = 0;
charlesmn	0:3ac96e360672	496	pstate->cfg_gph_id =
charlesmn	0:3ac96e360672	497	VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	498	pstate->cfg_timing_status = 0;
charlesmn	0:3ac96e360672	499	pstate->cfg_zone_id = 0;
charlesmn	0:3ac96e360672	500	break;
charlesmn	0:3ac96e360672	501	}
charlesmn	0:3ac96e360672	502	}
charlesmn	0:3ac96e360672	503
charlesmn	0:3ac96e360672	504
charlesmn	0:3ac96e360672	505	if (pdev->zone_cfg.active_zones == 0) {
charlesmn	0:3ac96e360672	506
charlesmn	0:3ac96e360672	507	pZ->VL53L1_p_002[prev_cfg_zone_id].expected_stream_count
charlesmn	0:3ac96e360672	508	= prev_cfg_stream_count - 1;
charlesmn	0:3ac96e360672	509
charlesmn	0:3ac96e360672	510	pZ->VL53L1_p_002[pstate->rd_zone_id].expected_gph_id =
charlesmn	0:3ac96e360672	511	prev_cfg_gph_id ^ VL53L1_GROUPEDPARAMETERHOLD_ID_MASK;
charlesmn	0:3ac96e360672	512	} else {
charlesmn	0:3ac96e360672	513	pZ->VL53L1_p_002[prev_cfg_zone_id].expected_stream_count
charlesmn	0:3ac96e360672	514	= prev_cfg_stream_count;
charlesmn	0:3ac96e360672	515	pZ->VL53L1_p_002[prev_cfg_zone_id].expected_gph_id =
charlesmn	0:3ac96e360672	516	prev_cfg_gph_id;
charlesmn	0:3ac96e360672	517	}
charlesmn	0:3ac96e360672	518
charlesmn	0:3ac96e360672	519
charlesmn	0:3ac96e360672	520
charlesmn	0:3ac96e360672	521	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	522
charlesmn	0:3ac96e360672	523	return status;
charlesmn	0:3ac96e360672	524	}
charlesmn	0:3ac96e360672	525
charlesmn	0:3ac96e360672	526
charlesmn	0:3ac96e360672	527	void VL53L1_copy_rtn_good_spads_to_buffer(
charlesmn	0:3ac96e360672	528	VL53L1_nvm_copy_data_t *pdata,
charlesmn	0:3ac96e360672	529	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	530	{
charlesmn	0:3ac96e360672	531
charlesmn	0:3ac96e360672	532
charlesmn	0:3ac96e360672	533	*(pbuffer + 0) = pdata->global_config__spad_enables_rtn_0;
charlesmn	0:3ac96e360672	534	*(pbuffer + 1) = pdata->global_config__spad_enables_rtn_1;
charlesmn	0:3ac96e360672	535	*(pbuffer + 2) = pdata->global_config__spad_enables_rtn_2;
charlesmn	0:3ac96e360672	536	*(pbuffer + 3) = pdata->global_config__spad_enables_rtn_3;
charlesmn	0:3ac96e360672	537	*(pbuffer + 4) = pdata->global_config__spad_enables_rtn_4;
charlesmn	0:3ac96e360672	538	*(pbuffer + 5) = pdata->global_config__spad_enables_rtn_5;
charlesmn	0:3ac96e360672	539	*(pbuffer + 6) = pdata->global_config__spad_enables_rtn_6;
charlesmn	0:3ac96e360672	540	*(pbuffer + 7) = pdata->global_config__spad_enables_rtn_7;
charlesmn	0:3ac96e360672	541	*(pbuffer + 8) = pdata->global_config__spad_enables_rtn_8;
charlesmn	0:3ac96e360672	542	*(pbuffer + 9) = pdata->global_config__spad_enables_rtn_9;
charlesmn	0:3ac96e360672	543	*(pbuffer + 10) = pdata->global_config__spad_enables_rtn_10;
charlesmn	0:3ac96e360672	544	*(pbuffer + 11) = pdata->global_config__spad_enables_rtn_11;
charlesmn	0:3ac96e360672	545	*(pbuffer + 12) = pdata->global_config__spad_enables_rtn_12;
charlesmn	0:3ac96e360672	546	*(pbuffer + 13) = pdata->global_config__spad_enables_rtn_13;
charlesmn	0:3ac96e360672	547	*(pbuffer + 14) = pdata->global_config__spad_enables_rtn_14;
charlesmn	0:3ac96e360672	548	*(pbuffer + 15) = pdata->global_config__spad_enables_rtn_15;
charlesmn	0:3ac96e360672	549	*(pbuffer + 16) = pdata->global_config__spad_enables_rtn_16;
charlesmn	0:3ac96e360672	550	*(pbuffer + 17) = pdata->global_config__spad_enables_rtn_17;
charlesmn	0:3ac96e360672	551	*(pbuffer + 18) = pdata->global_config__spad_enables_rtn_18;
charlesmn	0:3ac96e360672	552	*(pbuffer + 19) = pdata->global_config__spad_enables_rtn_19;
charlesmn	0:3ac96e360672	553	*(pbuffer + 20) = pdata->global_config__spad_enables_rtn_20;
charlesmn	0:3ac96e360672	554	*(pbuffer + 21) = pdata->global_config__spad_enables_rtn_21;
charlesmn	0:3ac96e360672	555	*(pbuffer + 22) = pdata->global_config__spad_enables_rtn_22;
charlesmn	0:3ac96e360672	556	*(pbuffer + 23) = pdata->global_config__spad_enables_rtn_23;
charlesmn	0:3ac96e360672	557	*(pbuffer + 24) = pdata->global_config__spad_enables_rtn_24;
charlesmn	0:3ac96e360672	558	*(pbuffer + 25) = pdata->global_config__spad_enables_rtn_25;
charlesmn	0:3ac96e360672	559	*(pbuffer + 26) = pdata->global_config__spad_enables_rtn_26;
charlesmn	0:3ac96e360672	560	*(pbuffer + 27) = pdata->global_config__spad_enables_rtn_27;
charlesmn	0:3ac96e360672	561	*(pbuffer + 28) = pdata->global_config__spad_enables_rtn_28;
charlesmn	0:3ac96e360672	562	*(pbuffer + 29) = pdata->global_config__spad_enables_rtn_29;
charlesmn	0:3ac96e360672	563	*(pbuffer + 30) = pdata->global_config__spad_enables_rtn_30;
charlesmn	0:3ac96e360672	564	*(pbuffer + 31) = pdata->global_config__spad_enables_rtn_31;
charlesmn	0:3ac96e360672	565	}
charlesmn	0:3ac96e360672	566
charlesmn	0:3ac96e360672	567
charlesmn	0:3ac96e360672	568	void VL53L1_init_system_results(
charlesmn	0:3ac96e360672	569	VL53L1_system_results_t *pdata)
charlesmn	0:3ac96e360672	570	{
charlesmn	0:3ac96e360672	571
charlesmn	0:3ac96e360672	572
charlesmn	0:3ac96e360672	573	pdata->result__interrupt_status = 0xFF;
charlesmn	0:3ac96e360672	574	pdata->result__range_status = 0xFF;
charlesmn	0:3ac96e360672	575	pdata->result__report_status = 0xFF;
charlesmn	0:3ac96e360672	576	pdata->result__stream_count = 0xFF;
charlesmn	0:3ac96e360672	577
charlesmn	0:3ac96e360672	578	pdata->result__dss_actual_effective_spads_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	579	pdata->result__peak_signal_count_rate_mcps_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	580	pdata->result__ambient_count_rate_mcps_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	581	pdata->result__sigma_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	582	pdata->result__phase_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	583	pdata->result__final_crosstalk_corrected_range_mm_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	584	pdata->result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 =
charlesmn	0:3ac96e360672	585	0xFFFF;
charlesmn	0:3ac96e360672	586	pdata->result__mm_inner_actual_effective_spads_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	587	pdata->result__mm_outer_actual_effective_spads_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	588	pdata->result__avg_signal_count_rate_mcps_sd0 = 0xFFFF;
charlesmn	0:3ac96e360672	589
charlesmn	0:3ac96e360672	590	pdata->result__dss_actual_effective_spads_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	591	pdata->result__peak_signal_count_rate_mcps_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	592	pdata->result__ambient_count_rate_mcps_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	593	pdata->result__sigma_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	594	pdata->result__phase_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	595	pdata->result__final_crosstalk_corrected_range_mm_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	596	pdata->result__spare_0_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	597	pdata->result__spare_1_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	598	pdata->result__spare_2_sd1 = 0xFFFF;
charlesmn	0:3ac96e360672	599	pdata->result__spare_3_sd1 = 0xFF;
charlesmn	0:3ac96e360672	600
charlesmn	0:3ac96e360672	601	}
charlesmn	0:3ac96e360672	602
charlesmn	0:3ac96e360672	603
charlesmn	0:3ac96e360672	604	void V53L1_init_zone_results_structure(
charlesmn	0:3ac96e360672	605	uint8_t active_zones,
charlesmn	0:3ac96e360672	606	VL53L1_zone_results_t *pdata)
charlesmn	0:3ac96e360672	607	{
charlesmn	0:3ac96e360672	608
charlesmn	0:3ac96e360672	609
charlesmn	0:3ac96e360672	610
charlesmn	0:3ac96e360672	611	uint8_t z = 0;
charlesmn	0:3ac96e360672	612	VL53L1_zone_objects_t *pobjects;
charlesmn	0:3ac96e360672	613
charlesmn	0:3ac96e360672	614	pdata->max_zones = VL53L1_MAX_USER_ZONES;
charlesmn	0:3ac96e360672	615	pdata->active_zones = active_zones;
charlesmn	0:3ac96e360672	616
charlesmn	0:3ac96e360672	617	for (z = 0; z < pdata->max_zones; z++) {
charlesmn	0:3ac96e360672	618	pobjects = &(pdata->VL53L1_p_002[z]);
charlesmn	0:3ac96e360672	619	pobjects->cfg_device_state = VL53L1_DEVICESTATE_SW_STANDBY;
charlesmn	0:3ac96e360672	620	pobjects->rd_device_state = VL53L1_DEVICESTATE_SW_STANDBY;
charlesmn	0:3ac96e360672	621	pobjects->max_objects = VL53L1_MAX_RANGE_RESULTS;
charlesmn	0:3ac96e360672	622	pobjects->active_objects = 0;
charlesmn	0:3ac96e360672	623	}
charlesmn	0:3ac96e360672	624	}
charlesmn	0:3ac96e360672	625
charlesmn	0:3ac96e360672	626	void V53L1_init_zone_dss_configs(
charlesmn	0:3ac96e360672	627	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	628	{
charlesmn	0:3ac96e360672	629
charlesmn	0:3ac96e360672	630
charlesmn	0:3ac96e360672	631
charlesmn	0:3ac96e360672	632	VL53L1_LLDriverResults_t *pres =
charlesmn	0:3ac96e360672	633	VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	634	uint8_t z = 0;
charlesmn	0:3ac96e360672	635	uint8_t max_zones = VL53L1_MAX_USER_ZONES;
charlesmn	0:3ac96e360672	636	VL53L1_zone_private_dyn_cfgs_t *pdata = &(pres->zone_dyn_cfgs);
charlesmn	0:3ac96e360672	637
charlesmn	0:3ac96e360672	638	for (z = 0; z < max_zones; z++) {
charlesmn	0:3ac96e360672	639	pdata->VL53L1_p_002[z].dss_mode =
charlesmn	0:3ac96e360672	640	VL53L1_DSS_CONTROL__MODE_TARGET_RATE;
charlesmn	0:3ac96e360672	641	pdata->VL53L1_p_002[z].dss_requested_effective_spad_count = 0;
charlesmn	0:3ac96e360672	642	}
charlesmn	0:3ac96e360672	643	}
charlesmn	0:3ac96e360672	644
charlesmn	0:3ac96e360672	645
charlesmn	0:3ac96e360672	646	void VL53L1_init_histogram_config_structure(
charlesmn	0:3ac96e360672	647	uint8_t even_bin0,
charlesmn	0:3ac96e360672	648	uint8_t even_bin1,
charlesmn	0:3ac96e360672	649	uint8_t even_bin2,
charlesmn	0:3ac96e360672	650	uint8_t even_bin3,
charlesmn	0:3ac96e360672	651	uint8_t even_bin4,
charlesmn	0:3ac96e360672	652	uint8_t even_bin5,
charlesmn	0:3ac96e360672	653	uint8_t odd_bin0,
charlesmn	0:3ac96e360672	654	uint8_t odd_bin1,
charlesmn	0:3ac96e360672	655	uint8_t odd_bin2,
charlesmn	0:3ac96e360672	656	uint8_t odd_bin3,
charlesmn	0:3ac96e360672	657	uint8_t odd_bin4,
charlesmn	0:3ac96e360672	658	uint8_t odd_bin5,
charlesmn	0:3ac96e360672	659	VL53L1_histogram_config_t *pdata)
charlesmn	0:3ac96e360672	660	{
charlesmn	0:3ac96e360672	661
charlesmn	0:3ac96e360672	662
charlesmn	0:3ac96e360672	663	pdata->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	664	(even_bin1 << 4) + even_bin0;
charlesmn	0:3ac96e360672	665	pdata->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	666	(even_bin3 << 4) + even_bin2;
charlesmn	0:3ac96e360672	667	pdata->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	668	(even_bin5 << 4) + even_bin4;
charlesmn	0:3ac96e360672	669
charlesmn	0:3ac96e360672	670	pdata->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	671	(odd_bin1 << 4) + odd_bin0;
charlesmn	0:3ac96e360672	672	pdata->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	673	(odd_bin3 << 4) + odd_bin2;
charlesmn	0:3ac96e360672	674	pdata->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	675	(odd_bin5 << 4) + odd_bin4;
charlesmn	0:3ac96e360672	676
charlesmn	0:3ac96e360672	677	pdata->histogram_config__mid_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	678	pdata->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	679	pdata->histogram_config__mid_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	680	pdata->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	681	pdata->histogram_config__mid_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	682	pdata->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	683
charlesmn	0:3ac96e360672	684	pdata->histogram_config__mid_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	685	pdata->histogram_config__low_amb_odd_bin_0_1;
charlesmn	0:3ac96e360672	686	pdata->histogram_config__mid_amb_odd_bin_2 = odd_bin2;
charlesmn	0:3ac96e360672	687	pdata->histogram_config__mid_amb_odd_bin_3_4 =
charlesmn	0:3ac96e360672	688	(odd_bin4 << 4) + odd_bin3;
charlesmn	0:3ac96e360672	689	pdata->histogram_config__mid_amb_odd_bin_5 = odd_bin5;
charlesmn	0:3ac96e360672	690
charlesmn	0:3ac96e360672	691	pdata->histogram_config__user_bin_offset = 0x00;
charlesmn	0:3ac96e360672	692
charlesmn	0:3ac96e360672	693	pdata->histogram_config__high_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	694	pdata->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	695	pdata->histogram_config__high_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	696	pdata->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	697	pdata->histogram_config__high_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	698	pdata->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	699
charlesmn	0:3ac96e360672	700	pdata->histogram_config__high_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	701	pdata->histogram_config__low_amb_odd_bin_0_1;
charlesmn	0:3ac96e360672	702	pdata->histogram_config__high_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	703	pdata->histogram_config__low_amb_odd_bin_2_3;
charlesmn	0:3ac96e360672	704	pdata->histogram_config__high_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	705	pdata->histogram_config__low_amb_odd_bin_4_5;
charlesmn	0:3ac96e360672	706
charlesmn	0:3ac96e360672	707
charlesmn	0:3ac96e360672	708
charlesmn	0:3ac96e360672	709	pdata->histogram_config__amb_thresh_low = 0xFFFF;
charlesmn	0:3ac96e360672	710	pdata->histogram_config__amb_thresh_high = 0xFFFF;
charlesmn	0:3ac96e360672	711
charlesmn	0:3ac96e360672	712
charlesmn	0:3ac96e360672	713
charlesmn	0:3ac96e360672	714	pdata->histogram_config__spad_array_selection = 0x00;
charlesmn	0:3ac96e360672	715
charlesmn	0:3ac96e360672	716	}
charlesmn	0:3ac96e360672	717
charlesmn	0:3ac96e360672	718	void VL53L1_init_histogram_multizone_config_structure(
charlesmn	0:3ac96e360672	719	uint8_t even_bin0,
charlesmn	0:3ac96e360672	720	uint8_t even_bin1,
charlesmn	0:3ac96e360672	721	uint8_t even_bin2,
charlesmn	0:3ac96e360672	722	uint8_t even_bin3,
charlesmn	0:3ac96e360672	723	uint8_t even_bin4,
charlesmn	0:3ac96e360672	724	uint8_t even_bin5,
charlesmn	0:3ac96e360672	725	uint8_t odd_bin0,
charlesmn	0:3ac96e360672	726	uint8_t odd_bin1,
charlesmn	0:3ac96e360672	727	uint8_t odd_bin2,
charlesmn	0:3ac96e360672	728	uint8_t odd_bin3,
charlesmn	0:3ac96e360672	729	uint8_t odd_bin4,
charlesmn	0:3ac96e360672	730	uint8_t odd_bin5,
charlesmn	0:3ac96e360672	731	VL53L1_histogram_config_t *pdata)
charlesmn	0:3ac96e360672	732	{
charlesmn	0:3ac96e360672	733
charlesmn	0:3ac96e360672	734
charlesmn	0:3ac96e360672	735	pdata->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	736	(even_bin1 << 4) + even_bin0;
charlesmn	0:3ac96e360672	737	pdata->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	738	(even_bin3 << 4) + even_bin2;
charlesmn	0:3ac96e360672	739	pdata->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	740	(even_bin5 << 4) + even_bin4;
charlesmn	0:3ac96e360672	741
charlesmn	0:3ac96e360672	742	pdata->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	743	pdata->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	744	pdata->histogram_config__low_amb_odd_bin_2_3
charlesmn	0:3ac96e360672	745	= pdata->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	746	pdata->histogram_config__low_amb_odd_bin_4_5
charlesmn	0:3ac96e360672	747	= pdata->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	748
charlesmn	0:3ac96e360672	749	pdata->histogram_config__mid_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	750	pdata->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	751	pdata->histogram_config__mid_amb_even_bin_2_3
charlesmn	0:3ac96e360672	752	= pdata->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	753	pdata->histogram_config__mid_amb_even_bin_4_5
charlesmn	0:3ac96e360672	754	= pdata->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	755
charlesmn	0:3ac96e360672	756	pdata->histogram_config__mid_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	757	= pdata->histogram_config__low_amb_odd_bin_0_1;
charlesmn	0:3ac96e360672	758	pdata->histogram_config__mid_amb_odd_bin_2 = odd_bin2;
charlesmn	0:3ac96e360672	759	pdata->histogram_config__mid_amb_odd_bin_3_4 =
charlesmn	0:3ac96e360672	760	(odd_bin4 << 4) + odd_bin3;
charlesmn	0:3ac96e360672	761	pdata->histogram_config__mid_amb_odd_bin_5 = odd_bin5;
charlesmn	0:3ac96e360672	762
charlesmn	0:3ac96e360672	763	pdata->histogram_config__user_bin_offset = 0x00;
charlesmn	0:3ac96e360672	764
charlesmn	0:3ac96e360672	765	pdata->histogram_config__high_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	766	(odd_bin1 << 4) + odd_bin0;
charlesmn	0:3ac96e360672	767	pdata->histogram_config__high_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	768	(odd_bin3 << 4) + odd_bin2;
charlesmn	0:3ac96e360672	769	pdata->histogram_config__high_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	770	(odd_bin5 << 4) + odd_bin4;
charlesmn	0:3ac96e360672	771
charlesmn	0:3ac96e360672	772	pdata->histogram_config__high_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	773	= pdata->histogram_config__high_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	774	pdata->histogram_config__high_amb_odd_bin_2_3
charlesmn	0:3ac96e360672	775	= pdata->histogram_config__high_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	776	pdata->histogram_config__high_amb_odd_bin_4_5
charlesmn	0:3ac96e360672	777	= pdata->histogram_config__high_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	778
charlesmn	0:3ac96e360672	779
charlesmn	0:3ac96e360672	780
charlesmn	0:3ac96e360672	781	pdata->histogram_config__amb_thresh_low = 0xFFFF;
charlesmn	0:3ac96e360672	782	pdata->histogram_config__amb_thresh_high = 0xFFFF;
charlesmn	0:3ac96e360672	783
charlesmn	0:3ac96e360672	784
charlesmn	0:3ac96e360672	785
charlesmn	0:3ac96e360672	786	pdata->histogram_config__spad_array_selection = 0x00;
charlesmn	0:3ac96e360672	787	}
charlesmn	0:3ac96e360672	788
charlesmn	0:3ac96e360672	789
charlesmn	0:3ac96e360672	790	void VL53L1_init_xtalk_bin_data_struct(
charlesmn	0:3ac96e360672	791	uint32_t bin_value,
charlesmn	0:3ac96e360672	792	uint16_t VL53L1_p_024,
charlesmn	0:3ac96e360672	793	VL53L1_xtalk_histogram_shape_t *pdata)
charlesmn	0:3ac96e360672	794	{
charlesmn	0:3ac96e360672	795
charlesmn	0:3ac96e360672	796
charlesmn	0:3ac96e360672	797
charlesmn	0:3ac96e360672	798	uint16_t i = 0;
charlesmn	0:3ac96e360672	799
charlesmn	0:3ac96e360672	800	pdata->zone_id = 0;
charlesmn	0:3ac96e360672	801	pdata->time_stamp = 0;
charlesmn	0:3ac96e360672	802
charlesmn	0:3ac96e360672	803	pdata->VL53L1_p_022 = 0;
charlesmn	0:3ac96e360672	804	pdata->VL53L1_p_023 = VL53L1_XTALK_HISTO_BINS;
charlesmn	0:3ac96e360672	805	pdata->VL53L1_p_024 = (uint8_t)VL53L1_p_024;
charlesmn	0:3ac96e360672	806
charlesmn	0:3ac96e360672	807	pdata->phasecal_result__reference_phase = 0;
charlesmn	0:3ac96e360672	808	pdata->phasecal_result__vcsel_start = 0;
charlesmn	0:3ac96e360672	809	pdata->cal_config__vcsel_start = 0;
charlesmn	0:3ac96e360672	810
charlesmn	0:3ac96e360672	811	pdata->vcsel_width = 0;
charlesmn	0:3ac96e360672	812	pdata->VL53L1_p_019 = 0;
charlesmn	0:3ac96e360672	813
charlesmn	0:3ac96e360672	814	pdata->zero_distance_phase = 0;
charlesmn	0:3ac96e360672	815
charlesmn	0:3ac96e360672	816	for (i = 0; i < VL53L1_XTALK_HISTO_BINS; i++) {
charlesmn	0:3ac96e360672	817	if (i < VL53L1_p_024)
charlesmn	0:3ac96e360672	818	pdata->bin_data[i] = bin_value;
charlesmn	0:3ac96e360672	819	else
charlesmn	0:3ac96e360672	820	pdata->bin_data[i] = 0;
charlesmn	0:3ac96e360672	821	}
charlesmn	0:3ac96e360672	822	}
charlesmn	0:3ac96e360672	823
charlesmn	0:3ac96e360672	824
charlesmn	0:3ac96e360672	825	void VL53L1_i2c_encode_uint16_t(
charlesmn	0:3ac96e360672	826	uint16_t ip_value,
charlesmn	0:3ac96e360672	827	uint16_t count,
charlesmn	0:3ac96e360672	828	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	829	{
charlesmn	0:3ac96e360672	830
charlesmn	0:3ac96e360672	831
charlesmn	0:3ac96e360672	832	uint16_t i = 0;
charlesmn	0:3ac96e360672	833	uint16_t VL53L1_p_002 = 0;
charlesmn	0:3ac96e360672	834
charlesmn	0:3ac96e360672	835	VL53L1_p_002 = ip_value;
charlesmn	0:3ac96e360672	836
charlesmn	0:3ac96e360672	837	for (i = 0; i < count; i++) {
charlesmn	0:3ac96e360672	838	pbuffer[count-i-1] = (uint8_t)(VL53L1_p_002 & 0x00FF);
charlesmn	0:3ac96e360672	839	VL53L1_p_002 = VL53L1_p_002 >> 8;
charlesmn	0:3ac96e360672	840	}
charlesmn	0:3ac96e360672	841	}
charlesmn	0:3ac96e360672	842
charlesmn	0:3ac96e360672	843	uint16_t VL53L1_i2c_decode_uint16_t(
charlesmn	0:3ac96e360672	844	uint16_t count,
charlesmn	0:3ac96e360672	845	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	846	{
charlesmn	0:3ac96e360672	847
charlesmn	0:3ac96e360672	848
charlesmn	0:3ac96e360672	849	uint16_t value = 0x00;
charlesmn	0:3ac96e360672	850
charlesmn	0:3ac96e360672	851	while (count-- > 0)
charlesmn	0:3ac96e360672	852	value = (value << 8) \| (uint16_t)*pbuffer++;
charlesmn	0:3ac96e360672	853
charlesmn	0:3ac96e360672	854	return value;
charlesmn	0:3ac96e360672	855	}
charlesmn	0:3ac96e360672	856
charlesmn	0:3ac96e360672	857
charlesmn	0:3ac96e360672	858	void VL53L1_i2c_encode_int16_t(
charlesmn	0:3ac96e360672	859	int16_t ip_value,
charlesmn	0:3ac96e360672	860	uint16_t count,
charlesmn	0:3ac96e360672	861	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	862	{
charlesmn	0:3ac96e360672	863
charlesmn	0:3ac96e360672	864
charlesmn	0:3ac96e360672	865	uint16_t i = 0;
charlesmn	0:3ac96e360672	866	int16_t VL53L1_p_002 = 0;
charlesmn	0:3ac96e360672	867
charlesmn	0:3ac96e360672	868	VL53L1_p_002 = ip_value;
charlesmn	0:3ac96e360672	869
charlesmn	0:3ac96e360672	870	for (i = 0; i < count; i++) {
charlesmn	0:3ac96e360672	871	pbuffer[count-i-1] = (uint8_t)(VL53L1_p_002 & 0x00FF);
charlesmn	0:3ac96e360672	872	VL53L1_p_002 = VL53L1_p_002 >> 8;
charlesmn	0:3ac96e360672	873	}
charlesmn	0:3ac96e360672	874	}
charlesmn	0:3ac96e360672	875
charlesmn	0:3ac96e360672	876	int16_t VL53L1_i2c_decode_int16_t(
charlesmn	0:3ac96e360672	877	uint16_t count,
charlesmn	0:3ac96e360672	878	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	879	{
charlesmn	0:3ac96e360672	880
charlesmn	0:3ac96e360672	881
charlesmn	0:3ac96e360672	882	int16_t value = 0x00;
charlesmn	0:3ac96e360672	883
charlesmn	0:3ac96e360672	884
charlesmn	0:3ac96e360672	885	if (*pbuffer >= 0x80)
charlesmn	0:3ac96e360672	886	value = 0xFFFF;
charlesmn	0:3ac96e360672	887
charlesmn	0:3ac96e360672	888	while (count-- > 0)
charlesmn	0:3ac96e360672	889	value = (value << 8) \| (int16_t)*pbuffer++;
charlesmn	0:3ac96e360672	890
charlesmn	0:3ac96e360672	891	return value;
charlesmn	0:3ac96e360672	892	}
charlesmn	0:3ac96e360672	893
charlesmn	0:3ac96e360672	894	void VL53L1_i2c_encode_uint32_t(
charlesmn	0:3ac96e360672	895	uint32_t ip_value,
charlesmn	0:3ac96e360672	896	uint16_t count,
charlesmn	0:3ac96e360672	897	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	898	{
charlesmn	0:3ac96e360672	899
charlesmn	0:3ac96e360672	900
charlesmn	0:3ac96e360672	901	uint16_t i = 0;
charlesmn	0:3ac96e360672	902	uint32_t VL53L1_p_002 = 0;
charlesmn	0:3ac96e360672	903
charlesmn	0:3ac96e360672	904	VL53L1_p_002 = ip_value;
charlesmn	0:3ac96e360672	905
charlesmn	0:3ac96e360672	906	for (i = 0; i < count; i++) {
charlesmn	0:3ac96e360672	907	pbuffer[count-i-1] = (uint8_t)(VL53L1_p_002 & 0x00FF);
charlesmn	0:3ac96e360672	908	VL53L1_p_002 = VL53L1_p_002 >> 8;
charlesmn	0:3ac96e360672	909	}
charlesmn	0:3ac96e360672	910	}
charlesmn	0:3ac96e360672	911
charlesmn	0:3ac96e360672	912	uint32_t VL53L1_i2c_decode_uint32_t(
charlesmn	0:3ac96e360672	913	uint16_t count,
charlesmn	0:3ac96e360672	914	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	915	{
charlesmn	0:3ac96e360672	916
charlesmn	0:3ac96e360672	917
charlesmn	0:3ac96e360672	918	uint32_t value = 0x00;
charlesmn	0:3ac96e360672	919
charlesmn	0:3ac96e360672	920	while (count-- > 0)
charlesmn	0:3ac96e360672	921	value = (value << 8) \| (uint32_t)*pbuffer++;
charlesmn	0:3ac96e360672	922
charlesmn	0:3ac96e360672	923	return value;
charlesmn	0:3ac96e360672	924	}
charlesmn	0:3ac96e360672	925
charlesmn	0:3ac96e360672	926
charlesmn	0:3ac96e360672	927	uint32_t VL53L1_i2c_decode_with_mask(
charlesmn	0:3ac96e360672	928	uint16_t count,
charlesmn	0:3ac96e360672	929	uint8_t *pbuffer,
charlesmn	0:3ac96e360672	930	uint32_t bit_mask,
charlesmn	0:3ac96e360672	931	uint32_t down_shift,
charlesmn	0:3ac96e360672	932	uint32_t offset)
charlesmn	0:3ac96e360672	933	{
charlesmn	0:3ac96e360672	934
charlesmn	0:3ac96e360672	935
charlesmn	0:3ac96e360672	936	uint32_t value = 0x00;
charlesmn	0:3ac96e360672	937
charlesmn	0:3ac96e360672	938
charlesmn	0:3ac96e360672	939	while (count-- > 0)
charlesmn	0:3ac96e360672	940	value = (value << 8) \| (uint32_t)*pbuffer++;
charlesmn	0:3ac96e360672	941
charlesmn	0:3ac96e360672	942
charlesmn	0:3ac96e360672	943	value = value & bit_mask;
charlesmn	0:3ac96e360672	944	if (down_shift > 0)
charlesmn	0:3ac96e360672	945	value = value >> down_shift;
charlesmn	0:3ac96e360672	946
charlesmn	0:3ac96e360672	947
charlesmn	0:3ac96e360672	948	value = value + offset;
charlesmn	0:3ac96e360672	949
charlesmn	0:3ac96e360672	950	return value;
charlesmn	0:3ac96e360672	951	}
charlesmn	0:3ac96e360672	952
charlesmn	0:3ac96e360672	953
charlesmn	0:3ac96e360672	954	void VL53L1_i2c_encode_int32_t(
charlesmn	0:3ac96e360672	955	int32_t ip_value,
charlesmn	0:3ac96e360672	956	uint16_t count,
charlesmn	0:3ac96e360672	957	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	958	{
charlesmn	0:3ac96e360672	959
charlesmn	0:3ac96e360672	960
charlesmn	0:3ac96e360672	961	uint16_t i = 0;
charlesmn	0:3ac96e360672	962	int32_t VL53L1_p_002 = 0;
charlesmn	0:3ac96e360672	963
charlesmn	0:3ac96e360672	964	VL53L1_p_002 = ip_value;
charlesmn	0:3ac96e360672	965
charlesmn	0:3ac96e360672	966	for (i = 0; i < count; i++) {
charlesmn	0:3ac96e360672	967	pbuffer[count-i-1] = (uint8_t)(VL53L1_p_002 & 0x00FF);
charlesmn	0:3ac96e360672	968	VL53L1_p_002 = VL53L1_p_002 >> 8;
charlesmn	0:3ac96e360672	969	}
charlesmn	0:3ac96e360672	970	}
charlesmn	0:3ac96e360672	971
charlesmn	0:3ac96e360672	972	int32_t VL53L1_i2c_decode_int32_t(
charlesmn	0:3ac96e360672	973	uint16_t count,
charlesmn	0:3ac96e360672	974	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	975	{
charlesmn	0:3ac96e360672	976
charlesmn	0:3ac96e360672	977
charlesmn	0:3ac96e360672	978	int32_t value = 0x00;
charlesmn	0:3ac96e360672	979
charlesmn	0:3ac96e360672	980
charlesmn	0:3ac96e360672	981	if (*pbuffer >= 0x80)
charlesmn	0:3ac96e360672	982	value = 0xFFFFFFFF;
charlesmn	0:3ac96e360672	983
charlesmn	0:3ac96e360672	984	while (count-- > 0)
charlesmn	0:3ac96e360672	985	value = (value << 8) \| (int32_t)*pbuffer++;
charlesmn	0:3ac96e360672	986
charlesmn	0:3ac96e360672	987	return value;
charlesmn	0:3ac96e360672	988	}
charlesmn	0:3ac96e360672	989
charlesmn	0:3ac96e360672	990
charlesmn	0:3ac96e360672	991	VL53L1_Error VL53L1_start_test(
charlesmn	0:3ac96e360672	992	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	993	uint8_t test_mode__ctrl)
charlesmn	0:3ac96e360672	994	{
charlesmn	0:3ac96e360672	995
charlesmn	0:3ac96e360672	996
charlesmn	0:3ac96e360672	997	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	998
charlesmn	0:3ac96e360672	999	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1000
charlesmn	0:3ac96e360672	1001	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	1002	status = VL53L1_WrByte(
charlesmn	0:3ac96e360672	1003	Dev,
charlesmn	0:3ac96e360672	1004	VL53L1_TEST_MODE__CTRL,
charlesmn	0:3ac96e360672	1005	test_mode__ctrl);
charlesmn	0:3ac96e360672	1006	}
charlesmn	0:3ac96e360672	1007
charlesmn	0:3ac96e360672	1008	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1009
charlesmn	0:3ac96e360672	1010	return status;
charlesmn	0:3ac96e360672	1011	}
charlesmn	0:3ac96e360672	1012
charlesmn	0:3ac96e360672	1013
charlesmn	0:3ac96e360672	1014	VL53L1_Error VL53L1_set_firmware_enable_register(
charlesmn	0:3ac96e360672	1015	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	1016	uint8_t value)
charlesmn	0:3ac96e360672	1017	{
charlesmn	0:3ac96e360672	1018
charlesmn	0:3ac96e360672	1019
charlesmn	0:3ac96e360672	1020	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1021	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	1022
charlesmn	0:3ac96e360672	1023	pdev->sys_ctrl.firmware__enable = value;
charlesmn	0:3ac96e360672	1024
charlesmn	0:3ac96e360672	1025	status = VL53L1_WrByte(
charlesmn	0:3ac96e360672	1026	Dev,
charlesmn	0:3ac96e360672	1027	VL53L1_FIRMWARE__ENABLE,
charlesmn	0:3ac96e360672	1028	pdev->sys_ctrl.firmware__enable);
charlesmn	0:3ac96e360672	1029
charlesmn	0:3ac96e360672	1030	return status;
charlesmn	0:3ac96e360672	1031	}
charlesmn	0:3ac96e360672	1032
charlesmn	0:3ac96e360672	1033	VL53L1_Error VL53L1_enable_firmware(
charlesmn	0:3ac96e360672	1034	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	1035	{
charlesmn	0:3ac96e360672	1036
charlesmn	0:3ac96e360672	1037
charlesmn	0:3ac96e360672	1038	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1039
charlesmn	0:3ac96e360672	1040	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1041
charlesmn	0:3ac96e360672	1042	status = VL53L1_set_firmware_enable_register(Dev, 0x01);
charlesmn	0:3ac96e360672	1043
charlesmn	0:3ac96e360672	1044	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1045
charlesmn	0:3ac96e360672	1046	return status;
charlesmn	0:3ac96e360672	1047	}
charlesmn	0:3ac96e360672	1048
charlesmn	0:3ac96e360672	1049
charlesmn	0:3ac96e360672	1050	VL53L1_Error VL53L1_disable_firmware(
charlesmn	0:3ac96e360672	1051	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	1052	{
charlesmn	0:3ac96e360672	1053
charlesmn	0:3ac96e360672	1054
charlesmn	0:3ac96e360672	1055	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1056
charlesmn	0:3ac96e360672	1057	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1058
charlesmn	0:3ac96e360672	1059	status = VL53L1_set_firmware_enable_register(Dev, 0x00);
charlesmn	0:3ac96e360672	1060
charlesmn	0:3ac96e360672	1061	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1062
charlesmn	0:3ac96e360672	1063	return status;
charlesmn	0:3ac96e360672	1064	}
charlesmn	0:3ac96e360672	1065
charlesmn	0:3ac96e360672	1066
charlesmn	0:3ac96e360672	1067	VL53L1_Error VL53L1_set_powerforce_register(
charlesmn	0:3ac96e360672	1068	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	1069	uint8_t value)
charlesmn	0:3ac96e360672	1070	{
charlesmn	0:3ac96e360672	1071
charlesmn	0:3ac96e360672	1072
charlesmn	0:3ac96e360672	1073	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1074	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	1075
charlesmn	0:3ac96e360672	1076	pdev->sys_ctrl.power_management__go1_power_force = value;
charlesmn	0:3ac96e360672	1077
charlesmn	0:3ac96e360672	1078	status = VL53L1_WrByte(
charlesmn	0:3ac96e360672	1079	Dev,
charlesmn	0:3ac96e360672	1080	VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE,
charlesmn	0:3ac96e360672	1081	pdev->sys_ctrl.power_management__go1_power_force);
charlesmn	0:3ac96e360672	1082
charlesmn	0:3ac96e360672	1083	return status;
charlesmn	0:3ac96e360672	1084	}
charlesmn	0:3ac96e360672	1085
charlesmn	0:3ac96e360672	1086
charlesmn	0:3ac96e360672	1087	VL53L1_Error VL53L1_enable_powerforce(
charlesmn	0:3ac96e360672	1088	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	1089	{
charlesmn	0:3ac96e360672	1090
charlesmn	0:3ac96e360672	1091
charlesmn	0:3ac96e360672	1092	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1093
charlesmn	0:3ac96e360672	1094	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1095
charlesmn	0:3ac96e360672	1096	status = VL53L1_set_powerforce_register(Dev, 0x01);
charlesmn	0:3ac96e360672	1097
charlesmn	0:3ac96e360672	1098	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1099
charlesmn	0:3ac96e360672	1100	return status;
charlesmn	0:3ac96e360672	1101	}
charlesmn	0:3ac96e360672	1102
charlesmn	0:3ac96e360672	1103
charlesmn	0:3ac96e360672	1104	VL53L1_Error VL53L1_disable_powerforce(
charlesmn	0:3ac96e360672	1105	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	1106	{
charlesmn	0:3ac96e360672	1107
charlesmn	0:3ac96e360672	1108
charlesmn	0:3ac96e360672	1109	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1110
charlesmn	0:3ac96e360672	1111	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1112
charlesmn	0:3ac96e360672	1113	status = VL53L1_set_powerforce_register(Dev, 0x00);
charlesmn	0:3ac96e360672	1114
charlesmn	0:3ac96e360672	1115	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1116
charlesmn	0:3ac96e360672	1117	return status;
charlesmn	0:3ac96e360672	1118	}
charlesmn	0:3ac96e360672	1119
charlesmn	0:3ac96e360672	1120
charlesmn	0:3ac96e360672	1121	VL53L1_Error VL53L1_clear_interrupt(
charlesmn	0:3ac96e360672	1122	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	1123	{
charlesmn	0:3ac96e360672	1124
charlesmn	0:3ac96e360672	1125
charlesmn	0:3ac96e360672	1126	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1127	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	1128
charlesmn	0:3ac96e360672	1129	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1130
charlesmn	0:3ac96e360672	1131	pdev->sys_ctrl.system__interrupt_clear = VL53L1_CLEAR_RANGE_INT;
charlesmn	0:3ac96e360672	1132
charlesmn	0:3ac96e360672	1133	status = VL53L1_WrByte(
charlesmn	0:3ac96e360672	1134	Dev,
charlesmn	0:3ac96e360672	1135	VL53L1_SYSTEM__INTERRUPT_CLEAR,
charlesmn	0:3ac96e360672	1136	pdev->sys_ctrl.system__interrupt_clear);
charlesmn	0:3ac96e360672	1137
charlesmn	0:3ac96e360672	1138	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1139
charlesmn	0:3ac96e360672	1140	return status;
charlesmn	0:3ac96e360672	1141	}
charlesmn	0:3ac96e360672	1142
charlesmn	0:3ac96e360672	1143
charlesmn	0:3ac96e360672	1144	VL53L1_Error VL53L1_force_shadow_stream_count_to_zero(
charlesmn	0:3ac96e360672	1145	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	1146	{
charlesmn	0:3ac96e360672	1147
charlesmn	0:3ac96e360672	1148
charlesmn	0:3ac96e360672	1149	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1150
charlesmn	0:3ac96e360672	1151	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	1152	status = VL53L1_disable_firmware(Dev);
charlesmn	0:3ac96e360672	1153
charlesmn	0:3ac96e360672	1154	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	1155	status = VL53L1_WrByte(
charlesmn	0:3ac96e360672	1156	Dev,
charlesmn	0:3ac96e360672	1157	VL53L1_SHADOW_RESULT__STREAM_COUNT,
charlesmn	0:3ac96e360672	1158	0x00);
charlesmn	0:3ac96e360672	1159	}
charlesmn	0:3ac96e360672	1160
charlesmn	0:3ac96e360672	1161	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	1162	status = VL53L1_enable_firmware(Dev);
charlesmn	0:3ac96e360672	1163
charlesmn	0:3ac96e360672	1164	return status;
charlesmn	0:3ac96e360672	1165	}
charlesmn	0:3ac96e360672	1166
charlesmn	0:3ac96e360672	1167
charlesmn	0:3ac96e360672	1168	uint32_t VL53L1_calc_macro_period_us(
charlesmn	0:3ac96e360672	1169	uint16_t fast_osc_frequency,
charlesmn	0:3ac96e360672	1170	uint8_t VL53L1_p_009)
charlesmn	0:3ac96e360672	1171	{
charlesmn	0:3ac96e360672	1172
charlesmn	0:3ac96e360672	1173
charlesmn	0:3ac96e360672	1174	uint32_t pll_period_us = 0;
charlesmn	0:3ac96e360672	1175	uint8_t VL53L1_p_031 = 0;
charlesmn	0:3ac96e360672	1176	uint32_t macro_period_us = 0;
charlesmn	0:3ac96e360672	1177
charlesmn	0:3ac96e360672	1178	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1179
charlesmn	0:3ac96e360672	1180
charlesmn	0:3ac96e360672	1181
charlesmn	0:3ac96e360672	1182	pll_period_us = VL53L1_calc_pll_period_us(fast_osc_frequency);
charlesmn	0:3ac96e360672	1183
charlesmn	0:3ac96e360672	1184
charlesmn	0:3ac96e360672	1185
charlesmn	0:3ac96e360672	1186	VL53L1_p_031 = VL53L1_decode_vcsel_period(VL53L1_p_009);
charlesmn	0:3ac96e360672	1187
charlesmn	0:3ac96e360672	1188
charlesmn	0:3ac96e360672	1189
charlesmn	0:3ac96e360672	1190	macro_period_us =
charlesmn	0:3ac96e360672	1191	(uint32_t)VL53L1_MACRO_PERIOD_VCSEL_PERIODS *
charlesmn	0:3ac96e360672	1192	pll_period_us;
charlesmn	0:3ac96e360672	1193	macro_period_us = macro_period_us >> 6;
charlesmn	0:3ac96e360672	1194
charlesmn	0:3ac96e360672	1195	macro_period_us = macro_period_us * (uint32_t)VL53L1_p_031;
charlesmn	0:3ac96e360672	1196	macro_period_us = macro_period_us >> 6;
charlesmn	0:3ac96e360672	1197
charlesmn	0:3ac96e360672	1198
charlesmn	0:3ac96e360672	1199
charlesmn	0:3ac96e360672	1200	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1201
charlesmn	0:3ac96e360672	1202	return macro_period_us;
charlesmn	0:3ac96e360672	1203	}
charlesmn	0:3ac96e360672	1204
charlesmn	0:3ac96e360672	1205
charlesmn	0:3ac96e360672	1206	uint16_t VL53L1_calc_range_ignore_threshold(
charlesmn	0:3ac96e360672	1207	uint32_t central_rate,
charlesmn	0:3ac96e360672	1208	int16_t x_gradient,
charlesmn	0:3ac96e360672	1209	int16_t y_gradient,
charlesmn	0:3ac96e360672	1210	uint8_t rate_mult)
charlesmn	0:3ac96e360672	1211	{
charlesmn	0:3ac96e360672	1212
charlesmn	0:3ac96e360672	1213
charlesmn	0:3ac96e360672	1214	int32_t range_ignore_thresh_int = 0;
charlesmn	0:3ac96e360672	1215	uint16_t range_ignore_thresh_kcps = 0;
charlesmn	0:3ac96e360672	1216	int32_t central_rate_int = 0;
charlesmn	0:3ac96e360672	1217	int16_t x_gradient_int = 0;
charlesmn	0:3ac96e360672	1218	int16_t y_gradient_int = 0;
charlesmn	0:3ac96e360672	1219
charlesmn	0:3ac96e360672	1220	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1221
charlesmn	0:3ac96e360672	1222
charlesmn	0:3ac96e360672	1223
charlesmn	0:3ac96e360672	1224	central_rate_int = ((int32_t)central_rate * (1 << 4)) / (1000);
charlesmn	0:3ac96e360672	1225
charlesmn	0:3ac96e360672	1226	if (x_gradient < 0)
charlesmn	0:3ac96e360672	1227	x_gradient_int = x_gradient * -1;
charlesmn	0:3ac96e360672	1228
charlesmn	0:3ac96e360672	1229	if (y_gradient < 0)
charlesmn	0:3ac96e360672	1230	y_gradient_int = y_gradient * -1;
charlesmn	0:3ac96e360672	1231
charlesmn	0:3ac96e360672	1232
charlesmn	0:3ac96e360672	1233
charlesmn	0:3ac96e360672	1234
charlesmn	0:3ac96e360672	1235
charlesmn	0:3ac96e360672	1236	range_ignore_thresh_int = (8 * x_gradient_int * 4) +
charlesmn	0:3ac96e360672	1237	(8 * y_gradient_int * 4);
charlesmn	0:3ac96e360672	1238
charlesmn	0:3ac96e360672	1239
charlesmn	0:3ac96e360672	1240
charlesmn	0:3ac96e360672	1241	range_ignore_thresh_int = range_ignore_thresh_int / 1000;
charlesmn	0:3ac96e360672	1242
charlesmn	0:3ac96e360672	1243
charlesmn	0:3ac96e360672	1244
charlesmn	0:3ac96e360672	1245	range_ignore_thresh_int = range_ignore_thresh_int + central_rate_int;
charlesmn	0:3ac96e360672	1246
charlesmn	0:3ac96e360672	1247
charlesmn	0:3ac96e360672	1248
charlesmn	0:3ac96e360672	1249	range_ignore_thresh_int = (int32_t)rate_mult * range_ignore_thresh_int;
charlesmn	0:3ac96e360672	1250
charlesmn	0:3ac96e360672	1251	range_ignore_thresh_int = (range_ignore_thresh_int + (1<<4)) / (1<<5);
charlesmn	0:3ac96e360672	1252
charlesmn	0:3ac96e360672	1253
charlesmn	0:3ac96e360672	1254
charlesmn	0:3ac96e360672	1255	if (range_ignore_thresh_int > 0xFFFF)
charlesmn	0:3ac96e360672	1256	range_ignore_thresh_kcps = 0xFFFF;
charlesmn	0:3ac96e360672	1257	else
charlesmn	0:3ac96e360672	1258	range_ignore_thresh_kcps = (uint16_t)range_ignore_thresh_int;
charlesmn	0:3ac96e360672	1259
charlesmn	0:3ac96e360672	1260
charlesmn	0:3ac96e360672	1261
charlesmn	0:3ac96e360672	1262	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1263
charlesmn	0:3ac96e360672	1264	return range_ignore_thresh_kcps;
charlesmn	0:3ac96e360672	1265	}
charlesmn	0:3ac96e360672	1266
charlesmn	0:3ac96e360672	1267
charlesmn	0:3ac96e360672	1268	uint32_t VL53L1_calc_timeout_mclks(
charlesmn	0:3ac96e360672	1269	uint32_t timeout_us,
charlesmn	0:3ac96e360672	1270	uint32_t macro_period_us)
charlesmn	0:3ac96e360672	1271	{
charlesmn	0:3ac96e360672	1272
charlesmn	0:3ac96e360672	1273
charlesmn	0:3ac96e360672	1274	uint32_t timeout_mclks = 0;
charlesmn	0:3ac96e360672	1275
charlesmn	0:3ac96e360672	1276	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1277
charlesmn	0:3ac96e360672	1278	timeout_mclks =
charlesmn	0:3ac96e360672	1279	((timeout_us << 12) + (macro_period_us>>1)) /
charlesmn	0:3ac96e360672	1280	macro_period_us;
charlesmn	0:3ac96e360672	1281
charlesmn	0:3ac96e360672	1282	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1283
charlesmn	0:3ac96e360672	1284	return timeout_mclks;
charlesmn	0:3ac96e360672	1285	}
charlesmn	0:3ac96e360672	1286
charlesmn	0:3ac96e360672	1287
charlesmn	0:3ac96e360672	1288	uint16_t VL53L1_calc_encoded_timeout(
charlesmn	0:3ac96e360672	1289	uint32_t timeout_us,
charlesmn	0:3ac96e360672	1290	uint32_t macro_period_us)
charlesmn	0:3ac96e360672	1291	{
charlesmn	0:3ac96e360672	1292
charlesmn	0:3ac96e360672	1293
charlesmn	0:3ac96e360672	1294	uint32_t timeout_mclks = 0;
charlesmn	0:3ac96e360672	1295	uint16_t timeout_encoded = 0;
charlesmn	0:3ac96e360672	1296
charlesmn	0:3ac96e360672	1297	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1298
charlesmn	0:3ac96e360672	1299	timeout_mclks =
charlesmn	0:3ac96e360672	1300	VL53L1_calc_timeout_mclks(timeout_us, macro_period_us);
charlesmn	0:3ac96e360672	1301
charlesmn	0:3ac96e360672	1302	timeout_encoded =
charlesmn	0:3ac96e360672	1303	VL53L1_encode_timeout(timeout_mclks);
charlesmn	0:3ac96e360672	1304
charlesmn	0:3ac96e360672	1305
charlesmn	0:3ac96e360672	1306
charlesmn	0:3ac96e360672	1307	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1308
charlesmn	0:3ac96e360672	1309	return timeout_encoded;
charlesmn	0:3ac96e360672	1310	}
charlesmn	0:3ac96e360672	1311
charlesmn	0:3ac96e360672	1312
charlesmn	0:3ac96e360672	1313	uint32_t VL53L1_calc_timeout_us(
charlesmn	0:3ac96e360672	1314	uint32_t timeout_mclks,
charlesmn	0:3ac96e360672	1315	uint32_t macro_period_us)
charlesmn	0:3ac96e360672	1316	{
charlesmn	0:3ac96e360672	1317
charlesmn	0:3ac96e360672	1318
charlesmn	0:3ac96e360672	1319	uint32_t timeout_us = 0;
charlesmn	0:3ac96e360672	1320	uint64_t tmp = 0;
charlesmn	0:3ac96e360672	1321
charlesmn	0:3ac96e360672	1322	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1323
charlesmn	0:3ac96e360672	1324	tmp = (uint64_t)timeout_mclks * (uint64_t)macro_period_us;
charlesmn	0:3ac96e360672	1325	tmp += 0x00800;
charlesmn	0:3ac96e360672	1326	tmp = tmp >> 12;
charlesmn	0:3ac96e360672	1327
charlesmn	0:3ac96e360672	1328	timeout_us = (uint32_t)tmp;
charlesmn	0:3ac96e360672	1329
charlesmn	0:3ac96e360672	1330
charlesmn	0:3ac96e360672	1331
charlesmn	0:3ac96e360672	1332	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1333
charlesmn	0:3ac96e360672	1334	return timeout_us;
charlesmn	0:3ac96e360672	1335	}
charlesmn	0:3ac96e360672	1336
charlesmn	0:3ac96e360672	1337	uint32_t VL53L1_calc_crosstalk_plane_offset_with_margin(
charlesmn	0:3ac96e360672	1338	uint32_t plane_offset_kcps,
charlesmn	0:3ac96e360672	1339	int16_t margin_offset_kcps)
charlesmn	0:3ac96e360672	1340	{
charlesmn	0:3ac96e360672	1341	uint32_t plane_offset_with_margin = 0;
charlesmn	0:3ac96e360672	1342	int32_t plane_offset_kcps_temp = 0;
charlesmn	0:3ac96e360672	1343
charlesmn	0:3ac96e360672	1344	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1345
charlesmn	0:3ac96e360672	1346	plane_offset_kcps_temp =
charlesmn	0:3ac96e360672	1347	(int32_t)plane_offset_kcps +
charlesmn	0:3ac96e360672	1348	(int32_t)margin_offset_kcps;
charlesmn	0:3ac96e360672	1349
charlesmn	0:3ac96e360672	1350	if (plane_offset_kcps_temp < 0)
charlesmn	0:3ac96e360672	1351	plane_offset_kcps_temp = 0;
charlesmn	0:3ac96e360672	1352	else
charlesmn	0:3ac96e360672	1353	if (plane_offset_kcps_temp > 0x3FFFF)
charlesmn	0:3ac96e360672	1354	plane_offset_kcps_temp = 0x3FFFF;
charlesmn	0:3ac96e360672	1355
charlesmn	0:3ac96e360672	1356	plane_offset_with_margin = (uint32_t) plane_offset_kcps_temp;
charlesmn	0:3ac96e360672	1357
charlesmn	0:3ac96e360672	1358	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1359
charlesmn	0:3ac96e360672	1360	return plane_offset_with_margin;
charlesmn	0:3ac96e360672	1361
charlesmn	0:3ac96e360672	1362	}
charlesmn	0:3ac96e360672	1363
charlesmn	0:3ac96e360672	1364	uint32_t VL53L1_calc_decoded_timeout_us(
charlesmn	0:3ac96e360672	1365	uint16_t timeout_encoded,
charlesmn	0:3ac96e360672	1366	uint32_t macro_period_us)
charlesmn	0:3ac96e360672	1367	{
charlesmn	0:3ac96e360672	1368
charlesmn	0:3ac96e360672	1369
charlesmn	0:3ac96e360672	1370	uint32_t timeout_mclks = 0;
charlesmn	0:3ac96e360672	1371	uint32_t timeout_us = 0;
charlesmn	0:3ac96e360672	1372
charlesmn	0:3ac96e360672	1373	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1374
charlesmn	0:3ac96e360672	1375	timeout_mclks =
charlesmn	0:3ac96e360672	1376	VL53L1_decode_timeout(timeout_encoded);
charlesmn	0:3ac96e360672	1377
charlesmn	0:3ac96e360672	1378	timeout_us =
charlesmn	0:3ac96e360672	1379	VL53L1_calc_timeout_us(timeout_mclks, macro_period_us);
charlesmn	0:3ac96e360672	1380
charlesmn	0:3ac96e360672	1381	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1382
charlesmn	0:3ac96e360672	1383	return timeout_us;
charlesmn	0:3ac96e360672	1384	}
charlesmn	0:3ac96e360672	1385
charlesmn	0:3ac96e360672	1386
charlesmn	0:3ac96e360672	1387	uint16_t VL53L1_encode_timeout(uint32_t timeout_mclks)
charlesmn	0:3ac96e360672	1388	{
charlesmn	0:3ac96e360672	1389
charlesmn	0:3ac96e360672	1390
charlesmn	0:3ac96e360672	1391	uint16_t encoded_timeout = 0;
charlesmn	0:3ac96e360672	1392	uint32_t ls_byte = 0;
charlesmn	0:3ac96e360672	1393	uint16_t ms_byte = 0;
charlesmn	0:3ac96e360672	1394
charlesmn	0:3ac96e360672	1395	if (timeout_mclks > 0) {
charlesmn	0:3ac96e360672	1396	ls_byte = timeout_mclks - 1;
charlesmn	0:3ac96e360672	1397
charlesmn	0:3ac96e360672	1398	while ((ls_byte & 0xFFFFFF00) > 0) {
charlesmn	0:3ac96e360672	1399	ls_byte = ls_byte >> 1;
charlesmn	0:3ac96e360672	1400	ms_byte++;
charlesmn	0:3ac96e360672	1401	}
charlesmn	0:3ac96e360672	1402
charlesmn	0:3ac96e360672	1403	encoded_timeout = (ms_byte << 8)
charlesmn	0:3ac96e360672	1404	+ (uint16_t) (ls_byte & 0x000000FF);
charlesmn	0:3ac96e360672	1405	}
charlesmn	0:3ac96e360672	1406
charlesmn	0:3ac96e360672	1407	return encoded_timeout;
charlesmn	0:3ac96e360672	1408	}
charlesmn	0:3ac96e360672	1409
charlesmn	0:3ac96e360672	1410
charlesmn	0:3ac96e360672	1411	uint32_t VL53L1_decode_timeout(uint16_t encoded_timeout)
charlesmn	0:3ac96e360672	1412	{
charlesmn	0:3ac96e360672	1413
charlesmn	0:3ac96e360672	1414
charlesmn	0:3ac96e360672	1415	uint32_t timeout_macro_clks = 0;
charlesmn	0:3ac96e360672	1416
charlesmn	0:3ac96e360672	1417	timeout_macro_clks = ((uint32_t) (encoded_timeout & 0x00FF)
charlesmn	0:3ac96e360672	1418	<< (uint32_t) ((encoded_timeout & 0xFF00) >> 8)) + 1;
charlesmn	0:3ac96e360672	1419
charlesmn	0:3ac96e360672	1420	return timeout_macro_clks;
charlesmn	0:3ac96e360672	1421	}
charlesmn	0:3ac96e360672	1422
charlesmn	0:3ac96e360672	1423
charlesmn	0:3ac96e360672	1424	VL53L1_Error VL53L1_calc_timeout_register_values(
charlesmn	0:3ac96e360672	1425	uint32_t phasecal_config_timeout_us,
charlesmn	0:3ac96e360672	1426	uint32_t mm_config_timeout_us,
charlesmn	0:3ac96e360672	1427	uint32_t range_config_timeout_us,
charlesmn	0:3ac96e360672	1428	uint16_t fast_osc_frequency,
charlesmn	0:3ac96e360672	1429	VL53L1_general_config_t *pgeneral,
charlesmn	0:3ac96e360672	1430	VL53L1_timing_config_t *ptiming)
charlesmn	0:3ac96e360672	1431	{
charlesmn	0:3ac96e360672	1432
charlesmn	0:3ac96e360672	1433
charlesmn	0:3ac96e360672	1434	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1435
charlesmn	0:3ac96e360672	1436	uint32_t macro_period_us = 0;
charlesmn	0:3ac96e360672	1437	uint32_t timeout_mclks = 0;
charlesmn	0:3ac96e360672	1438	uint16_t timeout_encoded = 0;
charlesmn	0:3ac96e360672	1439
charlesmn	0:3ac96e360672	1440	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1441
charlesmn	0:3ac96e360672	1442	if (fast_osc_frequency == 0) {
charlesmn	0:3ac96e360672	1443	status = VL53L1_ERROR_DIVISION_BY_ZERO;
charlesmn	0:3ac96e360672	1444	} else {
charlesmn	0:3ac96e360672	1445
charlesmn	0:3ac96e360672	1446	macro_period_us =
charlesmn	0:3ac96e360672	1447	VL53L1_calc_macro_period_us(
charlesmn	0:3ac96e360672	1448	fast_osc_frequency,
charlesmn	0:3ac96e360672	1449	ptiming->range_config__vcsel_period_a);
charlesmn	0:3ac96e360672	1450
charlesmn	0:3ac96e360672	1451
charlesmn	0:3ac96e360672	1452	timeout_mclks =
charlesmn	0:3ac96e360672	1453	VL53L1_calc_timeout_mclks(
charlesmn	0:3ac96e360672	1454	phasecal_config_timeout_us,
charlesmn	0:3ac96e360672	1455	macro_period_us);
charlesmn	0:3ac96e360672	1456
charlesmn	0:3ac96e360672	1457
charlesmn	0:3ac96e360672	1458	if (timeout_mclks > 0xFF)
charlesmn	0:3ac96e360672	1459	timeout_mclks = 0xFF;
charlesmn	0:3ac96e360672	1460
charlesmn	0:3ac96e360672	1461	pgeneral->phasecal_config__timeout_macrop =
charlesmn	0:3ac96e360672	1462	(uint8_t)timeout_mclks;
charlesmn	0:3ac96e360672	1463
charlesmn	0:3ac96e360672	1464
charlesmn	0:3ac96e360672	1465	timeout_encoded =
charlesmn	0:3ac96e360672	1466	VL53L1_calc_encoded_timeout(
charlesmn	0:3ac96e360672	1467	mm_config_timeout_us,
charlesmn	0:3ac96e360672	1468	macro_period_us);
charlesmn	0:3ac96e360672	1469
charlesmn	0:3ac96e360672	1470	ptiming->mm_config__timeout_macrop_a_hi =
charlesmn	0:3ac96e360672	1471	(uint8_t)((timeout_encoded & 0xFF00) >> 8);
charlesmn	0:3ac96e360672	1472	ptiming->mm_config__timeout_macrop_a_lo =
charlesmn	0:3ac96e360672	1473	(uint8_t) (timeout_encoded & 0x00FF);
charlesmn	0:3ac96e360672	1474
charlesmn	0:3ac96e360672	1475
charlesmn	0:3ac96e360672	1476	timeout_encoded =
charlesmn	0:3ac96e360672	1477	VL53L1_calc_encoded_timeout(
charlesmn	0:3ac96e360672	1478	range_config_timeout_us,
charlesmn	0:3ac96e360672	1479	macro_period_us);
charlesmn	0:3ac96e360672	1480
charlesmn	0:3ac96e360672	1481	ptiming->range_config__timeout_macrop_a_hi =
charlesmn	0:3ac96e360672	1482	(uint8_t)((timeout_encoded & 0xFF00) >> 8);
charlesmn	0:3ac96e360672	1483	ptiming->range_config__timeout_macrop_a_lo =
charlesmn	0:3ac96e360672	1484	(uint8_t) (timeout_encoded & 0x00FF);
charlesmn	0:3ac96e360672	1485
charlesmn	0:3ac96e360672	1486
charlesmn	0:3ac96e360672	1487	macro_period_us =
charlesmn	0:3ac96e360672	1488	VL53L1_calc_macro_period_us(
charlesmn	0:3ac96e360672	1489	fast_osc_frequency,
charlesmn	0:3ac96e360672	1490	ptiming->range_config__vcsel_period_b);
charlesmn	0:3ac96e360672	1491
charlesmn	0:3ac96e360672	1492
charlesmn	0:3ac96e360672	1493	timeout_encoded =
charlesmn	0:3ac96e360672	1494	VL53L1_calc_encoded_timeout(
charlesmn	0:3ac96e360672	1495	mm_config_timeout_us,
charlesmn	0:3ac96e360672	1496	macro_period_us);
charlesmn	0:3ac96e360672	1497
charlesmn	0:3ac96e360672	1498	ptiming->mm_config__timeout_macrop_b_hi =
charlesmn	0:3ac96e360672	1499	(uint8_t)((timeout_encoded & 0xFF00) >> 8);
charlesmn	0:3ac96e360672	1500	ptiming->mm_config__timeout_macrop_b_lo =
charlesmn	0:3ac96e360672	1501	(uint8_t) (timeout_encoded & 0x00FF);
charlesmn	0:3ac96e360672	1502
charlesmn	0:3ac96e360672	1503
charlesmn	0:3ac96e360672	1504	timeout_encoded = VL53L1_calc_encoded_timeout(
charlesmn	0:3ac96e360672	1505	range_config_timeout_us,
charlesmn	0:3ac96e360672	1506	macro_period_us);
charlesmn	0:3ac96e360672	1507
charlesmn	0:3ac96e360672	1508	ptiming->range_config__timeout_macrop_b_hi =
charlesmn	0:3ac96e360672	1509	(uint8_t)((timeout_encoded & 0xFF00) >> 8);
charlesmn	0:3ac96e360672	1510	ptiming->range_config__timeout_macrop_b_lo =
charlesmn	0:3ac96e360672	1511	(uint8_t) (timeout_encoded & 0x00FF);
charlesmn	0:3ac96e360672	1512	}
charlesmn	0:3ac96e360672	1513
charlesmn	0:3ac96e360672	1514	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1515
charlesmn	0:3ac96e360672	1516	return status;
charlesmn	0:3ac96e360672	1517
charlesmn	0:3ac96e360672	1518	}
charlesmn	0:3ac96e360672	1519
charlesmn	0:3ac96e360672	1520
charlesmn	0:3ac96e360672	1521	uint8_t VL53L1_encode_vcsel_period(uint8_t VL53L1_p_031)
charlesmn	0:3ac96e360672	1522	{
charlesmn	0:3ac96e360672	1523
charlesmn	0:3ac96e360672	1524
charlesmn	0:3ac96e360672	1525	uint8_t vcsel_period_reg = 0;
charlesmn	0:3ac96e360672	1526
charlesmn	0:3ac96e360672	1527	vcsel_period_reg = (VL53L1_p_031 >> 1) - 1;
charlesmn	0:3ac96e360672	1528
charlesmn	0:3ac96e360672	1529	return vcsel_period_reg;
charlesmn	0:3ac96e360672	1530	}
charlesmn	0:3ac96e360672	1531
charlesmn	0:3ac96e360672	1532
charlesmn	0:3ac96e360672	1533	uint32_t VL53L1_decode_unsigned_integer(
charlesmn	0:3ac96e360672	1534	uint8_t *pbuffer,
charlesmn	0:3ac96e360672	1535	uint8_t no_of_bytes)
charlesmn	0:3ac96e360672	1536	{
charlesmn	0:3ac96e360672	1537
charlesmn	0:3ac96e360672	1538
charlesmn	0:3ac96e360672	1539	uint8_t i = 0;
charlesmn	0:3ac96e360672	1540	uint32_t decoded_value = 0;
charlesmn	0:3ac96e360672	1541
charlesmn	0:3ac96e360672	1542	for (i = 0; i < no_of_bytes; i++)
charlesmn	0:3ac96e360672	1543	decoded_value = (decoded_value << 8) + (uint32_t)pbuffer[i];
charlesmn	0:3ac96e360672	1544
charlesmn	0:3ac96e360672	1545	return decoded_value;
charlesmn	0:3ac96e360672	1546	}
charlesmn	0:3ac96e360672	1547
charlesmn	0:3ac96e360672	1548
charlesmn	0:3ac96e360672	1549	void VL53L1_encode_unsigned_integer(
charlesmn	0:3ac96e360672	1550	uint32_t ip_value,
charlesmn	0:3ac96e360672	1551	uint8_t no_of_bytes,
charlesmn	0:3ac96e360672	1552	uint8_t *pbuffer)
charlesmn	0:3ac96e360672	1553	{
charlesmn	0:3ac96e360672	1554
charlesmn	0:3ac96e360672	1555
charlesmn	0:3ac96e360672	1556	uint8_t i = 0;
charlesmn	0:3ac96e360672	1557	uint32_t VL53L1_p_002 = 0;
charlesmn	0:3ac96e360672	1558
charlesmn	0:3ac96e360672	1559	VL53L1_p_002 = ip_value;
charlesmn	0:3ac96e360672	1560	for (i = 0; i < no_of_bytes; i++) {
charlesmn	0:3ac96e360672	1561	pbuffer[no_of_bytes-i-1] = VL53L1_p_002 & 0x00FF;
charlesmn	0:3ac96e360672	1562	VL53L1_p_002 = VL53L1_p_002 >> 8;
charlesmn	0:3ac96e360672	1563	}
charlesmn	0:3ac96e360672	1564	}
charlesmn	0:3ac96e360672	1565
charlesmn	0:3ac96e360672	1566
charlesmn	0:3ac96e360672	1567	VL53L1_Error VL53L1_hist_copy_and_scale_ambient_info(
charlesmn	0:3ac96e360672	1568	VL53L1_zone_hist_info_t *pidata,
charlesmn	0:3ac96e360672	1569	VL53L1_histogram_bin_data_t *podata)
charlesmn	0:3ac96e360672	1570	{
charlesmn	0:3ac96e360672	1571
charlesmn	0:3ac96e360672	1572
charlesmn	0:3ac96e360672	1573	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1574
charlesmn	0:3ac96e360672	1575	int64_t evts = 0;
charlesmn	0:3ac96e360672	1576	int64_t tmpi = 0;
charlesmn	0:3ac96e360672	1577	int64_t tmpo = 0;
charlesmn	0:3ac96e360672	1578
charlesmn	0:3ac96e360672	1579	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1580
charlesmn	0:3ac96e360672	1581
charlesmn	0:3ac96e360672	1582	if (pidata->result__dss_actual_effective_spads == 0) {
charlesmn	0:3ac96e360672	1583	status = VL53L1_ERROR_DIVISION_BY_ZERO;
charlesmn	0:3ac96e360672	1584	} else {
charlesmn	0:3ac96e360672	1585	if (pidata->number_of_ambient_bins > 0 &&
charlesmn	0:3ac96e360672	1586	podata->number_of_ambient_bins == 0) {
charlesmn	0:3ac96e360672	1587
charlesmn	0:3ac96e360672	1588
charlesmn	0:3ac96e360672	1589
charlesmn	0:3ac96e360672	1590	tmpo = 1 + (int64_t)podata->total_periods_elapsed;
charlesmn	0:3ac96e360672	1591	tmpo *=
charlesmn	0:3ac96e360672	1592	(int64_t)podata->result__dss_actual_effective_spads;
charlesmn	0:3ac96e360672	1593
charlesmn	0:3ac96e360672	1594	tmpi = 1 + (int64_t)pidata->total_periods_elapsed;
charlesmn	0:3ac96e360672	1595	tmpi *=
charlesmn	0:3ac96e360672	1596	(int64_t)pidata->result__dss_actual_effective_spads;
charlesmn	0:3ac96e360672	1597
charlesmn	0:3ac96e360672	1598	evts = tmpo *
charlesmn	0:3ac96e360672	1599	(int64_t)pidata->ambient_events_sum;
charlesmn	0:3ac96e360672	1600	evts += (tmpi/2);
charlesmn	0:3ac96e360672	1601
charlesmn	0:3ac96e360672	1602
charlesmn	0:3ac96e360672	1603	if (tmpi != 0)
charlesmn	0:3ac96e360672	1604	evts = do_division_s(evts, tmpi);
charlesmn	0:3ac96e360672	1605
charlesmn	0:3ac96e360672	1606	podata->ambient_events_sum = (int32_t)evts;
charlesmn	0:3ac96e360672	1607
charlesmn	0:3ac96e360672	1608
charlesmn	0:3ac96e360672	1609
charlesmn	0:3ac96e360672	1610	podata->VL53L1_p_004 =
charlesmn	0:3ac96e360672	1611	podata->ambient_events_sum;
charlesmn	0:3ac96e360672	1612	podata->VL53L1_p_004 +=
charlesmn	0:3ac96e360672	1613	((int32_t)pidata->number_of_ambient_bins / 2);
charlesmn	0:3ac96e360672	1614	podata->VL53L1_p_004 /=
charlesmn	0:3ac96e360672	1615	(int32_t)pidata->number_of_ambient_bins;
charlesmn	0:3ac96e360672	1616	}
charlesmn	0:3ac96e360672	1617	}
charlesmn	0:3ac96e360672	1618
charlesmn	0:3ac96e360672	1619	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1620
charlesmn	0:3ac96e360672	1621	return status;
charlesmn	0:3ac96e360672	1622	}
charlesmn	0:3ac96e360672	1623
charlesmn	0:3ac96e360672	1624
charlesmn	0:3ac96e360672	1625	void VL53L1_hist_get_bin_sequence_config(
charlesmn	0:3ac96e360672	1626	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	1627	VL53L1_histogram_bin_data_t *pdata)
charlesmn	0:3ac96e360672	1628	{
charlesmn	0:3ac96e360672	1629
charlesmn	0:3ac96e360672	1630
charlesmn	0:3ac96e360672	1631	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	1632
charlesmn	0:3ac96e360672	1633	int32_t amb_thresh_low = 0;
charlesmn	0:3ac96e360672	1634	int32_t amb_thresh_high = 0;
charlesmn	0:3ac96e360672	1635
charlesmn	0:3ac96e360672	1636	uint8_t i = 0;
charlesmn	0:3ac96e360672	1637
charlesmn	0:3ac96e360672	1638	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1639
charlesmn	0:3ac96e360672	1640
charlesmn	0:3ac96e360672	1641
charlesmn	0:3ac96e360672	1642	amb_thresh_low = 1024 *
charlesmn	0:3ac96e360672	1643	(int32_t)pdev->hist_cfg.histogram_config__amb_thresh_low;
charlesmn	0:3ac96e360672	1644	amb_thresh_high = 1024 *
charlesmn	0:3ac96e360672	1645	(int32_t)pdev->hist_cfg.histogram_config__amb_thresh_high;
charlesmn	0:3ac96e360672	1646
charlesmn	0:3ac96e360672	1647
charlesmn	0:3ac96e360672	1648
charlesmn	0:3ac96e360672	1649	if ((pdev->ll_state.rd_stream_count & 0x01) == 0) {
charlesmn	0:3ac96e360672	1650
charlesmn	0:3ac96e360672	1651	pdata->bin_seq[5] =
charlesmn	0:3ac96e360672	1652	pdev->hist_cfg.histogram_config__mid_amb_even_bin_4_5 >> 4;
charlesmn	0:3ac96e360672	1653	pdata->bin_seq[4] =
charlesmn	0:3ac96e360672	1654	pdev->hist_cfg.histogram_config__mid_amb_even_bin_4_5 & 0x0F;
charlesmn	0:3ac96e360672	1655	pdata->bin_seq[3] =
charlesmn	0:3ac96e360672	1656	pdev->hist_cfg.histogram_config__mid_amb_even_bin_2_3 >> 4;
charlesmn	0:3ac96e360672	1657	pdata->bin_seq[2] =
charlesmn	0:3ac96e360672	1658	pdev->hist_cfg.histogram_config__mid_amb_even_bin_2_3 & 0x0F;
charlesmn	0:3ac96e360672	1659	pdata->bin_seq[1] =
charlesmn	0:3ac96e360672	1660	pdev->hist_cfg.histogram_config__mid_amb_even_bin_0_1 >> 4;
charlesmn	0:3ac96e360672	1661	pdata->bin_seq[0] =
charlesmn	0:3ac96e360672	1662	pdev->hist_cfg.histogram_config__mid_amb_even_bin_0_1 & 0x0F;
charlesmn	0:3ac96e360672	1663
charlesmn	0:3ac96e360672	1664	if (pdata->ambient_events_sum > amb_thresh_high) {
charlesmn	0:3ac96e360672	1665	pdata->bin_seq[5] =
charlesmn	0:3ac96e360672	1666	pdev->hist_cfg.histogram_config__high_amb_even_bin_4_5
charlesmn	0:3ac96e360672	1667	>> 4;
charlesmn	0:3ac96e360672	1668	pdata->bin_seq[4] =
charlesmn	0:3ac96e360672	1669	pdev->hist_cfg.histogram_config__high_amb_even_bin_4_5
charlesmn	0:3ac96e360672	1670	& 0x0F;
charlesmn	0:3ac96e360672	1671	pdata->bin_seq[3] =
charlesmn	0:3ac96e360672	1672	pdev->hist_cfg.histogram_config__high_amb_even_bin_2_3
charlesmn	0:3ac96e360672	1673	>> 4;
charlesmn	0:3ac96e360672	1674	pdata->bin_seq[2] =
charlesmn	0:3ac96e360672	1675	pdev->hist_cfg.histogram_config__high_amb_even_bin_2_3
charlesmn	0:3ac96e360672	1676	& 0x0F;
charlesmn	0:3ac96e360672	1677	pdata->bin_seq[1] =
charlesmn	0:3ac96e360672	1678	pdev->hist_cfg.histogram_config__high_amb_even_bin_0_1
charlesmn	0:3ac96e360672	1679	>> 4;
charlesmn	0:3ac96e360672	1680	pdata->bin_seq[0] =
charlesmn	0:3ac96e360672	1681	pdev->hist_cfg.histogram_config__high_amb_even_bin_0_1
charlesmn	0:3ac96e360672	1682	& 0x0F;
charlesmn	0:3ac96e360672	1683	}
charlesmn	0:3ac96e360672	1684
charlesmn	0:3ac96e360672	1685	if (pdata->ambient_events_sum < amb_thresh_low) {
charlesmn	0:3ac96e360672	1686	pdata->bin_seq[5] =
charlesmn	0:3ac96e360672	1687	pdev->hist_cfg.histogram_config__low_amb_even_bin_4_5
charlesmn	0:3ac96e360672	1688	>> 4;
charlesmn	0:3ac96e360672	1689	pdata->bin_seq[4] =
charlesmn	0:3ac96e360672	1690	pdev->hist_cfg.histogram_config__low_amb_even_bin_4_5
charlesmn	0:3ac96e360672	1691	& 0x0F;
charlesmn	0:3ac96e360672	1692	pdata->bin_seq[3] =
charlesmn	0:3ac96e360672	1693	pdev->hist_cfg.histogram_config__low_amb_even_bin_2_3
charlesmn	0:3ac96e360672	1694	>> 4;
charlesmn	0:3ac96e360672	1695	pdata->bin_seq[2] =
charlesmn	0:3ac96e360672	1696	pdev->hist_cfg.histogram_config__low_amb_even_bin_2_3
charlesmn	0:3ac96e360672	1697	& 0x0F;
charlesmn	0:3ac96e360672	1698	pdata->bin_seq[1] =
charlesmn	0:3ac96e360672	1699	pdev->hist_cfg.histogram_config__low_amb_even_bin_0_1
charlesmn	0:3ac96e360672	1700	>> 4;
charlesmn	0:3ac96e360672	1701	pdata->bin_seq[0] =
charlesmn	0:3ac96e360672	1702	pdev->hist_cfg.histogram_config__low_amb_even_bin_0_1
charlesmn	0:3ac96e360672	1703	& 0x0F;
charlesmn	0:3ac96e360672	1704	}
charlesmn	0:3ac96e360672	1705
charlesmn	0:3ac96e360672	1706	} else {
charlesmn	0:3ac96e360672	1707	pdata->bin_seq[5] =
charlesmn	0:3ac96e360672	1708	pdev->hist_cfg.histogram_config__mid_amb_odd_bin_5
charlesmn	0:3ac96e360672	1709	& 0x0F;
charlesmn	0:3ac96e360672	1710	pdata->bin_seq[4] =
charlesmn	0:3ac96e360672	1711	pdev->hist_cfg.histogram_config__mid_amb_odd_bin_3_4
charlesmn	0:3ac96e360672	1712	& 0x0F;
charlesmn	0:3ac96e360672	1713	pdata->bin_seq[3] =
charlesmn	0:3ac96e360672	1714	pdev->hist_cfg.histogram_config__mid_amb_odd_bin_3_4
charlesmn	0:3ac96e360672	1715	>> 4;
charlesmn	0:3ac96e360672	1716	pdata->bin_seq[2] =
charlesmn	0:3ac96e360672	1717	pdev->hist_cfg.histogram_config__mid_amb_odd_bin_2 &
charlesmn	0:3ac96e360672	1718	0x0F;
charlesmn	0:3ac96e360672	1719	pdata->bin_seq[1] =
charlesmn	0:3ac96e360672	1720	pdev->hist_cfg.histogram_config__mid_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	1721	>> 4;
charlesmn	0:3ac96e360672	1722	pdata->bin_seq[0] =
charlesmn	0:3ac96e360672	1723	pdev->hist_cfg.histogram_config__mid_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	1724	& 0x0F;
charlesmn	0:3ac96e360672	1725
charlesmn	0:3ac96e360672	1726	if (pdata->ambient_events_sum > amb_thresh_high) {
charlesmn	0:3ac96e360672	1727	pdata->bin_seq[5] =
charlesmn	0:3ac96e360672	1728	pdev->hist_cfg.histogram_config__high_amb_odd_bin_4_5
charlesmn	0:3ac96e360672	1729	>> 4;
charlesmn	0:3ac96e360672	1730	pdata->bin_seq[4] =
charlesmn	0:3ac96e360672	1731	pdev->hist_cfg.histogram_config__high_amb_odd_bin_4_5
charlesmn	0:3ac96e360672	1732	& 0x0F;
charlesmn	0:3ac96e360672	1733	pdata->bin_seq[3] =
charlesmn	0:3ac96e360672	1734	pdev->hist_cfg.histogram_config__high_amb_odd_bin_2_3
charlesmn	0:3ac96e360672	1735	>> 4;
charlesmn	0:3ac96e360672	1736	pdata->bin_seq[2] =
charlesmn	0:3ac96e360672	1737	pdev->hist_cfg.histogram_config__high_amb_odd_bin_2_3
charlesmn	0:3ac96e360672	1738	& 0x0F;
charlesmn	0:3ac96e360672	1739	pdata->bin_seq[1] =
charlesmn	0:3ac96e360672	1740	pdev->hist_cfg.histogram_config__high_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	1741	>> 4;
charlesmn	0:3ac96e360672	1742	pdata->bin_seq[0] =
charlesmn	0:3ac96e360672	1743	pdev->hist_cfg.histogram_config__high_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	1744	& 0x0F;
charlesmn	0:3ac96e360672	1745	}
charlesmn	0:3ac96e360672	1746
charlesmn	0:3ac96e360672	1747	if (pdata->ambient_events_sum < amb_thresh_low) {
charlesmn	0:3ac96e360672	1748	pdata->bin_seq[5] =
charlesmn	0:3ac96e360672	1749	pdev->hist_cfg.histogram_config__low_amb_odd_bin_4_5
charlesmn	0:3ac96e360672	1750	>> 4;
charlesmn	0:3ac96e360672	1751	pdata->bin_seq[4] =
charlesmn	0:3ac96e360672	1752	pdev->hist_cfg.histogram_config__low_amb_odd_bin_4_5
charlesmn	0:3ac96e360672	1753	& 0x0F;
charlesmn	0:3ac96e360672	1754	pdata->bin_seq[3] =
charlesmn	0:3ac96e360672	1755	pdev->hist_cfg.histogram_config__low_amb_odd_bin_2_3
charlesmn	0:3ac96e360672	1756	>> 4;
charlesmn	0:3ac96e360672	1757	pdata->bin_seq[2] =
charlesmn	0:3ac96e360672	1758	pdev->hist_cfg.histogram_config__low_amb_odd_bin_2_3
charlesmn	0:3ac96e360672	1759	& 0x0F;
charlesmn	0:3ac96e360672	1760	pdata->bin_seq[1] =
charlesmn	0:3ac96e360672	1761	pdev->hist_cfg.histogram_config__low_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	1762	>> 4;
charlesmn	0:3ac96e360672	1763	pdata->bin_seq[0] =
charlesmn	0:3ac96e360672	1764	pdev->hist_cfg.histogram_config__low_amb_odd_bin_0_1
charlesmn	0:3ac96e360672	1765	& 0x0F;
charlesmn	0:3ac96e360672	1766	}
charlesmn	0:3ac96e360672	1767	}
charlesmn	0:3ac96e360672	1768
charlesmn	0:3ac96e360672	1769
charlesmn	0:3ac96e360672	1770
charlesmn	0:3ac96e360672	1771	for (i = 0; i < VL53L1_MAX_BIN_SEQUENCE_LENGTH; i++)
charlesmn	0:3ac96e360672	1772	pdata->bin_rep[i] = 1;
charlesmn	0:3ac96e360672	1773
charlesmn	0:3ac96e360672	1774	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	1775
charlesmn	0:3ac96e360672	1776	}
charlesmn	0:3ac96e360672	1777
charlesmn	0:3ac96e360672	1778
charlesmn	0:3ac96e360672	1779	VL53L1_Error VL53L1_hist_phase_consistency_check(
charlesmn	0:3ac96e360672	1780	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	1781	VL53L1_zone_hist_info_t *phist_prev,
charlesmn	0:3ac96e360672	1782	VL53L1_zone_objects_t *prange_prev,
charlesmn	0:3ac96e360672	1783	VL53L1_range_results_t *prange_curr)
charlesmn	0:3ac96e360672	1784	{
charlesmn	0:3ac96e360672	1785
charlesmn	0:3ac96e360672	1786
charlesmn	0:3ac96e360672	1787
charlesmn	0:3ac96e360672	1788	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1789	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	1790	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	1791
charlesmn	0:3ac96e360672	1792	uint8_t lc = 0;
charlesmn	0:3ac96e360672	1793	uint8_t p = 0;
charlesmn	0:3ac96e360672	1794
charlesmn	0:3ac96e360672	1795	uint16_t phase_delta = 0;
charlesmn	0:3ac96e360672	1796	uint16_t phase_tolerance = 0;
charlesmn	0:3ac96e360672	1797
charlesmn	0:3ac96e360672	1798	int32_t events_delta = 0;
charlesmn	0:3ac96e360672	1799	int32_t events_tolerance = 0;
charlesmn	0:3ac96e360672	1800
charlesmn	0:3ac96e360672	1801
charlesmn	0:3ac96e360672	1802	uint8_t event_sigma;
charlesmn	0:3ac96e360672	1803	uint16_t event_min_spad_count;
charlesmn	0:3ac96e360672	1804	uint16_t min_max_tolerance;
charlesmn	0:3ac96e360672	1805	uint8_t pht;
charlesmn	0:3ac96e360672	1806
charlesmn	0:3ac96e360672	1807	VL53L1_DeviceError range_status = 0;
charlesmn	0:3ac96e360672	1808
charlesmn	0:3ac96e360672	1809	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	1810
charlesmn	0:3ac96e360672	1811	event_sigma =
charlesmn	0:3ac96e360672	1812	pdev->histpostprocess.algo__consistency_check__event_sigma;
charlesmn	0:3ac96e360672	1813	event_min_spad_count =
charlesmn	0:3ac96e360672	1814	pdev->histpostprocess.algo__consistency_check__event_min_spad_count;
charlesmn	0:3ac96e360672	1815	min_max_tolerance =
charlesmn	0:3ac96e360672	1816	pdev->histpostprocess.algo__consistency_check__min_max_tolerance;
charlesmn	0:3ac96e360672	1817
charlesmn	0:3ac96e360672	1818
charlesmn	0:3ac96e360672	1819	pht = pdev->histpostprocess.algo__consistency_check__phase_tolerance;
charlesmn	0:3ac96e360672	1820	phase_tolerance = (uint16_t)pht;
charlesmn	0:3ac96e360672	1821	phase_tolerance = phase_tolerance << 8;
charlesmn	0:3ac96e360672	1822
charlesmn	0:3ac96e360672	1823
charlesmn	0:3ac96e360672	1824
charlesmn	0:3ac96e360672	1825	if (prange_prev->rd_device_state !=
charlesmn	0:3ac96e360672	1826	VL53L1_DEVICESTATE_RANGING_GATHER_DATA &&
charlesmn	0:3ac96e360672	1827	prange_prev->rd_device_state !=
charlesmn	0:3ac96e360672	1828	VL53L1_DEVICESTATE_RANGING_OUTPUT_DATA)
charlesmn	0:3ac96e360672	1829	return status;
charlesmn	0:3ac96e360672	1830
charlesmn	0:3ac96e360672	1831
charlesmn	0:3ac96e360672	1832
charlesmn	0:3ac96e360672	1833	if (phase_tolerance == 0)
charlesmn	0:3ac96e360672	1834	return status;
charlesmn	0:3ac96e360672	1835
charlesmn	0:3ac96e360672	1836	for (lc = 0; lc < prange_curr->active_results; lc++) {
charlesmn	0:3ac96e360672	1837
charlesmn	0:3ac96e360672	1838	if (!((prange_curr->VL53L1_p_002[lc].range_status ==
charlesmn	0:3ac96e360672	1839	VL53L1_DEVICEERROR_RANGECOMPLETE) \|\|
charlesmn	0:3ac96e360672	1840	(prange_curr->VL53L1_p_002[lc].range_status ==
charlesmn	0:3ac96e360672	1841	VL53L1_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK)))
charlesmn	0:3ac96e360672	1842	continue;
charlesmn	0:3ac96e360672	1843
charlesmn	0:3ac96e360672	1844
charlesmn	0:3ac96e360672	1845
charlesmn	0:3ac96e360672	1846
charlesmn	0:3ac96e360672	1847
charlesmn	0:3ac96e360672	1848
charlesmn	0:3ac96e360672	1849	if (prange_prev->active_objects == 0)
charlesmn	0:3ac96e360672	1850	prange_curr->VL53L1_p_002[lc].range_status =
charlesmn	0:3ac96e360672	1851	VL53L1_DEVICEERROR_PREV_RANGE_NO_TARGETS;
charlesmn	0:3ac96e360672	1852	else
charlesmn	0:3ac96e360672	1853	prange_curr->VL53L1_p_002[lc].range_status =
charlesmn	0:3ac96e360672	1854	VL53L1_DEVICEERROR_PHASECONSISTENCY;
charlesmn	0:3ac96e360672	1855
charlesmn	0:3ac96e360672	1856
charlesmn	0:3ac96e360672	1857
charlesmn	0:3ac96e360672	1858
charlesmn	0:3ac96e360672	1859
charlesmn	0:3ac96e360672	1860	for (p = 0; p < prange_prev->active_objects; p++) {
charlesmn	0:3ac96e360672	1861
charlesmn	0:3ac96e360672	1862	if (prange_curr->VL53L1_p_002[lc].VL53L1_p_014 >
charlesmn	0:3ac96e360672	1863	prange_prev->VL53L1_p_002[p].VL53L1_p_014) {
charlesmn	0:3ac96e360672	1864	phase_delta =
charlesmn	0:3ac96e360672	1865	prange_curr->VL53L1_p_002[lc].VL53L1_p_014 -
charlesmn	0:3ac96e360672	1866	prange_prev->VL53L1_p_002[p].VL53L1_p_014;
charlesmn	0:3ac96e360672	1867	} else {
charlesmn	0:3ac96e360672	1868	phase_delta =
charlesmn	0:3ac96e360672	1869	prange_prev->VL53L1_p_002[p].VL53L1_p_014 -
charlesmn	0:3ac96e360672	1870	prange_curr->VL53L1_p_002[lc].VL53L1_p_014;
charlesmn	0:3ac96e360672	1871	}
charlesmn	0:3ac96e360672	1872
charlesmn	0:3ac96e360672	1873	if (phase_delta < phase_tolerance) {
charlesmn	0:3ac96e360672	1874
charlesmn	0:3ac96e360672	1875
charlesmn	0:3ac96e360672	1876
charlesmn	0:3ac96e360672	1877
charlesmn	0:3ac96e360672	1878
charlesmn	0:3ac96e360672	1879	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	1880	status =
charlesmn	0:3ac96e360672	1881	VL53L1_hist_events_consistency_check(
charlesmn	0:3ac96e360672	1882	event_sigma,
charlesmn	0:3ac96e360672	1883	event_min_spad_count,
charlesmn	0:3ac96e360672	1884	phist_prev,
charlesmn	0:3ac96e360672	1885	&(prange_prev->VL53L1_p_002[p]),
charlesmn	0:3ac96e360672	1886	&(prange_curr->VL53L1_p_002[lc]),
charlesmn	0:3ac96e360672	1887	&events_tolerance,
charlesmn	0:3ac96e360672	1888	&events_delta,
charlesmn	0:3ac96e360672	1889	&range_status);
charlesmn	0:3ac96e360672	1890
charlesmn	0:3ac96e360672	1891
charlesmn	0:3ac96e360672	1892
charlesmn	0:3ac96e360672	1893
charlesmn	0:3ac96e360672	1894	if (status == VL53L1_ERROR_NONE &&
charlesmn	0:3ac96e360672	1895	range_status ==
charlesmn	0:3ac96e360672	1896	VL53L1_DEVICEERROR_RANGECOMPLETE)
charlesmn	0:3ac96e360672	1897	status =
charlesmn	0:3ac96e360672	1898	VL53L1_hist_merged_pulse_check(
charlesmn	0:3ac96e360672	1899	min_max_tolerance,
charlesmn	0:3ac96e360672	1900	&(prange_curr->VL53L1_p_002[lc]),
charlesmn	0:3ac96e360672	1901	&range_status);
charlesmn	0:3ac96e360672	1902
charlesmn	0:3ac96e360672	1903	prange_curr->VL53L1_p_002[lc].range_status =
charlesmn	0:3ac96e360672	1904	range_status;
charlesmn	0:3ac96e360672	1905	}
charlesmn	0:3ac96e360672	1906	}
charlesmn	0:3ac96e360672	1907
charlesmn	0:3ac96e360672	1908	}
charlesmn	0:3ac96e360672	1909
charlesmn	0:3ac96e360672	1910	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	1911
charlesmn	0:3ac96e360672	1912	return status;
charlesmn	0:3ac96e360672	1913	}
charlesmn	0:3ac96e360672	1914
charlesmn	0:3ac96e360672	1915
charlesmn	0:3ac96e360672	1916
charlesmn	0:3ac96e360672	1917	VL53L1_Error VL53L1_hist_events_consistency_check(
charlesmn	0:3ac96e360672	1918	uint8_t event_sigma,
charlesmn	0:3ac96e360672	1919	uint16_t min_effective_spad_count,
charlesmn	0:3ac96e360672	1920	VL53L1_zone_hist_info_t *phist_prev,
charlesmn	0:3ac96e360672	1921	VL53L1_object_data_t *prange_prev,
charlesmn	0:3ac96e360672	1922	VL53L1_range_data_t *prange_curr,
charlesmn	0:3ac96e360672	1923	int32_t *pevents_tolerance,
charlesmn	0:3ac96e360672	1924	int32_t *pevents_delta,
charlesmn	0:3ac96e360672	1925	VL53L1_DeviceError *prange_status)
charlesmn	0:3ac96e360672	1926	{
charlesmn	0:3ac96e360672	1927
charlesmn	0:3ac96e360672	1928
charlesmn	0:3ac96e360672	1929
charlesmn	0:3ac96e360672	1930	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	1931
charlesmn	0:3ac96e360672	1932	int64_t tmpp = 0;
charlesmn	0:3ac96e360672	1933	int64_t tmpc = 0;
charlesmn	0:3ac96e360672	1934	int64_t events_scaler = 0;
charlesmn	0:3ac96e360672	1935	int64_t events_scaler_sq = 0;
charlesmn	0:3ac96e360672	1936	int64_t c_signal_events = 0;
charlesmn	0:3ac96e360672	1937	int64_t c_sig_noise_sq = 0;
charlesmn	0:3ac96e360672	1938	int64_t c_amb_noise_sq = 0;
charlesmn	0:3ac96e360672	1939	int64_t p_amb_noise_sq = 0;
charlesmn	0:3ac96e360672	1940
charlesmn	0:3ac96e360672	1941	int32_t p_signal_events = 0;
charlesmn	0:3ac96e360672	1942	uint32_t noise_sq_sum = 0;
charlesmn	0:3ac96e360672	1943
charlesmn	0:3ac96e360672	1944
charlesmn	0:3ac96e360672	1945
charlesmn	0:3ac96e360672	1946	if (event_sigma == 0) {
charlesmn	0:3ac96e360672	1947	*prange_status = VL53L1_DEVICEERROR_RANGECOMPLETE;
charlesmn	0:3ac96e360672	1948	return status;
charlesmn	0:3ac96e360672	1949	}
charlesmn	0:3ac96e360672	1950
charlesmn	0:3ac96e360672	1951
charlesmn	0:3ac96e360672	1952
charlesmn	0:3ac96e360672	1953	tmpp = 1 + (int64_t)phist_prev->total_periods_elapsed;
charlesmn	0:3ac96e360672	1954	tmpp *= (int64_t)phist_prev->result__dss_actual_effective_spads;
charlesmn	0:3ac96e360672	1955
charlesmn	0:3ac96e360672	1956
charlesmn	0:3ac96e360672	1957
charlesmn	0:3ac96e360672	1958	tmpc = 1 + (int64_t)prange_curr->total_periods_elapsed;
charlesmn	0:3ac96e360672	1959	tmpc *= (int64_t)prange_curr->VL53L1_p_006;
charlesmn	0:3ac96e360672	1960
charlesmn	0:3ac96e360672	1961
charlesmn	0:3ac96e360672	1962
charlesmn	0:3ac96e360672	1963	events_scaler = tmpp * 4096;
charlesmn	0:3ac96e360672	1964	events_scaler += (tmpc/2);
charlesmn	0:3ac96e360672	1965	if (tmpc != 0)
charlesmn	0:3ac96e360672	1966	events_scaler = do_division_s(events_scaler, tmpc);
charlesmn	0:3ac96e360672	1967
charlesmn	0:3ac96e360672	1968	events_scaler_sq = events_scaler * events_scaler;
charlesmn	0:3ac96e360672	1969	events_scaler_sq += 2048;
charlesmn	0:3ac96e360672	1970	events_scaler_sq /= 4096;
charlesmn	0:3ac96e360672	1971
charlesmn	0:3ac96e360672	1972
charlesmn	0:3ac96e360672	1973
charlesmn	0:3ac96e360672	1974	c_signal_events = (int64_t)prange_curr->VL53L1_p_021;
charlesmn	0:3ac96e360672	1975	c_signal_events -= (int64_t)prange_curr->VL53L1_p_020;
charlesmn	0:3ac96e360672	1976	c_signal_events *= (int64_t)events_scaler;
charlesmn	0:3ac96e360672	1977	c_signal_events += 2048;
charlesmn	0:3ac96e360672	1978	c_signal_events /= 4096;
charlesmn	0:3ac96e360672	1979
charlesmn	0:3ac96e360672	1980	c_sig_noise_sq = (int64_t)events_scaler_sq;
charlesmn	0:3ac96e360672	1981	c_sig_noise_sq *= (int64_t)prange_curr->VL53L1_p_021;
charlesmn	0:3ac96e360672	1982	c_sig_noise_sq += 2048;
charlesmn	0:3ac96e360672	1983	c_sig_noise_sq /= 4096;
charlesmn	0:3ac96e360672	1984
charlesmn	0:3ac96e360672	1985	c_amb_noise_sq = (int64_t)events_scaler_sq;
charlesmn	0:3ac96e360672	1986	c_amb_noise_sq *= (int64_t)prange_curr->VL53L1_p_020;
charlesmn	0:3ac96e360672	1987	c_amb_noise_sq += 2048;
charlesmn	0:3ac96e360672	1988	c_amb_noise_sq /= 4096;
charlesmn	0:3ac96e360672	1989
charlesmn	0:3ac96e360672	1990
charlesmn	0:3ac96e360672	1991	c_amb_noise_sq += 2;
charlesmn	0:3ac96e360672	1992	c_amb_noise_sq /= 4;
charlesmn	0:3ac96e360672	1993
charlesmn	0:3ac96e360672	1994
charlesmn	0:3ac96e360672	1995
charlesmn	0:3ac96e360672	1996	p_amb_noise_sq =
charlesmn	0:3ac96e360672	1997	(int64_t)prange_prev->VL53L1_p_020;
charlesmn	0:3ac96e360672	1998
charlesmn	0:3ac96e360672	1999
charlesmn	0:3ac96e360672	2000	p_amb_noise_sq += 2;
charlesmn	0:3ac96e360672	2001	p_amb_noise_sq /= 4;
charlesmn	0:3ac96e360672	2002
charlesmn	0:3ac96e360672	2003	noise_sq_sum =
charlesmn	0:3ac96e360672	2004	(uint32_t)prange_prev->VL53L1_p_021 +
charlesmn	0:3ac96e360672	2005	(uint32_t)c_sig_noise_sq +
charlesmn	0:3ac96e360672	2006	(uint32_t)p_amb_noise_sq +
charlesmn	0:3ac96e360672	2007	(uint32_t)c_amb_noise_sq;
charlesmn	0:3ac96e360672	2008
charlesmn	0:3ac96e360672	2009	*pevents_tolerance =
charlesmn	0:3ac96e360672	2010	(int32_t)VL53L1_isqrt(noise_sq_sum * 16);
charlesmn	0:3ac96e360672	2011
charlesmn	0:3ac96e360672	2012	pevents_tolerance = (int32_t)event_sigma;
charlesmn	0:3ac96e360672	2013	*pevents_tolerance += 32;
charlesmn	0:3ac96e360672	2014	*pevents_tolerance /= 64;
charlesmn	0:3ac96e360672	2015
charlesmn	0:3ac96e360672	2016	p_signal_events = (int32_t)prange_prev->VL53L1_p_021;
charlesmn	0:3ac96e360672	2017	p_signal_events -= (int32_t)prange_prev->VL53L1_p_020;
charlesmn	0:3ac96e360672	2018
charlesmn	0:3ac96e360672	2019	if ((int32_t)c_signal_events > p_signal_events)
charlesmn	0:3ac96e360672	2020	*pevents_delta =
charlesmn	0:3ac96e360672	2021	(int32_t)c_signal_events - p_signal_events;
charlesmn	0:3ac96e360672	2022	else
charlesmn	0:3ac96e360672	2023	*pevents_delta =
charlesmn	0:3ac96e360672	2024	p_signal_events - (int32_t)c_signal_events;
charlesmn	0:3ac96e360672	2025
charlesmn	0:3ac96e360672	2026	if (pevents_delta > pevents_tolerance &&
charlesmn	0:3ac96e360672	2027	prange_curr->VL53L1_p_006 > min_effective_spad_count)
charlesmn	0:3ac96e360672	2028	*prange_status = VL53L1_DEVICEERROR_EVENTCONSISTENCY;
charlesmn	0:3ac96e360672	2029	else
charlesmn	0:3ac96e360672	2030	*prange_status = VL53L1_DEVICEERROR_RANGECOMPLETE;
charlesmn	0:3ac96e360672	2031
charlesmn	0:3ac96e360672	2032
charlesmn	0:3ac96e360672	2033
charlesmn	0:3ac96e360672	2034
charlesmn	0:3ac96e360672	2035
charlesmn	0:3ac96e360672	2036	return status;
charlesmn	0:3ac96e360672	2037	}
charlesmn	0:3ac96e360672	2038
charlesmn	0:3ac96e360672	2039
charlesmn	0:3ac96e360672	2040
charlesmn	0:3ac96e360672	2041
charlesmn	0:3ac96e360672	2042	VL53L1_Error VL53L1_hist_merged_pulse_check(
charlesmn	0:3ac96e360672	2043	int16_t min_max_tolerance_mm,
charlesmn	0:3ac96e360672	2044	VL53L1_range_data_t *pdata,
charlesmn	0:3ac96e360672	2045	VL53L1_DeviceError *prange_status)
charlesmn	0:3ac96e360672	2046	{
charlesmn	0:3ac96e360672	2047
charlesmn	0:3ac96e360672	2048
charlesmn	0:3ac96e360672	2049	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2050	int16_t delta_mm = 0;
charlesmn	0:3ac96e360672	2051
charlesmn	0:3ac96e360672	2052	if (pdata->max_range_mm > pdata->min_range_mm)
charlesmn	0:3ac96e360672	2053	delta_mm =
charlesmn	0:3ac96e360672	2054	pdata->max_range_mm - pdata->min_range_mm;
charlesmn	0:3ac96e360672	2055	else
charlesmn	0:3ac96e360672	2056	delta_mm =
charlesmn	0:3ac96e360672	2057	pdata->min_range_mm - pdata->max_range_mm;
charlesmn	0:3ac96e360672	2058
charlesmn	0:3ac96e360672	2059	if (min_max_tolerance_mm > 0 &&
charlesmn	0:3ac96e360672	2060	delta_mm > min_max_tolerance_mm)
charlesmn	0:3ac96e360672	2061	*prange_status = VL53L1_DEVICEERROR_RANGECOMPLETE_MERGED_PULSE;
charlesmn	0:3ac96e360672	2062	else
charlesmn	0:3ac96e360672	2063	*prange_status = VL53L1_DEVICEERROR_RANGECOMPLETE;
charlesmn	0:3ac96e360672	2064
charlesmn	0:3ac96e360672	2065	return status;
charlesmn	0:3ac96e360672	2066	}
charlesmn	0:3ac96e360672	2067
charlesmn	0:3ac96e360672	2068
charlesmn	0:3ac96e360672	2069
charlesmn	0:3ac96e360672	2070
charlesmn	0:3ac96e360672	2071	VL53L1_Error VL53L1_hist_xmonitor_consistency_check(
charlesmn	0:3ac96e360672	2072	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	2073	VL53L1_zone_hist_info_t *phist_prev,
charlesmn	0:3ac96e360672	2074	VL53L1_zone_objects_t *prange_prev,
charlesmn	0:3ac96e360672	2075	VL53L1_range_data_t *prange_curr)
charlesmn	0:3ac96e360672	2076	{
charlesmn	0:3ac96e360672	2077
charlesmn	0:3ac96e360672	2078
charlesmn	0:3ac96e360672	2079	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2080	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	2081	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	2082
charlesmn	0:3ac96e360672	2083	int32_t events_delta = 0;
charlesmn	0:3ac96e360672	2084	int32_t events_tolerance = 0;
charlesmn	0:3ac96e360672	2085	uint8_t event_sigma;
charlesmn	0:3ac96e360672	2086	uint16_t min_spad_count;
charlesmn	0:3ac96e360672	2087
charlesmn	0:3ac96e360672	2088	event_sigma = pdev->histpostprocess.algo__crosstalk_detect_event_sigma;
charlesmn	0:3ac96e360672	2089	min_spad_count =
charlesmn	0:3ac96e360672	2090	pdev->histpostprocess.algo__consistency_check__event_min_spad_count;
charlesmn	0:3ac96e360672	2091
charlesmn	0:3ac96e360672	2092	if (prange_curr->range_status == VL53L1_DEVICEERROR_RANGECOMPLETE \|\|
charlesmn	0:3ac96e360672	2093	prange_curr->range_status ==
charlesmn	0:3ac96e360672	2094	VL53L1_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK \|\|
charlesmn	0:3ac96e360672	2095	prange_curr->range_status ==
charlesmn	0:3ac96e360672	2096	VL53L1_DEVICEERROR_EVENTCONSISTENCY) {
charlesmn	0:3ac96e360672	2097
charlesmn	0:3ac96e360672	2098	if (prange_prev->xmonitor.range_status ==
charlesmn	0:3ac96e360672	2099	VL53L1_DEVICEERROR_RANGECOMPLETE \|\|
charlesmn	0:3ac96e360672	2100	prange_prev->xmonitor.range_status ==
charlesmn	0:3ac96e360672	2101	VL53L1_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK \|\|
charlesmn	0:3ac96e360672	2102	prange_prev->xmonitor.range_status ==
charlesmn	0:3ac96e360672	2103	VL53L1_DEVICEERROR_EVENTCONSISTENCY) {
charlesmn	0:3ac96e360672	2104
charlesmn	0:3ac96e360672	2105	prange_curr->range_status =
charlesmn	0:3ac96e360672	2106	VL53L1_DEVICEERROR_RANGECOMPLETE;
charlesmn	0:3ac96e360672	2107
charlesmn	0:3ac96e360672	2108	status =
charlesmn	0:3ac96e360672	2109	VL53L1_hist_events_consistency_check(
charlesmn	0:3ac96e360672	2110	event_sigma,
charlesmn	0:3ac96e360672	2111	min_spad_count,
charlesmn	0:3ac96e360672	2112	phist_prev,
charlesmn	0:3ac96e360672	2113	&(prange_prev->xmonitor),
charlesmn	0:3ac96e360672	2114	prange_curr,
charlesmn	0:3ac96e360672	2115	&events_tolerance,
charlesmn	0:3ac96e360672	2116	&events_delta,
charlesmn	0:3ac96e360672	2117	&(prange_curr->range_status));
charlesmn	0:3ac96e360672	2118
charlesmn	0:3ac96e360672	2119	}
charlesmn	0:3ac96e360672	2120	}
charlesmn	0:3ac96e360672	2121
charlesmn	0:3ac96e360672	2122	return status;
charlesmn	0:3ac96e360672	2123	}
charlesmn	0:3ac96e360672	2124
charlesmn	0:3ac96e360672	2125
charlesmn	0:3ac96e360672	2126
charlesmn	0:3ac96e360672	2127
charlesmn	0:3ac96e360672	2128	VL53L1_Error VL53L1_hist_wrap_dmax(
charlesmn	0:3ac96e360672	2129	VL53L1_hist_post_process_config_t *phistpostprocess,
charlesmn	0:3ac96e360672	2130	VL53L1_histogram_bin_data_t *pcurrent,
charlesmn	0:3ac96e360672	2131	int16_t *pwrap_dmax_mm)
charlesmn	0:3ac96e360672	2132	{
charlesmn	0:3ac96e360672	2133
charlesmn	0:3ac96e360672	2134
charlesmn	0:3ac96e360672	2135
charlesmn	0:3ac96e360672	2136	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2137
charlesmn	0:3ac96e360672	2138	uint32_t pll_period_mm = 0;
charlesmn	0:3ac96e360672	2139	uint32_t wrap_dmax_phase = 0;
charlesmn	0:3ac96e360672	2140	uint32_t range_mm = 0;
charlesmn	0:3ac96e360672	2141
charlesmn	0:3ac96e360672	2142	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2143
charlesmn	0:3ac96e360672	2144	*pwrap_dmax_mm = 0;
charlesmn	0:3ac96e360672	2145
charlesmn	0:3ac96e360672	2146
charlesmn	0:3ac96e360672	2147	if (pcurrent->VL53L1_p_019 != 0) {
charlesmn	0:3ac96e360672	2148
charlesmn	0:3ac96e360672	2149
charlesmn	0:3ac96e360672	2150
charlesmn	0:3ac96e360672	2151	pll_period_mm =
charlesmn	0:3ac96e360672	2152	VL53L1_calc_pll_period_mm(
charlesmn	0:3ac96e360672	2153	pcurrent->VL53L1_p_019);
charlesmn	0:3ac96e360672	2154
charlesmn	0:3ac96e360672	2155
charlesmn	0:3ac96e360672	2156
charlesmn	0:3ac96e360672	2157	wrap_dmax_phase =
charlesmn	0:3ac96e360672	2158	(uint32_t)phistpostprocess->valid_phase_high << 8;
charlesmn	0:3ac96e360672	2159
charlesmn	0:3ac96e360672	2160
charlesmn	0:3ac96e360672	2161
charlesmn	0:3ac96e360672	2162	range_mm = wrap_dmax_phase * pll_period_mm;
charlesmn	0:3ac96e360672	2163	range_mm = (range_mm + (1<<14)) >> 15;
charlesmn	0:3ac96e360672	2164
charlesmn	0:3ac96e360672	2165	*pwrap_dmax_mm = (int16_t)range_mm;
charlesmn	0:3ac96e360672	2166	}
charlesmn	0:3ac96e360672	2167
charlesmn	0:3ac96e360672	2168	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	2169
charlesmn	0:3ac96e360672	2170	return status;
charlesmn	0:3ac96e360672	2171	}
charlesmn	0:3ac96e360672	2172
charlesmn	0:3ac96e360672	2173
charlesmn	0:3ac96e360672	2174	void VL53L1_hist_combine_mm1_mm2_offsets(
charlesmn	0:3ac96e360672	2175	int16_t mm1_offset_mm,
charlesmn	0:3ac96e360672	2176	int16_t mm2_offset_mm,
charlesmn	0:3ac96e360672	2177	uint8_t encoded_mm_roi_centre,
charlesmn	0:3ac96e360672	2178	uint8_t encoded_mm_roi_size,
charlesmn	0:3ac96e360672	2179	uint8_t encoded_zone_centre,
charlesmn	0:3ac96e360672	2180	uint8_t encoded_zone_size,
charlesmn	0:3ac96e360672	2181	VL53L1_additional_offset_cal_data_t *pcal_data,
charlesmn	0:3ac96e360672	2182	uint8_t *pgood_spads,
charlesmn	0:3ac96e360672	2183	uint16_t aperture_attenuation,
charlesmn	0:3ac96e360672	2184	int16_t *prange_offset_mm)
charlesmn	0:3ac96e360672	2185	{
charlesmn	0:3ac96e360672	2186
charlesmn	0:3ac96e360672	2187
charlesmn	0:3ac96e360672	2188
charlesmn	0:3ac96e360672	2189	uint16_t max_mm_inner_effective_spads = 0;
charlesmn	0:3ac96e360672	2190	uint16_t max_mm_outer_effective_spads = 0;
charlesmn	0:3ac96e360672	2191	uint16_t mm_inner_effective_spads = 0;
charlesmn	0:3ac96e360672	2192	uint16_t mm_outer_effective_spads = 0;
charlesmn	0:3ac96e360672	2193
charlesmn	0:3ac96e360672	2194	uint32_t scaled_mm1_peak_rate_mcps = 0;
charlesmn	0:3ac96e360672	2195	uint32_t scaled_mm2_peak_rate_mcps = 0;
charlesmn	0:3ac96e360672	2196
charlesmn	0:3ac96e360672	2197	int32_t tmp0 = 0;
charlesmn	0:3ac96e360672	2198	int32_t tmp1 = 0;
charlesmn	0:3ac96e360672	2199
charlesmn	0:3ac96e360672	2200
charlesmn	0:3ac96e360672	2201
charlesmn	0:3ac96e360672	2202	VL53L1_calc_mm_effective_spads(
charlesmn	0:3ac96e360672	2203	encoded_mm_roi_centre,
charlesmn	0:3ac96e360672	2204	encoded_mm_roi_size,
charlesmn	0:3ac96e360672	2205	0xC7,
charlesmn	0:3ac96e360672	2206	0xFF,
charlesmn	0:3ac96e360672	2207	pgood_spads,
charlesmn	0:3ac96e360672	2208	aperture_attenuation,
charlesmn	0:3ac96e360672	2209	&max_mm_inner_effective_spads,
charlesmn	0:3ac96e360672	2210	&max_mm_outer_effective_spads);
charlesmn	0:3ac96e360672	2211
charlesmn	0:3ac96e360672	2212	if ((max_mm_inner_effective_spads == 0) \|\|
charlesmn	0:3ac96e360672	2213	(max_mm_outer_effective_spads == 0))
charlesmn	0:3ac96e360672	2214	goto FAIL;
charlesmn	0:3ac96e360672	2215
charlesmn	0:3ac96e360672	2216
charlesmn	0:3ac96e360672	2217
charlesmn	0:3ac96e360672	2218	VL53L1_calc_mm_effective_spads(
charlesmn	0:3ac96e360672	2219	encoded_mm_roi_centre,
charlesmn	0:3ac96e360672	2220	encoded_mm_roi_size,
charlesmn	0:3ac96e360672	2221	encoded_zone_centre,
charlesmn	0:3ac96e360672	2222	encoded_zone_size,
charlesmn	0:3ac96e360672	2223	pgood_spads,
charlesmn	0:3ac96e360672	2224	aperture_attenuation,
charlesmn	0:3ac96e360672	2225	&mm_inner_effective_spads,
charlesmn	0:3ac96e360672	2226	&mm_outer_effective_spads);
charlesmn	0:3ac96e360672	2227
charlesmn	0:3ac96e360672	2228
charlesmn	0:3ac96e360672	2229
charlesmn	0:3ac96e360672	2230	scaled_mm1_peak_rate_mcps =
charlesmn	0:3ac96e360672	2231	(uint32_t)pcal_data->result__mm_inner_peak_signal_count_rtn_mcps;
charlesmn	0:3ac96e360672	2232	scaled_mm1_peak_rate_mcps *= (uint32_t)mm_inner_effective_spads;
charlesmn	0:3ac96e360672	2233	scaled_mm1_peak_rate_mcps /= (uint32_t)max_mm_inner_effective_spads;
charlesmn	0:3ac96e360672	2234
charlesmn	0:3ac96e360672	2235	scaled_mm2_peak_rate_mcps =
charlesmn	0:3ac96e360672	2236	(uint32_t)pcal_data->result__mm_outer_peak_signal_count_rtn_mcps;
charlesmn	0:3ac96e360672	2237	scaled_mm2_peak_rate_mcps *= (uint32_t)mm_outer_effective_spads;
charlesmn	0:3ac96e360672	2238	scaled_mm2_peak_rate_mcps /= (uint32_t)max_mm_outer_effective_spads;
charlesmn	0:3ac96e360672	2239
charlesmn	0:3ac96e360672	2240
charlesmn	0:3ac96e360672	2241
charlesmn	0:3ac96e360672	2242	tmp0 = ((int32_t)mm1_offset_mm * (int32_t)scaled_mm1_peak_rate_mcps);
charlesmn	0:3ac96e360672	2243	tmp0 += ((int32_t)mm2_offset_mm * (int32_t)scaled_mm2_peak_rate_mcps);
charlesmn	0:3ac96e360672	2244
charlesmn	0:3ac96e360672	2245	tmp1 = (int32_t)scaled_mm1_peak_rate_mcps +
charlesmn	0:3ac96e360672	2246	(int32_t)scaled_mm2_peak_rate_mcps;
charlesmn	0:3ac96e360672	2247
charlesmn	0:3ac96e360672	2248
charlesmn	0:3ac96e360672	2249
charlesmn	0:3ac96e360672	2250	if (tmp1 != 0)
charlesmn	0:3ac96e360672	2251	tmp0 = (tmp0 * 4) / tmp1;
charlesmn	0:3ac96e360672	2252	FAIL:
charlesmn	0:3ac96e360672	2253	*prange_offset_mm = (int16_t)tmp0;
charlesmn	0:3ac96e360672	2254
charlesmn	0:3ac96e360672	2255	}
charlesmn	0:3ac96e360672	2256
charlesmn	0:3ac96e360672	2257
charlesmn	0:3ac96e360672	2258	VL53L1_Error VL53L1_hist_xtalk_extract_calc_window(
charlesmn	0:3ac96e360672	2259	int16_t target_distance_mm,
charlesmn	0:3ac96e360672	2260	uint16_t target_width_oversize,
charlesmn	0:3ac96e360672	2261	VL53L1_histogram_bin_data_t *phist_bins,
charlesmn	0:3ac96e360672	2262	VL53L1_hist_xtalk_extract_data_t *pxtalk_data)
charlesmn	0:3ac96e360672	2263	{
charlesmn	0:3ac96e360672	2264
charlesmn	0:3ac96e360672	2265
charlesmn	0:3ac96e360672	2266	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2267
charlesmn	0:3ac96e360672	2268	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2269
charlesmn	0:3ac96e360672	2270
charlesmn	0:3ac96e360672	2271	pxtalk_data->pll_period_mm =
charlesmn	0:3ac96e360672	2272	VL53L1_calc_pll_period_mm(phist_bins->VL53L1_p_019);
charlesmn	0:3ac96e360672	2273
charlesmn	0:3ac96e360672	2274
charlesmn	0:3ac96e360672	2275	pxtalk_data->xtalk_width_phase =
charlesmn	0:3ac96e360672	2276	(int32_t)phist_bins->vcsel_width * 128;
charlesmn	0:3ac96e360672	2277	pxtalk_data->target_width_phase =
charlesmn	0:3ac96e360672	2278	pxtalk_data->xtalk_width_phase +
charlesmn	0:3ac96e360672	2279	(int32_t)target_width_oversize * 128;
charlesmn	0:3ac96e360672	2280
charlesmn	0:3ac96e360672	2281
charlesmn	0:3ac96e360672	2282
charlesmn	0:3ac96e360672	2283	pxtalk_data->xtalk_start_phase =
charlesmn	0:3ac96e360672	2284	(int32_t)phist_bins->zero_distance_phase -
charlesmn	0:3ac96e360672	2285	(pxtalk_data->xtalk_width_phase / 2);
charlesmn	0:3ac96e360672	2286	pxtalk_data->xtalk_end_phase =
charlesmn	0:3ac96e360672	2287	(int32_t)pxtalk_data->xtalk_start_phase +
charlesmn	0:3ac96e360672	2288	pxtalk_data->xtalk_width_phase;
charlesmn	0:3ac96e360672	2289
charlesmn	0:3ac96e360672	2290	if (pxtalk_data->xtalk_start_phase < 0)
charlesmn	0:3ac96e360672	2291	pxtalk_data->xtalk_start_phase = 0;
charlesmn	0:3ac96e360672	2292
charlesmn	0:3ac96e360672	2293
charlesmn	0:3ac96e360672	2294
charlesmn	0:3ac96e360672	2295
charlesmn	0:3ac96e360672	2296	pxtalk_data->VL53L1_p_015 =
charlesmn	0:3ac96e360672	2297	(uint8_t)(pxtalk_data->xtalk_start_phase / 2048);
charlesmn	0:3ac96e360672	2298
charlesmn	0:3ac96e360672	2299
charlesmn	0:3ac96e360672	2300	pxtalk_data->VL53L1_p_016 =
charlesmn	0:3ac96e360672	2301	(uint8_t)((pxtalk_data->xtalk_end_phase + 2047) / 2048);
charlesmn	0:3ac96e360672	2302
charlesmn	0:3ac96e360672	2303
charlesmn	0:3ac96e360672	2304
charlesmn	0:3ac96e360672	2305	pxtalk_data->target_start_phase =
charlesmn	0:3ac96e360672	2306	(int32_t)target_distance_mm * 2048 * 16;
charlesmn	0:3ac96e360672	2307	pxtalk_data->target_start_phase +=
charlesmn	0:3ac96e360672	2308	((int32_t)pxtalk_data->pll_period_mm / 2);
charlesmn	0:3ac96e360672	2309	pxtalk_data->target_start_phase /= (int32_t)pxtalk_data->pll_period_mm;
charlesmn	0:3ac96e360672	2310	pxtalk_data->target_start_phase +=
charlesmn	0:3ac96e360672	2311	(int32_t)phist_bins->zero_distance_phase;
charlesmn	0:3ac96e360672	2312
charlesmn	0:3ac96e360672	2313
charlesmn	0:3ac96e360672	2314
charlesmn	0:3ac96e360672	2315	pxtalk_data->target_start_phase -=
charlesmn	0:3ac96e360672	2316	(pxtalk_data->target_width_phase / 2);
charlesmn	0:3ac96e360672	2317	pxtalk_data->target_end_phase =
charlesmn	0:3ac96e360672	2318	(int32_t)pxtalk_data->target_start_phase +
charlesmn	0:3ac96e360672	2319	pxtalk_data->target_width_phase;
charlesmn	0:3ac96e360672	2320
charlesmn	0:3ac96e360672	2321	if (pxtalk_data->target_start_phase < 0)
charlesmn	0:3ac96e360672	2322	pxtalk_data->target_start_phase = 0;
charlesmn	0:3ac96e360672	2323
charlesmn	0:3ac96e360672	2324
charlesmn	0:3ac96e360672	2325	pxtalk_data->target_start =
charlesmn	0:3ac96e360672	2326	(uint8_t)(pxtalk_data->target_start_phase / 2048);
charlesmn	0:3ac96e360672	2327
charlesmn	0:3ac96e360672	2328
charlesmn	0:3ac96e360672	2329	if (pxtalk_data->VL53L1_p_016 > (pxtalk_data->target_start-1))
charlesmn	0:3ac96e360672	2330	pxtalk_data->VL53L1_p_016 = pxtalk_data->target_start-1;
charlesmn	0:3ac96e360672	2331
charlesmn	0:3ac96e360672	2332
charlesmn	0:3ac96e360672	2333	pxtalk_data->effective_width =
charlesmn	0:3ac96e360672	2334	(2048 * ((int32_t)pxtalk_data->VL53L1_p_016+1));
charlesmn	0:3ac96e360672	2335	pxtalk_data->effective_width -= pxtalk_data->xtalk_start_phase;
charlesmn	0:3ac96e360672	2336
charlesmn	0:3ac96e360672	2337
charlesmn	0:3ac96e360672	2338	if (pxtalk_data->effective_width > pxtalk_data->xtalk_width_phase)
charlesmn	0:3ac96e360672	2339	pxtalk_data->effective_width = pxtalk_data->xtalk_width_phase;
charlesmn	0:3ac96e360672	2340
charlesmn	0:3ac96e360672	2341	if (pxtalk_data->effective_width < 1)
charlesmn	0:3ac96e360672	2342	pxtalk_data->effective_width = 1;
charlesmn	0:3ac96e360672	2343
charlesmn	0:3ac96e360672	2344
charlesmn	0:3ac96e360672	2345	pxtalk_data->event_scaler = pxtalk_data->xtalk_width_phase * 1000;
charlesmn	0:3ac96e360672	2346	pxtalk_data->event_scaler += (pxtalk_data->effective_width / 2);
charlesmn	0:3ac96e360672	2347	pxtalk_data->event_scaler /= pxtalk_data->effective_width;
charlesmn	0:3ac96e360672	2348
charlesmn	0:3ac96e360672	2349
charlesmn	0:3ac96e360672	2350	if (pxtalk_data->event_scaler < 1000)
charlesmn	0:3ac96e360672	2351	pxtalk_data->event_scaler = 1000;
charlesmn	0:3ac96e360672	2352
charlesmn	0:3ac96e360672	2353	if (pxtalk_data->event_scaler > 4000)
charlesmn	0:3ac96e360672	2354	pxtalk_data->event_scaler = 4000;
charlesmn	0:3ac96e360672	2355
charlesmn	0:3ac96e360672	2356
charlesmn	0:3ac96e360672	2357	pxtalk_data->event_scaler_sum += pxtalk_data->event_scaler;
charlesmn	0:3ac96e360672	2358
charlesmn	0:3ac96e360672	2359
charlesmn	0:3ac96e360672	2360	pxtalk_data->peak_duration_us_sum +=
charlesmn	0:3ac96e360672	2361	(uint32_t)phist_bins->peak_duration_us;
charlesmn	0:3ac96e360672	2362
charlesmn	0:3ac96e360672	2363
charlesmn	0:3ac96e360672	2364	pxtalk_data->effective_spad_count_sum +=
charlesmn	0:3ac96e360672	2365	(uint32_t)phist_bins->result__dss_actual_effective_spads;
charlesmn	0:3ac96e360672	2366
charlesmn	0:3ac96e360672	2367
charlesmn	0:3ac96e360672	2368	pxtalk_data->zero_distance_phase_sum +=
charlesmn	0:3ac96e360672	2369	(uint32_t)phist_bins->zero_distance_phase;
charlesmn	0:3ac96e360672	2370
charlesmn	0:3ac96e360672	2371	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	2372
charlesmn	0:3ac96e360672	2373	return status;
charlesmn	0:3ac96e360672	2374	}
charlesmn	0:3ac96e360672	2375
charlesmn	0:3ac96e360672	2376
charlesmn	0:3ac96e360672	2377	VL53L1_Error VL53L1_hist_xtalk_extract_calc_event_sums(
charlesmn	0:3ac96e360672	2378	VL53L1_histogram_bin_data_t *phist_bins,
charlesmn	0:3ac96e360672	2379	VL53L1_hist_xtalk_extract_data_t *pxtalk_data)
charlesmn	0:3ac96e360672	2380	{
charlesmn	0:3ac96e360672	2381
charlesmn	0:3ac96e360672	2382
charlesmn	0:3ac96e360672	2383
charlesmn	0:3ac96e360672	2384	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2385
charlesmn	0:3ac96e360672	2386	uint8_t lb = 0;
charlesmn	0:3ac96e360672	2387	uint8_t i = 0;
charlesmn	0:3ac96e360672	2388
charlesmn	0:3ac96e360672	2389	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2390
charlesmn	0:3ac96e360672	2391
charlesmn	0:3ac96e360672	2392
charlesmn	0:3ac96e360672	2393	for (lb = pxtalk_data->VL53L1_p_015;
charlesmn	0:3ac96e360672	2394	lb <= pxtalk_data->VL53L1_p_016;
charlesmn	0:3ac96e360672	2395	lb++) {
charlesmn	0:3ac96e360672	2396
charlesmn	0:3ac96e360672	2397
charlesmn	0:3ac96e360672	2398	i = (lb + phist_bins->number_of_ambient_bins +
charlesmn	0:3ac96e360672	2399	phist_bins->VL53L1_p_024) %
charlesmn	0:3ac96e360672	2400	phist_bins->VL53L1_p_024;
charlesmn	0:3ac96e360672	2401
charlesmn	0:3ac96e360672	2402
charlesmn	0:3ac96e360672	2403	pxtalk_data->signal_events_sum += phist_bins->bin_data[i];
charlesmn	0:3ac96e360672	2404	pxtalk_data->signal_events_sum -=
charlesmn	0:3ac96e360672	2405	phist_bins->VL53L1_p_004;
charlesmn	0:3ac96e360672	2406	}
charlesmn	0:3ac96e360672	2407
charlesmn	0:3ac96e360672	2408
charlesmn	0:3ac96e360672	2409
charlesmn	0:3ac96e360672	2410	for (lb = 0; lb < VL53L1_XTALK_HISTO_BINS &&
charlesmn	0:3ac96e360672	2411	lb < phist_bins->VL53L1_p_024; lb++) {
charlesmn	0:3ac96e360672	2412
charlesmn	0:3ac96e360672	2413
charlesmn	0:3ac96e360672	2414	i = (lb + phist_bins->number_of_ambient_bins +
charlesmn	0:3ac96e360672	2415	phist_bins->VL53L1_p_024) %
charlesmn	0:3ac96e360672	2416	phist_bins->VL53L1_p_024;
charlesmn	0:3ac96e360672	2417
charlesmn	0:3ac96e360672	2418
charlesmn	0:3ac96e360672	2419	pxtalk_data->bin_data_sums[lb] += phist_bins->bin_data[i];
charlesmn	0:3ac96e360672	2420	pxtalk_data->bin_data_sums[lb] -=
charlesmn	0:3ac96e360672	2421	phist_bins->VL53L1_p_004;
charlesmn	0:3ac96e360672	2422	}
charlesmn	0:3ac96e360672	2423
charlesmn	0:3ac96e360672	2424	pxtalk_data->sample_count += 1;
charlesmn	0:3ac96e360672	2425
charlesmn	0:3ac96e360672	2426	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	2427
charlesmn	0:3ac96e360672	2428	return status;
charlesmn	0:3ac96e360672	2429	}
charlesmn	0:3ac96e360672	2430
charlesmn	0:3ac96e360672	2431
charlesmn	0:3ac96e360672	2432	VL53L1_Error VL53L1_hist_xtalk_extract_calc_rate_per_spad(
charlesmn	0:3ac96e360672	2433	VL53L1_hist_xtalk_extract_data_t *pxtalk_data)
charlesmn	0:3ac96e360672	2434	{
charlesmn	0:3ac96e360672	2435
charlesmn	0:3ac96e360672	2436
charlesmn	0:3ac96e360672	2437
charlesmn	0:3ac96e360672	2438	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2439
charlesmn	0:3ac96e360672	2440	uint64_t tmp64_0 = 0;
charlesmn	0:3ac96e360672	2441	uint64_t tmp64_1 = 0;
charlesmn	0:3ac96e360672	2442	uint64_t xtalk_per_spad = 0;
charlesmn	0:3ac96e360672	2443
charlesmn	0:3ac96e360672	2444	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2445
charlesmn	0:3ac96e360672	2446
charlesmn	0:3ac96e360672	2447
charlesmn	0:3ac96e360672	2448
charlesmn	0:3ac96e360672	2449
charlesmn	0:3ac96e360672	2450
charlesmn	0:3ac96e360672	2451	if (pxtalk_data->signal_events_sum > 0) {
charlesmn	0:3ac96e360672	2452	tmp64_0 =
charlesmn	0:3ac96e360672	2453	((uint64_t)pxtalk_data->signal_events_sum *
charlesmn	0:3ac96e360672	2454	(uint64_t)pxtalk_data->sample_count *
charlesmn	0:3ac96e360672	2455	(uint64_t)pxtalk_data->event_scaler_avg * 256U) << 9U;
charlesmn	0:3ac96e360672	2456	tmp64_1 =
charlesmn	0:3ac96e360672	2457	(uint64_t)pxtalk_data->effective_spad_count_sum *
charlesmn	0:3ac96e360672	2458	(uint64_t)pxtalk_data->peak_duration_us_sum;
charlesmn	0:3ac96e360672	2459
charlesmn	0:3ac96e360672	2460
charlesmn	0:3ac96e360672	2461
charlesmn	0:3ac96e360672	2462	if (tmp64_1 > 0U) {
charlesmn	0:3ac96e360672	2463
charlesmn	0:3ac96e360672	2464	tmp64_0 = tmp64_0 + (tmp64_1 >> 1U);
charlesmn	0:3ac96e360672	2465	xtalk_per_spad = do_division_u(tmp64_0, tmp64_1);
charlesmn	0:3ac96e360672	2466	} else {
charlesmn	0:3ac96e360672	2467	xtalk_per_spad = (uint64_t)tmp64_0;
charlesmn	0:3ac96e360672	2468	}
charlesmn	0:3ac96e360672	2469
charlesmn	0:3ac96e360672	2470	} else {
charlesmn	0:3ac96e360672	2471	status = VL53L1_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL;
charlesmn	0:3ac96e360672	2472	}
charlesmn	0:3ac96e360672	2473
charlesmn	0:3ac96e360672	2474	pxtalk_data->xtalk_rate_kcps_per_spad = (uint32_t)xtalk_per_spad;
charlesmn	0:3ac96e360672	2475
charlesmn	0:3ac96e360672	2476	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	2477
charlesmn	0:3ac96e360672	2478	return status;
charlesmn	0:3ac96e360672	2479	}
charlesmn	0:3ac96e360672	2480
charlesmn	0:3ac96e360672	2481
charlesmn	0:3ac96e360672	2482	VL53L1_Error VL53L1_hist_xtalk_extract_calc_shape(
charlesmn	0:3ac96e360672	2483	VL53L1_hist_xtalk_extract_data_t *pxtalk_data,
charlesmn	0:3ac96e360672	2484	VL53L1_xtalk_histogram_shape_t *pxtalk_shape)
charlesmn	0:3ac96e360672	2485	{
charlesmn	0:3ac96e360672	2486
charlesmn	0:3ac96e360672	2487
charlesmn	0:3ac96e360672	2488	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2489
charlesmn	0:3ac96e360672	2490	int32_t lb = 0;
charlesmn	0:3ac96e360672	2491	uint64_t total_events = 0U;
charlesmn	0:3ac96e360672	2492	uint64_t tmp64_0 = 0U;
charlesmn	0:3ac96e360672	2493	int32_t remaining_area = 1024;
charlesmn	0:3ac96e360672	2494
charlesmn	0:3ac96e360672	2495	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2496
charlesmn	0:3ac96e360672	2497
charlesmn	0:3ac96e360672	2498
charlesmn	0:3ac96e360672	2499	pxtalk_shape->VL53L1_p_022 = 0;
charlesmn	0:3ac96e360672	2500	pxtalk_shape->VL53L1_p_023 = VL53L1_XTALK_HISTO_BINS;
charlesmn	0:3ac96e360672	2501	pxtalk_shape->VL53L1_p_024 = VL53L1_XTALK_HISTO_BINS;
charlesmn	0:3ac96e360672	2502
charlesmn	0:3ac96e360672	2503	pxtalk_shape->zero_distance_phase =
charlesmn	0:3ac96e360672	2504	(uint16_t)pxtalk_data->zero_distance_phase_avg;
charlesmn	0:3ac96e360672	2505	pxtalk_shape->phasecal_result__reference_phase =
charlesmn	0:3ac96e360672	2506	(uint16_t)pxtalk_data->zero_distance_phase_avg + (3*2048);
charlesmn	0:3ac96e360672	2507
charlesmn	0:3ac96e360672	2508
charlesmn	0:3ac96e360672	2509
charlesmn	0:3ac96e360672	2510	if (pxtalk_data->signal_events_sum > 0)
charlesmn	0:3ac96e360672	2511	total_events =
charlesmn	0:3ac96e360672	2512	(uint64_t)pxtalk_data->signal_events_sum *
charlesmn	0:3ac96e360672	2513	(uint64_t)pxtalk_data->event_scaler_avg;
charlesmn	0:3ac96e360672	2514	else
charlesmn	0:3ac96e360672	2515	total_events = 1;
charlesmn	0:3ac96e360672	2516	if (total_events == 0)
charlesmn	0:3ac96e360672	2517	total_events = 1;
charlesmn	0:3ac96e360672	2518
charlesmn	0:3ac96e360672	2519
charlesmn	0:3ac96e360672	2520	remaining_area = 1024;
charlesmn	0:3ac96e360672	2521	pxtalk_data->max_shape_value = 0;
charlesmn	0:3ac96e360672	2522
charlesmn	0:3ac96e360672	2523	for (lb = 0; lb < VL53L1_XTALK_HISTO_BINS; lb++) {
charlesmn	0:3ac96e360672	2524
charlesmn	0:3ac96e360672	2525	if ((lb < (int32_t)pxtalk_data->VL53L1_p_015 \|\|
charlesmn	0:3ac96e360672	2526	lb > (int32_t)pxtalk_data->VL53L1_p_016) \|\|
charlesmn	0:3ac96e360672	2527	pxtalk_data->bin_data_sums[lb] < 0) {
charlesmn	0:3ac96e360672	2528
charlesmn	0:3ac96e360672	2529
charlesmn	0:3ac96e360672	2530	if (remaining_area > 0 && remaining_area < 1024) {
charlesmn	0:3ac96e360672	2531	if (remaining_area >
charlesmn	0:3ac96e360672	2532	pxtalk_data->max_shape_value) {
charlesmn	0:3ac96e360672	2533	pxtalk_shape->bin_data[lb] =
charlesmn	0:3ac96e360672	2534	(uint32_t)pxtalk_data->max_shape_value;
charlesmn	0:3ac96e360672	2535	remaining_area -=
charlesmn	0:3ac96e360672	2536	pxtalk_data->max_shape_value;
charlesmn	0:3ac96e360672	2537	} else {
charlesmn	0:3ac96e360672	2538	pxtalk_shape->bin_data[lb] =
charlesmn	0:3ac96e360672	2539	(uint32_t)remaining_area;
charlesmn	0:3ac96e360672	2540	remaining_area = 0;
charlesmn	0:3ac96e360672	2541	}
charlesmn	0:3ac96e360672	2542	} else {
charlesmn	0:3ac96e360672	2543	pxtalk_shape->bin_data[lb] = 0;
charlesmn	0:3ac96e360672	2544	}
charlesmn	0:3ac96e360672	2545
charlesmn	0:3ac96e360672	2546	} else {
charlesmn	0:3ac96e360672	2547
charlesmn	0:3ac96e360672	2548	tmp64_0 =
charlesmn	0:3ac96e360672	2549	(uint64_t)pxtalk_data->bin_data_sums[lb]
charlesmn	0:3ac96e360672	2550	* 1024U * 1000U;
charlesmn	0:3ac96e360672	2551	tmp64_0 += (total_events >> 1);
charlesmn	0:3ac96e360672	2552	tmp64_0 = do_division_u(tmp64_0, total_events);
charlesmn	0:3ac96e360672	2553	if (tmp64_0 > 0xFFFFU)
charlesmn	0:3ac96e360672	2554	tmp64_0 = 0xFFFFU;
charlesmn	0:3ac96e360672	2555
charlesmn	0:3ac96e360672	2556	pxtalk_shape->bin_data[lb] = (uint32_t)tmp64_0;
charlesmn	0:3ac96e360672	2557
charlesmn	0:3ac96e360672	2558
charlesmn	0:3ac96e360672	2559	if ((int32_t)pxtalk_shape->bin_data[lb] >
charlesmn	0:3ac96e360672	2560	pxtalk_data->max_shape_value)
charlesmn	0:3ac96e360672	2561	pxtalk_data->max_shape_value =
charlesmn	0:3ac96e360672	2562	(int32_t)pxtalk_shape->bin_data[lb];
charlesmn	0:3ac96e360672	2563
charlesmn	0:3ac96e360672	2564	remaining_area -= (int32_t)pxtalk_shape->bin_data[lb];
charlesmn	0:3ac96e360672	2565	}
charlesmn	0:3ac96e360672	2566	}
charlesmn	0:3ac96e360672	2567
charlesmn	0:3ac96e360672	2568	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	2569
charlesmn	0:3ac96e360672	2570	return status;
charlesmn	0:3ac96e360672	2571	}
charlesmn	0:3ac96e360672	2572
charlesmn	0:3ac96e360672	2573
charlesmn	0:3ac96e360672	2574	VL53L1_Error VL53L1_hist_xtalk_shape_model(
charlesmn	0:3ac96e360672	2575	uint16_t events_per_bin,
charlesmn	0:3ac96e360672	2576	uint16_t pulse_centre,
charlesmn	0:3ac96e360672	2577	uint16_t pulse_width,
charlesmn	0:3ac96e360672	2578	VL53L1_xtalk_histogram_shape_t *pxtalk_shape)
charlesmn	0:3ac96e360672	2579	{
charlesmn	0:3ac96e360672	2580
charlesmn	0:3ac96e360672	2581
charlesmn	0:3ac96e360672	2582	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	2583
charlesmn	0:3ac96e360672	2584	uint32_t phase_start = 0;
charlesmn	0:3ac96e360672	2585	uint32_t phase_stop = 0;
charlesmn	0:3ac96e360672	2586	uint32_t phase_bin = 0;
charlesmn	0:3ac96e360672	2587
charlesmn	0:3ac96e360672	2588	uint32_t bin_start = 0;
charlesmn	0:3ac96e360672	2589	uint32_t bin_stop = 0;
charlesmn	0:3ac96e360672	2590
charlesmn	0:3ac96e360672	2591	uint32_t lb = 0;
charlesmn	0:3ac96e360672	2592	uint16_t VL53L1_p_008 = 0;
charlesmn	0:3ac96e360672	2593
charlesmn	0:3ac96e360672	2594	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2595
charlesmn	0:3ac96e360672	2596
charlesmn	0:3ac96e360672	2597
charlesmn	0:3ac96e360672	2598	pxtalk_shape->VL53L1_p_022 = 0;
charlesmn	0:3ac96e360672	2599	pxtalk_shape->VL53L1_p_023 = VL53L1_XTALK_HISTO_BINS;
charlesmn	0:3ac96e360672	2600	pxtalk_shape->VL53L1_p_024 = VL53L1_XTALK_HISTO_BINS;
charlesmn	0:3ac96e360672	2601
charlesmn	0:3ac96e360672	2602	pxtalk_shape->zero_distance_phase = pulse_centre;
charlesmn	0:3ac96e360672	2603	pxtalk_shape->phasecal_result__reference_phase =
charlesmn	0:3ac96e360672	2604	pulse_centre + (3*2048);
charlesmn	0:3ac96e360672	2605
charlesmn	0:3ac96e360672	2606
charlesmn	0:3ac96e360672	2607	if (pulse_centre > (pulse_width >> 1))
charlesmn	0:3ac96e360672	2608	phase_start = (uint32_t)pulse_centre -
charlesmn	0:3ac96e360672	2609	((uint32_t)pulse_width >> 1);
charlesmn	0:3ac96e360672	2610	else
charlesmn	0:3ac96e360672	2611	phase_start = 0;
charlesmn	0:3ac96e360672	2612
charlesmn	0:3ac96e360672	2613	phase_stop = (uint32_t)pulse_centre +
charlesmn	0:3ac96e360672	2614	((uint32_t)pulse_width >> 1);
charlesmn	0:3ac96e360672	2615
charlesmn	0:3ac96e360672	2616
charlesmn	0:3ac96e360672	2617	bin_start = (phase_start / 2048);
charlesmn	0:3ac96e360672	2618	bin_stop = (phase_stop / 2048);
charlesmn	0:3ac96e360672	2619
charlesmn	0:3ac96e360672	2620	for (lb = 0; lb < VL53L1_XTALK_HISTO_BINS; lb++) {
charlesmn	0:3ac96e360672	2621	VL53L1_p_008 = 0;
charlesmn	0:3ac96e360672	2622
charlesmn	0:3ac96e360672	2623
charlesmn	0:3ac96e360672	2624	if (lb == bin_start && lb == bin_stop) {
charlesmn	0:3ac96e360672	2625	VL53L1_p_008 =
charlesmn	0:3ac96e360672	2626	VL53L1_hist_xtalk_shape_model_interp(
charlesmn	0:3ac96e360672	2627	events_per_bin,
charlesmn	0:3ac96e360672	2628	phase_stop - phase_start);
charlesmn	0:3ac96e360672	2629
charlesmn	0:3ac96e360672	2630	} else if (lb > bin_start && lb < bin_stop) {
charlesmn	0:3ac96e360672	2631
charlesmn	0:3ac96e360672	2632
charlesmn	0:3ac96e360672	2633	VL53L1_p_008 = events_per_bin;
charlesmn	0:3ac96e360672	2634
charlesmn	0:3ac96e360672	2635	} else if (lb == bin_start) {
charlesmn	0:3ac96e360672	2636
charlesmn	0:3ac96e360672	2637
charlesmn	0:3ac96e360672	2638	phase_bin = (lb + 1) * 2048;
charlesmn	0:3ac96e360672	2639	VL53L1_p_008 =
charlesmn	0:3ac96e360672	2640	VL53L1_hist_xtalk_shape_model_interp(
charlesmn	0:3ac96e360672	2641	events_per_bin,
charlesmn	0:3ac96e360672	2642	(phase_bin - phase_start));
charlesmn	0:3ac96e360672	2643
charlesmn	0:3ac96e360672	2644	} else if (lb == bin_stop) {
charlesmn	0:3ac96e360672	2645
charlesmn	0:3ac96e360672	2646
charlesmn	0:3ac96e360672	2647	phase_bin = lb * 2048;
charlesmn	0:3ac96e360672	2648	VL53L1_p_008 =
charlesmn	0:3ac96e360672	2649	VL53L1_hist_xtalk_shape_model_interp(
charlesmn	0:3ac96e360672	2650	events_per_bin,
charlesmn	0:3ac96e360672	2651	(phase_stop - phase_bin));
charlesmn	0:3ac96e360672	2652	}
charlesmn	0:3ac96e360672	2653
charlesmn	0:3ac96e360672	2654	pxtalk_shape->bin_data[lb] = VL53L1_p_008;
charlesmn	0:3ac96e360672	2655	}
charlesmn	0:3ac96e360672	2656
charlesmn	0:3ac96e360672	2657	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	2658
charlesmn	0:3ac96e360672	2659	return status;
charlesmn	0:3ac96e360672	2660	}
charlesmn	0:3ac96e360672	2661
charlesmn	0:3ac96e360672	2662
charlesmn	0:3ac96e360672	2663	uint16_t VL53L1_hist_xtalk_shape_model_interp(
charlesmn	0:3ac96e360672	2664	uint16_t events_per_bin,
charlesmn	0:3ac96e360672	2665	uint32_t phase_delta)
charlesmn	0:3ac96e360672	2666	{
charlesmn	0:3ac96e360672	2667
charlesmn	0:3ac96e360672	2668
charlesmn	0:3ac96e360672	2669	uint32_t VL53L1_p_008 = 0;
charlesmn	0:3ac96e360672	2670
charlesmn	0:3ac96e360672	2671	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	2672
charlesmn	0:3ac96e360672	2673
charlesmn	0:3ac96e360672	2674	VL53L1_p_008 = (uint32_t)events_per_bin * phase_delta;
charlesmn	0:3ac96e360672	2675	VL53L1_p_008 += 1024;
charlesmn	0:3ac96e360672	2676	VL53L1_p_008 /= 2048;
charlesmn	0:3ac96e360672	2677
charlesmn	0:3ac96e360672	2678
charlesmn	0:3ac96e360672	2679	if (VL53L1_p_008 > 0xFFFFU)
charlesmn	0:3ac96e360672	2680	VL53L1_p_008 = 0xFFFFU;
charlesmn	0:3ac96e360672	2681
charlesmn	0:3ac96e360672	2682	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	2683
charlesmn	0:3ac96e360672	2684	return (uint16_t)VL53L1_p_008;
charlesmn	0:3ac96e360672	2685	}
charlesmn	0:3ac96e360672	2686
charlesmn	0:3ac96e360672	2687
charlesmn	0:3ac96e360672	2688	void VL53L1_spad_number_to_byte_bit_index(
charlesmn	0:3ac96e360672	2689	uint8_t spad_number,
charlesmn	0:3ac96e360672	2690	uint8_t *pbyte_index,
charlesmn	0:3ac96e360672	2691	uint8_t *pbit_index,
charlesmn	0:3ac96e360672	2692	uint8_t *pbit_mask)
charlesmn	0:3ac96e360672	2693	{
charlesmn	0:3ac96e360672	2694
charlesmn	0:3ac96e360672	2695
charlesmn	0:3ac96e360672	2696
charlesmn	0:3ac96e360672	2697	*pbyte_index = spad_number >> 3;
charlesmn	0:3ac96e360672	2698	*pbit_index = spad_number & 0x07;
charlesmn	0:3ac96e360672	2699	pbit_mask = 0x01 << pbit_index;
charlesmn	0:3ac96e360672	2700
charlesmn	0:3ac96e360672	2701	}
charlesmn	0:3ac96e360672	2702
charlesmn	0:3ac96e360672	2703
charlesmn	0:3ac96e360672	2704	void VL53L1_encode_row_col(
charlesmn	0:3ac96e360672	2705	uint8_t row,
charlesmn	0:3ac96e360672	2706	uint8_t col,
charlesmn	0:3ac96e360672	2707	uint8_t *pspad_number)
charlesmn	0:3ac96e360672	2708	{
charlesmn	0:3ac96e360672	2709
charlesmn	0:3ac96e360672	2710
charlesmn	0:3ac96e360672	2711	if (row > 7)
charlesmn	0:3ac96e360672	2712	*pspad_number = 128 + (col << 3) + (15-row);
charlesmn	0:3ac96e360672	2713	else
charlesmn	0:3ac96e360672	2714	*pspad_number = ((15-col) << 3) + row;
charlesmn	0:3ac96e360672	2715
charlesmn	0:3ac96e360672	2716	}
charlesmn	0:3ac96e360672	2717
charlesmn	0:3ac96e360672	2718
charlesmn	0:3ac96e360672	2719	void VL53L1_decode_zone_size(
charlesmn	0:3ac96e360672	2720	uint8_t encoded_xy_size,
charlesmn	0:3ac96e360672	2721	uint8_t *pwidth,
charlesmn	0:3ac96e360672	2722	uint8_t *pheight)
charlesmn	0:3ac96e360672	2723	{
charlesmn	0:3ac96e360672	2724
charlesmn	0:3ac96e360672	2725
charlesmn	0:3ac96e360672	2726
charlesmn	0:3ac96e360672	2727	*pheight = encoded_xy_size >> 4;
charlesmn	0:3ac96e360672	2728	*pwidth = encoded_xy_size & 0x0F;
charlesmn	0:3ac96e360672	2729
charlesmn	0:3ac96e360672	2730	}
charlesmn	0:3ac96e360672	2731
charlesmn	0:3ac96e360672	2732
charlesmn	0:3ac96e360672	2733	void VL53L1_encode_zone_size(
charlesmn	0:3ac96e360672	2734	uint8_t width,
charlesmn	0:3ac96e360672	2735	uint8_t height,
charlesmn	0:3ac96e360672	2736	uint8_t *pencoded_xy_size)
charlesmn	0:3ac96e360672	2737	{
charlesmn	0:3ac96e360672	2738
charlesmn	0:3ac96e360672	2739
charlesmn	0:3ac96e360672	2740	*pencoded_xy_size = (height << 4) + width;
charlesmn	0:3ac96e360672	2741
charlesmn	0:3ac96e360672	2742	}
charlesmn	0:3ac96e360672	2743
charlesmn	0:3ac96e360672	2744
charlesmn	0:3ac96e360672	2745	void VL53L1_decode_zone_limits(
charlesmn	0:3ac96e360672	2746	uint8_t encoded_xy_centre,
charlesmn	0:3ac96e360672	2747	uint8_t encoded_xy_size,
charlesmn	0:3ac96e360672	2748	int16_t *px_ll,
charlesmn	0:3ac96e360672	2749	int16_t *py_ll,
charlesmn	0:3ac96e360672	2750	int16_t *px_ur,
charlesmn	0:3ac96e360672	2751	int16_t *py_ur)
charlesmn	0:3ac96e360672	2752	{
charlesmn	0:3ac96e360672	2753
charlesmn	0:3ac96e360672	2754
charlesmn	0:3ac96e360672	2755
charlesmn	0:3ac96e360672	2756	uint8_t x_centre = 0;
charlesmn	0:3ac96e360672	2757	uint8_t y_centre = 0;
charlesmn	0:3ac96e360672	2758	uint8_t width = 0;
charlesmn	0:3ac96e360672	2759	uint8_t height = 0;
charlesmn	0:3ac96e360672	2760
charlesmn	0:3ac96e360672	2761
charlesmn	0:3ac96e360672	2762
charlesmn	0:3ac96e360672	2763	VL53L1_decode_row_col(
charlesmn	0:3ac96e360672	2764	encoded_xy_centre,
charlesmn	0:3ac96e360672	2765	&y_centre,
charlesmn	0:3ac96e360672	2766	&x_centre);
charlesmn	0:3ac96e360672	2767
charlesmn	0:3ac96e360672	2768	VL53L1_decode_zone_size(
charlesmn	0:3ac96e360672	2769	encoded_xy_size,
charlesmn	0:3ac96e360672	2770	&width,
charlesmn	0:3ac96e360672	2771	&height);
charlesmn	0:3ac96e360672	2772
charlesmn	0:3ac96e360672	2773
charlesmn	0:3ac96e360672	2774
charlesmn	0:3ac96e360672	2775	*px_ll = (int16_t)x_centre - ((int16_t)width + 1) / 2;
charlesmn	0:3ac96e360672	2776	if (*px_ll < 0)
charlesmn	0:3ac96e360672	2777	*px_ll = 0;
charlesmn	0:3ac96e360672	2778
charlesmn	0:3ac96e360672	2779	px_ur = px_ll + (int16_t)width;
charlesmn	0:3ac96e360672	2780	if (*px_ur > (VL53L1_SPAD_ARRAY_WIDTH-1))
charlesmn	0:3ac96e360672	2781	*px_ur = VL53L1_SPAD_ARRAY_WIDTH-1;
charlesmn	0:3ac96e360672	2782
charlesmn	0:3ac96e360672	2783	*py_ll = (int16_t)y_centre - ((int16_t)height + 1) / 2;
charlesmn	0:3ac96e360672	2784	if (*py_ll < 0)
charlesmn	0:3ac96e360672	2785	*py_ll = 0;
charlesmn	0:3ac96e360672	2786
charlesmn	0:3ac96e360672	2787	py_ur = py_ll + (int16_t)height;
charlesmn	0:3ac96e360672	2788	if (*py_ur > (VL53L1_SPAD_ARRAY_HEIGHT-1))
charlesmn	0:3ac96e360672	2789	*py_ur = VL53L1_SPAD_ARRAY_HEIGHT-1;
charlesmn	0:3ac96e360672	2790	}
charlesmn	0:3ac96e360672	2791
charlesmn	0:3ac96e360672	2792
charlesmn	0:3ac96e360672	2793	uint8_t VL53L1_is_aperture_location(
charlesmn	0:3ac96e360672	2794	uint8_t row,
charlesmn	0:3ac96e360672	2795	uint8_t col)
charlesmn	0:3ac96e360672	2796	{
charlesmn	0:3ac96e360672	2797
charlesmn	0:3ac96e360672	2798
charlesmn	0:3ac96e360672	2799	uint8_t is_aperture = 0;
charlesmn	0:3ac96e360672	2800	uint8_t mod_row = row % 4;
charlesmn	0:3ac96e360672	2801	uint8_t mod_col = col % 4;
charlesmn	0:3ac96e360672	2802
charlesmn	0:3ac96e360672	2803	if (mod_row == 0 && mod_col == 2)
charlesmn	0:3ac96e360672	2804	is_aperture = 1;
charlesmn	0:3ac96e360672	2805
charlesmn	0:3ac96e360672	2806	if (mod_row == 2 && mod_col == 0)
charlesmn	0:3ac96e360672	2807	is_aperture = 1;
charlesmn	0:3ac96e360672	2808
charlesmn	0:3ac96e360672	2809	return is_aperture;
charlesmn	0:3ac96e360672	2810	}
charlesmn	0:3ac96e360672	2811
charlesmn	0:3ac96e360672	2812
charlesmn	0:3ac96e360672	2813	void VL53L1_calc_max_effective_spads(
charlesmn	0:3ac96e360672	2814	uint8_t encoded_zone_centre,
charlesmn	0:3ac96e360672	2815	uint8_t encoded_zone_size,
charlesmn	0:3ac96e360672	2816	uint8_t *pgood_spads,
charlesmn	0:3ac96e360672	2817	uint16_t aperture_attenuation,
charlesmn	0:3ac96e360672	2818	uint16_t *pmax_effective_spads)
charlesmn	0:3ac96e360672	2819	{
charlesmn	0:3ac96e360672	2820
charlesmn	0:3ac96e360672	2821
charlesmn	0:3ac96e360672	2822
charlesmn	0:3ac96e360672	2823	int16_t x = 0;
charlesmn	0:3ac96e360672	2824	int16_t y = 0;
charlesmn	0:3ac96e360672	2825
charlesmn	0:3ac96e360672	2826	int16_t zone_x_ll = 0;
charlesmn	0:3ac96e360672	2827	int16_t zone_y_ll = 0;
charlesmn	0:3ac96e360672	2828	int16_t zone_x_ur = 0;
charlesmn	0:3ac96e360672	2829	int16_t zone_y_ur = 0;
charlesmn	0:3ac96e360672	2830
charlesmn	0:3ac96e360672	2831	uint8_t spad_number = 0;
charlesmn	0:3ac96e360672	2832	uint8_t byte_index = 0;
charlesmn	0:3ac96e360672	2833	uint8_t bit_index = 0;
charlesmn	0:3ac96e360672	2834	uint8_t bit_mask = 0;
charlesmn	0:3ac96e360672	2835
charlesmn	0:3ac96e360672	2836	uint8_t is_aperture = 0;
charlesmn	0:3ac96e360672	2837
charlesmn	0:3ac96e360672	2838
charlesmn	0:3ac96e360672	2839
charlesmn	0:3ac96e360672	2840	VL53L1_decode_zone_limits(
charlesmn	0:3ac96e360672	2841	encoded_zone_centre,
charlesmn	0:3ac96e360672	2842	encoded_zone_size,
charlesmn	0:3ac96e360672	2843	&zone_x_ll,
charlesmn	0:3ac96e360672	2844	&zone_y_ll,
charlesmn	0:3ac96e360672	2845	&zone_x_ur,
charlesmn	0:3ac96e360672	2846	&zone_y_ur);
charlesmn	0:3ac96e360672	2847
charlesmn	0:3ac96e360672	2848
charlesmn	0:3ac96e360672	2849
charlesmn	0:3ac96e360672	2850	*pmax_effective_spads = 0;
charlesmn	0:3ac96e360672	2851
charlesmn	0:3ac96e360672	2852	for (y = zone_y_ll; y <= zone_y_ur; y++) {
charlesmn	0:3ac96e360672	2853	for (x = zone_x_ll; x <= zone_x_ur; x++) {
charlesmn	0:3ac96e360672	2854
charlesmn	0:3ac96e360672	2855
charlesmn	0:3ac96e360672	2856
charlesmn	0:3ac96e360672	2857	VL53L1_encode_row_col(
charlesmn	0:3ac96e360672	2858	(uint8_t)y,
charlesmn	0:3ac96e360672	2859	(uint8_t)x,
charlesmn	0:3ac96e360672	2860	&spad_number);
charlesmn	0:3ac96e360672	2861
charlesmn	0:3ac96e360672	2862
charlesmn	0:3ac96e360672	2863
charlesmn	0:3ac96e360672	2864	VL53L1_spad_number_to_byte_bit_index(
charlesmn	0:3ac96e360672	2865	spad_number,
charlesmn	0:3ac96e360672	2866	&byte_index,
charlesmn	0:3ac96e360672	2867	&bit_index,
charlesmn	0:3ac96e360672	2868	&bit_mask);
charlesmn	0:3ac96e360672	2869
charlesmn	0:3ac96e360672	2870
charlesmn	0:3ac96e360672	2871
charlesmn	0:3ac96e360672	2872	if ((pgood_spads[byte_index] & bit_mask) > 0) {
charlesmn	0:3ac96e360672	2873
charlesmn	0:3ac96e360672	2874
charlesmn	0:3ac96e360672	2875	is_aperture = VL53L1_is_aperture_location(
charlesmn	0:3ac96e360672	2876	(uint8_t)y,
charlesmn	0:3ac96e360672	2877	(uint8_t)x);
charlesmn	0:3ac96e360672	2878
charlesmn	0:3ac96e360672	2879	if (is_aperture > 0)
charlesmn	0:3ac96e360672	2880	*pmax_effective_spads +=
charlesmn	0:3ac96e360672	2881	aperture_attenuation;
charlesmn	0:3ac96e360672	2882	else
charlesmn	0:3ac96e360672	2883	*pmax_effective_spads += 0x0100;
charlesmn	0:3ac96e360672	2884
charlesmn	0:3ac96e360672	2885	}
charlesmn	0:3ac96e360672	2886	}
charlesmn	0:3ac96e360672	2887	}
charlesmn	0:3ac96e360672	2888	}
charlesmn	0:3ac96e360672	2889
charlesmn	0:3ac96e360672	2890
charlesmn	0:3ac96e360672	2891	void VL53L1_calc_mm_effective_spads(
charlesmn	0:3ac96e360672	2892	uint8_t encoded_mm_roi_centre,
charlesmn	0:3ac96e360672	2893	uint8_t encoded_mm_roi_size,
charlesmn	0:3ac96e360672	2894	uint8_t encoded_zone_centre,
charlesmn	0:3ac96e360672	2895	uint8_t encoded_zone_size,
charlesmn	0:3ac96e360672	2896	uint8_t *pgood_spads,
charlesmn	0:3ac96e360672	2897	uint16_t aperture_attenuation,
charlesmn	0:3ac96e360672	2898	uint16_t *pmm_inner_effective_spads,
charlesmn	0:3ac96e360672	2899	uint16_t *pmm_outer_effective_spads)
charlesmn	0:3ac96e360672	2900	{
charlesmn	0:3ac96e360672	2901
charlesmn	0:3ac96e360672	2902
charlesmn	0:3ac96e360672	2903
charlesmn	0:3ac96e360672	2904	int16_t x = 0;
charlesmn	0:3ac96e360672	2905	int16_t y = 0;
charlesmn	0:3ac96e360672	2906
charlesmn	0:3ac96e360672	2907	int16_t mm_x_ll = 0;
charlesmn	0:3ac96e360672	2908	int16_t mm_y_ll = 0;
charlesmn	0:3ac96e360672	2909	int16_t mm_x_ur = 0;
charlesmn	0:3ac96e360672	2910	int16_t mm_y_ur = 0;
charlesmn	0:3ac96e360672	2911
charlesmn	0:3ac96e360672	2912	int16_t zone_x_ll = 0;
charlesmn	0:3ac96e360672	2913	int16_t zone_y_ll = 0;
charlesmn	0:3ac96e360672	2914	int16_t zone_x_ur = 0;
charlesmn	0:3ac96e360672	2915	int16_t zone_y_ur = 0;
charlesmn	0:3ac96e360672	2916
charlesmn	0:3ac96e360672	2917	uint8_t spad_number = 0;
charlesmn	0:3ac96e360672	2918	uint8_t byte_index = 0;
charlesmn	0:3ac96e360672	2919	uint8_t bit_index = 0;
charlesmn	0:3ac96e360672	2920	uint8_t bit_mask = 0;
charlesmn	0:3ac96e360672	2921
charlesmn	0:3ac96e360672	2922	uint8_t is_aperture = 0;
charlesmn	0:3ac96e360672	2923	uint16_t spad_attenuation = 0;
charlesmn	0:3ac96e360672	2924
charlesmn	0:3ac96e360672	2925
charlesmn	0:3ac96e360672	2926
charlesmn	0:3ac96e360672	2927	VL53L1_decode_zone_limits(
charlesmn	0:3ac96e360672	2928	encoded_mm_roi_centre,
charlesmn	0:3ac96e360672	2929	encoded_mm_roi_size,
charlesmn	0:3ac96e360672	2930	&mm_x_ll,
charlesmn	0:3ac96e360672	2931	&mm_y_ll,
charlesmn	0:3ac96e360672	2932	&mm_x_ur,
charlesmn	0:3ac96e360672	2933	&mm_y_ur);
charlesmn	0:3ac96e360672	2934
charlesmn	0:3ac96e360672	2935	VL53L1_decode_zone_limits(
charlesmn	0:3ac96e360672	2936	encoded_zone_centre,
charlesmn	0:3ac96e360672	2937	encoded_zone_size,
charlesmn	0:3ac96e360672	2938	&zone_x_ll,
charlesmn	0:3ac96e360672	2939	&zone_y_ll,
charlesmn	0:3ac96e360672	2940	&zone_x_ur,
charlesmn	0:3ac96e360672	2941	&zone_y_ur);
charlesmn	0:3ac96e360672	2942
charlesmn	0:3ac96e360672	2943
charlesmn	0:3ac96e360672	2944
charlesmn	0:3ac96e360672	2945	*pmm_inner_effective_spads = 0;
charlesmn	0:3ac96e360672	2946	*pmm_outer_effective_spads = 0;
charlesmn	0:3ac96e360672	2947
charlesmn	0:3ac96e360672	2948	for (y = zone_y_ll; y <= zone_y_ur; y++) {
charlesmn	0:3ac96e360672	2949	for (x = zone_x_ll; x <= zone_x_ur; x++) {
charlesmn	0:3ac96e360672	2950
charlesmn	0:3ac96e360672	2951
charlesmn	0:3ac96e360672	2952
charlesmn	0:3ac96e360672	2953	VL53L1_encode_row_col(
charlesmn	0:3ac96e360672	2954	(uint8_t)y,
charlesmn	0:3ac96e360672	2955	(uint8_t)x,
charlesmn	0:3ac96e360672	2956	&spad_number);
charlesmn	0:3ac96e360672	2957
charlesmn	0:3ac96e360672	2958
charlesmn	0:3ac96e360672	2959
charlesmn	0:3ac96e360672	2960	VL53L1_spad_number_to_byte_bit_index(
charlesmn	0:3ac96e360672	2961	spad_number,
charlesmn	0:3ac96e360672	2962	&byte_index,
charlesmn	0:3ac96e360672	2963	&bit_index,
charlesmn	0:3ac96e360672	2964	&bit_mask);
charlesmn	0:3ac96e360672	2965
charlesmn	0:3ac96e360672	2966
charlesmn	0:3ac96e360672	2967
charlesmn	0:3ac96e360672	2968	if ((pgood_spads[byte_index] & bit_mask) > 0) {
charlesmn	0:3ac96e360672	2969
charlesmn	0:3ac96e360672	2970
charlesmn	0:3ac96e360672	2971	is_aperture = VL53L1_is_aperture_location(
charlesmn	0:3ac96e360672	2972	(uint8_t)y,
charlesmn	0:3ac96e360672	2973	(uint8_t)x);
charlesmn	0:3ac96e360672	2974
charlesmn	0:3ac96e360672	2975	if (is_aperture > 0)
charlesmn	0:3ac96e360672	2976	spad_attenuation = aperture_attenuation;
charlesmn	0:3ac96e360672	2977	else
charlesmn	0:3ac96e360672	2978	spad_attenuation = 0x0100;
charlesmn	0:3ac96e360672	2979
charlesmn	0:3ac96e360672	2980
charlesmn	0:3ac96e360672	2981
charlesmn	0:3ac96e360672	2982	if (x >= mm_x_ll && x <= mm_x_ur &&
charlesmn	0:3ac96e360672	2983	y >= mm_y_ll && y <= mm_y_ur)
charlesmn	0:3ac96e360672	2984	*pmm_inner_effective_spads +=
charlesmn	0:3ac96e360672	2985	spad_attenuation;
charlesmn	0:3ac96e360672	2986	else
charlesmn	0:3ac96e360672	2987	*pmm_outer_effective_spads +=
charlesmn	0:3ac96e360672	2988	spad_attenuation;
charlesmn	0:3ac96e360672	2989	}
charlesmn	0:3ac96e360672	2990	}
charlesmn	0:3ac96e360672	2991	}
charlesmn	0:3ac96e360672	2992	}
charlesmn	0:3ac96e360672	2993
charlesmn	0:3ac96e360672	2994
charlesmn	0:3ac96e360672	2995	void VL53L1_hist_copy_results_to_sys_and_core(
charlesmn	0:3ac96e360672	2996	VL53L1_histogram_bin_data_t *pbins,
charlesmn	0:3ac96e360672	2997	VL53L1_range_results_t *phist,
charlesmn	0:3ac96e360672	2998	VL53L1_system_results_t *psys,
charlesmn	0:3ac96e360672	2999	VL53L1_core_results_t *pcore)
charlesmn	0:3ac96e360672	3000	{
charlesmn	0:3ac96e360672	3001
charlesmn	0:3ac96e360672	3002
charlesmn	0:3ac96e360672	3003	uint8_t i = 0;
charlesmn	0:3ac96e360672	3004
charlesmn	0:3ac96e360672	3005	VL53L1_range_data_t *pdata;
charlesmn	0:3ac96e360672	3006
charlesmn	0:3ac96e360672	3007	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3008
charlesmn	0:3ac96e360672	3009
charlesmn	0:3ac96e360672	3010
charlesmn	0:3ac96e360672	3011	VL53L1_init_system_results(psys);
charlesmn	0:3ac96e360672	3012
charlesmn	0:3ac96e360672	3013
charlesmn	0:3ac96e360672	3014
charlesmn	0:3ac96e360672	3015	psys->result__interrupt_status = pbins->result__interrupt_status;
charlesmn	0:3ac96e360672	3016	psys->result__range_status = phist->active_results;
charlesmn	0:3ac96e360672	3017	psys->result__report_status = pbins->result__report_status;
charlesmn	0:3ac96e360672	3018	psys->result__stream_count = pbins->result__stream_count;
charlesmn	0:3ac96e360672	3019
charlesmn	0:3ac96e360672	3020	pdata = &(phist->VL53L1_p_002[0]);
charlesmn	0:3ac96e360672	3021
charlesmn	0:3ac96e360672	3022	for (i = 0; i < phist->active_results; i++) {
charlesmn	0:3ac96e360672	3023
charlesmn	0:3ac96e360672	3024	switch (i) {
charlesmn	0:3ac96e360672	3025	case 0:
charlesmn	0:3ac96e360672	3026	psys->result__dss_actual_effective_spads_sd0 =
charlesmn	0:3ac96e360672	3027	pdata->VL53L1_p_006;
charlesmn	0:3ac96e360672	3028	psys->result__peak_signal_count_rate_mcps_sd0 =
charlesmn	0:3ac96e360672	3029	pdata->peak_signal_count_rate_mcps;
charlesmn	0:3ac96e360672	3030	psys->result__avg_signal_count_rate_mcps_sd0 =
charlesmn	0:3ac96e360672	3031	pdata->avg_signal_count_rate_mcps;
charlesmn	0:3ac96e360672	3032	psys->result__ambient_count_rate_mcps_sd0 =
charlesmn	0:3ac96e360672	3033	pdata->ambient_count_rate_mcps;
charlesmn	0:3ac96e360672	3034
charlesmn	0:3ac96e360672	3035	psys->result__sigma_sd0 = pdata->VL53L1_p_005;
charlesmn	0:3ac96e360672	3036	psys->result__phase_sd0 = pdata->VL53L1_p_014;
charlesmn	0:3ac96e360672	3037
charlesmn	0:3ac96e360672	3038	psys->result__final_crosstalk_corrected_range_mm_sd0 =
charlesmn	0:3ac96e360672	3039	(uint16_t)pdata->median_range_mm;
charlesmn	0:3ac96e360672	3040
charlesmn	0:3ac96e360672	3041	psys->result__phase_sd1 = pdata->zero_distance_phase;
charlesmn	0:3ac96e360672	3042
charlesmn	0:3ac96e360672	3043	pcore->result_core__ranging_total_events_sd0 =
charlesmn	0:3ac96e360672	3044	pdata->VL53L1_p_021;
charlesmn	0:3ac96e360672	3045	pcore->result_core__signal_total_events_sd0 =
charlesmn	0:3ac96e360672	3046	pdata->VL53L1_p_013;
charlesmn	0:3ac96e360672	3047	pcore->result_core__total_periods_elapsed_sd0 =
charlesmn	0:3ac96e360672	3048	pdata->total_periods_elapsed;
charlesmn	0:3ac96e360672	3049	pcore->result_core__ambient_window_events_sd0 =
charlesmn	0:3ac96e360672	3050	pdata->VL53L1_p_020;
charlesmn	0:3ac96e360672	3051
charlesmn	0:3ac96e360672	3052	break;
charlesmn	0:3ac96e360672	3053	case 1:
charlesmn	0:3ac96e360672	3054	psys->result__dss_actual_effective_spads_sd1 =
charlesmn	0:3ac96e360672	3055	pdata->VL53L1_p_006;
charlesmn	0:3ac96e360672	3056	psys->result__peak_signal_count_rate_mcps_sd1 =
charlesmn	0:3ac96e360672	3057	pdata->peak_signal_count_rate_mcps;
charlesmn	0:3ac96e360672	3058	psys->result__ambient_count_rate_mcps_sd1 =
charlesmn	0:3ac96e360672	3059	pdata->ambient_count_rate_mcps;
charlesmn	0:3ac96e360672	3060
charlesmn	0:3ac96e360672	3061	psys->result__sigma_sd1 = pdata->VL53L1_p_005;
charlesmn	0:3ac96e360672	3062	psys->result__phase_sd1 = pdata->VL53L1_p_014;
charlesmn	0:3ac96e360672	3063
charlesmn	0:3ac96e360672	3064	psys->result__final_crosstalk_corrected_range_mm_sd1 =
charlesmn	0:3ac96e360672	3065	(uint16_t)pdata->median_range_mm;
charlesmn	0:3ac96e360672	3066
charlesmn	0:3ac96e360672	3067	pcore->result_core__ranging_total_events_sd1 =
charlesmn	0:3ac96e360672	3068	pdata->VL53L1_p_021;
charlesmn	0:3ac96e360672	3069	pcore->result_core__signal_total_events_sd1 =
charlesmn	0:3ac96e360672	3070	pdata->VL53L1_p_013;
charlesmn	0:3ac96e360672	3071	pcore->result_core__total_periods_elapsed_sd1 =
charlesmn	0:3ac96e360672	3072	pdata->total_periods_elapsed;
charlesmn	0:3ac96e360672	3073	pcore->result_core__ambient_window_events_sd1 =
charlesmn	0:3ac96e360672	3074	pdata->VL53L1_p_020;
charlesmn	0:3ac96e360672	3075	break;
charlesmn	0:3ac96e360672	3076	}
charlesmn	0:3ac96e360672	3077
charlesmn	0:3ac96e360672	3078	pdata++;
charlesmn	0:3ac96e360672	3079	}
charlesmn	0:3ac96e360672	3080
charlesmn	0:3ac96e360672	3081	LOG_FUNCTION_END(0);
charlesmn	0:3ac96e360672	3082
charlesmn	0:3ac96e360672	3083	}
charlesmn	0:3ac96e360672	3084
charlesmn	0:3ac96e360672	3085
charlesmn	0:3ac96e360672	3086	VL53L1_Error VL53L1_sum_histogram_data(
charlesmn	0:3ac96e360672	3087	VL53L1_histogram_bin_data_t *phist_input,
charlesmn	0:3ac96e360672	3088	VL53L1_histogram_bin_data_t *phist_output)
charlesmn	0:3ac96e360672	3089	{
charlesmn	0:3ac96e360672	3090
charlesmn	0:3ac96e360672	3091
charlesmn	0:3ac96e360672	3092	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3093
charlesmn	0:3ac96e360672	3094	uint8_t i = 0;
charlesmn	0:3ac96e360672	3095	uint8_t smallest_bin_num = 0;
charlesmn	0:3ac96e360672	3096
charlesmn	0:3ac96e360672	3097	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3098
charlesmn	0:3ac96e360672	3099
charlesmn	0:3ac96e360672	3100
charlesmn	0:3ac96e360672	3101	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	3102	if (phist_output->VL53L1_p_024 >=
charlesmn	0:3ac96e360672	3103	phist_input->VL53L1_p_024)
charlesmn	0:3ac96e360672	3104	smallest_bin_num = phist_input->VL53L1_p_024;
charlesmn	0:3ac96e360672	3105	else
charlesmn	0:3ac96e360672	3106	smallest_bin_num = phist_output->VL53L1_p_024;
charlesmn	0:3ac96e360672	3107	}
charlesmn	0:3ac96e360672	3108
charlesmn	0:3ac96e360672	3109
charlesmn	0:3ac96e360672	3110
charlesmn	0:3ac96e360672	3111
charlesmn	0:3ac96e360672	3112
charlesmn	0:3ac96e360672	3113	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3114	for (i = 0; i < smallest_bin_num; i++)
charlesmn	0:3ac96e360672	3115
charlesmn	0:3ac96e360672	3116	phist_output->bin_data[i] += phist_input->bin_data[i];
charlesmn	0:3ac96e360672	3117
charlesmn	0:3ac96e360672	3118	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3119	phist_output->VL53L1_p_004 +=
charlesmn	0:3ac96e360672	3120	phist_input->VL53L1_p_004;
charlesmn	0:3ac96e360672	3121
charlesmn	0:3ac96e360672	3122
charlesmn	0:3ac96e360672	3123	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3124
charlesmn	0:3ac96e360672	3125	return status;
charlesmn	0:3ac96e360672	3126	}
charlesmn	0:3ac96e360672	3127
charlesmn	0:3ac96e360672	3128
charlesmn	0:3ac96e360672	3129	VL53L1_Error VL53L1_avg_histogram_data(
charlesmn	0:3ac96e360672	3130	uint8_t no_of_samples,
charlesmn	0:3ac96e360672	3131	VL53L1_histogram_bin_data_t *phist_sum,
charlesmn	0:3ac96e360672	3132	VL53L1_histogram_bin_data_t *phist_avg)
charlesmn	0:3ac96e360672	3133	{
charlesmn	0:3ac96e360672	3134
charlesmn	0:3ac96e360672	3135
charlesmn	0:3ac96e360672	3136	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3137
charlesmn	0:3ac96e360672	3138	uint8_t i = 0;
charlesmn	0:3ac96e360672	3139
charlesmn	0:3ac96e360672	3140	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3141
charlesmn	0:3ac96e360672	3142
charlesmn	0:3ac96e360672	3143
charlesmn	0:3ac96e360672	3144
charlesmn	0:3ac96e360672	3145
charlesmn	0:3ac96e360672	3146	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	3147	for (i = 0; i < phist_sum->VL53L1_p_024; i++) {
charlesmn	0:3ac96e360672	3148
charlesmn	0:3ac96e360672	3149
charlesmn	0:3ac96e360672	3150
charlesmn	0:3ac96e360672	3151	if (no_of_samples > 0)
charlesmn	0:3ac96e360672	3152	phist_avg->bin_data[i] =
charlesmn	0:3ac96e360672	3153	phist_sum->bin_data[i] /
charlesmn	0:3ac96e360672	3154	(int32_t)no_of_samples;
charlesmn	0:3ac96e360672	3155	else
charlesmn	0:3ac96e360672	3156	phist_avg->bin_data[i] = phist_sum->bin_data[i];
charlesmn	0:3ac96e360672	3157	}
charlesmn	0:3ac96e360672	3158	}
charlesmn	0:3ac96e360672	3159
charlesmn	0:3ac96e360672	3160	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	3161	if (no_of_samples > 0)
charlesmn	0:3ac96e360672	3162	phist_avg->VL53L1_p_004 =
charlesmn	0:3ac96e360672	3163	phist_sum->VL53L1_p_004 /
charlesmn	0:3ac96e360672	3164	(int32_t)no_of_samples;
charlesmn	0:3ac96e360672	3165	else
charlesmn	0:3ac96e360672	3166	phist_avg->VL53L1_p_004 =
charlesmn	0:3ac96e360672	3167	phist_sum->VL53L1_p_004;
charlesmn	0:3ac96e360672	3168	}
charlesmn	0:3ac96e360672	3169
charlesmn	0:3ac96e360672	3170	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3171
charlesmn	0:3ac96e360672	3172	return status;
charlesmn	0:3ac96e360672	3173	}
charlesmn	0:3ac96e360672	3174
charlesmn	0:3ac96e360672	3175
charlesmn	0:3ac96e360672	3176	VL53L1_Error VL53L1_save_cfg_data(
charlesmn	0:3ac96e360672	3177	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	3178	{
charlesmn	0:3ac96e360672	3179
charlesmn	0:3ac96e360672	3180
charlesmn	0:3ac96e360672	3181	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3182
charlesmn	0:3ac96e360672	3183	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	3184	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3185	VL53L1_LLDriverResults_t *pres =
charlesmn	0:3ac96e360672	3186	VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	3187
charlesmn	0:3ac96e360672	3188	VL53L1_zone_private_dyn_cfg_t *pzone_dyn_cfg;
charlesmn	0:3ac96e360672	3189	VL53L1_dynamic_config_t *pdynamic = &(pdev->dyn_cfg);
charlesmn	0:3ac96e360672	3190
charlesmn	0:3ac96e360672	3191	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3192
charlesmn	0:3ac96e360672	3193	pzone_dyn_cfg =
charlesmn	0:3ac96e360672	3194	&(pres->zone_dyn_cfgs.VL53L1_p_002[pdev->ll_state.cfg_zone_id]);
charlesmn	0:3ac96e360672	3195
charlesmn	0:3ac96e360672	3196	pzone_dyn_cfg->expected_stream_count =
charlesmn	0:3ac96e360672	3197	pdev->ll_state.cfg_stream_count;
charlesmn	0:3ac96e360672	3198
charlesmn	0:3ac96e360672	3199	pzone_dyn_cfg->expected_gph_id =
charlesmn	0:3ac96e360672	3200	pdev->ll_state.cfg_gph_id;
charlesmn	0:3ac96e360672	3201
charlesmn	0:3ac96e360672	3202	pzone_dyn_cfg->roi_config__user_roi_centre_spad =
charlesmn	0:3ac96e360672	3203	pdynamic->roi_config__user_roi_centre_spad;
charlesmn	0:3ac96e360672	3204
charlesmn	0:3ac96e360672	3205	pzone_dyn_cfg->roi_config__user_roi_requested_global_xy_size =
charlesmn	0:3ac96e360672	3206	pdynamic->roi_config__user_roi_requested_global_xy_size;
charlesmn	0:3ac96e360672	3207
charlesmn	0:3ac96e360672	3208	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3209
charlesmn	0:3ac96e360672	3210	return status;
charlesmn	0:3ac96e360672	3211	}
charlesmn	0:3ac96e360672	3212
charlesmn	0:3ac96e360672	3213
charlesmn	0:3ac96e360672	3214	VL53L1_Error VL53L1_dynamic_zone_update(
charlesmn	0:3ac96e360672	3215	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3216	VL53L1_range_results_t *presults)
charlesmn	0:3ac96e360672	3217	{
charlesmn	0:3ac96e360672	3218
charlesmn	0:3ac96e360672	3219
charlesmn	0:3ac96e360672	3220	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3221
charlesmn	0:3ac96e360672	3222	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	3223	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3224	VL53L1_LLDriverResults_t *pres =
charlesmn	0:3ac96e360672	3225	VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	3226	VL53L1_zone_private_dyn_cfgs_t *pZ = &(pres->zone_dyn_cfgs);
charlesmn	0:3ac96e360672	3227
charlesmn	0:3ac96e360672	3228	uint8_t zone_id = pdev->ll_state.rd_zone_id;
charlesmn	0:3ac96e360672	3229	uint8_t i;
charlesmn	0:3ac96e360672	3230	uint16_t max_total_rate_per_spads;
charlesmn	0:3ac96e360672	3231	uint16_t target_rate =
charlesmn	0:3ac96e360672	3232	pdev->stat_cfg.dss_config__target_total_rate_mcps;
charlesmn	0:3ac96e360672	3233	uint32_t temp = 0xFFFF;
charlesmn	0:3ac96e360672	3234	#ifdef VL53L1_LOG_ENABLE
charlesmn	0:3ac96e360672	3235	uint16_t eff_spad_cnt =
charlesmn	0:3ac96e360672	3236	pZ->VL53L1_p_002[zone_id].dss_requested_effective_spad_count;
charlesmn	0:3ac96e360672	3237	#endif
charlesmn	0:3ac96e360672	3238
charlesmn	0:3ac96e360672	3239	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3240
charlesmn	0:3ac96e360672	3241	pZ->VL53L1_p_002[zone_id].dss_requested_effective_spad_count = 0;
charlesmn	0:3ac96e360672	3242
charlesmn	0:3ac96e360672	3243	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3244	" DYNZONEUPDATE: peak signal count rate mcps:");
charlesmn	0:3ac96e360672	3245
charlesmn	0:3ac96e360672	3246	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3247	"%u actual effective spads: %u\n",
charlesmn	0:3ac96e360672	3248	presults->VL53L1_p_002[0].peak_signal_count_rate_mcps,
charlesmn	0:3ac96e360672	3249	presults->VL53L1_p_002[0].VL53L1_p_006);
charlesmn	0:3ac96e360672	3250
charlesmn	0:3ac96e360672	3251	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3252	" DYNZONEUPDATE: active results: %u\n",
charlesmn	0:3ac96e360672	3253	presults->active_results);
charlesmn	0:3ac96e360672	3254
charlesmn	0:3ac96e360672	3255	max_total_rate_per_spads =
charlesmn	0:3ac96e360672	3256	presults->VL53L1_p_002[0].total_rate_per_spad_mcps;
charlesmn	0:3ac96e360672	3257
charlesmn	0:3ac96e360672	3258	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3259	" DYNZONEUPDATE: max total rate per spad at start: %u\n",
charlesmn	0:3ac96e360672	3260	max_total_rate_per_spads);
charlesmn	0:3ac96e360672	3261
charlesmn	0:3ac96e360672	3262	for (i = 1; i < presults->active_results; i++) {
charlesmn	0:3ac96e360672	3263	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3264	" DYNZONEUPDATE: zone total rate per spad: zone_id: %u,",
charlesmn	0:3ac96e360672	3265	i);
charlesmn	0:3ac96e360672	3266
charlesmn	0:3ac96e360672	3267	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3268	"total rate per spad: %u\n",
charlesmn	0:3ac96e360672	3269	presults->VL53L1_p_002[i].total_rate_per_spad_mcps);
charlesmn	0:3ac96e360672	3270
charlesmn	0:3ac96e360672	3271	if (presults->VL53L1_p_002[i].total_rate_per_spad_mcps >
charlesmn	0:3ac96e360672	3272	max_total_rate_per_spads)
charlesmn	0:3ac96e360672	3273	max_total_rate_per_spads =
charlesmn	0:3ac96e360672	3274	presults->VL53L1_p_002[i].total_rate_per_spad_mcps;
charlesmn	0:3ac96e360672	3275
charlesmn	0:3ac96e360672	3276	}
charlesmn	0:3ac96e360672	3277
charlesmn	0:3ac96e360672	3278	if (max_total_rate_per_spads == 0) {
charlesmn	0:3ac96e360672	3279
charlesmn	0:3ac96e360672	3280	temp = 0xFFFF;
charlesmn	0:3ac96e360672	3281	} else {
charlesmn	0:3ac96e360672	3282
charlesmn	0:3ac96e360672	3283	temp = target_rate << 14;
charlesmn	0:3ac96e360672	3284	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3285	" DYNZONEUPDATE: 1: temp: %u\n",
charlesmn	0:3ac96e360672	3286	temp);
charlesmn	0:3ac96e360672	3287
charlesmn	0:3ac96e360672	3288
charlesmn	0:3ac96e360672	3289	temp = temp / max_total_rate_per_spads;
charlesmn	0:3ac96e360672	3290
charlesmn	0:3ac96e360672	3291	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3292	" DYNZONEUPDATE: 2: temp: %u\n",
charlesmn	0:3ac96e360672	3293	temp);
charlesmn	0:3ac96e360672	3294
charlesmn	0:3ac96e360672	3295
charlesmn	0:3ac96e360672	3296	if (temp > 0xFFFF)
charlesmn	0:3ac96e360672	3297	temp = 0xFFFF;
charlesmn	0:3ac96e360672	3298
charlesmn	0:3ac96e360672	3299	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3300	" DYNZONEUPDATE: 3: temp: %u\n",
charlesmn	0:3ac96e360672	3301	temp);
charlesmn	0:3ac96e360672	3302	}
charlesmn	0:3ac96e360672	3303
charlesmn	0:3ac96e360672	3304	pZ->VL53L1_p_002[zone_id].dss_requested_effective_spad_count =
charlesmn	0:3ac96e360672	3305	(uint16_t)temp;
charlesmn	0:3ac96e360672	3306
charlesmn	0:3ac96e360672	3307	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3308	" DYNZONEUPDATE: zone_id: %u, target_rate: %u,",
charlesmn	0:3ac96e360672	3309	zone_id,
charlesmn	0:3ac96e360672	3310	target_rate);
charlesmn	0:3ac96e360672	3311
charlesmn	0:3ac96e360672	3312	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3313	"max_total_rate_per_spads: %u, requested_spads: %u\n",
charlesmn	0:3ac96e360672	3314	max_total_rate_per_spads,
charlesmn	0:3ac96e360672	3315	eff_spad_cnt);
charlesmn	0:3ac96e360672	3316
charlesmn	0:3ac96e360672	3317	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3318
charlesmn	0:3ac96e360672	3319	return status;
charlesmn	0:3ac96e360672	3320	}
charlesmn	0:3ac96e360672	3321
charlesmn	0:3ac96e360672	3322	VL53L1_Error VL53L1_multizone_hist_bins_update(
charlesmn	0:3ac96e360672	3323	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	3324	{
charlesmn	0:3ac96e360672	3325
charlesmn	0:3ac96e360672	3326
charlesmn	0:3ac96e360672	3327	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3328
charlesmn	0:3ac96e360672	3329	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3330	VL53L1_ll_driver_state_t *pstate = &(pdev->ll_state);
charlesmn	0:3ac96e360672	3331	VL53L1_zone_config_t *pzone_cfg = &(pdev->zone_cfg);
charlesmn	0:3ac96e360672	3332	VL53L1_histogram_config_t *phist_cfg = &(pdev->hist_cfg);
charlesmn	0:3ac96e360672	3333	VL53L1_histogram_config_t *pmulti_hist =
charlesmn	0:3ac96e360672	3334	&(pzone_cfg->multizone_hist_cfg);
charlesmn	0:3ac96e360672	3335
charlesmn	0:3ac96e360672	3336	uint8_t next_range_is_odd_timing = (pstate->cfg_stream_count) % 2;
charlesmn	0:3ac96e360672	3337
charlesmn	0:3ac96e360672	3338	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3339
charlesmn	0:3ac96e360672	3340
charlesmn	0:3ac96e360672	3341	if (pzone_cfg->bin_config[pdev->ll_state.cfg_zone_id] ==
charlesmn	0:3ac96e360672	3342	VL53L1_ZONECONFIG_BINCONFIG__LOWAMB) {
charlesmn	0:3ac96e360672	3343	if (!next_range_is_odd_timing) {
charlesmn	0:3ac96e360672	3344	trace_print (VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3345	" HISTBINCONFIGUPDATE: Setting LOWAMB EVEN timing\n");
charlesmn	0:3ac96e360672	3346	phist_cfg->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	3347	pmulti_hist->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3348	phist_cfg->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	3349	pmulti_hist->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3350	phist_cfg->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	3351	pmulti_hist->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3352	}
charlesmn	0:3ac96e360672	3353
charlesmn	0:3ac96e360672	3354	if (next_range_is_odd_timing) {
charlesmn	0:3ac96e360672	3355	trace_print (VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3356	" HISTBINCONFIGUPDATE: Setting LOWAMB ODD timing\n");
charlesmn	0:3ac96e360672	3357	phist_cfg->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	3358	pmulti_hist->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3359	phist_cfg->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	3360	pmulti_hist->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3361	phist_cfg->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	3362	pmulti_hist->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3363	}
charlesmn	0:3ac96e360672	3364	} else if (pzone_cfg->bin_config[pdev->ll_state.cfg_zone_id] ==
charlesmn	0:3ac96e360672	3365	VL53L1_ZONECONFIG_BINCONFIG__MIDAMB) {
charlesmn	0:3ac96e360672	3366	trace_print (VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3367	" HISTBINCONFIGUPDATE: Setting MIDAMB timing\n");
charlesmn	0:3ac96e360672	3368	if (!next_range_is_odd_timing) {
charlesmn	0:3ac96e360672	3369	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3370	" HISTBINCONFIGUPDATE: Setting MIDAMB EVEN timing\n");
charlesmn	0:3ac96e360672	3371	phist_cfg->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	3372	pmulti_hist->histogram_config__mid_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3373	phist_cfg->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	3374	pmulti_hist->histogram_config__mid_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3375	phist_cfg->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	3376	pmulti_hist->histogram_config__mid_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3377	}
charlesmn	0:3ac96e360672	3378
charlesmn	0:3ac96e360672	3379	if (next_range_is_odd_timing) {
charlesmn	0:3ac96e360672	3380	trace_print (VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3381	" HISTBINCONFIGUPDATE: Setting MIDAMB ODD timing\n");
charlesmn	0:3ac96e360672	3382	phist_cfg->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	3383	pmulti_hist->histogram_config__mid_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3384	phist_cfg->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	3385	pmulti_hist->histogram_config__mid_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3386	phist_cfg->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	3387	pmulti_hist->histogram_config__mid_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3388	}
charlesmn	0:3ac96e360672	3389	} else if (pzone_cfg->bin_config[pdev->ll_state.cfg_zone_id] ==
charlesmn	0:3ac96e360672	3390	VL53L1_ZONECONFIG_BINCONFIG__HIGHAMB) {
charlesmn	0:3ac96e360672	3391	if (!next_range_is_odd_timing) {
charlesmn	0:3ac96e360672	3392	trace_print (VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3393	" HISTBINCONFIGUPDATE: Setting HIGHAMB EVEN timing\n"
charlesmn	0:3ac96e360672	3394	);
charlesmn	0:3ac96e360672	3395	phist_cfg->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	3396	pmulti_hist->histogram_config__high_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3397	phist_cfg->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	3398	pmulti_hist->histogram_config__high_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3399	phist_cfg->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	3400	pmulti_hist->histogram_config__high_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3401	}
charlesmn	0:3ac96e360672	3402
charlesmn	0:3ac96e360672	3403	if (next_range_is_odd_timing) {
charlesmn	0:3ac96e360672	3404	trace_print (VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3405	" HISTBINCONFIGUPDATE: Setting HIGHAMB ODD timing\n");
charlesmn	0:3ac96e360672	3406	phist_cfg->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	3407	pmulti_hist->histogram_config__high_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3408	phist_cfg->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	3409	pmulti_hist->histogram_config__high_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3410	phist_cfg->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	3411	pmulti_hist->histogram_config__high_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3412	}
charlesmn	0:3ac96e360672	3413	}
charlesmn	0:3ac96e360672	3414
charlesmn	0:3ac96e360672	3415
charlesmn	0:3ac96e360672	3416
charlesmn	0:3ac96e360672	3417	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	3418	VL53L1_copy_hist_bins_to_static_cfg(
charlesmn	0:3ac96e360672	3419	phist_cfg,
charlesmn	0:3ac96e360672	3420	&(pdev->stat_cfg),
charlesmn	0:3ac96e360672	3421	&(pdev->tim_cfg));
charlesmn	0:3ac96e360672	3422	}
charlesmn	0:3ac96e360672	3423
charlesmn	0:3ac96e360672	3424	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3425
charlesmn	0:3ac96e360672	3426	return status;
charlesmn	0:3ac96e360672	3427	}
charlesmn	0:3ac96e360672	3428
charlesmn	0:3ac96e360672	3429
charlesmn	0:3ac96e360672	3430
charlesmn	0:3ac96e360672	3431	VL53L1_Error VL53L1_update_internal_stream_counters(
charlesmn	0:3ac96e360672	3432	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3433	uint8_t external_stream_count,
charlesmn	0:3ac96e360672	3434	uint8_t *pinternal_stream_count,
charlesmn	0:3ac96e360672	3435	uint8_t *pinternal_stream_count_val)
charlesmn	0:3ac96e360672	3436	{
charlesmn	0:3ac96e360672	3437
charlesmn	0:3ac96e360672	3438	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3439	uint8_t stream_divider;
charlesmn	0:3ac96e360672	3440
charlesmn	0:3ac96e360672	3441	VL53L1_LLDriverData_t *pdev =
charlesmn	0:3ac96e360672	3442	VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3443
charlesmn	0:3ac96e360672	3444	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3445
charlesmn	0:3ac96e360672	3446	stream_divider = pdev->gen_cfg.global_config__stream_divider;
charlesmn	0:3ac96e360672	3447
charlesmn	0:3ac96e360672	3448	if (stream_divider == 0) {
charlesmn	0:3ac96e360672	3449
charlesmn	0:3ac96e360672	3450
charlesmn	0:3ac96e360672	3451	*pinternal_stream_count = external_stream_count;
charlesmn	0:3ac96e360672	3452
charlesmn	0:3ac96e360672	3453	} else if (*pinternal_stream_count_val == (stream_divider-1)) {
charlesmn	0:3ac96e360672	3454
charlesmn	0:3ac96e360672	3455
charlesmn	0:3ac96e360672	3456	if (*pinternal_stream_count == 0xFF)
charlesmn	0:3ac96e360672	3457	*pinternal_stream_count = 0x80;
charlesmn	0:3ac96e360672	3458	else
charlesmn	0:3ac96e360672	3459	pinternal_stream_count = pinternal_stream_count + 1;
charlesmn	0:3ac96e360672	3460
charlesmn	0:3ac96e360672	3461
charlesmn	0:3ac96e360672	3462	*pinternal_stream_count_val = 0;
charlesmn	0:3ac96e360672	3463
charlesmn	0:3ac96e360672	3464	} else {
charlesmn	0:3ac96e360672	3465
charlesmn	0:3ac96e360672	3466
charlesmn	0:3ac96e360672	3467	pinternal_stream_count_val = pinternal_stream_count_val + 1;
charlesmn	0:3ac96e360672	3468	}
charlesmn	0:3ac96e360672	3469
charlesmn	0:3ac96e360672	3470	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3471	"UPDINTSTREAMCOUNT internal_steam_count: %d,",
charlesmn	0:3ac96e360672	3472	*pinternal_stream_count);
charlesmn	0:3ac96e360672	3473
charlesmn	0:3ac96e360672	3474	trace_print(VL53L1_TRACE_LEVEL_DEBUG,
charlesmn	0:3ac96e360672	3475	"internal_stream_count_val: %d, divider: %d\n",
charlesmn	0:3ac96e360672	3476	*pinternal_stream_count_val,
charlesmn	0:3ac96e360672	3477	stream_divider);
charlesmn	0:3ac96e360672	3478
charlesmn	0:3ac96e360672	3479	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3480
charlesmn	0:3ac96e360672	3481	return status;
charlesmn	0:3ac96e360672	3482	}
charlesmn	0:3ac96e360672	3483
charlesmn	0:3ac96e360672	3484
charlesmn	0:3ac96e360672	3485
charlesmn	0:3ac96e360672	3486	VL53L1_Error VL53L1_set_histogram_multizone_initial_bin_config(
charlesmn	0:3ac96e360672	3487	VL53L1_zone_config_t *pzone_cfg,
charlesmn	0:3ac96e360672	3488	VL53L1_histogram_config_t *phist_cfg,
charlesmn	0:3ac96e360672	3489	VL53L1_histogram_config_t *pmulti_hist)
charlesmn	0:3ac96e360672	3490	{
charlesmn	0:3ac96e360672	3491	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3492
charlesmn	0:3ac96e360672	3493	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3494
charlesmn	0:3ac96e360672	3495
charlesmn	0:3ac96e360672	3496	if (pzone_cfg->bin_config[0] ==
charlesmn	0:3ac96e360672	3497	VL53L1_ZONECONFIG_BINCONFIG__LOWAMB) {
charlesmn	0:3ac96e360672	3498	phist_cfg->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	3499	pmulti_hist->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3500	phist_cfg->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	3501	pmulti_hist->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3502	phist_cfg->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	3503	pmulti_hist->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3504
charlesmn	0:3ac96e360672	3505	phist_cfg->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	3506	pmulti_hist->histogram_config__low_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3507	phist_cfg->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	3508	pmulti_hist->histogram_config__low_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3509	phist_cfg->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	3510	pmulti_hist->histogram_config__low_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3511	} else if (pzone_cfg->bin_config[0] ==
charlesmn	0:3ac96e360672	3512	VL53L1_ZONECONFIG_BINCONFIG__MIDAMB) {
charlesmn	0:3ac96e360672	3513	phist_cfg->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	3514	pmulti_hist->histogram_config__mid_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3515	phist_cfg->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	3516	pmulti_hist->histogram_config__mid_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3517	phist_cfg->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	3518	pmulti_hist->histogram_config__mid_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3519
charlesmn	0:3ac96e360672	3520	phist_cfg->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	3521	pmulti_hist->histogram_config__mid_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3522	phist_cfg->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	3523	pmulti_hist->histogram_config__mid_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3524	phist_cfg->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	3525	pmulti_hist->histogram_config__mid_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3526	} else if (pzone_cfg->bin_config[0] ==
charlesmn	0:3ac96e360672	3527	VL53L1_ZONECONFIG_BINCONFIG__HIGHAMB) {
charlesmn	0:3ac96e360672	3528	phist_cfg->histogram_config__low_amb_even_bin_0_1 =
charlesmn	0:3ac96e360672	3529	pmulti_hist->histogram_config__high_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3530	phist_cfg->histogram_config__low_amb_even_bin_2_3 =
charlesmn	0:3ac96e360672	3531	pmulti_hist->histogram_config__high_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3532	phist_cfg->histogram_config__low_amb_even_bin_4_5 =
charlesmn	0:3ac96e360672	3533	pmulti_hist->histogram_config__high_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3534	phist_cfg->histogram_config__low_amb_odd_bin_0_1 =
charlesmn	0:3ac96e360672	3535	pmulti_hist->histogram_config__high_amb_even_bin_0_1;
charlesmn	0:3ac96e360672	3536	phist_cfg->histogram_config__low_amb_odd_bin_2_3 =
charlesmn	0:3ac96e360672	3537	pmulti_hist->histogram_config__high_amb_even_bin_2_3;
charlesmn	0:3ac96e360672	3538	phist_cfg->histogram_config__low_amb_odd_bin_4_5 =
charlesmn	0:3ac96e360672	3539	pmulti_hist->histogram_config__high_amb_even_bin_4_5;
charlesmn	0:3ac96e360672	3540	}
charlesmn	0:3ac96e360672	3541
charlesmn	0:3ac96e360672	3542	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3543	return status;
charlesmn	0:3ac96e360672	3544	}
charlesmn	0:3ac96e360672	3545
charlesmn	0:3ac96e360672	3546
charlesmn	0:3ac96e360672	3547
charlesmn	0:3ac96e360672	3548	uint8_t VL53L1_encode_GPIO_interrupt_config(
charlesmn	0:3ac96e360672	3549	VL53L1_GPIO_interrupt_config_t *pintconf)
charlesmn	0:3ac96e360672	3550	{
charlesmn	0:3ac96e360672	3551	uint8_t system__interrupt_config;
charlesmn	0:3ac96e360672	3552
charlesmn	0:3ac96e360672	3553	system__interrupt_config = pintconf->intr_mode_distance;
charlesmn	0:3ac96e360672	3554	system__interrupt_config \|= ((pintconf->intr_mode_rate) << 2);
charlesmn	0:3ac96e360672	3555	system__interrupt_config \|= ((pintconf->intr_new_measure_ready) << 5);
charlesmn	0:3ac96e360672	3556	system__interrupt_config \|= ((pintconf->intr_no_target) << 6);
charlesmn	0:3ac96e360672	3557	system__interrupt_config \|= ((pintconf->intr_combined_mode) << 7);
charlesmn	0:3ac96e360672	3558
charlesmn	0:3ac96e360672	3559	return system__interrupt_config;
charlesmn	0:3ac96e360672	3560	}
charlesmn	0:3ac96e360672	3561
charlesmn	0:3ac96e360672	3562
charlesmn	0:3ac96e360672	3563
charlesmn	0:3ac96e360672	3564	VL53L1_GPIO_interrupt_config_t VL53L1_decode_GPIO_interrupt_config(
charlesmn	0:3ac96e360672	3565	uint8_t system__interrupt_config)
charlesmn	0:3ac96e360672	3566	{
charlesmn	0:3ac96e360672	3567	VL53L1_GPIO_interrupt_config_t intconf;
charlesmn	0:3ac96e360672	3568
charlesmn	0:3ac96e360672	3569	intconf.intr_mode_distance = system__interrupt_config & 0x03;
charlesmn	0:3ac96e360672	3570	intconf.intr_mode_rate = (system__interrupt_config >> 2) & 0x03;
charlesmn	0:3ac96e360672	3571	intconf.intr_new_measure_ready = (system__interrupt_config >> 5) & 0x01;
charlesmn	0:3ac96e360672	3572	intconf.intr_no_target = (system__interrupt_config >> 6) & 0x01;
charlesmn	0:3ac96e360672	3573	intconf.intr_combined_mode = (system__interrupt_config >> 7) & 0x01;
charlesmn	0:3ac96e360672	3574
charlesmn	0:3ac96e360672	3575
charlesmn	0:3ac96e360672	3576	intconf.threshold_rate_low = 0;
charlesmn	0:3ac96e360672	3577	intconf.threshold_rate_high = 0;
charlesmn	0:3ac96e360672	3578	intconf.threshold_distance_low = 0;
charlesmn	0:3ac96e360672	3579	intconf.threshold_distance_high = 0;
charlesmn	0:3ac96e360672	3580
charlesmn	0:3ac96e360672	3581	return intconf;
charlesmn	0:3ac96e360672	3582	}
charlesmn	0:3ac96e360672	3583
charlesmn	0:3ac96e360672	3584
charlesmn	0:3ac96e360672	3585
charlesmn	0:3ac96e360672	3586	VL53L1_Error VL53L1_set_GPIO_distance_threshold(
charlesmn	0:3ac96e360672	3587	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3588	uint16_t threshold_high,
charlesmn	0:3ac96e360672	3589	uint16_t threshold_low)
charlesmn	0:3ac96e360672	3590	{
charlesmn	0:3ac96e360672	3591	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3592
charlesmn	0:3ac96e360672	3593	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3594
charlesmn	0:3ac96e360672	3595	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3596
charlesmn	0:3ac96e360672	3597	pdev->dyn_cfg.system__thresh_high = threshold_high;
charlesmn	0:3ac96e360672	3598	pdev->dyn_cfg.system__thresh_low = threshold_low;
charlesmn	0:3ac96e360672	3599
charlesmn	0:3ac96e360672	3600	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3601	return status;
charlesmn	0:3ac96e360672	3602	}
charlesmn	0:3ac96e360672	3603
charlesmn	0:3ac96e360672	3604
charlesmn	0:3ac96e360672	3605
charlesmn	0:3ac96e360672	3606	VL53L1_Error VL53L1_set_GPIO_rate_threshold(
charlesmn	0:3ac96e360672	3607	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3608	uint16_t threshold_high,
charlesmn	0:3ac96e360672	3609	uint16_t threshold_low)
charlesmn	0:3ac96e360672	3610	{
charlesmn	0:3ac96e360672	3611	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3612
charlesmn	0:3ac96e360672	3613	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3614
charlesmn	0:3ac96e360672	3615	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3616
charlesmn	0:3ac96e360672	3617	pdev->gen_cfg.system__thresh_rate_high = threshold_high;
charlesmn	0:3ac96e360672	3618	pdev->gen_cfg.system__thresh_rate_low = threshold_low;
charlesmn	0:3ac96e360672	3619
charlesmn	0:3ac96e360672	3620	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3621	return status;
charlesmn	0:3ac96e360672	3622	}
charlesmn	0:3ac96e360672	3623
charlesmn	0:3ac96e360672	3624
charlesmn	0:3ac96e360672	3625
charlesmn	0:3ac96e360672	3626	VL53L1_Error VL53L1_set_GPIO_thresholds_from_struct(
charlesmn	0:3ac96e360672	3627	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3628	VL53L1_GPIO_interrupt_config_t *pintconf)
charlesmn	0:3ac96e360672	3629	{
charlesmn	0:3ac96e360672	3630	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3631
charlesmn	0:3ac96e360672	3632	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3633
charlesmn	0:3ac96e360672	3634	status = VL53L1_set_GPIO_distance_threshold(
charlesmn	0:3ac96e360672	3635	Dev,
charlesmn	0:3ac96e360672	3636	pintconf->threshold_distance_high,
charlesmn	0:3ac96e360672	3637	pintconf->threshold_distance_low);
charlesmn	0:3ac96e360672	3638
charlesmn	0:3ac96e360672	3639	if (status == VL53L1_ERROR_NONE) {
charlesmn	0:3ac96e360672	3640	status =
charlesmn	0:3ac96e360672	3641	VL53L1_set_GPIO_rate_threshold(
charlesmn	0:3ac96e360672	3642	Dev,
charlesmn	0:3ac96e360672	3643	pintconf->threshold_rate_high,
charlesmn	0:3ac96e360672	3644	pintconf->threshold_rate_low);
charlesmn	0:3ac96e360672	3645	}
charlesmn	0:3ac96e360672	3646
charlesmn	0:3ac96e360672	3647	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3648	return status;
charlesmn	0:3ac96e360672	3649	}
charlesmn	0:3ac96e360672	3650
charlesmn	0:3ac96e360672	3651
charlesmn	0:3ac96e360672	3652	VL53L1_Error VL53L1_set_ref_spad_char_config(
charlesmn	0:3ac96e360672	3653	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3654	uint8_t vcsel_period_a,
charlesmn	0:3ac96e360672	3655	uint32_t phasecal_timeout_us,
charlesmn	0:3ac96e360672	3656	uint16_t total_rate_target_mcps,
charlesmn	0:3ac96e360672	3657	uint16_t max_count_rate_rtn_limit_mcps,
charlesmn	0:3ac96e360672	3658	uint16_t min_count_rate_rtn_limit_mcps,
charlesmn	0:3ac96e360672	3659	uint16_t fast_osc_frequency)
charlesmn	0:3ac96e360672	3660	{
charlesmn	0:3ac96e360672	3661
charlesmn	0:3ac96e360672	3662
charlesmn	0:3ac96e360672	3663	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3664	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3665
charlesmn	0:3ac96e360672	3666	uint8_t buffer[2];
charlesmn	0:3ac96e360672	3667
charlesmn	0:3ac96e360672	3668	uint32_t macro_period_us = 0;
charlesmn	0:3ac96e360672	3669	uint32_t timeout_mclks = 0;
charlesmn	0:3ac96e360672	3670
charlesmn	0:3ac96e360672	3671	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3672
charlesmn	0:3ac96e360672	3673
charlesmn	0:3ac96e360672	3674	macro_period_us =
charlesmn	0:3ac96e360672	3675	VL53L1_calc_macro_period_us(
charlesmn	0:3ac96e360672	3676	fast_osc_frequency,
charlesmn	0:3ac96e360672	3677	vcsel_period_a);
charlesmn	0:3ac96e360672	3678
charlesmn	0:3ac96e360672	3679
charlesmn	0:3ac96e360672	3680
charlesmn	0:3ac96e360672	3681	timeout_mclks = phasecal_timeout_us << 12;
charlesmn	0:3ac96e360672	3682	timeout_mclks = timeout_mclks + (macro_period_us>>1);
charlesmn	0:3ac96e360672	3683	timeout_mclks = timeout_mclks / macro_period_us;
charlesmn	0:3ac96e360672	3684
charlesmn	0:3ac96e360672	3685	if (timeout_mclks > 0xFF)
charlesmn	0:3ac96e360672	3686	pdev->gen_cfg.phasecal_config__timeout_macrop = 0xFF;
charlesmn	0:3ac96e360672	3687	else
charlesmn	0:3ac96e360672	3688	pdev->gen_cfg.phasecal_config__timeout_macrop =
charlesmn	0:3ac96e360672	3689	(uint8_t)timeout_mclks;
charlesmn	0:3ac96e360672	3690
charlesmn	0:3ac96e360672	3691	pdev->tim_cfg.range_config__vcsel_period_a = vcsel_period_a;
charlesmn	0:3ac96e360672	3692
charlesmn	0:3ac96e360672	3693
charlesmn	0:3ac96e360672	3694
charlesmn	0:3ac96e360672	3695	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3696	status =
charlesmn	0:3ac96e360672	3697	VL53L1_WrByte(
charlesmn	0:3ac96e360672	3698	Dev,
charlesmn	0:3ac96e360672	3699	VL53L1_PHASECAL_CONFIG__TIMEOUT_MACROP,
charlesmn	0:3ac96e360672	3700	pdev->gen_cfg.phasecal_config__timeout_macrop);
charlesmn	0:3ac96e360672	3701
charlesmn	0:3ac96e360672	3702	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3703	status =
charlesmn	0:3ac96e360672	3704	VL53L1_WrByte(
charlesmn	0:3ac96e360672	3705	Dev,
charlesmn	0:3ac96e360672	3706	VL53L1_RANGE_CONFIG__VCSEL_PERIOD_A,
charlesmn	0:3ac96e360672	3707	pdev->tim_cfg.range_config__vcsel_period_a);
charlesmn	0:3ac96e360672	3708
charlesmn	0:3ac96e360672	3709
charlesmn	0:3ac96e360672	3710
charlesmn	0:3ac96e360672	3711	buffer[0] = pdev->tim_cfg.range_config__vcsel_period_a;
charlesmn	0:3ac96e360672	3712	buffer[1] = pdev->tim_cfg.range_config__vcsel_period_a;
charlesmn	0:3ac96e360672	3713
charlesmn	0:3ac96e360672	3714	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3715	status =
charlesmn	0:3ac96e360672	3716	VL53L1_WriteMulti(
charlesmn	0:3ac96e360672	3717	Dev,
charlesmn	0:3ac96e360672	3718	VL53L1_SD_CONFIG__WOI_SD0,
charlesmn	0:3ac96e360672	3719	buffer,
charlesmn	0:3ac96e360672	3720	2);
charlesmn	0:3ac96e360672	3721
charlesmn	0:3ac96e360672	3722
charlesmn	0:3ac96e360672	3723
charlesmn	0:3ac96e360672	3724	pdev->customer.ref_spad_char__total_rate_target_mcps =
charlesmn	0:3ac96e360672	3725	total_rate_target_mcps;
charlesmn	0:3ac96e360672	3726
charlesmn	0:3ac96e360672	3727	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3728	status =
charlesmn	0:3ac96e360672	3729	VL53L1_WrWord(
charlesmn	0:3ac96e360672	3730	Dev,
charlesmn	0:3ac96e360672	3731	VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS,
charlesmn	0:3ac96e360672	3732	total_rate_target_mcps);
charlesmn	0:3ac96e360672	3733
charlesmn	0:3ac96e360672	3734	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3735	status =
charlesmn	0:3ac96e360672	3736	VL53L1_WrWord(
charlesmn	0:3ac96e360672	3737	Dev,
charlesmn	0:3ac96e360672	3738	VL53L1_RANGE_CONFIG__SIGMA_THRESH,
charlesmn	0:3ac96e360672	3739	max_count_rate_rtn_limit_mcps);
charlesmn	0:3ac96e360672	3740
charlesmn	0:3ac96e360672	3741	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3742	status =
charlesmn	0:3ac96e360672	3743	VL53L1_WrWord(
charlesmn	0:3ac96e360672	3744	Dev,
charlesmn	0:3ac96e360672	3745	VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS,
charlesmn	0:3ac96e360672	3746	min_count_rate_rtn_limit_mcps);
charlesmn	0:3ac96e360672	3747
charlesmn	0:3ac96e360672	3748	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3749
charlesmn	0:3ac96e360672	3750	return status;
charlesmn	0:3ac96e360672	3751	}
charlesmn	0:3ac96e360672	3752
charlesmn	0:3ac96e360672	3753
charlesmn	0:3ac96e360672	3754	VL53L1_Error VL53L1_set_ssc_config(
charlesmn	0:3ac96e360672	3755	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3756	VL53L1_ssc_config_t *pssc_cfg,
charlesmn	0:3ac96e360672	3757	uint16_t fast_osc_frequency)
charlesmn	0:3ac96e360672	3758	{
charlesmn	0:3ac96e360672	3759
charlesmn	0:3ac96e360672	3760
charlesmn	0:3ac96e360672	3761	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3762	uint8_t buffer[5];
charlesmn	0:3ac96e360672	3763
charlesmn	0:3ac96e360672	3764	uint32_t macro_period_us = 0;
charlesmn	0:3ac96e360672	3765	uint16_t timeout_encoded = 0;
charlesmn	0:3ac96e360672	3766
charlesmn	0:3ac96e360672	3767	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3768
charlesmn	0:3ac96e360672	3769
charlesmn	0:3ac96e360672	3770	macro_period_us =
charlesmn	0:3ac96e360672	3771	VL53L1_calc_macro_period_us(
charlesmn	0:3ac96e360672	3772	fast_osc_frequency,
charlesmn	0:3ac96e360672	3773	pssc_cfg->VL53L1_p_009);
charlesmn	0:3ac96e360672	3774
charlesmn	0:3ac96e360672	3775
charlesmn	0:3ac96e360672	3776	timeout_encoded =
charlesmn	0:3ac96e360672	3777	VL53L1_calc_encoded_timeout(
charlesmn	0:3ac96e360672	3778	pssc_cfg->timeout_us,
charlesmn	0:3ac96e360672	3779	macro_period_us);
charlesmn	0:3ac96e360672	3780
charlesmn	0:3ac96e360672	3781
charlesmn	0:3ac96e360672	3782
charlesmn	0:3ac96e360672	3783	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3784	status =
charlesmn	0:3ac96e360672	3785	VL53L1_WrByte(
charlesmn	0:3ac96e360672	3786	Dev,
charlesmn	0:3ac96e360672	3787	VL53L1_CAL_CONFIG__VCSEL_START,
charlesmn	0:3ac96e360672	3788	pssc_cfg->vcsel_start);
charlesmn	0:3ac96e360672	3789
charlesmn	0:3ac96e360672	3790	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3791	status =
charlesmn	0:3ac96e360672	3792	VL53L1_WrByte(
charlesmn	0:3ac96e360672	3793	Dev,
charlesmn	0:3ac96e360672	3794	VL53L1_GLOBAL_CONFIG__VCSEL_WIDTH,
charlesmn	0:3ac96e360672	3795	pssc_cfg->vcsel_width);
charlesmn	0:3ac96e360672	3796
charlesmn	0:3ac96e360672	3797
charlesmn	0:3ac96e360672	3798
charlesmn	0:3ac96e360672	3799	buffer[0] = (uint8_t)((timeout_encoded & 0x0000FF00) >> 8);
charlesmn	0:3ac96e360672	3800	buffer[1] = (uint8_t) (timeout_encoded & 0x000000FF);
charlesmn	0:3ac96e360672	3801	buffer[2] = pssc_cfg->VL53L1_p_009;
charlesmn	0:3ac96e360672	3802	buffer[3] = (uint8_t)((pssc_cfg->rate_limit_mcps & 0x0000FF00) >> 8);
charlesmn	0:3ac96e360672	3803	buffer[4] = (uint8_t) (pssc_cfg->rate_limit_mcps & 0x000000FF);
charlesmn	0:3ac96e360672	3804
charlesmn	0:3ac96e360672	3805	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3806	status =
charlesmn	0:3ac96e360672	3807	VL53L1_WriteMulti(
charlesmn	0:3ac96e360672	3808	Dev,
charlesmn	0:3ac96e360672	3809	VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_HI,
charlesmn	0:3ac96e360672	3810	buffer,
charlesmn	0:3ac96e360672	3811	5);
charlesmn	0:3ac96e360672	3812
charlesmn	0:3ac96e360672	3813
charlesmn	0:3ac96e360672	3814
charlesmn	0:3ac96e360672	3815	buffer[0] = pssc_cfg->VL53L1_p_009;
charlesmn	0:3ac96e360672	3816	buffer[1] = pssc_cfg->VL53L1_p_009;
charlesmn	0:3ac96e360672	3817
charlesmn	0:3ac96e360672	3818	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3819	status =
charlesmn	0:3ac96e360672	3820	VL53L1_WriteMulti(
charlesmn	0:3ac96e360672	3821	Dev,
charlesmn	0:3ac96e360672	3822	VL53L1_SD_CONFIG__WOI_SD0,
charlesmn	0:3ac96e360672	3823	buffer,
charlesmn	0:3ac96e360672	3824	2);
charlesmn	0:3ac96e360672	3825
charlesmn	0:3ac96e360672	3826
charlesmn	0:3ac96e360672	3827	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3828	status =
charlesmn	0:3ac96e360672	3829	VL53L1_WrByte(
charlesmn	0:3ac96e360672	3830	Dev,
charlesmn	0:3ac96e360672	3831	VL53L1_NVM_BIST__CTRL,
charlesmn	0:3ac96e360672	3832	pssc_cfg->array_select);
charlesmn	0:3ac96e360672	3833
charlesmn	0:3ac96e360672	3834	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3835
charlesmn	0:3ac96e360672	3836	return status;
charlesmn	0:3ac96e360672	3837	}
charlesmn	0:3ac96e360672	3838
charlesmn	0:3ac96e360672	3839
charlesmn	0:3ac96e360672	3840	VL53L1_Error VL53L1_get_spad_rate_data(
charlesmn	0:3ac96e360672	3841	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3842	VL53L1_spad_rate_data_t *pspad_rates)
charlesmn	0:3ac96e360672	3843	{
charlesmn	0:3ac96e360672	3844
charlesmn	0:3ac96e360672	3845
charlesmn	0:3ac96e360672	3846
charlesmn	0:3ac96e360672	3847	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3848	int i = 0;
charlesmn	0:3ac96e360672	3849
charlesmn	0:3ac96e360672	3850	uint8_t VL53L1_p_002[512];
charlesmn	0:3ac96e360672	3851	uint8_t *pdata = &VL53L1_p_002[0];
charlesmn	0:3ac96e360672	3852
charlesmn	0:3ac96e360672	3853	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3854
charlesmn	0:3ac96e360672	3855
charlesmn	0:3ac96e360672	3856
charlesmn	0:3ac96e360672	3857	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3858	status = VL53L1_disable_firmware(Dev);
charlesmn	0:3ac96e360672	3859
charlesmn	0:3ac96e360672	3860
charlesmn	0:3ac96e360672	3861
charlesmn	0:3ac96e360672	3862	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3863	status =
charlesmn	0:3ac96e360672	3864	VL53L1_ReadMulti(
charlesmn	0:3ac96e360672	3865	Dev,
charlesmn	0:3ac96e360672	3866	VL53L1_PRIVATE__PATCH_BASE_ADDR_RSLV,
charlesmn	0:3ac96e360672	3867	pdata,
charlesmn	0:3ac96e360672	3868	512);
charlesmn	0:3ac96e360672	3869
charlesmn	0:3ac96e360672	3870
charlesmn	0:3ac96e360672	3871	pdata = &VL53L1_p_002[0];
charlesmn	0:3ac96e360672	3872	for (i = 0; i < VL53L1_NO_OF_SPAD_ENABLES; i++) {
charlesmn	0:3ac96e360672	3873	pspad_rates->rate_data[i] =
charlesmn	0:3ac96e360672	3874	(uint16_t)VL53L1_decode_unsigned_integer(pdata, 2);
charlesmn	0:3ac96e360672	3875	pdata += 2;
charlesmn	0:3ac96e360672	3876	}
charlesmn	0:3ac96e360672	3877
charlesmn	0:3ac96e360672	3878
charlesmn	0:3ac96e360672	3879
charlesmn	0:3ac96e360672	3880	pspad_rates->VL53L1_p_023 = VL53L1_NO_OF_SPAD_ENABLES;
charlesmn	0:3ac96e360672	3881	pspad_rates->no_of_values = VL53L1_NO_OF_SPAD_ENABLES;
charlesmn	0:3ac96e360672	3882	pspad_rates->fractional_bits = 15;
charlesmn	0:3ac96e360672	3883
charlesmn	0:3ac96e360672	3884
charlesmn	0:3ac96e360672	3885
charlesmn	0:3ac96e360672	3886	if (status == VL53L1_ERROR_NONE)
charlesmn	0:3ac96e360672	3887	status = VL53L1_enable_firmware(Dev);
charlesmn	0:3ac96e360672	3888
charlesmn	0:3ac96e360672	3889	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3890
charlesmn	0:3ac96e360672	3891	return status;
charlesmn	0:3ac96e360672	3892	}
charlesmn	0:3ac96e360672	3893
charlesmn	0:3ac96e360672	3894
charlesmn	0:3ac96e360672	3895
charlesmn	0:3ac96e360672	3896	VL53L1_Error VL53L1_dynamic_xtalk_correction_calc_required_samples(
charlesmn	0:3ac96e360672	3897	VL53L1_DEV Dev
charlesmn	0:3ac96e360672	3898	)
charlesmn	0:3ac96e360672	3899	{
charlesmn	0:3ac96e360672	3900
charlesmn	0:3ac96e360672	3901
charlesmn	0:3ac96e360672	3902
charlesmn	0:3ac96e360672	3903	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3904
charlesmn	0:3ac96e360672	3905	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3906	VL53L1_LLDriverResults_t *pres = VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	3907	VL53L1_smudge_corrector_config_t *pconfig =
charlesmn	0:3ac96e360672	3908	&(pdev->smudge_correct_config);
charlesmn	0:3ac96e360672	3909	VL53L1_smudge_corrector_internals_t *pint =
charlesmn	0:3ac96e360672	3910	&(pdev->smudge_corrector_internals);
charlesmn	0:3ac96e360672	3911
charlesmn	0:3ac96e360672	3912	VL53L1_range_results_t *presults = &(pres->range_results);
charlesmn	0:3ac96e360672	3913	VL53L1_range_data_t *pxmonitor = &(presults->xmonitor);
charlesmn	0:3ac96e360672	3914
charlesmn	0:3ac96e360672	3915	uint32_t peak_duration_us = pxmonitor->peak_duration_us;
charlesmn	0:3ac96e360672	3916
charlesmn	0:3ac96e360672	3917	uint64_t temp64a;
charlesmn	0:3ac96e360672	3918	uint64_t temp64z;
charlesmn	0:3ac96e360672	3919
charlesmn	0:3ac96e360672	3920	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3921
charlesmn	0:3ac96e360672	3922	if (peak_duration_us == 0)
charlesmn	0:3ac96e360672	3923	peak_duration_us = 1000;
charlesmn	0:3ac96e360672	3924
charlesmn	0:3ac96e360672	3925	temp64a = pxmonitor->VL53L1_p_021 +
charlesmn	0:3ac96e360672	3926	pxmonitor->VL53L1_p_020;
charlesmn	0:3ac96e360672	3927	temp64a = do_division_u((temp64a * 1000), peak_duration_us);
charlesmn	0:3ac96e360672	3928	temp64a = do_division_u((temp64a * 1000), peak_duration_us);
charlesmn	0:3ac96e360672	3929
charlesmn	0:3ac96e360672	3930	temp64z = pconfig->noise_margin * pxmonitor->VL53L1_p_006;
charlesmn	0:3ac96e360672	3931	if (temp64z == 0)
charlesmn	0:3ac96e360672	3932	temp64z = 1;
charlesmn	0:3ac96e360672	3933	temp64a = temp64a * 1000 * 256;
charlesmn	0:3ac96e360672	3934	temp64a = do_division_u(temp64a, temp64z);
charlesmn	0:3ac96e360672	3935	temp64a = temp64a * 1000 * 256;
charlesmn	0:3ac96e360672	3936	temp64a = do_division_u(temp64a, temp64z);
charlesmn	0:3ac96e360672	3937
charlesmn	0:3ac96e360672	3938	pint->required_samples = (uint32_t)temp64a;
charlesmn	0:3ac96e360672	3939
charlesmn	0:3ac96e360672	3940
charlesmn	0:3ac96e360672	3941	if (pint->required_samples < 2)
charlesmn	0:3ac96e360672	3942	pint->required_samples = 2;
charlesmn	0:3ac96e360672	3943
charlesmn	0:3ac96e360672	3944	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	3945
charlesmn	0:3ac96e360672	3946	return status;
charlesmn	0:3ac96e360672	3947	}
charlesmn	0:3ac96e360672	3948
charlesmn	0:3ac96e360672	3949	VL53L1_Error VL53L1_dynamic_xtalk_correction_calc_new_xtalk(
charlesmn	0:3ac96e360672	3950	VL53L1_DEV Dev,
charlesmn	0:3ac96e360672	3951	uint32_t xtalk_offset_out,
charlesmn	0:3ac96e360672	3952	VL53L1_smudge_corrector_config_t *pconfig,
charlesmn	0:3ac96e360672	3953	VL53L1_smudge_corrector_data_t *pout,
charlesmn	0:3ac96e360672	3954	uint8_t add_smudge,
charlesmn	0:3ac96e360672	3955	uint8_t soft_update
charlesmn	0:3ac96e360672	3956	)
charlesmn	0:3ac96e360672	3957	{
charlesmn	0:3ac96e360672	3958
charlesmn	0:3ac96e360672	3959
charlesmn	0:3ac96e360672	3960
charlesmn	0:3ac96e360672	3961	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	3962	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	3963
charlesmn	0:3ac96e360672	3964	int16_t x_gradient_scaler;
charlesmn	0:3ac96e360672	3965	int16_t y_gradient_scaler;
charlesmn	0:3ac96e360672	3966	uint32_t orig_xtalk_offset;
charlesmn	0:3ac96e360672	3967	int16_t orig_x_gradient;
charlesmn	0:3ac96e360672	3968	int16_t orig_y_gradient;
charlesmn	0:3ac96e360672	3969	uint8_t histo_merge_nb;
charlesmn	0:3ac96e360672	3970	uint8_t i;
charlesmn	0:3ac96e360672	3971	int32_t itemp32;
charlesmn	0:3ac96e360672	3972	uint32_t SmudgeFactor;
charlesmn	0:3ac96e360672	3973	VL53L1_xtalk_config_t *pX = &(pdev->xtalk_cfg);
charlesmn	0:3ac96e360672	3974	VL53L1_xtalk_calibration_results_t *pC = &(pdev->xtalk_cal);
charlesmn	0:3ac96e360672	3975	uint32_t *pcpo;
charlesmn	0:3ac96e360672	3976	uint32_t max, nXtalk, cXtalk;
charlesmn	0:3ac96e360672	3977	uint8_t merge_enabled;
charlesmn	0:3ac96e360672	3978
charlesmn	0:3ac96e360672	3979
charlesmn	0:3ac96e360672	3980	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	3981
charlesmn	0:3ac96e360672	3982	merge_enabled = (pdev->tuning_parms.tp_hist_merge == 1) &&
charlesmn	0:3ac96e360672	3983	(VL53L1DevDataGet(Dev, CurrentParameters.PresetMode) ==
charlesmn	0:3ac96e360672	3984	VL53L1_PRESETMODE_RANGING);
charlesmn	0:3ac96e360672	3985
charlesmn	0:3ac96e360672	3986
charlesmn	0:3ac96e360672	3987	if (add_smudge == 1) {
charlesmn	0:3ac96e360672	3988	pout->algo__crosstalk_compensation_plane_offset_kcps =
charlesmn	0:3ac96e360672	3989	(uint32_t)xtalk_offset_out +
charlesmn	0:3ac96e360672	3990	(uint32_t)pconfig->smudge_margin;
charlesmn	0:3ac96e360672	3991	} else {
charlesmn	0:3ac96e360672	3992	pout->algo__crosstalk_compensation_plane_offset_kcps =
charlesmn	0:3ac96e360672	3993	(uint32_t)xtalk_offset_out;
charlesmn	0:3ac96e360672	3994	}
charlesmn	0:3ac96e360672	3995
charlesmn	0:3ac96e360672	3996
charlesmn	0:3ac96e360672	3997	orig_xtalk_offset =
charlesmn	0:3ac96e360672	3998	pX->nvm_default__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:3ac96e360672	3999
charlesmn	0:3ac96e360672	4000	orig_x_gradient =
charlesmn	0:3ac96e360672	4001	pX->nvm_default__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:3ac96e360672	4002
charlesmn	0:3ac96e360672	4003	orig_y_gradient =
charlesmn	0:3ac96e360672	4004	pX->nvm_default__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:3ac96e360672	4005
charlesmn	0:3ac96e360672	4006	if (((pconfig->user_scaler_set == 0) \|\|
charlesmn	0:3ac96e360672	4007	(pconfig->scaler_calc_method == 1)) &&
charlesmn	0:3ac96e360672	4008	(pC->algo__crosstalk_compensation_plane_offset_kcps != 0)) {
charlesmn	0:3ac96e360672	4009
charlesmn	0:3ac96e360672	4010	VL53L1_compute_histo_merge_nb(Dev, &histo_merge_nb);
charlesmn	0:3ac96e360672	4011	if (histo_merge_nb == 0)
charlesmn	0:3ac96e360672	4012	histo_merge_nb = 1;
charlesmn	0:3ac96e360672	4013	if (!merge_enabled)
charlesmn	0:3ac96e360672	4014	orig_xtalk_offset =
charlesmn	0:3ac96e360672	4015	pC->algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:3ac96e360672	4016	else
charlesmn	0:3ac96e360672	4017	orig_xtalk_offset =
charlesmn	0:3ac96e360672	4018	pC->algo__xtalk_cpo_HistoMerge_kcps[histo_merge_nb-1];
charlesmn	0:3ac96e360672	4019
charlesmn	0:3ac96e360672	4020	orig_x_gradient =
charlesmn	0:3ac96e360672	4021	pC->algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:3ac96e360672	4022
charlesmn	0:3ac96e360672	4023	orig_y_gradient =
charlesmn	0:3ac96e360672	4024	pC->algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:3ac96e360672	4025	}
charlesmn	0:3ac96e360672	4026
charlesmn	0:3ac96e360672	4027
charlesmn	0:3ac96e360672	4028	if ((pconfig->user_scaler_set == 0) && (orig_x_gradient == 0))
charlesmn	0:3ac96e360672	4029	pout->gradient_zero_flag \|= 0x01;
charlesmn	0:3ac96e360672	4030
charlesmn	0:3ac96e360672	4031	if ((pconfig->user_scaler_set == 0) && (orig_y_gradient == 0))
charlesmn	0:3ac96e360672	4032	pout->gradient_zero_flag \|= 0x02;
charlesmn	0:3ac96e360672	4033
charlesmn	0:3ac96e360672	4034
charlesmn	0:3ac96e360672	4035
charlesmn	0:3ac96e360672	4036	if (orig_xtalk_offset == 0)
charlesmn	0:3ac96e360672	4037	orig_xtalk_offset = 1;
charlesmn	0:3ac96e360672	4038
charlesmn	0:3ac96e360672	4039
charlesmn	0:3ac96e360672	4040
charlesmn	0:3ac96e360672	4041	if (pconfig->user_scaler_set == 1) {
charlesmn	0:3ac96e360672	4042	x_gradient_scaler = pconfig->x_gradient_scaler;
charlesmn	0:3ac96e360672	4043	y_gradient_scaler = pconfig->y_gradient_scaler;
charlesmn	0:3ac96e360672	4044	} else {
charlesmn	0:3ac96e360672	4045
charlesmn	0:3ac96e360672	4046	x_gradient_scaler = (int16_t)do_division_s(
charlesmn	0:3ac96e360672	4047	(((int32_t)orig_x_gradient) << 6),
charlesmn	0:3ac96e360672	4048	orig_xtalk_offset);
charlesmn	0:3ac96e360672	4049	pconfig->x_gradient_scaler = x_gradient_scaler;
charlesmn	0:3ac96e360672	4050	y_gradient_scaler = (int16_t)do_division_s(
charlesmn	0:3ac96e360672	4051	(((int32_t)orig_y_gradient) << 6),
charlesmn	0:3ac96e360672	4052	orig_xtalk_offset);
charlesmn	0:3ac96e360672	4053	pconfig->y_gradient_scaler = y_gradient_scaler;
charlesmn	0:3ac96e360672	4054	}
charlesmn	0:3ac96e360672	4055
charlesmn	0:3ac96e360672	4056
charlesmn	0:3ac96e360672	4057
charlesmn	0:3ac96e360672	4058	if (pconfig->scaler_calc_method == 0) {
charlesmn	0:3ac96e360672	4059
charlesmn	0:3ac96e360672	4060
charlesmn	0:3ac96e360672	4061	itemp32 = (int32_t)(
charlesmn	0:3ac96e360672	4062	pout->algo__crosstalk_compensation_plane_offset_kcps *
charlesmn	0:3ac96e360672	4063	x_gradient_scaler);
charlesmn	0:3ac96e360672	4064	itemp32 = itemp32 >> 6;
charlesmn	0:3ac96e360672	4065	if (itemp32 > 0xFFFF)
charlesmn	0:3ac96e360672	4066	itemp32 = 0xFFFF;
charlesmn	0:3ac96e360672	4067
charlesmn	0:3ac96e360672	4068	pout->algo__crosstalk_compensation_x_plane_gradient_kcps =
charlesmn	0:3ac96e360672	4069	(int16_t)itemp32;
charlesmn	0:3ac96e360672	4070
charlesmn	0:3ac96e360672	4071	itemp32 = (int32_t)(
charlesmn	0:3ac96e360672	4072	pout->algo__crosstalk_compensation_plane_offset_kcps *
charlesmn	0:3ac96e360672	4073	y_gradient_scaler);
charlesmn	0:3ac96e360672	4074	itemp32 = itemp32 >> 6;
charlesmn	0:3ac96e360672	4075	if (itemp32 > 0xFFFF)
charlesmn	0:3ac96e360672	4076	itemp32 = 0xFFFF;
charlesmn	0:3ac96e360672	4077
charlesmn	0:3ac96e360672	4078	pout->algo__crosstalk_compensation_y_plane_gradient_kcps =
charlesmn	0:3ac96e360672	4079	(int16_t)itemp32;
charlesmn	0:3ac96e360672	4080	} else if (pconfig->scaler_calc_method == 1) {
charlesmn	0:3ac96e360672	4081
charlesmn	0:3ac96e360672	4082
charlesmn	0:3ac96e360672	4083	itemp32 = (int32_t)(orig_xtalk_offset -
charlesmn	0:3ac96e360672	4084	pout->algo__crosstalk_compensation_plane_offset_kcps);
charlesmn	0:3ac96e360672	4085	itemp32 = (int32_t)(do_division_s(itemp32, 16));
charlesmn	0:3ac96e360672	4086	itemp32 = itemp32 << 2;
charlesmn	0:3ac96e360672	4087	itemp32 = itemp32 + (int32_t)(orig_x_gradient);
charlesmn	0:3ac96e360672	4088	if (itemp32 > 0xFFFF)
charlesmn	0:3ac96e360672	4089	itemp32 = 0xFFFF;
charlesmn	0:3ac96e360672	4090
charlesmn	0:3ac96e360672	4091	pout->algo__crosstalk_compensation_x_plane_gradient_kcps =
charlesmn	0:3ac96e360672	4092	(int16_t)itemp32;
charlesmn	0:3ac96e360672	4093
charlesmn	0:3ac96e360672	4094	itemp32 = (int32_t)(orig_xtalk_offset -
charlesmn	0:3ac96e360672	4095	pout->algo__crosstalk_compensation_plane_offset_kcps);
charlesmn	0:3ac96e360672	4096	itemp32 = (int32_t)(do_division_s(itemp32, 80));
charlesmn	0:3ac96e360672	4097	itemp32 = itemp32 << 2;
charlesmn	0:3ac96e360672	4098	itemp32 = itemp32 + (int32_t)(orig_y_gradient);
charlesmn	0:3ac96e360672	4099	if (itemp32 > 0xFFFF)
charlesmn	0:3ac96e360672	4100	itemp32 = 0xFFFF;
charlesmn	0:3ac96e360672	4101
charlesmn	0:3ac96e360672	4102	pout->algo__crosstalk_compensation_y_plane_gradient_kcps =
charlesmn	0:3ac96e360672	4103	(int16_t)itemp32;
charlesmn	0:3ac96e360672	4104	}
charlesmn	0:3ac96e360672	4105
charlesmn	0:3ac96e360672	4106
charlesmn	0:3ac96e360672	4107	if (pconfig->smudge_corr_apply_enabled == 1 &&
charlesmn	0:3ac96e360672	4108	(soft_update != 1)) {
charlesmn	0:3ac96e360672	4109	pout->new_xtalk_applied_flag = 1;
charlesmn	0:3ac96e360672	4110	nXtalk = pout->algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:3ac96e360672	4111
charlesmn	0:3ac96e360672	4112	VL53L1_compute_histo_merge_nb(Dev, &histo_merge_nb);
charlesmn	0:3ac96e360672	4113	max = pdev->tuning_parms.tp_hist_merge_max_size;
charlesmn	0:3ac96e360672	4114	pcpo = &(pC->algo__xtalk_cpo_HistoMerge_kcps[0]);
charlesmn	0:3ac96e360672	4115	if ((histo_merge_nb > 0) && merge_enabled && (nXtalk != 0)) {
charlesmn	0:3ac96e360672	4116	cXtalk =
charlesmn	0:3ac96e360672	4117	pC->algo__xtalk_cpo_HistoMerge_kcps[histo_merge_nb-1];
charlesmn	0:3ac96e360672	4118	SmudgeFactor = cXtalk * 1000 / nXtalk;
charlesmn	0:3ac96e360672	4119	if (SmudgeFactor >= pconfig->max_smudge_factor)
charlesmn	0:3ac96e360672	4120	pout->new_xtalk_applied_flag = 0;
charlesmn	0:3ac96e360672	4121	else if (SmudgeFactor > 0)
charlesmn	0:3ac96e360672	4122	for (i = 0; i < max; i++) {
charlesmn	0:3ac96e360672	4123	pcpo = 1000;
charlesmn	0:3ac96e360672	4124	*pcpo /= SmudgeFactor;
charlesmn	0:3ac96e360672	4125	pcpo++;
charlesmn	0:3ac96e360672	4126	}
charlesmn	0:3ac96e360672	4127	}
charlesmn	0:3ac96e360672	4128	if (pout->new_xtalk_applied_flag) {
charlesmn	0:3ac96e360672	4129
charlesmn	0:3ac96e360672	4130	pX->algo__crosstalk_compensation_plane_offset_kcps =
charlesmn	0:3ac96e360672	4131	pout->algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:3ac96e360672	4132	pX->algo__crosstalk_compensation_x_plane_gradient_kcps =
charlesmn	0:3ac96e360672	4133	pout->algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:3ac96e360672	4134	pX->algo__crosstalk_compensation_y_plane_gradient_kcps =
charlesmn	0:3ac96e360672	4135	pout->algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:3ac96e360672	4136
charlesmn	0:3ac96e360672	4137	if (pconfig->smudge_corr_single_apply == 1) {
charlesmn	0:3ac96e360672	4138
charlesmn	0:3ac96e360672	4139	pconfig->smudge_corr_apply_enabled = 0;
charlesmn	0:3ac96e360672	4140	pconfig->smudge_corr_single_apply = 0;
charlesmn	0:3ac96e360672	4141	}
charlesmn	0:3ac96e360672	4142	}
charlesmn	0:3ac96e360672	4143	}
charlesmn	0:3ac96e360672	4144
charlesmn	0:3ac96e360672	4145
charlesmn	0:3ac96e360672	4146	if (soft_update != 1)
charlesmn	0:3ac96e360672	4147	pout->smudge_corr_valid = 1;
charlesmn	0:3ac96e360672	4148
charlesmn	0:3ac96e360672	4149	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4150
charlesmn	0:3ac96e360672	4151	return status;
charlesmn	0:3ac96e360672	4152	}
charlesmn	0:3ac96e360672	4153
charlesmn	0:3ac96e360672	4154	#define CONT_CONTINUE 0
charlesmn	0:3ac96e360672	4155	#define CONT_NEXT_LOOP 1
charlesmn	0:3ac96e360672	4156	#define CONT_RESET 2
charlesmn	0:3ac96e360672	4157	VL53L1_Error VL53L1_dynamic_xtalk_correction_corrector(
charlesmn	0:3ac96e360672	4158	VL53L1_DEV Dev
charlesmn	0:3ac96e360672	4159	)
charlesmn	0:3ac96e360672	4160	{
charlesmn	0:3ac96e360672	4161
charlesmn	0:3ac96e360672	4162
charlesmn	0:3ac96e360672	4163
charlesmn	0:3ac96e360672	4164	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4165
charlesmn	0:3ac96e360672	4166	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4167	VL53L1_LLDriverResults_t *pres = VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	4168	VL53L1_smudge_corrector_config_t *pconfig =
charlesmn	0:3ac96e360672	4169	&(pdev->smudge_correct_config);
charlesmn	0:3ac96e360672	4170	VL53L1_smudge_corrector_internals_t *pint =
charlesmn	0:3ac96e360672	4171	&(pdev->smudge_corrector_internals);
charlesmn	0:3ac96e360672	4172	VL53L1_smudge_corrector_data_t *pout =
charlesmn	0:3ac96e360672	4173	&(pres->range_results.smudge_corrector_data);
charlesmn	0:3ac96e360672	4174	VL53L1_range_results_t *pR = &(pres->range_results);
charlesmn	0:3ac96e360672	4175	VL53L1_xtalk_config_t *pX = &(pdev->xtalk_cfg);
charlesmn	0:3ac96e360672	4176
charlesmn	0:3ac96e360672	4177	uint8_t run_smudge_detection = 0;
charlesmn	0:3ac96e360672	4178	uint8_t merging_complete = 0;
charlesmn	0:3ac96e360672	4179	uint8_t run_nodetect = 0;
charlesmn	0:3ac96e360672	4180	uint8_t ambient_check = 0;
charlesmn	0:3ac96e360672	4181	int32_t itemp32 = 0;
charlesmn	0:3ac96e360672	4182	uint64_t utemp64 = 0;
charlesmn	0:3ac96e360672	4183	uint8_t continue_processing = CONT_CONTINUE;
charlesmn	0:3ac96e360672	4184	uint32_t xtalk_offset_out = 0;
charlesmn	0:3ac96e360672	4185	uint32_t xtalk_offset_in = 0;
charlesmn	0:3ac96e360672	4186	uint32_t current_xtalk = 0;
charlesmn	0:3ac96e360672	4187	uint32_t smudge_margin_adjusted = 0;
charlesmn	0:3ac96e360672	4188	uint8_t i = 0;
charlesmn	0:3ac96e360672	4189	uint8_t nodetect_index = 0;
charlesmn	0:3ac96e360672	4190	uint16_t amr;
charlesmn	0:3ac96e360672	4191	uint32_t cco;
charlesmn	0:3ac96e360672	4192	uint8_t histo_merge_nb;
charlesmn	0:3ac96e360672	4193	uint8_t merge_enabled;
charlesmn	0:3ac96e360672	4194
charlesmn	0:3ac96e360672	4195
charlesmn	0:3ac96e360672	4196	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4197
charlesmn	0:3ac96e360672	4198	merge_enabled = (pdev->tuning_parms.tp_hist_merge == 1) &&
charlesmn	0:3ac96e360672	4199	(VL53L1DevDataGet(Dev, CurrentParameters.PresetMode) ==
charlesmn	0:3ac96e360672	4200	VL53L1_PRESETMODE_RANGING);
charlesmn	0:3ac96e360672	4201
charlesmn	0:3ac96e360672	4202	VL53L1_compute_histo_merge_nb(Dev, &histo_merge_nb);
charlesmn	0:3ac96e360672	4203	if ((histo_merge_nb == 0) \|\| (!merge_enabled))
charlesmn	0:3ac96e360672	4204	histo_merge_nb = 1;
charlesmn	0:3ac96e360672	4205
charlesmn	0:3ac96e360672	4206
charlesmn	0:3ac96e360672	4207	VL53L1_dynamic_xtalk_correction_output_init(pres);
charlesmn	0:3ac96e360672	4208
charlesmn	0:3ac96e360672	4209
charlesmn	0:3ac96e360672	4210	ambient_check = (pconfig->smudge_corr_ambient_threshold == 0) \|\|
charlesmn	0:3ac96e360672	4211	((pconfig->smudge_corr_ambient_threshold * histo_merge_nb) >
charlesmn	0:3ac96e360672	4212	((uint32_t)pR->xmonitor.ambient_count_rate_mcps));
charlesmn	0:3ac96e360672	4213
charlesmn	0:3ac96e360672	4214
charlesmn	0:3ac96e360672	4215	merging_complete = ((!merge_enabled) \|\|
charlesmn	0:3ac96e360672	4216	(histo_merge_nb == pdev->tuning_parms.tp_hist_merge_max_size));
charlesmn	0:3ac96e360672	4217
charlesmn	0:3ac96e360672	4218	run_smudge_detection =
charlesmn	0:3ac96e360672	4219	(pconfig->smudge_corr_enabled == 1) &&
charlesmn	0:3ac96e360672	4220	ambient_check &&
charlesmn	0:3ac96e360672	4221	(pR->xmonitor.range_status
charlesmn	0:3ac96e360672	4222	== VL53L1_DEVICEERROR_RANGECOMPLETE) &&
charlesmn	0:3ac96e360672	4223	merging_complete;
charlesmn	0:3ac96e360672	4224
charlesmn	0:3ac96e360672	4225
charlesmn	0:3ac96e360672	4226	if ((pR->xmonitor.range_status
charlesmn	0:3ac96e360672	4227	!= VL53L1_DEVICEERROR_RANGECOMPLETE) &&
charlesmn	0:3ac96e360672	4228	(pconfig->smudge_corr_enabled == 1)) {
charlesmn	0:3ac96e360672	4229
charlesmn	0:3ac96e360672	4230	run_nodetect = 2;
charlesmn	0:3ac96e360672	4231	for (i = 0; i < pR->active_results; i++) {
charlesmn	0:3ac96e360672	4232	if (pR->VL53L1_p_002[i].range_status ==
charlesmn	0:3ac96e360672	4233	VL53L1_DEVICEERROR_RANGECOMPLETE) {
charlesmn	0:3ac96e360672	4234	if (pR->VL53L1_p_002[i].median_range_mm
charlesmn	0:3ac96e360672	4235	<=
charlesmn	0:3ac96e360672	4236	pconfig->nodetect_min_range_mm) {
charlesmn	0:3ac96e360672	4237	run_nodetect = 0;
charlesmn	0:3ac96e360672	4238	} else {
charlesmn	0:3ac96e360672	4239	if (run_nodetect == 2) {
charlesmn	0:3ac96e360672	4240	run_nodetect = 1;
charlesmn	0:3ac96e360672	4241	nodetect_index = i;
charlesmn	0:3ac96e360672	4242	}
charlesmn	0:3ac96e360672	4243	}
charlesmn	0:3ac96e360672	4244	}
charlesmn	0:3ac96e360672	4245	}
charlesmn	0:3ac96e360672	4246
charlesmn	0:3ac96e360672	4247	if (run_nodetect == 2)
charlesmn	0:3ac96e360672	4248
charlesmn	0:3ac96e360672	4249	run_nodetect = 0;
charlesmn	0:3ac96e360672	4250
charlesmn	0:3ac96e360672	4251	amr =
charlesmn	0:3ac96e360672	4252	pR->VL53L1_p_002[nodetect_index].ambient_count_rate_mcps;
charlesmn	0:3ac96e360672	4253
charlesmn	0:3ac96e360672	4254	if (run_nodetect == 1) {
charlesmn	0:3ac96e360672	4255
charlesmn	0:3ac96e360672	4256
charlesmn	0:3ac96e360672	4257
charlesmn	0:3ac96e360672	4258
charlesmn	0:3ac96e360672	4259	utemp64 = 1000 * ((uint64_t)amr);
charlesmn	0:3ac96e360672	4260
charlesmn	0:3ac96e360672	4261
charlesmn	0:3ac96e360672	4262	utemp64 = utemp64 << 9;
charlesmn	0:3ac96e360672	4263
charlesmn	0:3ac96e360672	4264
charlesmn	0:3ac96e360672	4265	if (utemp64 < pconfig->nodetect_ambient_threshold)
charlesmn	0:3ac96e360672	4266	run_nodetect = 1;
charlesmn	0:3ac96e360672	4267	else
charlesmn	0:3ac96e360672	4268	run_nodetect = 0;
charlesmn	0:3ac96e360672	4269
charlesmn	0:3ac96e360672	4270	}
charlesmn	0:3ac96e360672	4271	}
charlesmn	0:3ac96e360672	4272
charlesmn	0:3ac96e360672	4273
charlesmn	0:3ac96e360672	4274	if (run_smudge_detection) {
charlesmn	0:3ac96e360672	4275
charlesmn	0:3ac96e360672	4276	pint->nodetect_counter = 0;
charlesmn	0:3ac96e360672	4277
charlesmn	0:3ac96e360672	4278
charlesmn	0:3ac96e360672	4279	VL53L1_dynamic_xtalk_correction_calc_required_samples(Dev);
charlesmn	0:3ac96e360672	4280
charlesmn	0:3ac96e360672	4281
charlesmn	0:3ac96e360672	4282	xtalk_offset_in =
charlesmn	0:3ac96e360672	4283	pR->xmonitor.VL53L1_p_012;
charlesmn	0:3ac96e360672	4284
charlesmn	0:3ac96e360672	4285
charlesmn	0:3ac96e360672	4286	cco = pX->algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:3ac96e360672	4287	current_xtalk = ((uint32_t)cco) << 2;
charlesmn	0:3ac96e360672	4288
charlesmn	0:3ac96e360672	4289
charlesmn	0:3ac96e360672	4290	smudge_margin_adjusted =
charlesmn	0:3ac96e360672	4291	((uint32_t)(pconfig->smudge_margin)) << 2;
charlesmn	0:3ac96e360672	4292
charlesmn	0:3ac96e360672	4293
charlesmn	0:3ac96e360672	4294	itemp32 = xtalk_offset_in - current_xtalk +
charlesmn	0:3ac96e360672	4295	smudge_margin_adjusted;
charlesmn	0:3ac96e360672	4296
charlesmn	0:3ac96e360672	4297	if (itemp32 < 0)
charlesmn	0:3ac96e360672	4298	itemp32 = itemp32 * (-1);
charlesmn	0:3ac96e360672	4299
charlesmn	0:3ac96e360672	4300
charlesmn	0:3ac96e360672	4301	if (itemp32 > ((int32_t)pconfig->single_xtalk_delta)) {
charlesmn	0:3ac96e360672	4302	if ((int32_t)xtalk_offset_in >
charlesmn	0:3ac96e360672	4303	((int32_t)current_xtalk -
charlesmn	0:3ac96e360672	4304	(int32_t)smudge_margin_adjusted)) {
charlesmn	0:3ac96e360672	4305	pout->single_xtalk_delta_flag = 1;
charlesmn	0:3ac96e360672	4306	} else {
charlesmn	0:3ac96e360672	4307	pout->single_xtalk_delta_flag = 2;
charlesmn	0:3ac96e360672	4308	}
charlesmn	0:3ac96e360672	4309	}
charlesmn	0:3ac96e360672	4310
charlesmn	0:3ac96e360672	4311
charlesmn	0:3ac96e360672	4312	pint->current_samples = pint->current_samples + 1;
charlesmn	0:3ac96e360672	4313
charlesmn	0:3ac96e360672	4314
charlesmn	0:3ac96e360672	4315	if (pint->current_samples > pconfig->sample_limit) {
charlesmn	0:3ac96e360672	4316	pout->sample_limit_exceeded_flag = 1;
charlesmn	0:3ac96e360672	4317	continue_processing = CONT_RESET;
charlesmn	0:3ac96e360672	4318	} else {
charlesmn	0:3ac96e360672	4319	pint->accumulator = pint->accumulator +
charlesmn	0:3ac96e360672	4320	xtalk_offset_in;
charlesmn	0:3ac96e360672	4321	}
charlesmn	0:3ac96e360672	4322
charlesmn	0:3ac96e360672	4323	if (pint->current_samples < pint->required_samples)
charlesmn	0:3ac96e360672	4324	continue_processing = CONT_NEXT_LOOP;
charlesmn	0:3ac96e360672	4325
charlesmn	0:3ac96e360672	4326
charlesmn	0:3ac96e360672	4327	xtalk_offset_out =
charlesmn	0:3ac96e360672	4328	(uint32_t)(do_division_u(pint->accumulator,
charlesmn	0:3ac96e360672	4329	pint->current_samples));
charlesmn	0:3ac96e360672	4330
charlesmn	0:3ac96e360672	4331
charlesmn	0:3ac96e360672	4332	itemp32 = xtalk_offset_out - current_xtalk +
charlesmn	0:3ac96e360672	4333	smudge_margin_adjusted;
charlesmn	0:3ac96e360672	4334
charlesmn	0:3ac96e360672	4335	if (itemp32 < 0)
charlesmn	0:3ac96e360672	4336	itemp32 = itemp32 * (-1);
charlesmn	0:3ac96e360672	4337
charlesmn	0:3ac96e360672	4338	if (continue_processing == CONT_CONTINUE &&
charlesmn	0:3ac96e360672	4339	(itemp32 >= ((int32_t)(pconfig->averaged_xtalk_delta)))
charlesmn	0:3ac96e360672	4340	) {
charlesmn	0:3ac96e360672	4341	if ((int32_t)xtalk_offset_out >
charlesmn	0:3ac96e360672	4342	((int32_t)current_xtalk -
charlesmn	0:3ac96e360672	4343	(int32_t)smudge_margin_adjusted))
charlesmn	0:3ac96e360672	4344	pout->averaged_xtalk_delta_flag = 1;
charlesmn	0:3ac96e360672	4345	else
charlesmn	0:3ac96e360672	4346	pout->averaged_xtalk_delta_flag = 2;
charlesmn	0:3ac96e360672	4347	}
charlesmn	0:3ac96e360672	4348
charlesmn	0:3ac96e360672	4349	if (continue_processing == CONT_CONTINUE &&
charlesmn	0:3ac96e360672	4350	(itemp32 < ((int32_t)(pconfig->averaged_xtalk_delta)))
charlesmn	0:3ac96e360672	4351	)
charlesmn	0:3ac96e360672	4352
charlesmn	0:3ac96e360672	4353	continue_processing = CONT_RESET;
charlesmn	0:3ac96e360672	4354
charlesmn	0:3ac96e360672	4355
charlesmn	0:3ac96e360672	4356
charlesmn	0:3ac96e360672	4357	pout->smudge_corr_clipped = 0;
charlesmn	0:3ac96e360672	4358	if ((continue_processing == CONT_CONTINUE) &&
charlesmn	0:3ac96e360672	4359	(pconfig->smudge_corr_clip_limit != 0)) {
charlesmn	0:3ac96e360672	4360	if (xtalk_offset_out >
charlesmn	0:3ac96e360672	4361	(pconfig->smudge_corr_clip_limit * histo_merge_nb)) {
charlesmn	0:3ac96e360672	4362	pout->smudge_corr_clipped = 1;
charlesmn	0:3ac96e360672	4363	continue_processing = CONT_RESET;
charlesmn	0:3ac96e360672	4364	}
charlesmn	0:3ac96e360672	4365	}
charlesmn	0:3ac96e360672	4366
charlesmn	0:3ac96e360672	4367
charlesmn	0:3ac96e360672	4368
charlesmn	0:3ac96e360672	4369	if (pconfig->user_xtalk_offset_limit_hi &&
charlesmn	0:3ac96e360672	4370	(xtalk_offset_out >
charlesmn	0:3ac96e360672	4371	pconfig->user_xtalk_offset_limit))
charlesmn	0:3ac96e360672	4372	xtalk_offset_out =
charlesmn	0:3ac96e360672	4373	pconfig->user_xtalk_offset_limit;
charlesmn	0:3ac96e360672	4374
charlesmn	0:3ac96e360672	4375
charlesmn	0:3ac96e360672	4376
charlesmn	0:3ac96e360672	4377	if ((pconfig->user_xtalk_offset_limit_hi == 0) &&
charlesmn	0:3ac96e360672	4378	(xtalk_offset_out <
charlesmn	0:3ac96e360672	4379	pconfig->user_xtalk_offset_limit))
charlesmn	0:3ac96e360672	4380	xtalk_offset_out =
charlesmn	0:3ac96e360672	4381	pconfig->user_xtalk_offset_limit;
charlesmn	0:3ac96e360672	4382
charlesmn	0:3ac96e360672	4383
charlesmn	0:3ac96e360672	4384
charlesmn	0:3ac96e360672	4385	xtalk_offset_out = xtalk_offset_out >> 2;
charlesmn	0:3ac96e360672	4386	if (xtalk_offset_out > 0x3FFFF)
charlesmn	0:3ac96e360672	4387	xtalk_offset_out = 0x3FFFF;
charlesmn	0:3ac96e360672	4388
charlesmn	0:3ac96e360672	4389
charlesmn	0:3ac96e360672	4390	if (continue_processing == CONT_CONTINUE) {
charlesmn	0:3ac96e360672	4391
charlesmn	0:3ac96e360672	4392	VL53L1_dynamic_xtalk_correction_calc_new_xtalk(
charlesmn	0:3ac96e360672	4393	Dev,
charlesmn	0:3ac96e360672	4394	xtalk_offset_out,
charlesmn	0:3ac96e360672	4395	pconfig,
charlesmn	0:3ac96e360672	4396	pout,
charlesmn	0:3ac96e360672	4397	1,
charlesmn	0:3ac96e360672	4398	0
charlesmn	0:3ac96e360672	4399	);
charlesmn	0:3ac96e360672	4400
charlesmn	0:3ac96e360672	4401
charlesmn	0:3ac96e360672	4402	continue_processing = CONT_RESET;
charlesmn	0:3ac96e360672	4403	} else {
charlesmn	0:3ac96e360672	4404
charlesmn	0:3ac96e360672	4405	VL53L1_dynamic_xtalk_correction_calc_new_xtalk(
charlesmn	0:3ac96e360672	4406	Dev,
charlesmn	0:3ac96e360672	4407	xtalk_offset_out,
charlesmn	0:3ac96e360672	4408	pconfig,
charlesmn	0:3ac96e360672	4409	pout,
charlesmn	0:3ac96e360672	4410	1,
charlesmn	0:3ac96e360672	4411	1
charlesmn	0:3ac96e360672	4412	);
charlesmn	0:3ac96e360672	4413	}
charlesmn	0:3ac96e360672	4414
charlesmn	0:3ac96e360672	4415
charlesmn	0:3ac96e360672	4416	if (continue_processing == CONT_RESET) {
charlesmn	0:3ac96e360672	4417	pint->accumulator = 0;
charlesmn	0:3ac96e360672	4418	pint->current_samples = 0;
charlesmn	0:3ac96e360672	4419	pint->nodetect_counter = 0;
charlesmn	0:3ac96e360672	4420	}
charlesmn	0:3ac96e360672	4421
charlesmn	0:3ac96e360672	4422	}
charlesmn	0:3ac96e360672	4423
charlesmn	0:3ac96e360672	4424	continue_processing = CONT_CONTINUE;
charlesmn	0:3ac96e360672	4425	if (run_nodetect == 1) {
charlesmn	0:3ac96e360672	4426
charlesmn	0:3ac96e360672	4427	pint->nodetect_counter += 1;
charlesmn	0:3ac96e360672	4428
charlesmn	0:3ac96e360672	4429
charlesmn	0:3ac96e360672	4430	if (pint->nodetect_counter < pconfig->nodetect_sample_limit)
charlesmn	0:3ac96e360672	4431	continue_processing = CONT_NEXT_LOOP;
charlesmn	0:3ac96e360672	4432
charlesmn	0:3ac96e360672	4433
charlesmn	0:3ac96e360672	4434	xtalk_offset_out = (uint32_t)(pconfig->nodetect_xtalk_offset);
charlesmn	0:3ac96e360672	4435
charlesmn	0:3ac96e360672	4436	if (continue_processing == CONT_CONTINUE) {
charlesmn	0:3ac96e360672	4437
charlesmn	0:3ac96e360672	4438	VL53L1_dynamic_xtalk_correction_calc_new_xtalk(
charlesmn	0:3ac96e360672	4439	Dev,
charlesmn	0:3ac96e360672	4440	xtalk_offset_out,
charlesmn	0:3ac96e360672	4441	pconfig,
charlesmn	0:3ac96e360672	4442	pout,
charlesmn	0:3ac96e360672	4443	0,
charlesmn	0:3ac96e360672	4444	0
charlesmn	0:3ac96e360672	4445	);
charlesmn	0:3ac96e360672	4446
charlesmn	0:3ac96e360672	4447
charlesmn	0:3ac96e360672	4448	pout->smudge_corr_valid = 2;
charlesmn	0:3ac96e360672	4449
charlesmn	0:3ac96e360672	4450
charlesmn	0:3ac96e360672	4451	continue_processing = CONT_RESET;
charlesmn	0:3ac96e360672	4452	} else {
charlesmn	0:3ac96e360672	4453
charlesmn	0:3ac96e360672	4454	VL53L1_dynamic_xtalk_correction_calc_new_xtalk(
charlesmn	0:3ac96e360672	4455	Dev,
charlesmn	0:3ac96e360672	4456	xtalk_offset_out,
charlesmn	0:3ac96e360672	4457	pconfig,
charlesmn	0:3ac96e360672	4458	pout,
charlesmn	0:3ac96e360672	4459	0,
charlesmn	0:3ac96e360672	4460	1
charlesmn	0:3ac96e360672	4461	);
charlesmn	0:3ac96e360672	4462	}
charlesmn	0:3ac96e360672	4463
charlesmn	0:3ac96e360672	4464
charlesmn	0:3ac96e360672	4465	if (continue_processing == CONT_RESET) {
charlesmn	0:3ac96e360672	4466	pint->accumulator = 0;
charlesmn	0:3ac96e360672	4467	pint->current_samples = 0;
charlesmn	0:3ac96e360672	4468	pint->nodetect_counter = 0;
charlesmn	0:3ac96e360672	4469	}
charlesmn	0:3ac96e360672	4470	}
charlesmn	0:3ac96e360672	4471
charlesmn	0:3ac96e360672	4472	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4473
charlesmn	0:3ac96e360672	4474	return status;
charlesmn	0:3ac96e360672	4475	}
charlesmn	0:3ac96e360672	4476
charlesmn	0:3ac96e360672	4477	VL53L1_Error VL53L1_dynamic_xtalk_correction_data_init(
charlesmn	0:3ac96e360672	4478	VL53L1_DEV Dev
charlesmn	0:3ac96e360672	4479	)
charlesmn	0:3ac96e360672	4480	{
charlesmn	0:3ac96e360672	4481
charlesmn	0:3ac96e360672	4482
charlesmn	0:3ac96e360672	4483
charlesmn	0:3ac96e360672	4484
charlesmn	0:3ac96e360672	4485	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4486
charlesmn	0:3ac96e360672	4487	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4488	VL53L1_LLDriverResults_t *pres = VL53L1DevStructGetLLResultsHandle(Dev);
charlesmn	0:3ac96e360672	4489
charlesmn	0:3ac96e360672	4490	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4491
charlesmn	0:3ac96e360672	4492
charlesmn	0:3ac96e360672	4493
charlesmn	0:3ac96e360672	4494	pdev->smudge_correct_config.smudge_corr_enabled = 1;
charlesmn	0:3ac96e360672	4495	pdev->smudge_correct_config.smudge_corr_apply_enabled = 1;
charlesmn	0:3ac96e360672	4496	pdev->smudge_correct_config.smudge_corr_single_apply =
charlesmn	0:3ac96e360672	4497	VL53L1_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY_DEFAULT;
charlesmn	0:3ac96e360672	4498
charlesmn	0:3ac96e360672	4499	pdev->smudge_correct_config.smudge_margin =
charlesmn	0:3ac96e360672	4500	VL53L1_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN_DEFAULT;
charlesmn	0:3ac96e360672	4501	pdev->smudge_correct_config.noise_margin =
charlesmn	0:3ac96e360672	4502	VL53L1_TUNINGPARM_DYNXTALK_NOISE_MARGIN_DEFAULT;
charlesmn	0:3ac96e360672	4503	pdev->smudge_correct_config.user_xtalk_offset_limit =
charlesmn	0:3ac96e360672	4504	VL53L1_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_DEFAULT;
charlesmn	0:3ac96e360672	4505	pdev->smudge_correct_config.user_xtalk_offset_limit_hi =
charlesmn	0:3ac96e360672	4506	VL53L1_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI_DEFAULT;
charlesmn	0:3ac96e360672	4507	pdev->smudge_correct_config.sample_limit =
charlesmn	0:3ac96e360672	4508	VL53L1_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT_DEFAULT;
charlesmn	0:3ac96e360672	4509	pdev->smudge_correct_config.single_xtalk_delta =
charlesmn	0:3ac96e360672	4510	VL53L1_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA_DEFAULT;
charlesmn	0:3ac96e360672	4511	pdev->smudge_correct_config.averaged_xtalk_delta =
charlesmn	0:3ac96e360672	4512	VL53L1_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA_DEFAULT;
charlesmn	0:3ac96e360672	4513	pdev->smudge_correct_config.smudge_corr_clip_limit =
charlesmn	0:3ac96e360672	4514	VL53L1_TUNINGPARM_DYNXTALK_CLIP_LIMIT_DEFAULT;
charlesmn	0:3ac96e360672	4515	pdev->smudge_correct_config.smudge_corr_ambient_threshold =
charlesmn	0:3ac96e360672	4516	VL53L1_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD_DEFAULT;
charlesmn	0:3ac96e360672	4517	pdev->smudge_correct_config.scaler_calc_method =
charlesmn	0:3ac96e360672	4518	0;
charlesmn	0:3ac96e360672	4519	pdev->smudge_correct_config.x_gradient_scaler =
charlesmn	0:3ac96e360672	4520	VL53L1_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER_DEFAULT;
charlesmn	0:3ac96e360672	4521	pdev->smudge_correct_config.y_gradient_scaler =
charlesmn	0:3ac96e360672	4522	VL53L1_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER_DEFAULT;
charlesmn	0:3ac96e360672	4523	pdev->smudge_correct_config.user_scaler_set =
charlesmn	0:3ac96e360672	4524	VL53L1_TUNINGPARM_DYNXTALK_USER_SCALER_SET_DEFAULT;
charlesmn	0:3ac96e360672	4525	pdev->smudge_correct_config.nodetect_ambient_threshold =
charlesmn	0:3ac96e360672	4526	VL53L1_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS_DEFAULT;
charlesmn	0:3ac96e360672	4527	pdev->smudge_correct_config.nodetect_sample_limit =
charlesmn	0:3ac96e360672	4528	VL53L1_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT_DEFAULT;
charlesmn	0:3ac96e360672	4529	pdev->smudge_correct_config.nodetect_xtalk_offset =
charlesmn	0:3ac96e360672	4530	VL53L1_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS_DEFAULT;
charlesmn	0:3ac96e360672	4531	pdev->smudge_correct_config.nodetect_min_range_mm =
charlesmn	0:3ac96e360672	4532	VL53L1_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM_DEFAULT;
charlesmn	0:3ac96e360672	4533	pdev->smudge_correct_config.max_smudge_factor =
charlesmn	0:3ac96e360672	4534	VL53L1_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR_DEFAULT;
charlesmn	0:3ac96e360672	4535
charlesmn	0:3ac96e360672	4536
charlesmn	0:3ac96e360672	4537	pdev->smudge_corrector_internals.current_samples = 0;
charlesmn	0:3ac96e360672	4538	pdev->smudge_corrector_internals.required_samples = 0;
charlesmn	0:3ac96e360672	4539	pdev->smudge_corrector_internals.accumulator = 0;
charlesmn	0:3ac96e360672	4540	pdev->smudge_corrector_internals.nodetect_counter = 0;
charlesmn	0:3ac96e360672	4541
charlesmn	0:3ac96e360672	4542
charlesmn	0:3ac96e360672	4543	VL53L1_dynamic_xtalk_correction_output_init(pres);
charlesmn	0:3ac96e360672	4544
charlesmn	0:3ac96e360672	4545	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4546
charlesmn	0:3ac96e360672	4547	return status;
charlesmn	0:3ac96e360672	4548	}
charlesmn	0:3ac96e360672	4549
charlesmn	0:3ac96e360672	4550	VL53L1_Error VL53L1_dynamic_xtalk_correction_output_init(
charlesmn	0:3ac96e360672	4551	VL53L1_LLDriverResults_t *pres
charlesmn	0:3ac96e360672	4552	)
charlesmn	0:3ac96e360672	4553	{
charlesmn	0:3ac96e360672	4554
charlesmn	0:3ac96e360672	4555
charlesmn	0:3ac96e360672	4556
charlesmn	0:3ac96e360672	4557
charlesmn	0:3ac96e360672	4558	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4559
charlesmn	0:3ac96e360672	4560	VL53L1_smudge_corrector_data_t *pdata;
charlesmn	0:3ac96e360672	4561
charlesmn	0:3ac96e360672	4562	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4563
charlesmn	0:3ac96e360672	4564
charlesmn	0:3ac96e360672	4565	pdata = &(pres->range_results.smudge_corrector_data);
charlesmn	0:3ac96e360672	4566
charlesmn	0:3ac96e360672	4567	pdata->smudge_corr_valid = 0;
charlesmn	0:3ac96e360672	4568	pdata->smudge_corr_clipped = 0;
charlesmn	0:3ac96e360672	4569	pdata->single_xtalk_delta_flag = 0;
charlesmn	0:3ac96e360672	4570	pdata->averaged_xtalk_delta_flag = 0;
charlesmn	0:3ac96e360672	4571	pdata->sample_limit_exceeded_flag = 0;
charlesmn	0:3ac96e360672	4572	pdata->gradient_zero_flag = 0;
charlesmn	0:3ac96e360672	4573	pdata->new_xtalk_applied_flag = 0;
charlesmn	0:3ac96e360672	4574
charlesmn	0:3ac96e360672	4575	pdata->algo__crosstalk_compensation_plane_offset_kcps = 0;
charlesmn	0:3ac96e360672	4576	pdata->algo__crosstalk_compensation_x_plane_gradient_kcps = 0;
charlesmn	0:3ac96e360672	4577	pdata->algo__crosstalk_compensation_y_plane_gradient_kcps = 0;
charlesmn	0:3ac96e360672	4578
charlesmn	0:3ac96e360672	4579	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4580
charlesmn	0:3ac96e360672	4581	return status;
charlesmn	0:3ac96e360672	4582	}
charlesmn	0:3ac96e360672	4583
charlesmn	0:3ac96e360672	4584
charlesmn	0:3ac96e360672	4585	VL53L1_Error VL53L1_xtalk_cal_data_init(
charlesmn	0:3ac96e360672	4586	VL53L1_DEV Dev
charlesmn	0:3ac96e360672	4587	)
charlesmn	0:3ac96e360672	4588	{
charlesmn	0:3ac96e360672	4589
charlesmn	0:3ac96e360672	4590
charlesmn	0:3ac96e360672	4591
charlesmn	0:3ac96e360672	4592
charlesmn	0:3ac96e360672	4593	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4594
charlesmn	0:3ac96e360672	4595	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4596
charlesmn	0:3ac96e360672	4597	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4598
charlesmn	0:3ac96e360672	4599
charlesmn	0:3ac96e360672	4600
charlesmn	0:3ac96e360672	4601	pdev->xtalk_cal.algo__crosstalk_compensation_plane_offset_kcps = 0;
charlesmn	0:3ac96e360672	4602	pdev->xtalk_cal.algo__crosstalk_compensation_x_plane_gradient_kcps = 0;
charlesmn	0:3ac96e360672	4603	pdev->xtalk_cal.algo__crosstalk_compensation_y_plane_gradient_kcps = 0;
charlesmn	0:3ac96e360672	4604	memset(&pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[0], 0,
charlesmn	0:3ac96e360672	4605	sizeof(pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps));
charlesmn	0:3ac96e360672	4606
charlesmn	0:3ac96e360672	4607	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4608
charlesmn	0:3ac96e360672	4609	return status;
charlesmn	0:3ac96e360672	4610	}
charlesmn	0:3ac96e360672	4611
charlesmn	0:3ac96e360672	4612
charlesmn	0:3ac96e360672	4613
charlesmn	0:3ac96e360672	4614
charlesmn	0:3ac96e360672	4615
charlesmn	0:3ac96e360672	4616
charlesmn	0:3ac96e360672	4617	VL53L1_Error VL53L1_low_power_auto_data_init(
charlesmn	0:3ac96e360672	4618	VL53L1_DEV Dev
charlesmn	0:3ac96e360672	4619	)
charlesmn	0:3ac96e360672	4620	{
charlesmn	0:3ac96e360672	4621
charlesmn	0:3ac96e360672	4622
charlesmn	0:3ac96e360672	4623
charlesmn	0:3ac96e360672	4624
charlesmn	0:3ac96e360672	4625	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4626
charlesmn	0:3ac96e360672	4627	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4628
charlesmn	0:3ac96e360672	4629	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4630
charlesmn	0:3ac96e360672	4631	pdev->low_power_auto_data.vhv_loop_bound =
charlesmn	0:3ac96e360672	4632	VL53L1_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND_DEFAULT;
charlesmn	0:3ac96e360672	4633	pdev->low_power_auto_data.is_low_power_auto_mode = 0;
charlesmn	0:3ac96e360672	4634	pdev->low_power_auto_data.low_power_auto_range_count = 0;
charlesmn	0:3ac96e360672	4635	pdev->low_power_auto_data.saved_interrupt_config = 0;
charlesmn	0:3ac96e360672	4636	pdev->low_power_auto_data.saved_vhv_init = 0;
charlesmn	0:3ac96e360672	4637	pdev->low_power_auto_data.saved_vhv_timeout = 0;
charlesmn	0:3ac96e360672	4638	pdev->low_power_auto_data.first_run_phasecal_result = 0;
charlesmn	0:3ac96e360672	4639	pdev->low_power_auto_data.dss__total_rate_per_spad_mcps = 0;
charlesmn	0:3ac96e360672	4640	pdev->low_power_auto_data.dss__required_spads = 0;
charlesmn	0:3ac96e360672	4641
charlesmn	0:3ac96e360672	4642	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4643
charlesmn	0:3ac96e360672	4644	return status;
charlesmn	0:3ac96e360672	4645	}
charlesmn	0:3ac96e360672	4646
charlesmn	0:3ac96e360672	4647	VL53L1_Error VL53L1_low_power_auto_data_stop_range(
charlesmn	0:3ac96e360672	4648	VL53L1_DEV Dev
charlesmn	0:3ac96e360672	4649	)
charlesmn	0:3ac96e360672	4650	{
charlesmn	0:3ac96e360672	4651
charlesmn	0:3ac96e360672	4652
charlesmn	0:3ac96e360672	4653
charlesmn	0:3ac96e360672	4654
charlesmn	0:3ac96e360672	4655	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4656
charlesmn	0:3ac96e360672	4657	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4658
charlesmn	0:3ac96e360672	4659	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4660
charlesmn	0:3ac96e360672	4661
charlesmn	0:3ac96e360672	4662
charlesmn	0:3ac96e360672	4663	pdev->low_power_auto_data.low_power_auto_range_count = 0xFF;
charlesmn	0:3ac96e360672	4664
charlesmn	0:3ac96e360672	4665	pdev->low_power_auto_data.first_run_phasecal_result = 0;
charlesmn	0:3ac96e360672	4666	pdev->low_power_auto_data.dss__total_rate_per_spad_mcps = 0;
charlesmn	0:3ac96e360672	4667	pdev->low_power_auto_data.dss__required_spads = 0;
charlesmn	0:3ac96e360672	4668
charlesmn	0:3ac96e360672	4669
charlesmn	0:3ac96e360672	4670	if (pdev->low_power_auto_data.saved_vhv_init != 0)
charlesmn	0:3ac96e360672	4671	pdev->stat_nvm.vhv_config__init =
charlesmn	0:3ac96e360672	4672	pdev->low_power_auto_data.saved_vhv_init;
charlesmn	0:3ac96e360672	4673	if (pdev->low_power_auto_data.saved_vhv_timeout != 0)
charlesmn	0:3ac96e360672	4674	pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound =
charlesmn	0:3ac96e360672	4675	pdev->low_power_auto_data.saved_vhv_timeout;
charlesmn	0:3ac96e360672	4676
charlesmn	0:3ac96e360672	4677
charlesmn	0:3ac96e360672	4678	pdev->gen_cfg.phasecal_config__override = 0x00;
charlesmn	0:3ac96e360672	4679
charlesmn	0:3ac96e360672	4680	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4681
charlesmn	0:3ac96e360672	4682	return status;
charlesmn	0:3ac96e360672	4683	}
charlesmn	0:3ac96e360672	4684
charlesmn	0:3ac96e360672	4685	VL53L1_Error VL53L1_config_low_power_auto_mode(
charlesmn	0:3ac96e360672	4686	VL53L1_general_config_t *pgeneral,
charlesmn	0:3ac96e360672	4687	VL53L1_dynamic_config_t *pdynamic,
charlesmn	0:3ac96e360672	4688	VL53L1_low_power_auto_data_t *plpadata
charlesmn	0:3ac96e360672	4689	)
charlesmn	0:3ac96e360672	4690	{
charlesmn	0:3ac96e360672	4691
charlesmn	0:3ac96e360672	4692
charlesmn	0:3ac96e360672	4693
charlesmn	0:3ac96e360672	4694
charlesmn	0:3ac96e360672	4695	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4696
charlesmn	0:3ac96e360672	4697	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4698
charlesmn	0:3ac96e360672	4699
charlesmn	0:3ac96e360672	4700	plpadata->is_low_power_auto_mode = 1;
charlesmn	0:3ac96e360672	4701
charlesmn	0:3ac96e360672	4702
charlesmn	0:3ac96e360672	4703	plpadata->low_power_auto_range_count = 0;
charlesmn	0:3ac96e360672	4704
charlesmn	0:3ac96e360672	4705
charlesmn	0:3ac96e360672	4706	pdynamic->system__sequence_config =
charlesmn	0:3ac96e360672	4707	VL53L1_SEQUENCE_VHV_EN \|
charlesmn	0:3ac96e360672	4708	VL53L1_SEQUENCE_PHASECAL_EN \|
charlesmn	0:3ac96e360672	4709	VL53L1_SEQUENCE_DSS1_EN \|
charlesmn	0:3ac96e360672	4710
charlesmn	0:3ac96e360672	4711
charlesmn	0:3ac96e360672	4712
charlesmn	0:3ac96e360672	4713	VL53L1_SEQUENCE_RANGE_EN;
charlesmn	0:3ac96e360672	4714
charlesmn	0:3ac96e360672	4715
charlesmn	0:3ac96e360672	4716	pgeneral->dss_config__manual_effective_spads_select = 200 << 8;
charlesmn	0:3ac96e360672	4717	pgeneral->dss_config__roi_mode_control =
charlesmn	0:3ac96e360672	4718	VL53L1_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS;
charlesmn	0:3ac96e360672	4719
charlesmn	0:3ac96e360672	4720	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4721
charlesmn	0:3ac96e360672	4722	return status;
charlesmn	0:3ac96e360672	4723	}
charlesmn	0:3ac96e360672	4724
charlesmn	0:3ac96e360672	4725	VL53L1_Error VL53L1_low_power_auto_setup_manual_calibration(
charlesmn	0:3ac96e360672	4726	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	4727	{
charlesmn	0:3ac96e360672	4728
charlesmn	0:3ac96e360672	4729
charlesmn	0:3ac96e360672	4730
charlesmn	0:3ac96e360672	4731	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4732
charlesmn	0:3ac96e360672	4733
charlesmn	0:3ac96e360672	4734	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4735
charlesmn	0:3ac96e360672	4736	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4737
charlesmn	0:3ac96e360672	4738
charlesmn	0:3ac96e360672	4739	pdev->low_power_auto_data.saved_vhv_init =
charlesmn	0:3ac96e360672	4740	pdev->stat_nvm.vhv_config__init;
charlesmn	0:3ac96e360672	4741	pdev->low_power_auto_data.saved_vhv_timeout =
charlesmn	0:3ac96e360672	4742	pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound;
charlesmn	0:3ac96e360672	4743
charlesmn	0:3ac96e360672	4744
charlesmn	0:3ac96e360672	4745	pdev->stat_nvm.vhv_config__init &= 0x7F;
charlesmn	0:3ac96e360672	4746
charlesmn	0:3ac96e360672	4747	pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound =
charlesmn	0:3ac96e360672	4748	(pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound & 0x03) +
charlesmn	0:3ac96e360672	4749	(pdev->low_power_auto_data.vhv_loop_bound << 2);
charlesmn	0:3ac96e360672	4750
charlesmn	0:3ac96e360672	4751	pdev->gen_cfg.phasecal_config__override = 0x01;
charlesmn	0:3ac96e360672	4752	pdev->low_power_auto_data.first_run_phasecal_result =
charlesmn	0:3ac96e360672	4753	pdev->dbg_results.phasecal_result__vcsel_start;
charlesmn	0:3ac96e360672	4754	pdev->gen_cfg.cal_config__vcsel_start =
charlesmn	0:3ac96e360672	4755	pdev->low_power_auto_data.first_run_phasecal_result;
charlesmn	0:3ac96e360672	4756
charlesmn	0:3ac96e360672	4757	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4758
charlesmn	0:3ac96e360672	4759	return status;
charlesmn	0:3ac96e360672	4760	}
charlesmn	0:3ac96e360672	4761
charlesmn	0:3ac96e360672	4762	VL53L1_Error VL53L1_low_power_auto_update_DSS(
charlesmn	0:3ac96e360672	4763	VL53L1_DEV Dev)
charlesmn	0:3ac96e360672	4764	{
charlesmn	0:3ac96e360672	4765
charlesmn	0:3ac96e360672	4766
charlesmn	0:3ac96e360672	4767
charlesmn	0:3ac96e360672	4768	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4769
charlesmn	0:3ac96e360672	4770	VL53L1_system_results_t *pS = &(pdev->sys_results);
charlesmn	0:3ac96e360672	4771
charlesmn	0:3ac96e360672	4772
charlesmn	0:3ac96e360672	4773	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4774
charlesmn	0:3ac96e360672	4775	uint32_t utemp32a;
charlesmn	0:3ac96e360672	4776
charlesmn	0:3ac96e360672	4777	LOG_FUNCTION_START("");
charlesmn	0:3ac96e360672	4778
charlesmn	0:3ac96e360672	4779
charlesmn	0:3ac96e360672	4780
charlesmn	0:3ac96e360672	4781
charlesmn	0:3ac96e360672	4782	utemp32a =
charlesmn	0:3ac96e360672	4783	pS->result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0
charlesmn	0:3ac96e360672	4784	+ pS->result__ambient_count_rate_mcps_sd0;
charlesmn	0:3ac96e360672	4785
charlesmn	0:3ac96e360672	4786
charlesmn	0:3ac96e360672	4787	if (utemp32a > 0xFFFF)
charlesmn	0:3ac96e360672	4788	utemp32a = 0xFFFF;
charlesmn	0:3ac96e360672	4789
charlesmn	0:3ac96e360672	4790
charlesmn	0:3ac96e360672	4791
charlesmn	0:3ac96e360672	4792	utemp32a = utemp32a << 16;
charlesmn	0:3ac96e360672	4793
charlesmn	0:3ac96e360672	4794
charlesmn	0:3ac96e360672	4795	if (pdev->sys_results.result__dss_actual_effective_spads_sd0 == 0)
charlesmn	0:3ac96e360672	4796	status = VL53L1_ERROR_DIVISION_BY_ZERO;
charlesmn	0:3ac96e360672	4797	else {
charlesmn	0:3ac96e360672	4798
charlesmn	0:3ac96e360672	4799	utemp32a = utemp32a /
charlesmn	0:3ac96e360672	4800	pdev->sys_results.result__dss_actual_effective_spads_sd0;
charlesmn	0:3ac96e360672	4801
charlesmn	0:3ac96e360672	4802	pdev->low_power_auto_data.dss__total_rate_per_spad_mcps =
charlesmn	0:3ac96e360672	4803	utemp32a;
charlesmn	0:3ac96e360672	4804
charlesmn	0:3ac96e360672	4805
charlesmn	0:3ac96e360672	4806	utemp32a = pdev->stat_cfg.dss_config__target_total_rate_mcps <<
charlesmn	0:3ac96e360672	4807	16;
charlesmn	0:3ac96e360672	4808
charlesmn	0:3ac96e360672	4809
charlesmn	0:3ac96e360672	4810	if (pdev->low_power_auto_data.dss__total_rate_per_spad_mcps
charlesmn	0:3ac96e360672	4811	== 0)
charlesmn	0:3ac96e360672	4812	status = VL53L1_ERROR_DIVISION_BY_ZERO;
charlesmn	0:3ac96e360672	4813	else {
charlesmn	0:3ac96e360672	4814
charlesmn	0:3ac96e360672	4815	utemp32a = utemp32a /
charlesmn	0:3ac96e360672	4816	pdev->low_power_auto_data.dss__total_rate_per_spad_mcps;
charlesmn	0:3ac96e360672	4817
charlesmn	0:3ac96e360672	4818
charlesmn	0:3ac96e360672	4819	if (utemp32a > 0xFFFF)
charlesmn	0:3ac96e360672	4820	utemp32a = 0xFFFF;
charlesmn	0:3ac96e360672	4821
charlesmn	0:3ac96e360672	4822
charlesmn	0:3ac96e360672	4823	pdev->low_power_auto_data.dss__required_spads =
charlesmn	0:3ac96e360672	4824	(uint16_t)utemp32a;
charlesmn	0:3ac96e360672	4825
charlesmn	0:3ac96e360672	4826
charlesmn	0:3ac96e360672	4827	pdev->gen_cfg.dss_config__manual_effective_spads_select
charlesmn	0:3ac96e360672	4828	= pdev->low_power_auto_data.dss__required_spads;
charlesmn	0:3ac96e360672	4829	pdev->gen_cfg.dss_config__roi_mode_control =
charlesmn	0:3ac96e360672	4830	VL53L1_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS;
charlesmn	0:3ac96e360672	4831	}
charlesmn	0:3ac96e360672	4832
charlesmn	0:3ac96e360672	4833	}
charlesmn	0:3ac96e360672	4834
charlesmn	0:3ac96e360672	4835	if (status == VL53L1_ERROR_DIVISION_BY_ZERO) {
charlesmn	0:3ac96e360672	4836
charlesmn	0:3ac96e360672	4837
charlesmn	0:3ac96e360672	4838
charlesmn	0:3ac96e360672	4839	pdev->low_power_auto_data.dss__required_spads = 0x8000;
charlesmn	0:3ac96e360672	4840
charlesmn	0:3ac96e360672	4841
charlesmn	0:3ac96e360672	4842	pdev->gen_cfg.dss_config__manual_effective_spads_select =
charlesmn	0:3ac96e360672	4843	pdev->low_power_auto_data.dss__required_spads;
charlesmn	0:3ac96e360672	4844	pdev->gen_cfg.dss_config__roi_mode_control =
charlesmn	0:3ac96e360672	4845	VL53L1_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS;
charlesmn	0:3ac96e360672	4846
charlesmn	0:3ac96e360672	4847
charlesmn	0:3ac96e360672	4848	status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4849	}
charlesmn	0:3ac96e360672	4850
charlesmn	0:3ac96e360672	4851	LOG_FUNCTION_END(status);
charlesmn	0:3ac96e360672	4852
charlesmn	0:3ac96e360672	4853	return status;
charlesmn	0:3ac96e360672	4854	}
charlesmn	0:3ac96e360672	4855
charlesmn	0:3ac96e360672	4856
charlesmn	0:3ac96e360672	4857
charlesmn	0:3ac96e360672	4858
charlesmn	0:3ac96e360672	4859	VL53L1_Error VL53L1_compute_histo_merge_nb(
charlesmn	0:3ac96e360672	4860	VL53L1_DEV Dev, uint8_t *histo_merge_nb)
charlesmn	0:3ac96e360672	4861	{
charlesmn	0:3ac96e360672	4862	VL53L1_LLDriverData_t *pdev = VL53L1DevStructGetLLDriverHandle(Dev);
charlesmn	0:3ac96e360672	4863	VL53L1_Error status = VL53L1_ERROR_NONE;
charlesmn	0:3ac96e360672	4864	uint8_t i, timing;
charlesmn	0:3ac96e360672	4865	uint8_t sum = 0;
charlesmn	0:3ac96e360672	4866
charlesmn	0:3ac96e360672	4867	timing = (pdev->hist_data.bin_seq[0] == 7 ? 1 : 0);
charlesmn	0:3ac96e360672	4868	for (i = 0; i < VL53L1_BIN_REC_SIZE; i++)
charlesmn	0:3ac96e360672	4869	if (pdev->multi_bins_rec[i][timing][7] > 0)
charlesmn	0:3ac96e360672	4870	sum++;
charlesmn	0:3ac96e360672	4871	*histo_merge_nb = sum;
charlesmn	0:3ac96e360672	4872
charlesmn	0:3ac96e360672	4873	return status;
charlesmn	0:3ac96e360672	4874	}
charlesmn	0:3ac96e360672	4875
charlesmn	0:3ac96e360672	4876

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Type:	Library
Created:	06 Oct 2020
Imports:	8
Forks:	0
Commits:	19
Dependents:	3
Dependencies:	2
Followers:	63

src/vl53l1_core.c@0:3ac96e360672, 2020-11-06 (annotated)

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