ST Expansion SW Team
/
VL53L1CB
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: VL53L1CB_noshield_1sensor_polls_auton VL53L1CB_noshield_1sensor_interrupt_auton X_NUCLEO_53L1A2
inc/vl53l1_register_structs.h@0:3ac96e360672, 2020-11-06 (annotated)
- Committer:
- charlesmn
- Date:
- Fri Nov 06 10:06:37 2020 +0000
- Revision:
- 0:3ac96e360672
- Child:
- 7:1add29d51e72
Library for ST Vl53L1A1 time of flight sensor.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| charlesmn | 0:3ac96e360672 | 1 | |
| charlesmn | 0:3ac96e360672 | 2 | /******************************************************************************* |
| charlesmn | 0:3ac96e360672 | 3 | * Copyright (c) 2020, STMicroelectronics - All Rights Reserved |
| charlesmn | 0:3ac96e360672 | 4 | |
| charlesmn | 0:3ac96e360672 | 5 | This file is part of VL53L1 Core and is dual licensed, |
| charlesmn | 0:3ac96e360672 | 6 | either 'STMicroelectronics |
| charlesmn | 0:3ac96e360672 | 7 | Proprietary license' |
| charlesmn | 0:3ac96e360672 | 8 | or 'BSD 3-clause "New" or "Revised" License' , at your option. |
| charlesmn | 0:3ac96e360672 | 9 | |
| charlesmn | 0:3ac96e360672 | 10 | ******************************************************************************** |
| charlesmn | 0:3ac96e360672 | 11 | |
| charlesmn | 0:3ac96e360672 | 12 | 'STMicroelectronics Proprietary license' |
| charlesmn | 0:3ac96e360672 | 13 | |
| charlesmn | 0:3ac96e360672 | 14 | ******************************************************************************** |
| charlesmn | 0:3ac96e360672 | 15 | |
| charlesmn | 0:3ac96e360672 | 16 | License terms: STMicroelectronics Proprietary in accordance with licensing |
| charlesmn | 0:3ac96e360672 | 17 | terms at www.st.com/sla0081 |
| charlesmn | 0:3ac96e360672 | 18 | |
| charlesmn | 0:3ac96e360672 | 19 | STMicroelectronics confidential |
| charlesmn | 0:3ac96e360672 | 20 | Reproduction and Communication of this document is strictly prohibited unless |
| charlesmn | 0:3ac96e360672 | 21 | specifically authorized in writing by STMicroelectronics. |
| charlesmn | 0:3ac96e360672 | 22 | |
| charlesmn | 0:3ac96e360672 | 23 | |
| charlesmn | 0:3ac96e360672 | 24 | ******************************************************************************** |
| charlesmn | 0:3ac96e360672 | 25 | |
| charlesmn | 0:3ac96e360672 | 26 | Alternatively, VL53L1 Core may be distributed under the terms of |
| charlesmn | 0:3ac96e360672 | 27 | 'BSD 3-clause "New" or "Revised" License', in which case the following |
| charlesmn | 0:3ac96e360672 | 28 | provisions apply instead of the ones |
| charlesmn | 0:3ac96e360672 | 29 | mentioned above : |
| charlesmn | 0:3ac96e360672 | 30 | |
| charlesmn | 0:3ac96e360672 | 31 | ******************************************************************************** |
| charlesmn | 0:3ac96e360672 | 32 | |
| charlesmn | 0:3ac96e360672 | 33 | License terms: BSD 3-clause "New" or "Revised" License. |
| charlesmn | 0:3ac96e360672 | 34 | |
| charlesmn | 0:3ac96e360672 | 35 | Redistribution and use in source and binary forms, with or without |
| charlesmn | 0:3ac96e360672 | 36 | modification, are permitted provided that the following conditions are met: |
| charlesmn | 0:3ac96e360672 | 37 | |
| charlesmn | 0:3ac96e360672 | 38 | 1. Redistributions of source code must retain the above copyright notice, this |
| charlesmn | 0:3ac96e360672 | 39 | list of conditions and the following disclaimer. |
| charlesmn | 0:3ac96e360672 | 40 | |
| charlesmn | 0:3ac96e360672 | 41 | 2. Redistributions in binary form must reproduce the above copyright notice, |
| charlesmn | 0:3ac96e360672 | 42 | this list of conditions and the following disclaimer in the documentation |
| charlesmn | 0:3ac96e360672 | 43 | and/or other materials provided with the distribution. |
| charlesmn | 0:3ac96e360672 | 44 | |
| charlesmn | 0:3ac96e360672 | 45 | 3. Neither the name of the copyright holder nor the names of its contributors |
| charlesmn | 0:3ac96e360672 | 46 | may be used to endorse or promote products derived from this software |
| charlesmn | 0:3ac96e360672 | 47 | without specific prior written permission. |
| charlesmn | 0:3ac96e360672 | 48 | |
| charlesmn | 0:3ac96e360672 | 49 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| charlesmn | 0:3ac96e360672 | 50 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| charlesmn | 0:3ac96e360672 | 51 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| charlesmn | 0:3ac96e360672 | 52 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| charlesmn | 0:3ac96e360672 | 53 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| charlesmn | 0:3ac96e360672 | 54 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| charlesmn | 0:3ac96e360672 | 55 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| charlesmn | 0:3ac96e360672 | 56 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| charlesmn | 0:3ac96e360672 | 57 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| charlesmn | 0:3ac96e360672 | 58 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| charlesmn | 0:3ac96e360672 | 59 | |
| charlesmn | 0:3ac96e360672 | 60 | |
| charlesmn | 0:3ac96e360672 | 61 | ******************************************************************************** |
| charlesmn | 0:3ac96e360672 | 62 | |
| charlesmn | 0:3ac96e360672 | 63 | */ |
| charlesmn | 0:3ac96e360672 | 64 | |
| charlesmn | 0:3ac96e360672 | 65 | |
| charlesmn | 0:3ac96e360672 | 66 | |
| charlesmn | 0:3ac96e360672 | 67 | |
| charlesmn | 0:3ac96e360672 | 68 | #ifndef _VL53L1_REGISTER_STRUCTS_H_ |
| charlesmn | 0:3ac96e360672 | 69 | #define _VL53L1_REGISTER_STRUCTS_H_ |
| charlesmn | 0:3ac96e360672 | 70 | |
| charlesmn | 0:3ac96e360672 | 71 | #include "vl53l1_types.h" |
| charlesmn | 0:3ac96e360672 | 72 | #include "vl53l1_register_map.h" |
| charlesmn | 0:3ac96e360672 | 73 | |
| charlesmn | 0:3ac96e360672 | 74 | #define VL53L1_STATIC_NVM_MANAGED_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 75 | VL53L1_I2C_SLAVE__DEVICE_ADDRESS |
| charlesmn | 0:3ac96e360672 | 76 | #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 77 | VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 |
| charlesmn | 0:3ac96e360672 | 78 | #define VL53L1_STATIC_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 79 | VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS |
| charlesmn | 0:3ac96e360672 | 80 | #define VL53L1_GENERAL_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 81 | VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE |
| charlesmn | 0:3ac96e360672 | 82 | #define VL53L1_TIMING_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 83 | VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI |
| charlesmn | 0:3ac96e360672 | 84 | #define VL53L1_DYNAMIC_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 85 | VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0 |
| charlesmn | 0:3ac96e360672 | 86 | #define VL53L1_SYSTEM_CONTROL_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 87 | VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE |
| charlesmn | 0:3ac96e360672 | 88 | #define VL53L1_SYSTEM_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 89 | VL53L1_RESULT__INTERRUPT_STATUS |
| charlesmn | 0:3ac96e360672 | 90 | #define VL53L1_CORE_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 91 | VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 |
| charlesmn | 0:3ac96e360672 | 92 | #define VL53L1_DEBUG_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 93 | VL53L1_PHASECAL_RESULT__REFERENCE_PHASE |
| charlesmn | 0:3ac96e360672 | 94 | #define VL53L1_NVM_COPY_DATA_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 95 | VL53L1_IDENTIFICATION__MODEL_ID |
| charlesmn | 0:3ac96e360672 | 96 | #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 97 | VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS |
| charlesmn | 0:3ac96e360672 | 98 | #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 99 | VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 |
| charlesmn | 0:3ac96e360672 | 100 | #define VL53L1_PATCH_DEBUG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 101 | VL53L1_RESULT__DEBUG_STATUS |
| charlesmn | 0:3ac96e360672 | 102 | #define VL53L1_GPH_GENERAL_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 103 | VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH |
| charlesmn | 0:3ac96e360672 | 104 | #define VL53L1_GPH_STATIC_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 105 | VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL |
| charlesmn | 0:3ac96e360672 | 106 | #define VL53L1_GPH_TIMING_CONFIG_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 107 | VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI |
| charlesmn | 0:3ac96e360672 | 108 | #define VL53L1_FW_INTERNAL_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 109 | VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV |
| charlesmn | 0:3ac96e360672 | 110 | #define VL53L1_PATCH_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 111 | VL53L1_DSS_CALC__ROI_CTRL |
| charlesmn | 0:3ac96e360672 | 112 | #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 113 | VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START |
| charlesmn | 0:3ac96e360672 | 114 | #define VL53L1_SHADOW_CORE_RESULTS_I2C_INDEX \ |
| charlesmn | 0:3ac96e360672 | 115 | VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 |
| charlesmn | 0:3ac96e360672 | 116 | |
| charlesmn | 0:3ac96e360672 | 117 | #define VL53L1_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11 |
| charlesmn | 0:3ac96e360672 | 118 | #define VL53L1_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23 |
| charlesmn | 0:3ac96e360672 | 119 | #define VL53L1_STATIC_CONFIG_I2C_SIZE_BYTES 32 |
| charlesmn | 0:3ac96e360672 | 120 | #define VL53L1_GENERAL_CONFIG_I2C_SIZE_BYTES 22 |
| charlesmn | 0:3ac96e360672 | 121 | #define VL53L1_TIMING_CONFIG_I2C_SIZE_BYTES 23 |
| charlesmn | 0:3ac96e360672 | 122 | #define VL53L1_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18 |
| charlesmn | 0:3ac96e360672 | 123 | #define VL53L1_SYSTEM_CONTROL_I2C_SIZE_BYTES 5 |
| charlesmn | 0:3ac96e360672 | 124 | #define VL53L1_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 |
| charlesmn | 0:3ac96e360672 | 125 | #define VL53L1_CORE_RESULTS_I2C_SIZE_BYTES 33 |
| charlesmn | 0:3ac96e360672 | 126 | #define VL53L1_DEBUG_RESULTS_I2C_SIZE_BYTES 56 |
| charlesmn | 0:3ac96e360672 | 127 | #define VL53L1_NVM_COPY_DATA_I2C_SIZE_BYTES 49 |
| charlesmn | 0:3ac96e360672 | 128 | #define VL53L1_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 |
| charlesmn | 0:3ac96e360672 | 129 | #define VL53L1_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 |
| charlesmn | 0:3ac96e360672 | 130 | #define VL53L1_PATCH_DEBUG_I2C_SIZE_BYTES 2 |
| charlesmn | 0:3ac96e360672 | 131 | #define VL53L1_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5 |
| charlesmn | 0:3ac96e360672 | 132 | #define VL53L1_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6 |
| charlesmn | 0:3ac96e360672 | 133 | #define VL53L1_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16 |
| charlesmn | 0:3ac96e360672 | 134 | #define VL53L1_FW_INTERNAL_I2C_SIZE_BYTES 2 |
| charlesmn | 0:3ac96e360672 | 135 | #define VL53L1_PATCH_RESULTS_I2C_SIZE_BYTES 90 |
| charlesmn | 0:3ac96e360672 | 136 | #define VL53L1_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82 |
| charlesmn | 0:3ac96e360672 | 137 | #define VL53L1_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 |
| charlesmn | 0:3ac96e360672 | 138 | |
| charlesmn | 0:3ac96e360672 | 139 | |
| charlesmn | 0:3ac96e360672 | 140 | |
| charlesmn | 0:3ac96e360672 | 141 | |
| charlesmn | 0:3ac96e360672 | 142 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 143 | uint8_t i2c_slave__device_address; |
| charlesmn | 0:3ac96e360672 | 144 | |
| charlesmn | 0:3ac96e360672 | 145 | uint8_t ana_config__vhv_ref_sel_vddpix; |
| charlesmn | 0:3ac96e360672 | 146 | |
| charlesmn | 0:3ac96e360672 | 147 | uint8_t ana_config__vhv_ref_sel_vquench; |
| charlesmn | 0:3ac96e360672 | 148 | |
| charlesmn | 0:3ac96e360672 | 149 | uint8_t ana_config__reg_avdd1v2_sel; |
| charlesmn | 0:3ac96e360672 | 150 | |
| charlesmn | 0:3ac96e360672 | 151 | uint8_t ana_config__fast_osc__trim; |
| charlesmn | 0:3ac96e360672 | 152 | |
| charlesmn | 0:3ac96e360672 | 153 | uint16_t osc_measured__fast_osc__frequency; |
| charlesmn | 0:3ac96e360672 | 154 | |
| charlesmn | 0:3ac96e360672 | 155 | uint8_t vhv_config__timeout_macrop_loop_bound; |
| charlesmn | 0:3ac96e360672 | 156 | |
| charlesmn | 0:3ac96e360672 | 157 | uint8_t vhv_config__count_thresh; |
| charlesmn | 0:3ac96e360672 | 158 | |
| charlesmn | 0:3ac96e360672 | 159 | uint8_t vhv_config__offset; |
| charlesmn | 0:3ac96e360672 | 160 | |
| charlesmn | 0:3ac96e360672 | 161 | uint8_t vhv_config__init; |
| charlesmn | 0:3ac96e360672 | 162 | |
| charlesmn | 0:3ac96e360672 | 163 | } VL53L1_static_nvm_managed_t; |
| charlesmn | 0:3ac96e360672 | 164 | |
| charlesmn | 0:3ac96e360672 | 165 | |
| charlesmn | 0:3ac96e360672 | 166 | |
| charlesmn | 0:3ac96e360672 | 167 | |
| charlesmn | 0:3ac96e360672 | 168 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 169 | uint8_t global_config__spad_enables_ref_0; |
| charlesmn | 0:3ac96e360672 | 170 | |
| charlesmn | 0:3ac96e360672 | 171 | uint8_t global_config__spad_enables_ref_1; |
| charlesmn | 0:3ac96e360672 | 172 | |
| charlesmn | 0:3ac96e360672 | 173 | uint8_t global_config__spad_enables_ref_2; |
| charlesmn | 0:3ac96e360672 | 174 | |
| charlesmn | 0:3ac96e360672 | 175 | uint8_t global_config__spad_enables_ref_3; |
| charlesmn | 0:3ac96e360672 | 176 | |
| charlesmn | 0:3ac96e360672 | 177 | uint8_t global_config__spad_enables_ref_4; |
| charlesmn | 0:3ac96e360672 | 178 | |
| charlesmn | 0:3ac96e360672 | 179 | uint8_t global_config__spad_enables_ref_5; |
| charlesmn | 0:3ac96e360672 | 180 | |
| charlesmn | 0:3ac96e360672 | 181 | uint8_t global_config__ref_en_start_select; |
| charlesmn | 0:3ac96e360672 | 182 | |
| charlesmn | 0:3ac96e360672 | 183 | uint8_t ref_spad_man__num_requested_ref_spads; |
| charlesmn | 0:3ac96e360672 | 184 | |
| charlesmn | 0:3ac96e360672 | 185 | uint8_t ref_spad_man__ref_location; |
| charlesmn | 0:3ac96e360672 | 186 | |
| charlesmn | 0:3ac96e360672 | 187 | uint16_t algo__crosstalk_compensation_plane_offset_kcps; |
| charlesmn | 0:3ac96e360672 | 188 | |
| charlesmn | 0:3ac96e360672 | 189 | int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; |
| charlesmn | 0:3ac96e360672 | 190 | |
| charlesmn | 0:3ac96e360672 | 191 | int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; |
| charlesmn | 0:3ac96e360672 | 192 | |
| charlesmn | 0:3ac96e360672 | 193 | uint16_t ref_spad_char__total_rate_target_mcps; |
| charlesmn | 0:3ac96e360672 | 194 | |
| charlesmn | 0:3ac96e360672 | 195 | int16_t algo__part_to_part_range_offset_mm; |
| charlesmn | 0:3ac96e360672 | 196 | |
| charlesmn | 0:3ac96e360672 | 197 | int16_t mm_config__inner_offset_mm; |
| charlesmn | 0:3ac96e360672 | 198 | |
| charlesmn | 0:3ac96e360672 | 199 | int16_t mm_config__outer_offset_mm; |
| charlesmn | 0:3ac96e360672 | 200 | |
| charlesmn | 0:3ac96e360672 | 201 | } VL53L1_customer_nvm_managed_t; |
| charlesmn | 0:3ac96e360672 | 202 | |
| charlesmn | 0:3ac96e360672 | 203 | |
| charlesmn | 0:3ac96e360672 | 204 | |
| charlesmn | 0:3ac96e360672 | 205 | |
| charlesmn | 0:3ac96e360672 | 206 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 207 | uint16_t dss_config__target_total_rate_mcps; |
| charlesmn | 0:3ac96e360672 | 208 | |
| charlesmn | 0:3ac96e360672 | 209 | uint8_t debug__ctrl; |
| charlesmn | 0:3ac96e360672 | 210 | |
| charlesmn | 0:3ac96e360672 | 211 | uint8_t test_mode__ctrl; |
| charlesmn | 0:3ac96e360672 | 212 | |
| charlesmn | 0:3ac96e360672 | 213 | uint8_t clk_gating__ctrl; |
| charlesmn | 0:3ac96e360672 | 214 | |
| charlesmn | 0:3ac96e360672 | 215 | uint8_t nvm_bist__ctrl; |
| charlesmn | 0:3ac96e360672 | 216 | |
| charlesmn | 0:3ac96e360672 | 217 | uint8_t nvm_bist__num_nvm_words; |
| charlesmn | 0:3ac96e360672 | 218 | |
| charlesmn | 0:3ac96e360672 | 219 | uint8_t nvm_bist__start_address; |
| charlesmn | 0:3ac96e360672 | 220 | |
| charlesmn | 0:3ac96e360672 | 221 | uint8_t host_if__status; |
| charlesmn | 0:3ac96e360672 | 222 | |
| charlesmn | 0:3ac96e360672 | 223 | uint8_t pad_i2c_hv__config; |
| charlesmn | 0:3ac96e360672 | 224 | |
| charlesmn | 0:3ac96e360672 | 225 | uint8_t pad_i2c_hv__extsup_config; |
| charlesmn | 0:3ac96e360672 | 226 | |
| charlesmn | 0:3ac96e360672 | 227 | uint8_t gpio_hv_pad__ctrl; |
| charlesmn | 0:3ac96e360672 | 228 | |
| charlesmn | 0:3ac96e360672 | 229 | uint8_t gpio_hv_mux__ctrl; |
| charlesmn | 0:3ac96e360672 | 230 | |
| charlesmn | 0:3ac96e360672 | 231 | uint8_t gpio__tio_hv_status; |
| charlesmn | 0:3ac96e360672 | 232 | |
| charlesmn | 0:3ac96e360672 | 233 | uint8_t gpio__fio_hv_status; |
| charlesmn | 0:3ac96e360672 | 234 | |
| charlesmn | 0:3ac96e360672 | 235 | uint8_t ana_config__spad_sel_pswidth; |
| charlesmn | 0:3ac96e360672 | 236 | |
| charlesmn | 0:3ac96e360672 | 237 | uint8_t ana_config__vcsel_pulse_width_offset; |
| charlesmn | 0:3ac96e360672 | 238 | |
| charlesmn | 0:3ac96e360672 | 239 | uint8_t ana_config__fast_osc__config_ctrl; |
| charlesmn | 0:3ac96e360672 | 240 | |
| charlesmn | 0:3ac96e360672 | 241 | uint8_t sigma_estimator__effective_pulse_width_ns; |
| charlesmn | 0:3ac96e360672 | 242 | |
| charlesmn | 0:3ac96e360672 | 243 | uint8_t sigma_estimator__effective_ambient_width_ns; |
| charlesmn | 0:3ac96e360672 | 244 | |
| charlesmn | 0:3ac96e360672 | 245 | uint8_t sigma_estimator__sigma_ref_mm; |
| charlesmn | 0:3ac96e360672 | 246 | |
| charlesmn | 0:3ac96e360672 | 247 | uint8_t algo__crosstalk_compensation_valid_height_mm; |
| charlesmn | 0:3ac96e360672 | 248 | |
| charlesmn | 0:3ac96e360672 | 249 | uint8_t spare_host_config__static_config_spare_0; |
| charlesmn | 0:3ac96e360672 | 250 | |
| charlesmn | 0:3ac96e360672 | 251 | uint8_t spare_host_config__static_config_spare_1; |
| charlesmn | 0:3ac96e360672 | 252 | |
| charlesmn | 0:3ac96e360672 | 253 | uint16_t algo__range_ignore_threshold_mcps; |
| charlesmn | 0:3ac96e360672 | 254 | |
| charlesmn | 0:3ac96e360672 | 255 | uint8_t algo__range_ignore_valid_height_mm; |
| charlesmn | 0:3ac96e360672 | 256 | |
| charlesmn | 0:3ac96e360672 | 257 | uint8_t algo__range_min_clip; |
| charlesmn | 0:3ac96e360672 | 258 | |
| charlesmn | 0:3ac96e360672 | 259 | uint8_t algo__consistency_check__tolerance; |
| charlesmn | 0:3ac96e360672 | 260 | |
| charlesmn | 0:3ac96e360672 | 261 | uint8_t spare_host_config__static_config_spare_2; |
| charlesmn | 0:3ac96e360672 | 262 | |
| charlesmn | 0:3ac96e360672 | 263 | uint8_t sd_config__reset_stages_msb; |
| charlesmn | 0:3ac96e360672 | 264 | |
| charlesmn | 0:3ac96e360672 | 265 | uint8_t sd_config__reset_stages_lsb; |
| charlesmn | 0:3ac96e360672 | 266 | |
| charlesmn | 0:3ac96e360672 | 267 | } VL53L1_static_config_t; |
| charlesmn | 0:3ac96e360672 | 268 | |
| charlesmn | 0:3ac96e360672 | 269 | |
| charlesmn | 0:3ac96e360672 | 270 | |
| charlesmn | 0:3ac96e360672 | 271 | |
| charlesmn | 0:3ac96e360672 | 272 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 273 | uint8_t gph_config__stream_count_update_value; |
| charlesmn | 0:3ac96e360672 | 274 | |
| charlesmn | 0:3ac96e360672 | 275 | uint8_t global_config__stream_divider; |
| charlesmn | 0:3ac96e360672 | 276 | |
| charlesmn | 0:3ac96e360672 | 277 | uint8_t system__interrupt_config_gpio; |
| charlesmn | 0:3ac96e360672 | 278 | |
| charlesmn | 0:3ac96e360672 | 279 | uint8_t cal_config__vcsel_start; |
| charlesmn | 0:3ac96e360672 | 280 | |
| charlesmn | 0:3ac96e360672 | 281 | uint16_t cal_config__repeat_rate; |
| charlesmn | 0:3ac96e360672 | 282 | |
| charlesmn | 0:3ac96e360672 | 283 | uint8_t global_config__vcsel_width; |
| charlesmn | 0:3ac96e360672 | 284 | |
| charlesmn | 0:3ac96e360672 | 285 | uint8_t phasecal_config__timeout_macrop; |
| charlesmn | 0:3ac96e360672 | 286 | |
| charlesmn | 0:3ac96e360672 | 287 | uint8_t phasecal_config__target; |
| charlesmn | 0:3ac96e360672 | 288 | |
| charlesmn | 0:3ac96e360672 | 289 | uint8_t phasecal_config__override; |
| charlesmn | 0:3ac96e360672 | 290 | |
| charlesmn | 0:3ac96e360672 | 291 | uint8_t dss_config__roi_mode_control; |
| charlesmn | 0:3ac96e360672 | 292 | |
| charlesmn | 0:3ac96e360672 | 293 | uint16_t system__thresh_rate_high; |
| charlesmn | 0:3ac96e360672 | 294 | |
| charlesmn | 0:3ac96e360672 | 295 | uint16_t system__thresh_rate_low; |
| charlesmn | 0:3ac96e360672 | 296 | |
| charlesmn | 0:3ac96e360672 | 297 | uint16_t dss_config__manual_effective_spads_select; |
| charlesmn | 0:3ac96e360672 | 298 | |
| charlesmn | 0:3ac96e360672 | 299 | uint8_t dss_config__manual_block_select; |
| charlesmn | 0:3ac96e360672 | 300 | |
| charlesmn | 0:3ac96e360672 | 301 | uint8_t dss_config__aperture_attenuation; |
| charlesmn | 0:3ac96e360672 | 302 | |
| charlesmn | 0:3ac96e360672 | 303 | uint8_t dss_config__max_spads_limit; |
| charlesmn | 0:3ac96e360672 | 304 | |
| charlesmn | 0:3ac96e360672 | 305 | uint8_t dss_config__min_spads_limit; |
| charlesmn | 0:3ac96e360672 | 306 | |
| charlesmn | 0:3ac96e360672 | 307 | } VL53L1_general_config_t; |
| charlesmn | 0:3ac96e360672 | 308 | |
| charlesmn | 0:3ac96e360672 | 309 | |
| charlesmn | 0:3ac96e360672 | 310 | |
| charlesmn | 0:3ac96e360672 | 311 | |
| charlesmn | 0:3ac96e360672 | 312 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 313 | uint8_t mm_config__timeout_macrop_a_hi; |
| charlesmn | 0:3ac96e360672 | 314 | |
| charlesmn | 0:3ac96e360672 | 315 | uint8_t mm_config__timeout_macrop_a_lo; |
| charlesmn | 0:3ac96e360672 | 316 | |
| charlesmn | 0:3ac96e360672 | 317 | uint8_t mm_config__timeout_macrop_b_hi; |
| charlesmn | 0:3ac96e360672 | 318 | |
| charlesmn | 0:3ac96e360672 | 319 | uint8_t mm_config__timeout_macrop_b_lo; |
| charlesmn | 0:3ac96e360672 | 320 | |
| charlesmn | 0:3ac96e360672 | 321 | uint8_t range_config__timeout_macrop_a_hi; |
| charlesmn | 0:3ac96e360672 | 322 | |
| charlesmn | 0:3ac96e360672 | 323 | uint8_t range_config__timeout_macrop_a_lo; |
| charlesmn | 0:3ac96e360672 | 324 | |
| charlesmn | 0:3ac96e360672 | 325 | uint8_t range_config__vcsel_period_a; |
| charlesmn | 0:3ac96e360672 | 326 | |
| charlesmn | 0:3ac96e360672 | 327 | uint8_t range_config__timeout_macrop_b_hi; |
| charlesmn | 0:3ac96e360672 | 328 | |
| charlesmn | 0:3ac96e360672 | 329 | uint8_t range_config__timeout_macrop_b_lo; |
| charlesmn | 0:3ac96e360672 | 330 | |
| charlesmn | 0:3ac96e360672 | 331 | uint8_t range_config__vcsel_period_b; |
| charlesmn | 0:3ac96e360672 | 332 | |
| charlesmn | 0:3ac96e360672 | 333 | uint16_t range_config__sigma_thresh; |
| charlesmn | 0:3ac96e360672 | 334 | |
| charlesmn | 0:3ac96e360672 | 335 | uint16_t range_config__min_count_rate_rtn_limit_mcps; |
| charlesmn | 0:3ac96e360672 | 336 | |
| charlesmn | 0:3ac96e360672 | 337 | uint8_t range_config__valid_phase_low; |
| charlesmn | 0:3ac96e360672 | 338 | |
| charlesmn | 0:3ac96e360672 | 339 | uint8_t range_config__valid_phase_high; |
| charlesmn | 0:3ac96e360672 | 340 | |
| charlesmn | 0:3ac96e360672 | 341 | uint32_t system__intermeasurement_period; |
| charlesmn | 0:3ac96e360672 | 342 | |
| charlesmn | 0:3ac96e360672 | 343 | uint8_t system__fractional_enable; |
| charlesmn | 0:3ac96e360672 | 344 | |
| charlesmn | 0:3ac96e360672 | 345 | } VL53L1_timing_config_t; |
| charlesmn | 0:3ac96e360672 | 346 | |
| charlesmn | 0:3ac96e360672 | 347 | |
| charlesmn | 0:3ac96e360672 | 348 | |
| charlesmn | 0:3ac96e360672 | 349 | |
| charlesmn | 0:3ac96e360672 | 350 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 351 | uint8_t system__grouped_parameter_hold_0; |
| charlesmn | 0:3ac96e360672 | 352 | |
| charlesmn | 0:3ac96e360672 | 353 | uint16_t system__thresh_high; |
| charlesmn | 0:3ac96e360672 | 354 | |
| charlesmn | 0:3ac96e360672 | 355 | uint16_t system__thresh_low; |
| charlesmn | 0:3ac96e360672 | 356 | |
| charlesmn | 0:3ac96e360672 | 357 | uint8_t system__enable_xtalk_per_quadrant; |
| charlesmn | 0:3ac96e360672 | 358 | |
| charlesmn | 0:3ac96e360672 | 359 | uint8_t system__seed_config; |
| charlesmn | 0:3ac96e360672 | 360 | |
| charlesmn | 0:3ac96e360672 | 361 | uint8_t sd_config__woi_sd0; |
| charlesmn | 0:3ac96e360672 | 362 | |
| charlesmn | 0:3ac96e360672 | 363 | uint8_t sd_config__woi_sd1; |
| charlesmn | 0:3ac96e360672 | 364 | |
| charlesmn | 0:3ac96e360672 | 365 | uint8_t sd_config__initial_phase_sd0; |
| charlesmn | 0:3ac96e360672 | 366 | |
| charlesmn | 0:3ac96e360672 | 367 | uint8_t sd_config__initial_phase_sd1; |
| charlesmn | 0:3ac96e360672 | 368 | |
| charlesmn | 0:3ac96e360672 | 369 | uint8_t system__grouped_parameter_hold_1; |
| charlesmn | 0:3ac96e360672 | 370 | |
| charlesmn | 0:3ac96e360672 | 371 | uint8_t sd_config__first_order_select; |
| charlesmn | 0:3ac96e360672 | 372 | |
| charlesmn | 0:3ac96e360672 | 373 | uint8_t sd_config__quantifier; |
| charlesmn | 0:3ac96e360672 | 374 | |
| charlesmn | 0:3ac96e360672 | 375 | uint8_t roi_config__user_roi_centre_spad; |
| charlesmn | 0:3ac96e360672 | 376 | |
| charlesmn | 0:3ac96e360672 | 377 | uint8_t roi_config__user_roi_requested_global_xy_size; |
| charlesmn | 0:3ac96e360672 | 378 | |
| charlesmn | 0:3ac96e360672 | 379 | uint8_t system__sequence_config; |
| charlesmn | 0:3ac96e360672 | 380 | |
| charlesmn | 0:3ac96e360672 | 381 | uint8_t system__grouped_parameter_hold; |
| charlesmn | 0:3ac96e360672 | 382 | |
| charlesmn | 0:3ac96e360672 | 383 | } VL53L1_dynamic_config_t; |
| charlesmn | 0:3ac96e360672 | 384 | |
| charlesmn | 0:3ac96e360672 | 385 | |
| charlesmn | 0:3ac96e360672 | 386 | |
| charlesmn | 0:3ac96e360672 | 387 | |
| charlesmn | 0:3ac96e360672 | 388 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 389 | uint8_t power_management__go1_power_force; |
| charlesmn | 0:3ac96e360672 | 390 | |
| charlesmn | 0:3ac96e360672 | 391 | uint8_t system__stream_count_ctrl; |
| charlesmn | 0:3ac96e360672 | 392 | |
| charlesmn | 0:3ac96e360672 | 393 | uint8_t firmware__enable; |
| charlesmn | 0:3ac96e360672 | 394 | |
| charlesmn | 0:3ac96e360672 | 395 | uint8_t system__interrupt_clear; |
| charlesmn | 0:3ac96e360672 | 396 | |
| charlesmn | 0:3ac96e360672 | 397 | uint8_t system__mode_start; |
| charlesmn | 0:3ac96e360672 | 398 | |
| charlesmn | 0:3ac96e360672 | 399 | } VL53L1_system_control_t; |
| charlesmn | 0:3ac96e360672 | 400 | |
| charlesmn | 0:3ac96e360672 | 401 | |
| charlesmn | 0:3ac96e360672 | 402 | |
| charlesmn | 0:3ac96e360672 | 403 | |
| charlesmn | 0:3ac96e360672 | 404 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 405 | uint8_t result__interrupt_status; |
| charlesmn | 0:3ac96e360672 | 406 | |
| charlesmn | 0:3ac96e360672 | 407 | uint8_t result__range_status; |
| charlesmn | 0:3ac96e360672 | 408 | |
| charlesmn | 0:3ac96e360672 | 409 | uint8_t result__report_status; |
| charlesmn | 0:3ac96e360672 | 410 | |
| charlesmn | 0:3ac96e360672 | 411 | uint8_t result__stream_count; |
| charlesmn | 0:3ac96e360672 | 412 | |
| charlesmn | 0:3ac96e360672 | 413 | uint16_t result__dss_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 414 | |
| charlesmn | 0:3ac96e360672 | 415 | uint16_t result__peak_signal_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 416 | |
| charlesmn | 0:3ac96e360672 | 417 | uint16_t result__ambient_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 418 | |
| charlesmn | 0:3ac96e360672 | 419 | uint16_t result__sigma_sd0; |
| charlesmn | 0:3ac96e360672 | 420 | |
| charlesmn | 0:3ac96e360672 | 421 | uint16_t result__phase_sd0; |
| charlesmn | 0:3ac96e360672 | 422 | |
| charlesmn | 0:3ac96e360672 | 423 | uint16_t result__final_crosstalk_corrected_range_mm_sd0; |
| charlesmn | 0:3ac96e360672 | 424 | |
| charlesmn | 0:3ac96e360672 | 425 | uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 426 | |
| charlesmn | 0:3ac96e360672 | 427 | uint16_t result__mm_inner_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 428 | |
| charlesmn | 0:3ac96e360672 | 429 | uint16_t result__mm_outer_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 430 | |
| charlesmn | 0:3ac96e360672 | 431 | uint16_t result__avg_signal_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 432 | |
| charlesmn | 0:3ac96e360672 | 433 | uint16_t result__dss_actual_effective_spads_sd1; |
| charlesmn | 0:3ac96e360672 | 434 | |
| charlesmn | 0:3ac96e360672 | 435 | uint16_t result__peak_signal_count_rate_mcps_sd1; |
| charlesmn | 0:3ac96e360672 | 436 | |
| charlesmn | 0:3ac96e360672 | 437 | uint16_t result__ambient_count_rate_mcps_sd1; |
| charlesmn | 0:3ac96e360672 | 438 | |
| charlesmn | 0:3ac96e360672 | 439 | uint16_t result__sigma_sd1; |
| charlesmn | 0:3ac96e360672 | 440 | |
| charlesmn | 0:3ac96e360672 | 441 | uint16_t result__phase_sd1; |
| charlesmn | 0:3ac96e360672 | 442 | |
| charlesmn | 0:3ac96e360672 | 443 | uint16_t result__final_crosstalk_corrected_range_mm_sd1; |
| charlesmn | 0:3ac96e360672 | 444 | |
| charlesmn | 0:3ac96e360672 | 445 | uint16_t result__spare_0_sd1; |
| charlesmn | 0:3ac96e360672 | 446 | |
| charlesmn | 0:3ac96e360672 | 447 | uint16_t result__spare_1_sd1; |
| charlesmn | 0:3ac96e360672 | 448 | |
| charlesmn | 0:3ac96e360672 | 449 | uint16_t result__spare_2_sd1; |
| charlesmn | 0:3ac96e360672 | 450 | |
| charlesmn | 0:3ac96e360672 | 451 | uint8_t result__spare_3_sd1; |
| charlesmn | 0:3ac96e360672 | 452 | |
| charlesmn | 0:3ac96e360672 | 453 | uint8_t result__thresh_info; |
| charlesmn | 0:3ac96e360672 | 454 | |
| charlesmn | 0:3ac96e360672 | 455 | } VL53L1_system_results_t; |
| charlesmn | 0:3ac96e360672 | 456 | |
| charlesmn | 0:3ac96e360672 | 457 | |
| charlesmn | 0:3ac96e360672 | 458 | |
| charlesmn | 0:3ac96e360672 | 459 | |
| charlesmn | 0:3ac96e360672 | 460 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 461 | uint32_t result_core__ambient_window_events_sd0; |
| charlesmn | 0:3ac96e360672 | 462 | |
| charlesmn | 0:3ac96e360672 | 463 | uint32_t result_core__ranging_total_events_sd0; |
| charlesmn | 0:3ac96e360672 | 464 | |
| charlesmn | 0:3ac96e360672 | 465 | int32_t result_core__signal_total_events_sd0; |
| charlesmn | 0:3ac96e360672 | 466 | |
| charlesmn | 0:3ac96e360672 | 467 | uint32_t result_core__total_periods_elapsed_sd0; |
| charlesmn | 0:3ac96e360672 | 468 | |
| charlesmn | 0:3ac96e360672 | 469 | uint32_t result_core__ambient_window_events_sd1; |
| charlesmn | 0:3ac96e360672 | 470 | |
| charlesmn | 0:3ac96e360672 | 471 | uint32_t result_core__ranging_total_events_sd1; |
| charlesmn | 0:3ac96e360672 | 472 | |
| charlesmn | 0:3ac96e360672 | 473 | int32_t result_core__signal_total_events_sd1; |
| charlesmn | 0:3ac96e360672 | 474 | |
| charlesmn | 0:3ac96e360672 | 475 | uint32_t result_core__total_periods_elapsed_sd1; |
| charlesmn | 0:3ac96e360672 | 476 | |
| charlesmn | 0:3ac96e360672 | 477 | uint8_t result_core__spare_0; |
| charlesmn | 0:3ac96e360672 | 478 | |
| charlesmn | 0:3ac96e360672 | 479 | } VL53L1_core_results_t; |
| charlesmn | 0:3ac96e360672 | 480 | |
| charlesmn | 0:3ac96e360672 | 481 | |
| charlesmn | 0:3ac96e360672 | 482 | |
| charlesmn | 0:3ac96e360672 | 483 | |
| charlesmn | 0:3ac96e360672 | 484 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 485 | uint16_t phasecal_result__reference_phase; |
| charlesmn | 0:3ac96e360672 | 486 | |
| charlesmn | 0:3ac96e360672 | 487 | uint8_t phasecal_result__vcsel_start; |
| charlesmn | 0:3ac96e360672 | 488 | |
| charlesmn | 0:3ac96e360672 | 489 | uint8_t ref_spad_char_result__num_actual_ref_spads; |
| charlesmn | 0:3ac96e360672 | 490 | |
| charlesmn | 0:3ac96e360672 | 491 | uint8_t ref_spad_char_result__ref_location; |
| charlesmn | 0:3ac96e360672 | 492 | |
| charlesmn | 0:3ac96e360672 | 493 | uint8_t vhv_result__coldboot_status; |
| charlesmn | 0:3ac96e360672 | 494 | |
| charlesmn | 0:3ac96e360672 | 495 | uint8_t vhv_result__search_result; |
| charlesmn | 0:3ac96e360672 | 496 | |
| charlesmn | 0:3ac96e360672 | 497 | uint8_t vhv_result__latest_setting; |
| charlesmn | 0:3ac96e360672 | 498 | |
| charlesmn | 0:3ac96e360672 | 499 | uint16_t result__osc_calibrate_val; |
| charlesmn | 0:3ac96e360672 | 500 | |
| charlesmn | 0:3ac96e360672 | 501 | uint8_t ana_config__powerdown_go1; |
| charlesmn | 0:3ac96e360672 | 502 | |
| charlesmn | 0:3ac96e360672 | 503 | uint8_t ana_config__ref_bg_ctrl; |
| charlesmn | 0:3ac96e360672 | 504 | |
| charlesmn | 0:3ac96e360672 | 505 | uint8_t ana_config__regdvdd1v2_ctrl; |
| charlesmn | 0:3ac96e360672 | 506 | |
| charlesmn | 0:3ac96e360672 | 507 | uint8_t ana_config__osc_slow_ctrl; |
| charlesmn | 0:3ac96e360672 | 508 | |
| charlesmn | 0:3ac96e360672 | 509 | uint8_t test_mode__status; |
| charlesmn | 0:3ac96e360672 | 510 | |
| charlesmn | 0:3ac96e360672 | 511 | uint8_t firmware__system_status; |
| charlesmn | 0:3ac96e360672 | 512 | |
| charlesmn | 0:3ac96e360672 | 513 | uint8_t firmware__mode_status; |
| charlesmn | 0:3ac96e360672 | 514 | |
| charlesmn | 0:3ac96e360672 | 515 | uint8_t firmware__secondary_mode_status; |
| charlesmn | 0:3ac96e360672 | 516 | |
| charlesmn | 0:3ac96e360672 | 517 | uint16_t firmware__cal_repeat_rate_counter; |
| charlesmn | 0:3ac96e360672 | 518 | |
| charlesmn | 0:3ac96e360672 | 519 | uint16_t gph__system__thresh_high; |
| charlesmn | 0:3ac96e360672 | 520 | |
| charlesmn | 0:3ac96e360672 | 521 | uint16_t gph__system__thresh_low; |
| charlesmn | 0:3ac96e360672 | 522 | |
| charlesmn | 0:3ac96e360672 | 523 | uint8_t gph__system__enable_xtalk_per_quadrant; |
| charlesmn | 0:3ac96e360672 | 524 | |
| charlesmn | 0:3ac96e360672 | 525 | uint8_t gph__spare_0; |
| charlesmn | 0:3ac96e360672 | 526 | |
| charlesmn | 0:3ac96e360672 | 527 | uint8_t gph__sd_config__woi_sd0; |
| charlesmn | 0:3ac96e360672 | 528 | |
| charlesmn | 0:3ac96e360672 | 529 | uint8_t gph__sd_config__woi_sd1; |
| charlesmn | 0:3ac96e360672 | 530 | |
| charlesmn | 0:3ac96e360672 | 531 | uint8_t gph__sd_config__initial_phase_sd0; |
| charlesmn | 0:3ac96e360672 | 532 | |
| charlesmn | 0:3ac96e360672 | 533 | uint8_t gph__sd_config__initial_phase_sd1; |
| charlesmn | 0:3ac96e360672 | 534 | |
| charlesmn | 0:3ac96e360672 | 535 | uint8_t gph__sd_config__first_order_select; |
| charlesmn | 0:3ac96e360672 | 536 | |
| charlesmn | 0:3ac96e360672 | 537 | uint8_t gph__sd_config__quantifier; |
| charlesmn | 0:3ac96e360672 | 538 | |
| charlesmn | 0:3ac96e360672 | 539 | uint8_t gph__roi_config__user_roi_centre_spad; |
| charlesmn | 0:3ac96e360672 | 540 | |
| charlesmn | 0:3ac96e360672 | 541 | uint8_t gph__roi_config__user_roi_requested_global_xy_size; |
| charlesmn | 0:3ac96e360672 | 542 | |
| charlesmn | 0:3ac96e360672 | 543 | uint8_t gph__system__sequence_config; |
| charlesmn | 0:3ac96e360672 | 544 | |
| charlesmn | 0:3ac96e360672 | 545 | uint8_t gph__gph_id; |
| charlesmn | 0:3ac96e360672 | 546 | |
| charlesmn | 0:3ac96e360672 | 547 | uint8_t system__interrupt_set; |
| charlesmn | 0:3ac96e360672 | 548 | |
| charlesmn | 0:3ac96e360672 | 549 | uint8_t interrupt_manager__enables; |
| charlesmn | 0:3ac96e360672 | 550 | |
| charlesmn | 0:3ac96e360672 | 551 | uint8_t interrupt_manager__clear; |
| charlesmn | 0:3ac96e360672 | 552 | |
| charlesmn | 0:3ac96e360672 | 553 | uint8_t interrupt_manager__status; |
| charlesmn | 0:3ac96e360672 | 554 | |
| charlesmn | 0:3ac96e360672 | 555 | uint8_t mcu_to_host_bank__wr_access_en; |
| charlesmn | 0:3ac96e360672 | 556 | |
| charlesmn | 0:3ac96e360672 | 557 | uint8_t power_management__go1_reset_status; |
| charlesmn | 0:3ac96e360672 | 558 | |
| charlesmn | 0:3ac96e360672 | 559 | uint8_t pad_startup_mode__value_ro; |
| charlesmn | 0:3ac96e360672 | 560 | |
| charlesmn | 0:3ac96e360672 | 561 | uint8_t pad_startup_mode__value_ctrl; |
| charlesmn | 0:3ac96e360672 | 562 | |
| charlesmn | 0:3ac96e360672 | 563 | uint32_t pll_period_us; |
| charlesmn | 0:3ac96e360672 | 564 | |
| charlesmn | 0:3ac96e360672 | 565 | uint32_t interrupt_scheduler__data_out; |
| charlesmn | 0:3ac96e360672 | 566 | |
| charlesmn | 0:3ac96e360672 | 567 | uint8_t nvm_bist__complete; |
| charlesmn | 0:3ac96e360672 | 568 | |
| charlesmn | 0:3ac96e360672 | 569 | uint8_t nvm_bist__status; |
| charlesmn | 0:3ac96e360672 | 570 | |
| charlesmn | 0:3ac96e360672 | 571 | } VL53L1_debug_results_t; |
| charlesmn | 0:3ac96e360672 | 572 | |
| charlesmn | 0:3ac96e360672 | 573 | |
| charlesmn | 0:3ac96e360672 | 574 | |
| charlesmn | 0:3ac96e360672 | 575 | |
| charlesmn | 0:3ac96e360672 | 576 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 577 | uint8_t identification__model_id; |
| charlesmn | 0:3ac96e360672 | 578 | |
| charlesmn | 0:3ac96e360672 | 579 | uint8_t identification__module_type; |
| charlesmn | 0:3ac96e360672 | 580 | |
| charlesmn | 0:3ac96e360672 | 581 | uint8_t identification__revision_id; |
| charlesmn | 0:3ac96e360672 | 582 | |
| charlesmn | 0:3ac96e360672 | 583 | uint16_t identification__module_id; |
| charlesmn | 0:3ac96e360672 | 584 | |
| charlesmn | 0:3ac96e360672 | 585 | uint8_t ana_config__fast_osc__trim_max; |
| charlesmn | 0:3ac96e360672 | 586 | |
| charlesmn | 0:3ac96e360672 | 587 | uint8_t ana_config__fast_osc__freq_set; |
| charlesmn | 0:3ac96e360672 | 588 | |
| charlesmn | 0:3ac96e360672 | 589 | uint8_t ana_config__vcsel_trim; |
| charlesmn | 0:3ac96e360672 | 590 | |
| charlesmn | 0:3ac96e360672 | 591 | uint8_t ana_config__vcsel_selion; |
| charlesmn | 0:3ac96e360672 | 592 | |
| charlesmn | 0:3ac96e360672 | 593 | uint8_t ana_config__vcsel_selion_max; |
| charlesmn | 0:3ac96e360672 | 594 | |
| charlesmn | 0:3ac96e360672 | 595 | uint8_t protected_laser_safety__lock_bit; |
| charlesmn | 0:3ac96e360672 | 596 | |
| charlesmn | 0:3ac96e360672 | 597 | uint8_t laser_safety__key; |
| charlesmn | 0:3ac96e360672 | 598 | |
| charlesmn | 0:3ac96e360672 | 599 | uint8_t laser_safety__key_ro; |
| charlesmn | 0:3ac96e360672 | 600 | |
| charlesmn | 0:3ac96e360672 | 601 | uint8_t laser_safety__clip; |
| charlesmn | 0:3ac96e360672 | 602 | |
| charlesmn | 0:3ac96e360672 | 603 | uint8_t laser_safety__mult; |
| charlesmn | 0:3ac96e360672 | 604 | |
| charlesmn | 0:3ac96e360672 | 605 | uint8_t global_config__spad_enables_rtn_0; |
| charlesmn | 0:3ac96e360672 | 606 | |
| charlesmn | 0:3ac96e360672 | 607 | uint8_t global_config__spad_enables_rtn_1; |
| charlesmn | 0:3ac96e360672 | 608 | |
| charlesmn | 0:3ac96e360672 | 609 | uint8_t global_config__spad_enables_rtn_2; |
| charlesmn | 0:3ac96e360672 | 610 | |
| charlesmn | 0:3ac96e360672 | 611 | uint8_t global_config__spad_enables_rtn_3; |
| charlesmn | 0:3ac96e360672 | 612 | |
| charlesmn | 0:3ac96e360672 | 613 | uint8_t global_config__spad_enables_rtn_4; |
| charlesmn | 0:3ac96e360672 | 614 | |
| charlesmn | 0:3ac96e360672 | 615 | uint8_t global_config__spad_enables_rtn_5; |
| charlesmn | 0:3ac96e360672 | 616 | |
| charlesmn | 0:3ac96e360672 | 617 | uint8_t global_config__spad_enables_rtn_6; |
| charlesmn | 0:3ac96e360672 | 618 | |
| charlesmn | 0:3ac96e360672 | 619 | uint8_t global_config__spad_enables_rtn_7; |
| charlesmn | 0:3ac96e360672 | 620 | |
| charlesmn | 0:3ac96e360672 | 621 | uint8_t global_config__spad_enables_rtn_8; |
| charlesmn | 0:3ac96e360672 | 622 | |
| charlesmn | 0:3ac96e360672 | 623 | uint8_t global_config__spad_enables_rtn_9; |
| charlesmn | 0:3ac96e360672 | 624 | |
| charlesmn | 0:3ac96e360672 | 625 | uint8_t global_config__spad_enables_rtn_10; |
| charlesmn | 0:3ac96e360672 | 626 | |
| charlesmn | 0:3ac96e360672 | 627 | uint8_t global_config__spad_enables_rtn_11; |
| charlesmn | 0:3ac96e360672 | 628 | |
| charlesmn | 0:3ac96e360672 | 629 | uint8_t global_config__spad_enables_rtn_12; |
| charlesmn | 0:3ac96e360672 | 630 | |
| charlesmn | 0:3ac96e360672 | 631 | uint8_t global_config__spad_enables_rtn_13; |
| charlesmn | 0:3ac96e360672 | 632 | |
| charlesmn | 0:3ac96e360672 | 633 | uint8_t global_config__spad_enables_rtn_14; |
| charlesmn | 0:3ac96e360672 | 634 | |
| charlesmn | 0:3ac96e360672 | 635 | uint8_t global_config__spad_enables_rtn_15; |
| charlesmn | 0:3ac96e360672 | 636 | |
| charlesmn | 0:3ac96e360672 | 637 | uint8_t global_config__spad_enables_rtn_16; |
| charlesmn | 0:3ac96e360672 | 638 | |
| charlesmn | 0:3ac96e360672 | 639 | uint8_t global_config__spad_enables_rtn_17; |
| charlesmn | 0:3ac96e360672 | 640 | |
| charlesmn | 0:3ac96e360672 | 641 | uint8_t global_config__spad_enables_rtn_18; |
| charlesmn | 0:3ac96e360672 | 642 | |
| charlesmn | 0:3ac96e360672 | 643 | uint8_t global_config__spad_enables_rtn_19; |
| charlesmn | 0:3ac96e360672 | 644 | |
| charlesmn | 0:3ac96e360672 | 645 | uint8_t global_config__spad_enables_rtn_20; |
| charlesmn | 0:3ac96e360672 | 646 | |
| charlesmn | 0:3ac96e360672 | 647 | uint8_t global_config__spad_enables_rtn_21; |
| charlesmn | 0:3ac96e360672 | 648 | |
| charlesmn | 0:3ac96e360672 | 649 | uint8_t global_config__spad_enables_rtn_22; |
| charlesmn | 0:3ac96e360672 | 650 | |
| charlesmn | 0:3ac96e360672 | 651 | uint8_t global_config__spad_enables_rtn_23; |
| charlesmn | 0:3ac96e360672 | 652 | |
| charlesmn | 0:3ac96e360672 | 653 | uint8_t global_config__spad_enables_rtn_24; |
| charlesmn | 0:3ac96e360672 | 654 | |
| charlesmn | 0:3ac96e360672 | 655 | uint8_t global_config__spad_enables_rtn_25; |
| charlesmn | 0:3ac96e360672 | 656 | |
| charlesmn | 0:3ac96e360672 | 657 | uint8_t global_config__spad_enables_rtn_26; |
| charlesmn | 0:3ac96e360672 | 658 | |
| charlesmn | 0:3ac96e360672 | 659 | uint8_t global_config__spad_enables_rtn_27; |
| charlesmn | 0:3ac96e360672 | 660 | |
| charlesmn | 0:3ac96e360672 | 661 | uint8_t global_config__spad_enables_rtn_28; |
| charlesmn | 0:3ac96e360672 | 662 | |
| charlesmn | 0:3ac96e360672 | 663 | uint8_t global_config__spad_enables_rtn_29; |
| charlesmn | 0:3ac96e360672 | 664 | |
| charlesmn | 0:3ac96e360672 | 665 | uint8_t global_config__spad_enables_rtn_30; |
| charlesmn | 0:3ac96e360672 | 666 | |
| charlesmn | 0:3ac96e360672 | 667 | uint8_t global_config__spad_enables_rtn_31; |
| charlesmn | 0:3ac96e360672 | 668 | |
| charlesmn | 0:3ac96e360672 | 669 | uint8_t roi_config__mode_roi_centre_spad; |
| charlesmn | 0:3ac96e360672 | 670 | |
| charlesmn | 0:3ac96e360672 | 671 | uint8_t roi_config__mode_roi_xy_size; |
| charlesmn | 0:3ac96e360672 | 672 | |
| charlesmn | 0:3ac96e360672 | 673 | } VL53L1_nvm_copy_data_t; |
| charlesmn | 0:3ac96e360672 | 674 | |
| charlesmn | 0:3ac96e360672 | 675 | |
| charlesmn | 0:3ac96e360672 | 676 | |
| charlesmn | 0:3ac96e360672 | 677 | |
| charlesmn | 0:3ac96e360672 | 678 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 679 | uint8_t prev_shadow_result__interrupt_status; |
| charlesmn | 0:3ac96e360672 | 680 | |
| charlesmn | 0:3ac96e360672 | 681 | uint8_t prev_shadow_result__range_status; |
| charlesmn | 0:3ac96e360672 | 682 | |
| charlesmn | 0:3ac96e360672 | 683 | uint8_t prev_shadow_result__report_status; |
| charlesmn | 0:3ac96e360672 | 684 | |
| charlesmn | 0:3ac96e360672 | 685 | uint8_t prev_shadow_result__stream_count; |
| charlesmn | 0:3ac96e360672 | 686 | |
| charlesmn | 0:3ac96e360672 | 687 | uint16_t prev_shadow_result__dss_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 688 | |
| charlesmn | 0:3ac96e360672 | 689 | uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 690 | |
| charlesmn | 0:3ac96e360672 | 691 | uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 692 | |
| charlesmn | 0:3ac96e360672 | 693 | uint16_t prev_shadow_result__sigma_sd0; |
| charlesmn | 0:3ac96e360672 | 694 | |
| charlesmn | 0:3ac96e360672 | 695 | uint16_t prev_shadow_result__phase_sd0; |
| charlesmn | 0:3ac96e360672 | 696 | |
| charlesmn | 0:3ac96e360672 | 697 | uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0; |
| charlesmn | 0:3ac96e360672 | 698 | |
| charlesmn | 0:3ac96e360672 | 699 | uint16_t |
| charlesmn | 0:3ac96e360672 | 700 | psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 701 | |
| charlesmn | 0:3ac96e360672 | 702 | uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 703 | |
| charlesmn | 0:3ac96e360672 | 704 | uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 705 | |
| charlesmn | 0:3ac96e360672 | 706 | uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 707 | |
| charlesmn | 0:3ac96e360672 | 708 | uint16_t prev_shadow_result__dss_actual_effective_spads_sd1; |
| charlesmn | 0:3ac96e360672 | 709 | |
| charlesmn | 0:3ac96e360672 | 710 | uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1; |
| charlesmn | 0:3ac96e360672 | 711 | |
| charlesmn | 0:3ac96e360672 | 712 | uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1; |
| charlesmn | 0:3ac96e360672 | 713 | |
| charlesmn | 0:3ac96e360672 | 714 | uint16_t prev_shadow_result__sigma_sd1; |
| charlesmn | 0:3ac96e360672 | 715 | |
| charlesmn | 0:3ac96e360672 | 716 | uint16_t prev_shadow_result__phase_sd1; |
| charlesmn | 0:3ac96e360672 | 717 | |
| charlesmn | 0:3ac96e360672 | 718 | uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1; |
| charlesmn | 0:3ac96e360672 | 719 | |
| charlesmn | 0:3ac96e360672 | 720 | uint16_t prev_shadow_result__spare_0_sd1; |
| charlesmn | 0:3ac96e360672 | 721 | |
| charlesmn | 0:3ac96e360672 | 722 | uint16_t prev_shadow_result__spare_1_sd1; |
| charlesmn | 0:3ac96e360672 | 723 | |
| charlesmn | 0:3ac96e360672 | 724 | uint16_t prev_shadow_result__spare_2_sd1; |
| charlesmn | 0:3ac96e360672 | 725 | |
| charlesmn | 0:3ac96e360672 | 726 | uint16_t prev_shadow_result__spare_3_sd1; |
| charlesmn | 0:3ac96e360672 | 727 | |
| charlesmn | 0:3ac96e360672 | 728 | } VL53L1_prev_shadow_system_results_t; |
| charlesmn | 0:3ac96e360672 | 729 | |
| charlesmn | 0:3ac96e360672 | 730 | |
| charlesmn | 0:3ac96e360672 | 731 | |
| charlesmn | 0:3ac96e360672 | 732 | |
| charlesmn | 0:3ac96e360672 | 733 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 734 | uint32_t prev_shadow_result_core__ambient_window_events_sd0; |
| charlesmn | 0:3ac96e360672 | 735 | |
| charlesmn | 0:3ac96e360672 | 736 | uint32_t prev_shadow_result_core__ranging_total_events_sd0; |
| charlesmn | 0:3ac96e360672 | 737 | |
| charlesmn | 0:3ac96e360672 | 738 | int32_t prev_shadow_result_core__signal_total_events_sd0; |
| charlesmn | 0:3ac96e360672 | 739 | |
| charlesmn | 0:3ac96e360672 | 740 | uint32_t prev_shadow_result_core__total_periods_elapsed_sd0; |
| charlesmn | 0:3ac96e360672 | 741 | |
| charlesmn | 0:3ac96e360672 | 742 | uint32_t prev_shadow_result_core__ambient_window_events_sd1; |
| charlesmn | 0:3ac96e360672 | 743 | |
| charlesmn | 0:3ac96e360672 | 744 | uint32_t prev_shadow_result_core__ranging_total_events_sd1; |
| charlesmn | 0:3ac96e360672 | 745 | |
| charlesmn | 0:3ac96e360672 | 746 | int32_t prev_shadow_result_core__signal_total_events_sd1; |
| charlesmn | 0:3ac96e360672 | 747 | |
| charlesmn | 0:3ac96e360672 | 748 | uint32_t prev_shadow_result_core__total_periods_elapsed_sd1; |
| charlesmn | 0:3ac96e360672 | 749 | |
| charlesmn | 0:3ac96e360672 | 750 | uint8_t prev_shadow_result_core__spare_0; |
| charlesmn | 0:3ac96e360672 | 751 | |
| charlesmn | 0:3ac96e360672 | 752 | } VL53L1_prev_shadow_core_results_t; |
| charlesmn | 0:3ac96e360672 | 753 | |
| charlesmn | 0:3ac96e360672 | 754 | |
| charlesmn | 0:3ac96e360672 | 755 | |
| charlesmn | 0:3ac96e360672 | 756 | |
| charlesmn | 0:3ac96e360672 | 757 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 758 | uint8_t result__debug_status; |
| charlesmn | 0:3ac96e360672 | 759 | |
| charlesmn | 0:3ac96e360672 | 760 | uint8_t result__debug_stage; |
| charlesmn | 0:3ac96e360672 | 761 | |
| charlesmn | 0:3ac96e360672 | 762 | } VL53L1_patch_debug_t; |
| charlesmn | 0:3ac96e360672 | 763 | |
| charlesmn | 0:3ac96e360672 | 764 | |
| charlesmn | 0:3ac96e360672 | 765 | |
| charlesmn | 0:3ac96e360672 | 766 | |
| charlesmn | 0:3ac96e360672 | 767 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 768 | uint16_t gph__system__thresh_rate_high; |
| charlesmn | 0:3ac96e360672 | 769 | |
| charlesmn | 0:3ac96e360672 | 770 | uint16_t gph__system__thresh_rate_low; |
| charlesmn | 0:3ac96e360672 | 771 | |
| charlesmn | 0:3ac96e360672 | 772 | uint8_t gph__system__interrupt_config_gpio; |
| charlesmn | 0:3ac96e360672 | 773 | |
| charlesmn | 0:3ac96e360672 | 774 | } VL53L1_gph_general_config_t; |
| charlesmn | 0:3ac96e360672 | 775 | |
| charlesmn | 0:3ac96e360672 | 776 | |
| charlesmn | 0:3ac96e360672 | 777 | |
| charlesmn | 0:3ac96e360672 | 778 | |
| charlesmn | 0:3ac96e360672 | 779 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 780 | uint8_t gph__dss_config__roi_mode_control; |
| charlesmn | 0:3ac96e360672 | 781 | |
| charlesmn | 0:3ac96e360672 | 782 | uint16_t gph__dss_config__manual_effective_spads_select; |
| charlesmn | 0:3ac96e360672 | 783 | |
| charlesmn | 0:3ac96e360672 | 784 | uint8_t gph__dss_config__manual_block_select; |
| charlesmn | 0:3ac96e360672 | 785 | |
| charlesmn | 0:3ac96e360672 | 786 | uint8_t gph__dss_config__max_spads_limit; |
| charlesmn | 0:3ac96e360672 | 787 | |
| charlesmn | 0:3ac96e360672 | 788 | uint8_t gph__dss_config__min_spads_limit; |
| charlesmn | 0:3ac96e360672 | 789 | |
| charlesmn | 0:3ac96e360672 | 790 | } VL53L1_gph_static_config_t; |
| charlesmn | 0:3ac96e360672 | 791 | |
| charlesmn | 0:3ac96e360672 | 792 | |
| charlesmn | 0:3ac96e360672 | 793 | |
| charlesmn | 0:3ac96e360672 | 794 | |
| charlesmn | 0:3ac96e360672 | 795 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 796 | uint8_t gph__mm_config__timeout_macrop_a_hi; |
| charlesmn | 0:3ac96e360672 | 797 | |
| charlesmn | 0:3ac96e360672 | 798 | uint8_t gph__mm_config__timeout_macrop_a_lo; |
| charlesmn | 0:3ac96e360672 | 799 | |
| charlesmn | 0:3ac96e360672 | 800 | uint8_t gph__mm_config__timeout_macrop_b_hi; |
| charlesmn | 0:3ac96e360672 | 801 | |
| charlesmn | 0:3ac96e360672 | 802 | uint8_t gph__mm_config__timeout_macrop_b_lo; |
| charlesmn | 0:3ac96e360672 | 803 | |
| charlesmn | 0:3ac96e360672 | 804 | uint8_t gph__range_config__timeout_macrop_a_hi; |
| charlesmn | 0:3ac96e360672 | 805 | |
| charlesmn | 0:3ac96e360672 | 806 | uint8_t gph__range_config__timeout_macrop_a_lo; |
| charlesmn | 0:3ac96e360672 | 807 | |
| charlesmn | 0:3ac96e360672 | 808 | uint8_t gph__range_config__vcsel_period_a; |
| charlesmn | 0:3ac96e360672 | 809 | |
| charlesmn | 0:3ac96e360672 | 810 | uint8_t gph__range_config__vcsel_period_b; |
| charlesmn | 0:3ac96e360672 | 811 | |
| charlesmn | 0:3ac96e360672 | 812 | uint8_t gph__range_config__timeout_macrop_b_hi; |
| charlesmn | 0:3ac96e360672 | 813 | |
| charlesmn | 0:3ac96e360672 | 814 | uint8_t gph__range_config__timeout_macrop_b_lo; |
| charlesmn | 0:3ac96e360672 | 815 | |
| charlesmn | 0:3ac96e360672 | 816 | uint16_t gph__range_config__sigma_thresh; |
| charlesmn | 0:3ac96e360672 | 817 | |
| charlesmn | 0:3ac96e360672 | 818 | uint16_t gph__range_config__min_count_rate_rtn_limit_mcps; |
| charlesmn | 0:3ac96e360672 | 819 | |
| charlesmn | 0:3ac96e360672 | 820 | uint8_t gph__range_config__valid_phase_low; |
| charlesmn | 0:3ac96e360672 | 821 | |
| charlesmn | 0:3ac96e360672 | 822 | uint8_t gph__range_config__valid_phase_high; |
| charlesmn | 0:3ac96e360672 | 823 | |
| charlesmn | 0:3ac96e360672 | 824 | } VL53L1_gph_timing_config_t; |
| charlesmn | 0:3ac96e360672 | 825 | |
| charlesmn | 0:3ac96e360672 | 826 | |
| charlesmn | 0:3ac96e360672 | 827 | |
| charlesmn | 0:3ac96e360672 | 828 | |
| charlesmn | 0:3ac96e360672 | 829 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 830 | uint8_t firmware__internal_stream_count_div; |
| charlesmn | 0:3ac96e360672 | 831 | |
| charlesmn | 0:3ac96e360672 | 832 | uint8_t firmware__internal_stream_counter_val; |
| charlesmn | 0:3ac96e360672 | 833 | |
| charlesmn | 0:3ac96e360672 | 834 | } VL53L1_fw_internal_t; |
| charlesmn | 0:3ac96e360672 | 835 | |
| charlesmn | 0:3ac96e360672 | 836 | |
| charlesmn | 0:3ac96e360672 | 837 | |
| charlesmn | 0:3ac96e360672 | 838 | |
| charlesmn | 0:3ac96e360672 | 839 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 840 | uint8_t dss_calc__roi_ctrl; |
| charlesmn | 0:3ac96e360672 | 841 | |
| charlesmn | 0:3ac96e360672 | 842 | uint8_t dss_calc__spare_1; |
| charlesmn | 0:3ac96e360672 | 843 | |
| charlesmn | 0:3ac96e360672 | 844 | uint8_t dss_calc__spare_2; |
| charlesmn | 0:3ac96e360672 | 845 | |
| charlesmn | 0:3ac96e360672 | 846 | uint8_t dss_calc__spare_3; |
| charlesmn | 0:3ac96e360672 | 847 | |
| charlesmn | 0:3ac96e360672 | 848 | uint8_t dss_calc__spare_4; |
| charlesmn | 0:3ac96e360672 | 849 | |
| charlesmn | 0:3ac96e360672 | 850 | uint8_t dss_calc__spare_5; |
| charlesmn | 0:3ac96e360672 | 851 | |
| charlesmn | 0:3ac96e360672 | 852 | uint8_t dss_calc__spare_6; |
| charlesmn | 0:3ac96e360672 | 853 | |
| charlesmn | 0:3ac96e360672 | 854 | uint8_t dss_calc__spare_7; |
| charlesmn | 0:3ac96e360672 | 855 | |
| charlesmn | 0:3ac96e360672 | 856 | uint8_t dss_calc__user_roi_spad_en_0; |
| charlesmn | 0:3ac96e360672 | 857 | |
| charlesmn | 0:3ac96e360672 | 858 | uint8_t dss_calc__user_roi_spad_en_1; |
| charlesmn | 0:3ac96e360672 | 859 | |
| charlesmn | 0:3ac96e360672 | 860 | uint8_t dss_calc__user_roi_spad_en_2; |
| charlesmn | 0:3ac96e360672 | 861 | |
| charlesmn | 0:3ac96e360672 | 862 | uint8_t dss_calc__user_roi_spad_en_3; |
| charlesmn | 0:3ac96e360672 | 863 | |
| charlesmn | 0:3ac96e360672 | 864 | uint8_t dss_calc__user_roi_spad_en_4; |
| charlesmn | 0:3ac96e360672 | 865 | |
| charlesmn | 0:3ac96e360672 | 866 | uint8_t dss_calc__user_roi_spad_en_5; |
| charlesmn | 0:3ac96e360672 | 867 | |
| charlesmn | 0:3ac96e360672 | 868 | uint8_t dss_calc__user_roi_spad_en_6; |
| charlesmn | 0:3ac96e360672 | 869 | |
| charlesmn | 0:3ac96e360672 | 870 | uint8_t dss_calc__user_roi_spad_en_7; |
| charlesmn | 0:3ac96e360672 | 871 | |
| charlesmn | 0:3ac96e360672 | 872 | uint8_t dss_calc__user_roi_spad_en_8; |
| charlesmn | 0:3ac96e360672 | 873 | |
| charlesmn | 0:3ac96e360672 | 874 | uint8_t dss_calc__user_roi_spad_en_9; |
| charlesmn | 0:3ac96e360672 | 875 | |
| charlesmn | 0:3ac96e360672 | 876 | uint8_t dss_calc__user_roi_spad_en_10; |
| charlesmn | 0:3ac96e360672 | 877 | |
| charlesmn | 0:3ac96e360672 | 878 | uint8_t dss_calc__user_roi_spad_en_11; |
| charlesmn | 0:3ac96e360672 | 879 | |
| charlesmn | 0:3ac96e360672 | 880 | uint8_t dss_calc__user_roi_spad_en_12; |
| charlesmn | 0:3ac96e360672 | 881 | |
| charlesmn | 0:3ac96e360672 | 882 | uint8_t dss_calc__user_roi_spad_en_13; |
| charlesmn | 0:3ac96e360672 | 883 | |
| charlesmn | 0:3ac96e360672 | 884 | uint8_t dss_calc__user_roi_spad_en_14; |
| charlesmn | 0:3ac96e360672 | 885 | |
| charlesmn | 0:3ac96e360672 | 886 | uint8_t dss_calc__user_roi_spad_en_15; |
| charlesmn | 0:3ac96e360672 | 887 | |
| charlesmn | 0:3ac96e360672 | 888 | uint8_t dss_calc__user_roi_spad_en_16; |
| charlesmn | 0:3ac96e360672 | 889 | |
| charlesmn | 0:3ac96e360672 | 890 | uint8_t dss_calc__user_roi_spad_en_17; |
| charlesmn | 0:3ac96e360672 | 891 | |
| charlesmn | 0:3ac96e360672 | 892 | uint8_t dss_calc__user_roi_spad_en_18; |
| charlesmn | 0:3ac96e360672 | 893 | |
| charlesmn | 0:3ac96e360672 | 894 | uint8_t dss_calc__user_roi_spad_en_19; |
| charlesmn | 0:3ac96e360672 | 895 | |
| charlesmn | 0:3ac96e360672 | 896 | uint8_t dss_calc__user_roi_spad_en_20; |
| charlesmn | 0:3ac96e360672 | 897 | |
| charlesmn | 0:3ac96e360672 | 898 | uint8_t dss_calc__user_roi_spad_en_21; |
| charlesmn | 0:3ac96e360672 | 899 | |
| charlesmn | 0:3ac96e360672 | 900 | uint8_t dss_calc__user_roi_spad_en_22; |
| charlesmn | 0:3ac96e360672 | 901 | |
| charlesmn | 0:3ac96e360672 | 902 | uint8_t dss_calc__user_roi_spad_en_23; |
| charlesmn | 0:3ac96e360672 | 903 | |
| charlesmn | 0:3ac96e360672 | 904 | uint8_t dss_calc__user_roi_spad_en_24; |
| charlesmn | 0:3ac96e360672 | 905 | |
| charlesmn | 0:3ac96e360672 | 906 | uint8_t dss_calc__user_roi_spad_en_25; |
| charlesmn | 0:3ac96e360672 | 907 | |
| charlesmn | 0:3ac96e360672 | 908 | uint8_t dss_calc__user_roi_spad_en_26; |
| charlesmn | 0:3ac96e360672 | 909 | |
| charlesmn | 0:3ac96e360672 | 910 | uint8_t dss_calc__user_roi_spad_en_27; |
| charlesmn | 0:3ac96e360672 | 911 | |
| charlesmn | 0:3ac96e360672 | 912 | uint8_t dss_calc__user_roi_spad_en_28; |
| charlesmn | 0:3ac96e360672 | 913 | |
| charlesmn | 0:3ac96e360672 | 914 | uint8_t dss_calc__user_roi_spad_en_29; |
| charlesmn | 0:3ac96e360672 | 915 | |
| charlesmn | 0:3ac96e360672 | 916 | uint8_t dss_calc__user_roi_spad_en_30; |
| charlesmn | 0:3ac96e360672 | 917 | |
| charlesmn | 0:3ac96e360672 | 918 | uint8_t dss_calc__user_roi_spad_en_31; |
| charlesmn | 0:3ac96e360672 | 919 | |
| charlesmn | 0:3ac96e360672 | 920 | uint8_t dss_calc__user_roi_0; |
| charlesmn | 0:3ac96e360672 | 921 | |
| charlesmn | 0:3ac96e360672 | 922 | uint8_t dss_calc__user_roi_1; |
| charlesmn | 0:3ac96e360672 | 923 | |
| charlesmn | 0:3ac96e360672 | 924 | uint8_t dss_calc__mode_roi_0; |
| charlesmn | 0:3ac96e360672 | 925 | |
| charlesmn | 0:3ac96e360672 | 926 | uint8_t dss_calc__mode_roi_1; |
| charlesmn | 0:3ac96e360672 | 927 | |
| charlesmn | 0:3ac96e360672 | 928 | uint8_t sigma_estimator_calc__spare_0; |
| charlesmn | 0:3ac96e360672 | 929 | |
| charlesmn | 0:3ac96e360672 | 930 | uint16_t vhv_result__peak_signal_rate_mcps; |
| charlesmn | 0:3ac96e360672 | 931 | |
| charlesmn | 0:3ac96e360672 | 932 | uint32_t vhv_result__signal_total_events_ref; |
| charlesmn | 0:3ac96e360672 | 933 | |
| charlesmn | 0:3ac96e360672 | 934 | uint16_t phasecal_result__phase_output_ref; |
| charlesmn | 0:3ac96e360672 | 935 | |
| charlesmn | 0:3ac96e360672 | 936 | uint16_t dss_result__total_rate_per_spad; |
| charlesmn | 0:3ac96e360672 | 937 | |
| charlesmn | 0:3ac96e360672 | 938 | uint8_t dss_result__enabled_blocks; |
| charlesmn | 0:3ac96e360672 | 939 | |
| charlesmn | 0:3ac96e360672 | 940 | uint16_t dss_result__num_requested_spads; |
| charlesmn | 0:3ac96e360672 | 941 | |
| charlesmn | 0:3ac96e360672 | 942 | uint16_t mm_result__inner_intersection_rate; |
| charlesmn | 0:3ac96e360672 | 943 | |
| charlesmn | 0:3ac96e360672 | 944 | uint16_t mm_result__outer_complement_rate; |
| charlesmn | 0:3ac96e360672 | 945 | |
| charlesmn | 0:3ac96e360672 | 946 | uint16_t mm_result__total_offset; |
| charlesmn | 0:3ac96e360672 | 947 | |
| charlesmn | 0:3ac96e360672 | 948 | uint32_t xtalk_calc__xtalk_for_enabled_spads; |
| charlesmn | 0:3ac96e360672 | 949 | |
| charlesmn | 0:3ac96e360672 | 950 | uint32_t xtalk_result__avg_xtalk_user_roi_kcps; |
| charlesmn | 0:3ac96e360672 | 951 | |
| charlesmn | 0:3ac96e360672 | 952 | uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps; |
| charlesmn | 0:3ac96e360672 | 953 | |
| charlesmn | 0:3ac96e360672 | 954 | uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps; |
| charlesmn | 0:3ac96e360672 | 955 | |
| charlesmn | 0:3ac96e360672 | 956 | uint32_t range_result__accum_phase; |
| charlesmn | 0:3ac96e360672 | 957 | |
| charlesmn | 0:3ac96e360672 | 958 | uint16_t range_result__offset_corrected_range; |
| charlesmn | 0:3ac96e360672 | 959 | |
| charlesmn | 0:3ac96e360672 | 960 | } VL53L1_patch_results_t; |
| charlesmn | 0:3ac96e360672 | 961 | |
| charlesmn | 0:3ac96e360672 | 962 | |
| charlesmn | 0:3ac96e360672 | 963 | |
| charlesmn | 0:3ac96e360672 | 964 | |
| charlesmn | 0:3ac96e360672 | 965 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 966 | uint8_t shadow_phasecal_result__vcsel_start; |
| charlesmn | 0:3ac96e360672 | 967 | |
| charlesmn | 0:3ac96e360672 | 968 | uint8_t shadow_result__interrupt_status; |
| charlesmn | 0:3ac96e360672 | 969 | |
| charlesmn | 0:3ac96e360672 | 970 | uint8_t shadow_result__range_status; |
| charlesmn | 0:3ac96e360672 | 971 | |
| charlesmn | 0:3ac96e360672 | 972 | uint8_t shadow_result__report_status; |
| charlesmn | 0:3ac96e360672 | 973 | |
| charlesmn | 0:3ac96e360672 | 974 | uint8_t shadow_result__stream_count; |
| charlesmn | 0:3ac96e360672 | 975 | |
| charlesmn | 0:3ac96e360672 | 976 | uint16_t shadow_result__dss_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 977 | |
| charlesmn | 0:3ac96e360672 | 978 | uint16_t shadow_result__peak_signal_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 979 | |
| charlesmn | 0:3ac96e360672 | 980 | uint16_t shadow_result__ambient_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 981 | |
| charlesmn | 0:3ac96e360672 | 982 | uint16_t shadow_result__sigma_sd0; |
| charlesmn | 0:3ac96e360672 | 983 | |
| charlesmn | 0:3ac96e360672 | 984 | uint16_t shadow_result__phase_sd0; |
| charlesmn | 0:3ac96e360672 | 985 | |
| charlesmn | 0:3ac96e360672 | 986 | uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0; |
| charlesmn | 0:3ac96e360672 | 987 | |
| charlesmn | 0:3ac96e360672 | 988 | uint16_t |
| charlesmn | 0:3ac96e360672 | 989 | shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 990 | |
| charlesmn | 0:3ac96e360672 | 991 | uint16_t shadow_result__mm_inner_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 992 | |
| charlesmn | 0:3ac96e360672 | 993 | uint16_t shadow_result__mm_outer_actual_effective_spads_sd0; |
| charlesmn | 0:3ac96e360672 | 994 | |
| charlesmn | 0:3ac96e360672 | 995 | uint16_t shadow_result__avg_signal_count_rate_mcps_sd0; |
| charlesmn | 0:3ac96e360672 | 996 | |
| charlesmn | 0:3ac96e360672 | 997 | uint16_t shadow_result__dss_actual_effective_spads_sd1; |
| charlesmn | 0:3ac96e360672 | 998 | |
| charlesmn | 0:3ac96e360672 | 999 | uint16_t shadow_result__peak_signal_count_rate_mcps_sd1; |
| charlesmn | 0:3ac96e360672 | 1000 | |
| charlesmn | 0:3ac96e360672 | 1001 | uint16_t shadow_result__ambient_count_rate_mcps_sd1; |
| charlesmn | 0:3ac96e360672 | 1002 | |
| charlesmn | 0:3ac96e360672 | 1003 | uint16_t shadow_result__sigma_sd1; |
| charlesmn | 0:3ac96e360672 | 1004 | |
| charlesmn | 0:3ac96e360672 | 1005 | uint16_t shadow_result__phase_sd1; |
| charlesmn | 0:3ac96e360672 | 1006 | |
| charlesmn | 0:3ac96e360672 | 1007 | uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1; |
| charlesmn | 0:3ac96e360672 | 1008 | |
| charlesmn | 0:3ac96e360672 | 1009 | uint16_t shadow_result__spare_0_sd1; |
| charlesmn | 0:3ac96e360672 | 1010 | |
| charlesmn | 0:3ac96e360672 | 1011 | uint16_t shadow_result__spare_1_sd1; |
| charlesmn | 0:3ac96e360672 | 1012 | |
| charlesmn | 0:3ac96e360672 | 1013 | uint16_t shadow_result__spare_2_sd1; |
| charlesmn | 0:3ac96e360672 | 1014 | |
| charlesmn | 0:3ac96e360672 | 1015 | uint8_t shadow_result__spare_3_sd1; |
| charlesmn | 0:3ac96e360672 | 1016 | |
| charlesmn | 0:3ac96e360672 | 1017 | uint8_t shadow_result__thresh_info; |
| charlesmn | 0:3ac96e360672 | 1018 | |
| charlesmn | 0:3ac96e360672 | 1019 | uint8_t shadow_phasecal_result__reference_phase_hi; |
| charlesmn | 0:3ac96e360672 | 1020 | |
| charlesmn | 0:3ac96e360672 | 1021 | uint8_t shadow_phasecal_result__reference_phase_lo; |
| charlesmn | 0:3ac96e360672 | 1022 | |
| charlesmn | 0:3ac96e360672 | 1023 | } VL53L1_shadow_system_results_t; |
| charlesmn | 0:3ac96e360672 | 1024 | |
| charlesmn | 0:3ac96e360672 | 1025 | |
| charlesmn | 0:3ac96e360672 | 1026 | |
| charlesmn | 0:3ac96e360672 | 1027 | |
| charlesmn | 0:3ac96e360672 | 1028 | typedef struct { |
| charlesmn | 0:3ac96e360672 | 1029 | uint32_t shadow_result_core__ambient_window_events_sd0; |
| charlesmn | 0:3ac96e360672 | 1030 | |
| charlesmn | 0:3ac96e360672 | 1031 | uint32_t shadow_result_core__ranging_total_events_sd0; |
| charlesmn | 0:3ac96e360672 | 1032 | |
| charlesmn | 0:3ac96e360672 | 1033 | int32_t shadow_result_core__signal_total_events_sd0; |
| charlesmn | 0:3ac96e360672 | 1034 | |
| charlesmn | 0:3ac96e360672 | 1035 | uint32_t shadow_result_core__total_periods_elapsed_sd0; |
| charlesmn | 0:3ac96e360672 | 1036 | |
| charlesmn | 0:3ac96e360672 | 1037 | uint32_t shadow_result_core__ambient_window_events_sd1; |
| charlesmn | 0:3ac96e360672 | 1038 | |
| charlesmn | 0:3ac96e360672 | 1039 | uint32_t shadow_result_core__ranging_total_events_sd1; |
| charlesmn | 0:3ac96e360672 | 1040 | |
| charlesmn | 0:3ac96e360672 | 1041 | int32_t shadow_result_core__signal_total_events_sd1; |
| charlesmn | 0:3ac96e360672 | 1042 | |
| charlesmn | 0:3ac96e360672 | 1043 | uint32_t shadow_result_core__total_periods_elapsed_sd1; |
| charlesmn | 0:3ac96e360672 | 1044 | |
| charlesmn | 0:3ac96e360672 | 1045 | uint8_t shadow_result_core__spare_0; |
| charlesmn | 0:3ac96e360672 | 1046 | |
| charlesmn | 0:3ac96e360672 | 1047 | } VL53L1_shadow_core_results_t; |
| charlesmn | 0:3ac96e360672 | 1048 | |
| charlesmn | 0:3ac96e360672 | 1049 | |
| charlesmn | 0:3ac96e360672 | 1050 | #endif |
| charlesmn | 0:3ac96e360672 | 1051 | |
| charlesmn | 0:3ac96e360672 | 1052 | |
| charlesmn | 0:3ac96e360672 | 1053 |