ST Expansion SW Team
ST25R3911 library for the STMicroelectronics X-NUCLEO-NFC05A1
st25r3911_com.h@0:98fcd1266df0, 2019-11-14 (annotated)
- Committer:
- DiegoOstuni
- Date:
- Thu Nov 14 14:36:52 2019 +0000
- Revision:
- 0:98fcd1266df0
Fork of the GitHub
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| DiegoOstuni | 0:98fcd1266df0 | 1 | |
| DiegoOstuni | 0:98fcd1266df0 | 2 | /****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 3 | * @attention |
| DiegoOstuni | 0:98fcd1266df0 | 4 | * |
| DiegoOstuni | 0:98fcd1266df0 | 5 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| DiegoOstuni | 0:98fcd1266df0 | 6 | * |
| DiegoOstuni | 0:98fcd1266df0 | 7 | * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); |
| DiegoOstuni | 0:98fcd1266df0 | 8 | * You may not use this file except in compliance with the License. |
| DiegoOstuni | 0:98fcd1266df0 | 9 | * You may obtain a copy of the License at: |
| DiegoOstuni | 0:98fcd1266df0 | 10 | * |
| DiegoOstuni | 0:98fcd1266df0 | 11 | * http://www.st.com/myliberty |
| DiegoOstuni | 0:98fcd1266df0 | 12 | * |
| DiegoOstuni | 0:98fcd1266df0 | 13 | * Unless required by applicable law or agreed to in writing, software |
| DiegoOstuni | 0:98fcd1266df0 | 14 | * distributed under the License is distributed on an "AS IS" BASIS, |
| DiegoOstuni | 0:98fcd1266df0 | 15 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, |
| DiegoOstuni | 0:98fcd1266df0 | 16 | * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, |
| DiegoOstuni | 0:98fcd1266df0 | 17 | * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. |
| DiegoOstuni | 0:98fcd1266df0 | 18 | * See the License for the specific language governing permissions and |
| DiegoOstuni | 0:98fcd1266df0 | 19 | * limitations under the License. |
| DiegoOstuni | 0:98fcd1266df0 | 20 | * |
| DiegoOstuni | 0:98fcd1266df0 | 21 | ******************************************************************************/ |
| DiegoOstuni | 0:98fcd1266df0 | 22 | |
| DiegoOstuni | 0:98fcd1266df0 | 23 | |
| DiegoOstuni | 0:98fcd1266df0 | 24 | /* |
| DiegoOstuni | 0:98fcd1266df0 | 25 | * PROJECT: ST25R3911 firmware |
| DiegoOstuni | 0:98fcd1266df0 | 26 | * $Revision: $ |
| DiegoOstuni | 0:98fcd1266df0 | 27 | * LANGUAGE: ISO C99 |
| DiegoOstuni | 0:98fcd1266df0 | 28 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 29 | |
| DiegoOstuni | 0:98fcd1266df0 | 30 | /*! \file |
| DiegoOstuni | 0:98fcd1266df0 | 31 | * |
| DiegoOstuni | 0:98fcd1266df0 | 32 | * \author Ulrich Herrmann |
| DiegoOstuni | 0:98fcd1266df0 | 33 | * |
| DiegoOstuni | 0:98fcd1266df0 | 34 | * \brief ST25R3911 communication declaration file |
| DiegoOstuni | 0:98fcd1266df0 | 35 | * |
| DiegoOstuni | 0:98fcd1266df0 | 36 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 37 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 38 | * This driver provides basic abstraction for communication with the ST25R3911. |
| DiegoOstuni | 0:98fcd1266df0 | 39 | * It uses the SPI driver for interfacing with the ST25R3911. |
| DiegoOstuni | 0:98fcd1266df0 | 40 | * |
| DiegoOstuni | 0:98fcd1266df0 | 41 | * API: |
| DiegoOstuni | 0:98fcd1266df0 | 42 | * - Read Register: #st25r3911ReadRegister |
| DiegoOstuni | 0:98fcd1266df0 | 43 | * - Modify Register: #st25r3911ModifyRegister |
| DiegoOstuni | 0:98fcd1266df0 | 44 | * - Write Register: #mST25 -> writeRegister |
| DiegoOstuni | 0:98fcd1266df0 | 45 | * - Write Multiple Registers: #mST25 -> writeMultipleRegisters |
| DiegoOstuni | 0:98fcd1266df0 | 46 | * - Load ST25R3911 FIFO with data: #mST25 -> writeFifo |
| DiegoOstuni | 0:98fcd1266df0 | 47 | * - Read from ST25R3911 FIFO: #mST25 -> readFifo |
| DiegoOstuni | 0:98fcd1266df0 | 48 | * - Execute direct command: #mST25 -> executeCommand |
| DiegoOstuni | 0:98fcd1266df0 | 49 | * |
| DiegoOstuni | 0:98fcd1266df0 | 50 | * |
| DiegoOstuni | 0:98fcd1266df0 | 51 | * @addtogroup RFAL |
| DiegoOstuni | 0:98fcd1266df0 | 52 | * @{ |
| DiegoOstuni | 0:98fcd1266df0 | 53 | * |
| DiegoOstuni | 0:98fcd1266df0 | 54 | * @addtogroup RFAL-HAL |
| DiegoOstuni | 0:98fcd1266df0 | 55 | * @brief RFAL Hardware Abstraction Layer |
| DiegoOstuni | 0:98fcd1266df0 | 56 | * @{ |
| DiegoOstuni | 0:98fcd1266df0 | 57 | * |
| DiegoOstuni | 0:98fcd1266df0 | 58 | * @addtogroup ST25R3911 |
| DiegoOstuni | 0:98fcd1266df0 | 59 | * @brief RFAL ST25R3911 Driver |
| DiegoOstuni | 0:98fcd1266df0 | 60 | * @{ |
| DiegoOstuni | 0:98fcd1266df0 | 61 | * |
| DiegoOstuni | 0:98fcd1266df0 | 62 | * @addtogroup ST25R3911_Com |
| DiegoOstuni | 0:98fcd1266df0 | 63 | * @brief RFAL ST25R3911 Communication |
| DiegoOstuni | 0:98fcd1266df0 | 64 | * @{ |
| DiegoOstuni | 0:98fcd1266df0 | 65 | * |
| DiegoOstuni | 0:98fcd1266df0 | 66 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 67 | |
| DiegoOstuni | 0:98fcd1266df0 | 68 | #ifndef ST25R3911_COM_H |
| DiegoOstuni | 0:98fcd1266df0 | 69 | #define ST25R3911_COM_H |
| DiegoOstuni | 0:98fcd1266df0 | 70 | |
| DiegoOstuni | 0:98fcd1266df0 | 71 | /* |
| DiegoOstuni | 0:98fcd1266df0 | 72 | ****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 73 | * INCLUDES |
| DiegoOstuni | 0:98fcd1266df0 | 74 | ****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 75 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 76 | #include <stdint.h> |
| DiegoOstuni | 0:98fcd1266df0 | 77 | #include <stdbool.h> |
| DiegoOstuni | 0:98fcd1266df0 | 78 | #include "st_errno.h" |
| DiegoOstuni | 0:98fcd1266df0 | 79 | #include "platform1.h" |
| DiegoOstuni | 0:98fcd1266df0 | 80 | #include "ST25R3911.h" |
| DiegoOstuni | 0:98fcd1266df0 | 81 | #include "utils.h" |
| DiegoOstuni | 0:98fcd1266df0 | 82 | |
| DiegoOstuni | 0:98fcd1266df0 | 83 | |
| DiegoOstuni | 0:98fcd1266df0 | 84 | |
| DiegoOstuni | 0:98fcd1266df0 | 85 | /* |
| DiegoOstuni | 0:98fcd1266df0 | 86 | ****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 87 | * GLOBAL DEFINES |
| DiegoOstuni | 0:98fcd1266df0 | 88 | ****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 89 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 90 | |
| DiegoOstuni | 0:98fcd1266df0 | 91 | #define ST25R3911_FIFO_STATUS_LEN 2 /*!< Number of FIFO Status Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 92 | |
| DiegoOstuni | 0:98fcd1266df0 | 93 | |
| DiegoOstuni | 0:98fcd1266df0 | 94 | |
| DiegoOstuni | 0:98fcd1266df0 | 95 | |
| DiegoOstuni | 0:98fcd1266df0 | 96 | #define ST25R3911_REG_IO_CONF1 0x00 /*!< RW IO Configuration Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 97 | #define ST25R3911_REG_IO_CONF2 0x01 /*!< RW IO Configuration Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 98 | |
| DiegoOstuni | 0:98fcd1266df0 | 99 | #define ST25R3911_REG_OP_CONTROL 0x02 /*!< RW Operation Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 100 | #define ST25R3911_REG_MODE 0x03 /*!< RW Mode Definition Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 101 | #define ST25R3911_REG_BIT_RATE 0x04 /*!< RW Bit Rate Definition Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 102 | |
| DiegoOstuni | 0:98fcd1266df0 | 103 | #define ST25R3911_REG_ISO14443A_NFC 0x05 /*!< RW ISO14443A and NFC 106 kBit/s Settings Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 104 | #define ST25R3911_REG_ISO14443B_1 0x06 /*!< RW ISO14443B Settings Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 105 | #define ST25R3911_REG_ISO14443B_2 0x07 /*!< RW ISO14443B Settings Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 106 | #define ST25R3911_REG_STREAM_MODE 0x08 /*!< RW Stream Mode Definition Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 107 | #define ST25R3911_REG_AUX 0x09 /*!< RW Auxiliary Definition Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 108 | #define ST25R3911_REG_RX_CONF1 0x0A /*!< RW Receiver Configuration Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 109 | #define ST25R3911_REG_RX_CONF2 0x0B /*!< RW Receiver Configuration Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 110 | #define ST25R3911_REG_RX_CONF3 0x0C /*!< RW Receiver Configuration Register 3 */ |
| DiegoOstuni | 0:98fcd1266df0 | 111 | #define ST25R3911_REG_RX_CONF4 0x0D /*!< RW Receiver Configuration Register 4 */ |
| DiegoOstuni | 0:98fcd1266df0 | 112 | |
| DiegoOstuni | 0:98fcd1266df0 | 113 | #define ST25R3911_REG_MASK_RX_TIMER 0x0E /*!< RW Mask Receive Timer Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 114 | #define ST25R3911_REG_NO_RESPONSE_TIMER1 0x0F /*!< RW No-response Timer Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 115 | #define ST25R3911_REG_NO_RESPONSE_TIMER2 0x10 /*!< RW No-response Timer Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 116 | #define ST25R3911_REG_GPT_CONTROL 0x11 /*!< RW General Purpose Timer Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 117 | #define ST25R3911_REG_GPT1 0x12 /*!< RW General Purpose Timer Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 118 | #define ST25R3911_REG_GPT2 0x13 /*!< RW General Purpose Timer Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 119 | |
| DiegoOstuni | 0:98fcd1266df0 | 120 | #define ST25R3911_REG_IRQ_MASK_MAIN 0x14 /*!< RW Mask Main Interrupt Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 121 | #define ST25R3911_REG_IRQ_MASK_TIMER_NFC 0x15 /*!< RW Mask Timer and NFC Interrupt Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 122 | #define ST25R3911_REG_IRQ_MASK_ERROR_WUP 0x16 /*!< RW Mask Error and Wake-up Interrupt Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 123 | #define ST25R3911_REG_IRQ_MAIN 0x17 /*!< R Main Interrupt Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 124 | #define ST25R3911_REG_IRQ_TIMER_NFC 0x18 /*!< R Timer and NFC Interrupt Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 125 | #define ST25R3911_REG_IRQ_ERROR_WUP 0x19 /*!< R Error and Wake-up Interrupt Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 126 | #define ST25R3911_REG_FIFO_RX_STATUS1 0x1A /*!< R FIFO RX Status Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 127 | #define ST25R3911_REG_FIFO_RX_STATUS2 0x1B /*!< R FIFO RX Status Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 128 | #define ST25R3911_REG_COLLISION_STATUS 0x1C /*!< R Collision Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 129 | |
| DiegoOstuni | 0:98fcd1266df0 | 130 | #define ST25R3911_REG_NUM_TX_BYTES1 0x1D /*!< RW Number of Transmitted Bytes Register 1 */ |
| DiegoOstuni | 0:98fcd1266df0 | 131 | #define ST25R3911_REG_NUM_TX_BYTES2 0x1E /*!< RW Number of Transmitted Bytes Register 2 */ |
| DiegoOstuni | 0:98fcd1266df0 | 132 | |
| DiegoOstuni | 0:98fcd1266df0 | 133 | #define ST25R3911_REG_NFCIP1_BIT_RATE 0x1F /*!< R NFCIP Bit Rate Detection Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 134 | |
| DiegoOstuni | 0:98fcd1266df0 | 135 | #define ST25R3911_REG_AD_RESULT 0x20 /*!< R A/D Converter Output Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 136 | |
| DiegoOstuni | 0:98fcd1266df0 | 137 | #define ST25R3911_REG_ANT_CAL_CONTROL 0x21 /*!< RW Antenna Calibration Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 138 | #define ST25R3911_REG_ANT_CAL_TARGET 0x22 /*!< RW Antenna Calibration Target Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 139 | #define ST25R3911_REG_ANT_CAL_RESULT 0x23 /*!< R Antenna Calibration Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 140 | |
| DiegoOstuni | 0:98fcd1266df0 | 141 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL 0x24 /*!< RW AM Modulation Depth Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 142 | #define ST25R3911_REG_AM_MOD_DEPTH_RESULT 0x25 /*!< R AM Modulation Depth Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 143 | #define ST25R3911_REG_RFO_AM_ON_LEVEL 0x26 /*!< RW RFO AM Modulation (On) Level Definition Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 144 | #define ST25R3911_REG_RFO_AM_OFF_LEVEL 0x27 /*!< RW RFO Normal (AM Off) Level Definition Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 145 | |
| DiegoOstuni | 0:98fcd1266df0 | 146 | #define ST25R3911_REG_FIELD_THRESHOLD 0x29 /*!< RW External Field Detector Threshold Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 147 | |
| DiegoOstuni | 0:98fcd1266df0 | 148 | #define ST25R3911_REG_REGULATOR_CONTROL 0x2A /*!< RW Regulated Voltage Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 149 | #define ST25R3911_REG_REGULATOR_RESULT 0x2B /*!< R Regulator Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 150 | |
| DiegoOstuni | 0:98fcd1266df0 | 151 | #define ST25R3911_REG_RSSI_RESULT 0x2C /*!< R RSSI Display Register*/ |
| DiegoOstuni | 0:98fcd1266df0 | 152 | #define ST25R3911_REG_GAIN_RED_STATE 0x2D /*!< R Gain Reduction State Register*/ |
| DiegoOstuni | 0:98fcd1266df0 | 153 | |
| DiegoOstuni | 0:98fcd1266df0 | 154 | #define ST25R3911_REG_CAP_SENSOR_CONTROL 0x2E /*!< RW Capacitive Sensor Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 155 | #define ST25R3911_REG_CAP_SENSOR_RESULT 0x2F /*!< R Capacitive Sensor Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 156 | |
| DiegoOstuni | 0:98fcd1266df0 | 157 | #define ST25R3911_REG_AUX_DISPLAY 0x30 /*!< R Auxiliary Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 158 | |
| DiegoOstuni | 0:98fcd1266df0 | 159 | #define ST25R3911_REG_WUP_TIMER_CONTROL 0x31 /*!< RW Wake-up Timer Control Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 160 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF 0x32 /*!< RW Amplitude Measurement Configuration Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 161 | #define ST25R3911_REG_AMPLITUDE_MEASURE_REF 0x33 /*!< RW Amplitude Measurement Reference Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 162 | #define ST25R3911_REG_AMPLITUDE_MEASURE_AA_RESULT 0x34 /*!< R Amplitude Measurement Auto Averaging Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 163 | #define ST25R3911_REG_AMPLITUDE_MEASURE_RESULT 0x35 /*!< R Amplitude Measurement Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 164 | #define ST25R3911_REG_PHASE_MEASURE_CONF 0x36 /*!< RW Phase Measurement Configuration Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 165 | #define ST25R3911_REG_PHASE_MEASURE_REF 0x37 /*!< RW Phase Measurement Reference Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 166 | #define ST25R3911_REG_PHASE_MEASURE_AA_RESULT 0x38 /*!< R Phase Measurement Auto Averaging Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 167 | #define ST25R3911_REG_PHASE_MEASURE_RESULT 0x39 /*!< R Phase Measurement Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 168 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF 0x3A /*!< RW Capacitance Measurement Configuration Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 169 | #define ST25R3911_REG_CAPACITANCE_MEASURE_REF 0x3B /*!< RW Capacitance Measurement Reference Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 170 | #define ST25R3911_REG_CAPACITANCE_MEASURE_AA_RESULT 0x3C /*!< R Capacitance Measurement Auto Averaging Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 171 | #define ST25R3911_REG_CAPACITANCE_MEASURE_RESULT 0x3D /*!< R Capacitance Measurement Display Register */ |
| DiegoOstuni | 0:98fcd1266df0 | 172 | #define ST25R3911_REG_IC_IDENTITY 0x3F /*!< R Chip Id: 0 for old silicon, v2 silicon: 0x09 */ |
| DiegoOstuni | 0:98fcd1266df0 | 173 | |
| DiegoOstuni | 0:98fcd1266df0 | 174 | |
| DiegoOstuni | 0:98fcd1266df0 | 175 | /*! Register bit definitions \cond DOXYGEN_SUPRESS */ |
| DiegoOstuni | 0:98fcd1266df0 | 176 | |
| DiegoOstuni | 0:98fcd1266df0 | 177 | #define ST25R3911_REG_IO_CONF1_lf_clk_off (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 178 | #define ST25R3911_REG_IO_CONF1_out_cl0 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 179 | #define ST25R3911_REG_IO_CONF1_out_cl1 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 180 | #define ST25R3911_REG_IO_CONF1_osc (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 181 | #define ST25R3911_REG_IO_CONF1_fifo_lt (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 182 | #define ST25R3911_REG_IO_CONF1_fifo_lt_32bytes (0<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 183 | #define ST25R3911_REG_IO_CONF1_fifo_lt_16bytes (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 184 | #define ST25R3911_REG_IO_CONF1_fifo_lr (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 185 | #define ST25R3911_REG_IO_CONF1_fifo_lr_64bytes (0<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 186 | #define ST25R3911_REG_IO_CONF1_fifo_lr_80bytes (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 187 | #define ST25R3911_REG_IO_CONF1_rfo2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 188 | #define ST25R3911_REG_IO_CONF1_single (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 189 | #define ST25R3911_REG_IO_CONF2_slow_up (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 190 | #define ST25R3911_REG_IO_CONF2_io_18 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 191 | #define ST25R3911_REG_IO_CONF2_miso_pd1 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 192 | #define ST25R3911_REG_IO_CONF2_miso_pd2 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 193 | #define ST25R3911_REG_IO_CONF2_vspd_off (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 194 | #define ST25R3911_REG_IO_CONF2_sup3V (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 195 | #define ST25R3911_REG_OP_CONTROL_wu (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 196 | #define ST25R3911_REG_OP_CONTROL_tx_en (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 197 | #define ST25R3911_REG_OP_CONTROL_rx_man (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 198 | #define ST25R3911_REG_OP_CONTROL_rx_chn (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 199 | #define ST25R3911_REG_OP_CONTROL_rx_en (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 200 | #define ST25R3911_REG_OP_CONTROL_en (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 201 | #define ST25R3911_REG_MODE_nfc_ar (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 202 | #define ST25R3911_REG_MODE_nfc_ar_on (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 203 | #define ST25R3911_REG_MODE_nfc_ar_off (0<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 204 | #define ST25R3911_REG_MODE_mask_om (0xf<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 205 | #define ST25R3911_REG_MODE_om_nfc (0x0<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 206 | #define ST25R3911_REG_MODE_om_iso14443a (0x1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 207 | #define ST25R3911_REG_MODE_om_iso14443b (0x2<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 208 | #define ST25R3911_REG_MODE_om_felica (0x3<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 209 | #define ST25R3911_REG_MODE_om_topaz (0x4<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 210 | #define ST25R3911_REG_MODE_om_subcarrier_stream (0xe<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 211 | #define ST25R3911_REG_MODE_om_bpsk_stream (0xf<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 212 | #define ST25R3911_REG_MODE_om_bit_rate_detection (0x0<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 213 | #define ST25R3911_REG_MODE_om_nfcip1_normal_mode (0x1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 214 | #define ST25R3911_REG_MODE_targ (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 215 | #define ST25R3911_REG_MODE_targ_targ (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 216 | #define ST25R3911_REG_MODE_targ_init (0<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 217 | #define ST25R3911_REG_BIT_RATE_mask_txrate (0xf<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 218 | #define ST25R3911_REG_BIT_RATE_shift_txrate (4) |
| DiegoOstuni | 0:98fcd1266df0 | 219 | #define ST25R3911_REG_BIT_RATE_txrate_106 (0x0<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 220 | #define ST25R3911_REG_BIT_RATE_txrate_212 (0x1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 221 | #define ST25R3911_REG_BIT_RATE_txrate_424 (0x2<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 222 | #define ST25R3911_REG_BIT_RATE_txrate_848 (0x3<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 223 | #define ST25R3911_REG_BIT_RATE_txrate_1695 (0x4<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 224 | #define ST25R3911_REG_BIT_RATE_txrate_3390 (0x5<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 225 | #define ST25R3911_REG_BIT_RATE_txrate_6780 (0x6<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 226 | #define ST25R3911_REG_BIT_RATE_mask_rxrate (0xf<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 227 | #define ST25R3911_REG_BIT_RATE_shift_rxrate (0) |
| DiegoOstuni | 0:98fcd1266df0 | 228 | #define ST25R3911_REG_BIT_RATE_rxrate_106 (0x0<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 229 | #define ST25R3911_REG_BIT_RATE_rxrate_212 (0x1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 230 | #define ST25R3911_REG_BIT_RATE_rxrate_424 (0x2<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 231 | #define ST25R3911_REG_BIT_RATE_rxrate_848 (0x3<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 232 | #define ST25R3911_REG_BIT_RATE_rxrate_1695 (0x4<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 233 | #define ST25R3911_REG_BIT_RATE_rxrate_3390 (0x5<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 234 | #define ST25R3911_REG_BIT_RATE_rxrate_6780 (0x6<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 235 | #define ST25R3911_REG_ISO14443A_NFC_antcl (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 236 | #define ST25R3911_REG_ISO14443A_NFC_mask_p_len (0xf<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 237 | #define ST25R3911_REG_ISO14443A_NFC_shift_p_len (1) |
| DiegoOstuni | 0:98fcd1266df0 | 238 | #define ST25R3911_REG_ISO14443A_NFC_nfc_f0 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 239 | #define ST25R3911_REG_ISO14443A_NFC_nfc_f0_off (0<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 240 | #define ST25R3911_REG_ISO14443A_NFC_no_rx_par (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 241 | #define ST25R3911_REG_ISO14443A_NFC_no_rx_par_off (0<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 242 | #define ST25R3911_REG_ISO14443A_NFC_no_tx_par (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 243 | #define ST25R3911_REG_ISO14443A_NFC_no_tx_par_off (0<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 244 | #define ST25R3911_REG_ISO14443B_1_mask_eof (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 245 | #define ST25R3911_REG_ISO14443B_1_eof_10etu (0<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 246 | #define ST25R3911_REG_ISO14443B_1_eof_11etu (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 247 | #define ST25R3911_REG_ISO14443B_1_mask_sof (3<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 248 | #define ST25R3911_REG_ISO14443B_1_mask_sof_0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 249 | #define ST25R3911_REG_ISO14443B_1_sof_0_10etu (0<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 250 | #define ST25R3911_REG_ISO14443B_1_sof_0_11etu (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 251 | #define ST25R3911_REG_ISO14443B_1_mask_sof_1 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 252 | #define ST25R3911_REG_ISO14443B_1_sof_1_2etu (0<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 253 | #define ST25R3911_REG_ISO14443B_1_sof_2_3etu (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 254 | #define ST25R3911_REG_ISO14443B_1_mask_egt (7<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 255 | #define ST25R3911_REG_ISO14443B_1_shift_egt (5) |
| DiegoOstuni | 0:98fcd1266df0 | 256 | #define ST25R3911_REG_ISO14443B_2_eof_12 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 257 | #define ST25R3911_REG_ISO14443B_2_eof_12_10to11etu (0<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 258 | #define ST25R3911_REG_ISO14443B_2_eof_12_10to12etu (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 259 | #define ST25R3911_REG_ISO14443B_2_no_eof (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 260 | #define ST25R3911_REG_ISO14443B_2_no_sof (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 261 | #define ST25R3911_REG_ISO14443B_2_mask_tr1 (3<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 262 | #define ST25R3911_REG_ISO14443B_2_shift_tr1 (6) |
| DiegoOstuni | 0:98fcd1266df0 | 263 | #define ST25R3911_REG_ISO14443B_2_tr1_0 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 264 | #define ST25R3911_REG_ISO14443B_2_tr1_1 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 265 | #define ST25R3911_REG_ISO14443B_2_tr1_80fs80fs (0<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 266 | #define ST25R3911_REG_ISO14443B_2_tr1_64fs32fs (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 267 | #define ST25R3911_REG_STREAM_MODE_mask_stx (7<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 268 | #define ST25R3911_REG_STREAM_MODE_shift_stx (0) |
| DiegoOstuni | 0:98fcd1266df0 | 269 | #define ST25R3911_REG_STREAM_MODE_stx_106 (0<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 270 | #define ST25R3911_REG_STREAM_MODE_stx_212 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 271 | #define ST25R3911_REG_STREAM_MODE_stx_424 (2<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 272 | #define ST25R3911_REG_STREAM_MODE_stx_848 (3<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 273 | #define ST25R3911_REG_STREAM_MODE_stx_1695 (4<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 274 | #define ST25R3911_REG_STREAM_MODE_stx_3390 (5<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 275 | #define ST25R3911_REG_STREAM_MODE_stx_6780 (6<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 276 | #define ST25R3911_REG_STREAM_MODE_mask_scp (3<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 277 | #define ST25R3911_REG_STREAM_MODE_shift_scp (3) |
| DiegoOstuni | 0:98fcd1266df0 | 278 | #define ST25R3911_REG_STREAM_MODE_scp_1pulse (0<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 279 | #define ST25R3911_REG_STREAM_MODE_scp_2pulses (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 280 | #define ST25R3911_REG_STREAM_MODE_scp_4pulses (2<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 281 | #define ST25R3911_REG_STREAM_MODE_scp_8pulses (3<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 282 | #define ST25R3911_REG_STREAM_MODE_mask_scf (3<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 283 | #define ST25R3911_REG_STREAM_MODE_shift_scf (5) |
| DiegoOstuni | 0:98fcd1266df0 | 284 | #define ST25R3911_REG_STREAM_MODE_scf_bpsk848 (0<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 285 | #define ST25R3911_REG_STREAM_MODE_scf_bpsk1695 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 286 | #define ST25R3911_REG_STREAM_MODE_scf_bpsk3390 (2<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 287 | #define ST25R3911_REG_STREAM_MODE_scf_bpsk106 (3<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 288 | #define ST25R3911_REG_STREAM_MODE_scf_sc212 (0<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 289 | #define ST25R3911_REG_STREAM_MODE_scf_sc424 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 290 | #define ST25R3911_REG_STREAM_MODE_scf_sc848 (2<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 291 | #define ST25R3911_REG_STREAM_MODE_scf_sc1695 (3<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 292 | #define ST25R3911_REG_AUX_mask_nfc_n (3<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 293 | #define ST25R3911_REG_AUX_nfc_n0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 294 | #define ST25R3911_REG_AUX_nfc_n1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 295 | #define ST25R3911_REG_AUX_rx_tol (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 296 | #define ST25R3911_REG_AUX_ook_hr (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 297 | #define ST25R3911_REG_AUX_en_fd (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 298 | #define ST25R3911_REG_AUX_tr_am (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 299 | #define ST25R3911_REG_AUX_crc_2_fifo (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 300 | #define ST25R3911_REG_AUX_no_crc_rx (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 301 | #define ST25R3911_REG_RX_CONF1_z12k (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 302 | #define ST25R3911_REG_RX_CONF1_h80 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 303 | #define ST25R3911_REG_RX_CONF1_h200 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 304 | #define ST25R3911_REG_RX_CONF1_mask_lp (7<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 305 | #define ST25R3911_REG_RX_CONF1_lp_1200khz (0<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 306 | #define ST25R3911_REG_RX_CONF1_lp_600khz (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 307 | #define ST25R3911_REG_RX_CONF1_lp_300khz (2<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 308 | #define ST25R3911_REG_RX_CONF1_lp_2000khz (4<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 309 | #define ST25R3911_REG_RX_CONF1_lp_7000khz (5<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 310 | #define ST25R3911_REG_RX_CONF1_amd_sel (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 311 | #define ST25R3911_REG_RX_CONF1_ch_sel (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 312 | #define ST25R3911_REG_RX_CONF2_sqm_dyn (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 313 | #define ST25R3911_REG_RX_CONF2_agc_alg (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 314 | #define ST25R3911_REG_RX_CONF2_agc_m (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 315 | #define ST25R3911_REG_RX_CONF2_agc_en (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 316 | #define ST25R3911_REG_RX_CONF2_lf_en (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 317 | #define ST25R3911_REG_RX_CONF2_lf_op (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 318 | #define ST25R3911_REG_RX_CONF2_rx_lp (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 319 | #define ST25R3911_REG_RX_CONF3_rg_nfc (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 320 | #define ST25R3911_REG_RX_CONF3_lim (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 321 | #define ST25R3911_REG_RX_CONF3_shift_rg1_pm (2) |
| DiegoOstuni | 0:98fcd1266df0 | 322 | #define ST25R3911_REG_RX_CONF3_mask_rg1_pm (0x7<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 323 | #define ST25R3911_REG_RX_CONF3_rg1_pm0 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 324 | #define ST25R3911_REG_RX_CONF3_rg1_pm1 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 325 | #define ST25R3911_REG_RX_CONF3_rg1_pm2 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 326 | #define ST25R3911_REG_RX_CONF3_shift_rg1_am (5) |
| DiegoOstuni | 0:98fcd1266df0 | 327 | #define ST25R3911_REG_RX_CONF3_mask_rg1_am (0x7<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 328 | #define ST25R3911_REG_RX_CONF3_rg1_am0 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 329 | #define ST25R3911_REG_RX_CONF3_rg1_am1 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 330 | #define ST25R3911_REG_RX_CONF3_rg1_am2 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 331 | #define ST25R3911_REG_RX_CONF4_shift_rg2_pm (0) |
| DiegoOstuni | 0:98fcd1266df0 | 332 | #define ST25R3911_REG_RX_CONF4_mask_rg2_pm (0xf<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 333 | #define ST25R3911_REG_RX_CONF4_rg2_pm0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 334 | #define ST25R3911_REG_RX_CONF4_rg2_pm1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 335 | #define ST25R3911_REG_RX_CONF4_rg2_pm2 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 336 | #define ST25R3911_REG_RX_CONF4_rg2_pm3 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 337 | #define ST25R3911_REG_RX_CONF4_shift_rg2_am (4) |
| DiegoOstuni | 0:98fcd1266df0 | 338 | #define ST25R3911_REG_RX_CONF4_mask_rg2_am (0xf<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 339 | #define ST25R3911_REG_RX_CONF4_rg2_am0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 340 | #define ST25R3911_REG_RX_CONF4_rg2_am1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 341 | #define ST25R3911_REG_RX_CONF4_rg2_am2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 342 | #define ST25R3911_REG_RX_CONF4_rg2_am3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 343 | #define ST25R3911_REG_GPT_CONTROL_nrt_step (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 344 | #define ST25R3911_REG_GPT_CONTROL_nrt_emv (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 345 | #define ST25R3911_REG_GPT_CONTROL_gptc0 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 346 | #define ST25R3911_REG_GPT_CONTROL_gptc1 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 347 | #define ST25R3911_REG_GPT_CONTROL_gptc2 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 348 | #define ST25R3911_REG_GPT_CONTROL_gptc_mask (0x7<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 349 | #define ST25R3911_REG_GPT_CONTROL_gptc_no_trigger (0x0<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 350 | #define ST25R3911_REG_GPT_CONTROL_gptc_erx (0x1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 351 | #define ST25R3911_REG_GPT_CONTROL_gptc_srx (0x2<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 352 | #define ST25R3911_REG_GPT_CONTROL_gptc_etx_nfc (0x3<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 353 | #define ST25R3911_REG_FIFO_RX_STATUS2_np_lb (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 354 | #define ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb (7<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 355 | #define ST25R3911_REG_FIFO_RX_STATUS2_shift_fifo_lb (1) |
| DiegoOstuni | 0:98fcd1266df0 | 356 | #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb0 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 357 | #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb1 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 358 | #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb2 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 359 | #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_ncp (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 360 | #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_ovr (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 361 | #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_unf (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 362 | #define ST25R3911_REG_COLLISION_STATUS_c_pb (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 363 | #define ST25R3911_REG_COLLISION_STATUS_mask_c_bit (3<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 364 | #define ST25R3911_REG_COLLISION_STATUS_shift_c_bit (1) |
| DiegoOstuni | 0:98fcd1266df0 | 365 | #define ST25R3911_REG_COLLISION_STATUS_mask_c_byte (0xf<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 366 | #define ST25R3911_REG_COLLISION_STATUS_shift_c_byte (4) |
| DiegoOstuni | 0:98fcd1266df0 | 367 | #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 368 | #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 369 | #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 370 | #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 371 | #define ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_mask (0xf<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 372 | #define ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_shift (4) |
| DiegoOstuni | 0:98fcd1266df0 | 373 | #define ST25R3911_REG_ANT_CAL_CONTROL_mask_tre (0xf<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 374 | #define ST25R3911_REG_ANT_CAL_CONTROL_shift_tre (3) |
| DiegoOstuni | 0:98fcd1266df0 | 375 | #define ST25R3911_REG_ANT_CAL_CONTROL_tre_0 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 376 | #define ST25R3911_REG_ANT_CAL_CONTROL_tre_1 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 377 | #define ST25R3911_REG_ANT_CAL_CONTROL_tre_2 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 378 | #define ST25R3911_REG_ANT_CAL_CONTROL_tre_3 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 379 | #define ST25R3911_REG_ANT_CAL_CONTROL_trim_s (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 380 | #define ST25R3911_REG_ANT_CAL_RESULT_tri_err (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 381 | #define ST25R3911_REG_ANT_CAL_RESULT_tri_0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 382 | #define ST25R3911_REG_ANT_CAL_RESULT_tri_1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 383 | #define ST25R3911_REG_ANT_CAL_RESULT_tri_2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 384 | #define ST25R3911_REG_ANT_CAL_RESULT_tri_3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 385 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mask_mod (0x3f<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 386 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_shift_mod (1) |
| DiegoOstuni | 0:98fcd1266df0 | 387 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_8percent (0xb<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 388 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_10percent (0xe<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 389 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_14percent (0x14<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 390 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_20percent (0x20<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 391 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_25percent (0x2a<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 392 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_30percent (0x37<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 393 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_33percent (0x3f<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 394 | #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_am_s (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 395 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 396 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 397 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram2 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 398 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram3 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 399 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram4 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 400 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram5 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 401 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram6 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 402 | #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram7 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 403 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 404 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 405 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t2 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 406 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t3 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 407 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_l0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 408 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_l1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 409 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_l2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 410 | #define ST25R3911_REG_FIELD_THRESHOLD_mask_trg (0x07<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 411 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_75mV (0x00<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 412 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_105mV (0x01<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 413 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_150mV (0x02<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 414 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_205mV (0x03<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 415 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_290mV (0x04<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 416 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_400mV (0x05<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 417 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_560mV (0x06<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 418 | #define ST25R3911_REG_FIELD_THRESHOLD_trg_800mV (0x07<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 419 | #define ST25R3911_REG_FIELD_THRESHOLD_mask_rfe (0x0F<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 420 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_75mV (0x00<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 421 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_105mV (0x01<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 422 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_150mV (0x02<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 423 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_205mV (0x03<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 424 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_290mV (0x04<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 425 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_400mV (0x05<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 426 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_560mV (0x06<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 427 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_800mV (0x07<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 428 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_25mV (0x08<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 429 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_33mV (0x09<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 430 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_47mV (0x0A<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 431 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_64mV (0x0B<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 432 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_90mV (0x0C<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 433 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_125mV (0x0D<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 434 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_175mV (0x0E<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 435 | #define ST25R3911_REG_FIELD_THRESHOLD_rfe_250mV (0x0F<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 436 | #define ST25R3911_REG_REGULATOR_CONTROL_shift_mpsv (1) |
| DiegoOstuni | 0:98fcd1266df0 | 437 | #define ST25R3911_REG_REGULATOR_CONTROL_mask_mpsv (3<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 438 | #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vdd (0<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 439 | #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_a (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 440 | #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_d (2<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 441 | #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_rf (3<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 442 | #define ST25R3911_REG_REGULATOR_CONTROL_mask_rege (0xf<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 443 | #define ST25R3911_REG_REGULATOR_CONTROL_shift_rege (3) |
| DiegoOstuni | 0:98fcd1266df0 | 444 | #define ST25R3911_REG_REGULATOR_CONTROL_reg_s (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 445 | #define ST25R3911_REG_REGULATOR_RESULT_mrt_on (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 446 | #define ST25R3911_REG_REGULATOR_RESULT_nrt_on (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 447 | #define ST25R3911_REG_REGULATOR_RESULT_gpt_on (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 448 | #define ST25R3911_REG_REGULATOR_RESULT_mask_reg (0xf<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 449 | #define ST25R3911_REG_REGULATOR_RESULT_shift_reg (4) |
| DiegoOstuni | 0:98fcd1266df0 | 450 | #define ST25R3911_REG_REGULATOR_RESULT_reg_0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 451 | #define ST25R3911_REG_REGULATOR_RESULT_reg_1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 452 | #define ST25R3911_REG_REGULATOR_RESULT_reg_2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 453 | #define ST25R3911_REG_REGULATOR_RESULT_reg_3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 454 | #define ST25R3911_REG_RSSI_RESULT_rssi_pm0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 455 | #define ST25R3911_REG_RSSI_RESULT_rssi_pm1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 456 | #define ST25R3911_REG_RSSI_RESULT_rssi_pm2 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 457 | #define ST25R3911_REG_RSSI_RESULT_rssi_pm3 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 458 | #define ST25R3911_REG_RSSI_RESULT_rssi_am_0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 459 | #define ST25R3911_REG_RSSI_RESULT_rssi_am_1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 460 | #define ST25R3911_REG_RSSI_RESULT_rssi_am_2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 461 | #define ST25R3911_REG_RSSI_RESULT_rssi_am_3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 462 | #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 463 | #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 464 | #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_2 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 465 | #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_3 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 466 | #define ST25R3911_REG_GAIN_RED_STATE_gs_am_0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 467 | #define ST25R3911_REG_GAIN_RED_STATE_gs_am_1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 468 | #define ST25R3911_REG_GAIN_RED_STATE_gs_am_2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 469 | #define ST25R3911_REG_GAIN_RED_STATE_gs_am_3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 470 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g0 (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 471 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g1 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 472 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g2 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 473 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal0 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 474 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal1 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 475 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal2 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 476 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal3 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 477 | #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal4 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 478 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_err (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 479 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_end (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 480 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal0 (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 481 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal1 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 482 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal2 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 483 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal3 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 484 | #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal4 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 485 | #define ST25R3911_REG_AUX_DISPLAY_mrt_on (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 486 | #define ST25R3911_REG_AUX_DISPLAY_nrt_on (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 487 | #define ST25R3911_REG_AUX_DISPLAY_gpt_on (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 488 | #define ST25R3911_REG_AUX_DISPLAY_rx_on (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 489 | #define ST25R3911_REG_AUX_DISPLAY_osc_ok (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 490 | #define ST25R3911_REG_AUX_DISPLAY_tx_on (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 491 | #define ST25R3911_REG_AUX_DISPLAY_efd_o (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 492 | #define ST25R3911_REG_AUX_DISPLAY_a_cha (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 493 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wcap (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 494 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wph (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 495 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wam (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 496 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wto (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 497 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wut0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 498 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wut1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 499 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wut2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 500 | #define ST25R3911_REG_WUP_TIMER_CONTROL_shift_wut (4) |
| DiegoOstuni | 0:98fcd1266df0 | 501 | #define ST25R3911_REG_WUP_TIMER_CONTROL_wur (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 502 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_ae (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 503 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aew0 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 504 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aew1 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 505 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_aew (1) |
| DiegoOstuni | 0:98fcd1266df0 | 506 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_mask_am_aew (3<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 507 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aam (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 508 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 509 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 510 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 511 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 512 | #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_d (4) |
| DiegoOstuni | 0:98fcd1266df0 | 513 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_ae (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 514 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aew0 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 515 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aew1 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 516 | #define ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_aew (1) |
| DiegoOstuni | 0:98fcd1266df0 | 517 | #define ST25R3911_REG_PHASE_MEASURE_CONF_mask_pm_aew (3<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 518 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aam (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 519 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 520 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 521 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 522 | #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 523 | #define ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_d (4) |
| DiegoOstuni | 0:98fcd1266df0 | 524 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_ae (1<<0) |
| DiegoOstuni | 0:98fcd1266df0 | 525 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aew0 (1<<1) |
| DiegoOstuni | 0:98fcd1266df0 | 526 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aew1 (1<<2) |
| DiegoOstuni | 0:98fcd1266df0 | 527 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aam (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 528 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d0 (1<<4) |
| DiegoOstuni | 0:98fcd1266df0 | 529 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d1 (1<<5) |
| DiegoOstuni | 0:98fcd1266df0 | 530 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d2 (1<<6) |
| DiegoOstuni | 0:98fcd1266df0 | 531 | #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d3 (1<<7) |
| DiegoOstuni | 0:98fcd1266df0 | 532 | #define ST25R3911_REG_IC_IDENTITY_v2 (0x09) |
| DiegoOstuni | 0:98fcd1266df0 | 533 | #define ST25R3911_REG_IC_IDENTITY_ic_type (1<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 534 | #define ST25R3911_REG_IC_IDENTITY_mask_ic_type (0x1F<<3) |
| DiegoOstuni | 0:98fcd1266df0 | 535 | #define ST25R3911_REG_IC_IDENTITY_shift_ic_type (3) |
| DiegoOstuni | 0:98fcd1266df0 | 536 | #define ST25R3911_REG_IC_IDENTITY_mask_ic_rev (7) |
| DiegoOstuni | 0:98fcd1266df0 | 537 | |
| DiegoOstuni | 0:98fcd1266df0 | 538 | /*! \endcond DOXYGEN_SUPRESS */ |
| DiegoOstuni | 0:98fcd1266df0 | 539 | |
| DiegoOstuni | 0:98fcd1266df0 | 540 | /* |
| DiegoOstuni | 0:98fcd1266df0 | 541 | ****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 542 | * GLOBAL FUNCTION PROTOTYPES |
| DiegoOstuni | 0:98fcd1266df0 | 543 | ****************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 544 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 545 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 546 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 547 | * \brief Returns the content of a register within the ST25R3911 |
| DiegoOstuni | 0:98fcd1266df0 | 548 | * |
| DiegoOstuni | 0:98fcd1266df0 | 549 | * This function is used to read out the content of ST25R3911 registers. |
| DiegoOstuni | 0:98fcd1266df0 | 550 | * |
| DiegoOstuni | 0:98fcd1266df0 | 551 | * \param[in] reg: Address of register to read. |
| DiegoOstuni | 0:98fcd1266df0 | 552 | * \param[out] val: Returned value. |
| DiegoOstuni | 0:98fcd1266df0 | 553 | * |
| DiegoOstuni | 0:98fcd1266df0 | 554 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 555 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 556 | //extern void st25r3911ReadRegister(uint8_t reg, uint8_t* val); |
| DiegoOstuni | 0:98fcd1266df0 | 557 | |
| DiegoOstuni | 0:98fcd1266df0 | 558 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 559 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 560 | * \brief Writes a given value to a register within the ST25R3911 |
| DiegoOstuni | 0:98fcd1266df0 | 561 | * |
| DiegoOstuni | 0:98fcd1266df0 | 562 | * This function is used to write \a val to address \a reg within the ST25R3911. |
| DiegoOstuni | 0:98fcd1266df0 | 563 | * |
| DiegoOstuni | 0:98fcd1266df0 | 564 | * \param[in] reg: Address of the register to write. |
| DiegoOstuni | 0:98fcd1266df0 | 565 | * \param[in] val: Value to be written. |
| DiegoOstuni | 0:98fcd1266df0 | 566 | * |
| DiegoOstuni | 0:98fcd1266df0 | 567 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 568 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 569 | //extern void st25r3911WriteRegister(uint8_t reg, uint8_t val); |
| DiegoOstuni | 0:98fcd1266df0 | 570 | |
| DiegoOstuni | 0:98fcd1266df0 | 571 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 572 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 573 | * \brief Cleart bits on Register |
| DiegoOstuni | 0:98fcd1266df0 | 574 | * |
| DiegoOstuni | 0:98fcd1266df0 | 575 | * This function clears the given bitmask on the register |
| DiegoOstuni | 0:98fcd1266df0 | 576 | * |
| DiegoOstuni | 0:98fcd1266df0 | 577 | * \warning This method does not guarantee consistency of register content |
| DiegoOstuni | 0:98fcd1266df0 | 578 | * when called from multiple contexts (task, ISR, thread) |
| DiegoOstuni | 0:98fcd1266df0 | 579 | * |
| DiegoOstuni | 0:98fcd1266df0 | 580 | * \param[in] reg: Address of the register clear |
| DiegoOstuni | 0:98fcd1266df0 | 581 | * \param[in] clr_mask: Bitmask of bit to be cleared |
| DiegoOstuni | 0:98fcd1266df0 | 582 | * |
| DiegoOstuni | 0:98fcd1266df0 | 583 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 584 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 585 | extern void st25r3911ClrRegisterBits( uint8_t reg, uint8_t clr_mask, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 586 | |
| DiegoOstuni | 0:98fcd1266df0 | 587 | |
| DiegoOstuni | 0:98fcd1266df0 | 588 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 589 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 590 | * \brief Set bits on Register |
| DiegoOstuni | 0:98fcd1266df0 | 591 | * |
| DiegoOstuni | 0:98fcd1266df0 | 592 | * This function sets the given bitmask on the register |
| DiegoOstuni | 0:98fcd1266df0 | 593 | * |
| DiegoOstuni | 0:98fcd1266df0 | 594 | * \warning This method does not guarantee consistency of register content |
| DiegoOstuni | 0:98fcd1266df0 | 595 | * when called from multiple contexts (task, ISR, thread) |
| DiegoOstuni | 0:98fcd1266df0 | 596 | * |
| DiegoOstuni | 0:98fcd1266df0 | 597 | * \param[in] reg: Address of the register clear |
| DiegoOstuni | 0:98fcd1266df0 | 598 | * \param[in] set_mask: Bitmask of bit to be cleared |
| DiegoOstuni | 0:98fcd1266df0 | 599 | * |
| DiegoOstuni | 0:98fcd1266df0 | 600 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 601 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 602 | extern void st25r3911SetRegisterBits( uint8_t reg, uint8_t set_mask, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 603 | |
| DiegoOstuni | 0:98fcd1266df0 | 604 | |
| DiegoOstuni | 0:98fcd1266df0 | 605 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 606 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 607 | * \brief Changes the given bits on a ST25R3911 register |
| DiegoOstuni | 0:98fcd1266df0 | 608 | * |
| DiegoOstuni | 0:98fcd1266df0 | 609 | * This function is used if only a particular bits should be changed within |
| DiegoOstuni | 0:98fcd1266df0 | 610 | * an ST25R3911 register. |
| DiegoOstuni | 0:98fcd1266df0 | 611 | * |
| DiegoOstuni | 0:98fcd1266df0 | 612 | * \warning This method does not guarantee consistency of register content |
| DiegoOstuni | 0:98fcd1266df0 | 613 | * when called from multiple contexts (task, ISR, thread) |
| DiegoOstuni | 0:98fcd1266df0 | 614 | * |
| DiegoOstuni | 0:98fcd1266df0 | 615 | * \param[in] reg: Address of the register to write. |
| DiegoOstuni | 0:98fcd1266df0 | 616 | * \param[in] valueMask: bitmask of bits to be changed |
| DiegoOstuni | 0:98fcd1266df0 | 617 | * \param[in] value: the bits to be written on the enabled valueMask bits |
| DiegoOstuni | 0:98fcd1266df0 | 618 | * |
| DiegoOstuni | 0:98fcd1266df0 | 619 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 620 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 621 | extern void st25r3911ChangeRegisterBits(uint8_t reg, uint8_t valueMask, uint8_t value, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 622 | |
| DiegoOstuni | 0:98fcd1266df0 | 623 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 624 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 625 | * \brief Read a test register within the ST25R3911 |
| DiegoOstuni | 0:98fcd1266df0 | 626 | * |
| DiegoOstuni | 0:98fcd1266df0 | 627 | * This function is used to read the content of test address \a reg within the ST25R3911. |
| DiegoOstuni | 0:98fcd1266df0 | 628 | * |
| DiegoOstuni | 0:98fcd1266df0 | 629 | * \param[in] reg: Address of the register to read. |
| DiegoOstuni | 0:98fcd1266df0 | 630 | * \param[out] val: Returned read. |
| DiegoOstuni | 0:98fcd1266df0 | 631 | * |
| DiegoOstuni | 0:98fcd1266df0 | 632 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 633 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 634 | extern void st25r3911ReadTestRegister(uint8_t reg, uint8_t* val, ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 635 | |
| DiegoOstuni | 0:98fcd1266df0 | 636 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 637 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 638 | * \brief Writes a given value to a test register within the ST25R3911 |
| DiegoOstuni | 0:98fcd1266df0 | 639 | * |
| DiegoOstuni | 0:98fcd1266df0 | 640 | * This function is used to write \a val to test address \a reg within the ST25R3911. |
| DiegoOstuni | 0:98fcd1266df0 | 641 | * |
| DiegoOstuni | 0:98fcd1266df0 | 642 | * \param[in] reg: Address of the register to write. |
| DiegoOstuni | 0:98fcd1266df0 | 643 | * \param[in] val: Value to be written. |
| DiegoOstuni | 0:98fcd1266df0 | 644 | * |
| DiegoOstuni | 0:98fcd1266df0 | 645 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 646 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 647 | extern void st25r3911WriteTestRegister(uint8_t reg, uint8_t val, ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 648 | |
| DiegoOstuni | 0:98fcd1266df0 | 649 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 650 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 651 | * \brief Modifies a value within a ST25R3911 register |
| DiegoOstuni | 0:98fcd1266df0 | 652 | * |
| DiegoOstuni | 0:98fcd1266df0 | 653 | * This function is used if only a particular bits should be changed within |
| DiegoOstuni | 0:98fcd1266df0 | 654 | * an ST25R3911 register. |
| DiegoOstuni | 0:98fcd1266df0 | 655 | * |
| DiegoOstuni | 0:98fcd1266df0 | 656 | * \warning This method does not guarantee consistency of register content |
| DiegoOstuni | 0:98fcd1266df0 | 657 | * when called from multiple contexts (task, ISR, thread) |
| DiegoOstuni | 0:98fcd1266df0 | 658 | * |
| DiegoOstuni | 0:98fcd1266df0 | 659 | * \param[in] reg: Address of the register to write. |
| DiegoOstuni | 0:98fcd1266df0 | 660 | * \param[in] clr_mask: bitmask of bits to be cleared to 0. |
| DiegoOstuni | 0:98fcd1266df0 | 661 | * \param[in] set_mask: bitmask of bits to be set to 1. |
| DiegoOstuni | 0:98fcd1266df0 | 662 | * |
| DiegoOstuni | 0:98fcd1266df0 | 663 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 664 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 665 | extern void st25r3911ModifyRegister(uint8_t reg, uint8_t clr_mask, uint8_t set_mask, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 666 | |
| DiegoOstuni | 0:98fcd1266df0 | 667 | |
| DiegoOstuni | 0:98fcd1266df0 | 668 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 669 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 670 | * \brief Changes the given bits on a ST25R3911 Test register |
| DiegoOstuni | 0:98fcd1266df0 | 671 | * |
| DiegoOstuni | 0:98fcd1266df0 | 672 | * This function is used if only a particular bits should be changed within |
| DiegoOstuni | 0:98fcd1266df0 | 673 | * an ST25R3916 register. |
| DiegoOstuni | 0:98fcd1266df0 | 674 | * |
| DiegoOstuni | 0:98fcd1266df0 | 675 | * \param[in] reg: Address of the Test register to change. |
| DiegoOstuni | 0:98fcd1266df0 | 676 | * \param[in] valueMask: bitmask of bits to be changed |
| DiegoOstuni | 0:98fcd1266df0 | 677 | * \param[in] value: the bits to be written on the enabled valueMask bits |
| DiegoOstuni | 0:98fcd1266df0 | 678 | * |
| DiegoOstuni | 0:98fcd1266df0 | 679 | * \warning This method does not guarantee consistency of register content |
| DiegoOstuni | 0:98fcd1266df0 | 680 | * when called from multiple contexts (task, ISR, thread) |
| DiegoOstuni | 0:98fcd1266df0 | 681 | |
| DiegoOstuni | 0:98fcd1266df0 | 682 | * \return ERR_NONE : Operation successful |
| DiegoOstuni | 0:98fcd1266df0 | 683 | * \return ERR_PARAM : Invalid parameter |
| DiegoOstuni | 0:98fcd1266df0 | 684 | * \return ERR_SEND : Transmission error or acknowledge not received |
| DiegoOstuni | 0:98fcd1266df0 | 685 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 686 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 687 | extern void st25r3911ChangeTestRegisterBits( uint8_t reg, uint8_t valueMask, uint8_t value, ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); |
| DiegoOstuni | 0:98fcd1266df0 | 688 | |
| DiegoOstuni | 0:98fcd1266df0 | 689 | |
| DiegoOstuni | 0:98fcd1266df0 | 690 | /*! |
| DiegoOstuni | 0:98fcd1266df0 | 691 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 692 | * \brief Check if register ID is valid |
| DiegoOstuni | 0:98fcd1266df0 | 693 | * |
| DiegoOstuni | 0:98fcd1266df0 | 694 | * Checks if the given register ID a valid ST25R3911 register |
| DiegoOstuni | 0:98fcd1266df0 | 695 | * |
| DiegoOstuni | 0:98fcd1266df0 | 696 | * \param[in] reg: Address of register to check |
| DiegoOstuni | 0:98fcd1266df0 | 697 | * |
| DiegoOstuni | 0:98fcd1266df0 | 698 | * \return true if is a valid register ID |
| DiegoOstuni | 0:98fcd1266df0 | 699 | * \return false otherwise |
| DiegoOstuni | 0:98fcd1266df0 | 700 | * |
| DiegoOstuni | 0:98fcd1266df0 | 701 | ***************************************************************************** |
| DiegoOstuni | 0:98fcd1266df0 | 702 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 703 | extern bool st25r3911IsRegValid( uint8_t reg ); |
| DiegoOstuni | 0:98fcd1266df0 | 704 | |
| DiegoOstuni | 0:98fcd1266df0 | 705 | #endif /* ST25R3911_COM_H */ |
| DiegoOstuni | 0:98fcd1266df0 | 706 | |
| DiegoOstuni | 0:98fcd1266df0 | 707 | /** |
| DiegoOstuni | 0:98fcd1266df0 | 708 | * @} |
| DiegoOstuni | 0:98fcd1266df0 | 709 | * |
| DiegoOstuni | 0:98fcd1266df0 | 710 | * @} |
| DiegoOstuni | 0:98fcd1266df0 | 711 | * |
| DiegoOstuni | 0:98fcd1266df0 | 712 | * @} |
| DiegoOstuni | 0:98fcd1266df0 | 713 | * |
| DiegoOstuni | 0:98fcd1266df0 | 714 | * @} |
| DiegoOstuni | 0:98fcd1266df0 | 715 | */ |
| DiegoOstuni | 0:98fcd1266df0 | 716 |