ST Americas mbed Team / Nucleo_BLE_BlueNRG

BLE_BlueNRG for Nucleo board

Dependents:   Nucleo_BLE_HeartRate Nucleo_BLE_UART Nucleo_BLE_UART

Warning: Deprecated!

Supported drivers and applications can be found at this link.

hci/src/bluenrg_shield_bsp.c@2:905715088a9b, 2014-12-24 (annotated)

Committer:
sjallouli
Date:
Wed Dec 24 18:01:41 2014 +0000
Revision:
2:905715088a9b
Parent:
1:be1cb4be316f 
Add USER_BUTTON interrupt configuration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sjallouli 0:a948f5f3904c 1 /**
sjallouli 0:a948f5f3904c 2 ******************************************************************************
sjallouli 0:a948f5f3904c 3 * File Name : bluenrg_shield_bsp.c
sjallouli 0:a948f5f3904c 4 * Date : 01/10/2014
sjallouli 0:a948f5f3904c 5 * Description : This file provides code for the BlueNRG Shield driver
sjallouli 0:a948f5f3904c 6 * based on mbed HAL.
sjallouli 0:a948f5f3904c 7 ******************************************************************************
sjallouli 0:a948f5f3904c 8 *
sjallouli 0:a948f5f3904c 9 * COPYRIGHT(c) 2014 STMicroelectronics
sjallouli 0:a948f5f3904c 10 *
sjallouli 0:a948f5f3904c 11 * Redistribution and use in source and binary forms, with or without modification,
sjallouli 0:a948f5f3904c 12 * are permitted provided that the following conditions are met:
sjallouli 0:a948f5f3904c 13 * 1. Redistributions of source code must retain the above copyright notice,
sjallouli 0:a948f5f3904c 14 * this list of conditions and the following disclaimer.
sjallouli 0:a948f5f3904c 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
sjallouli 0:a948f5f3904c 16 * this list of conditions and the following disclaimer in the documentation
sjallouli 0:a948f5f3904c 17 * and/or other materials provided with the distribution.
sjallouli 0:a948f5f3904c 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sjallouli 0:a948f5f3904c 19 * may be used to endorse or promote products derived from this software
sjallouli 0:a948f5f3904c 20 * without specific prior written permission.
sjallouli 0:a948f5f3904c 21 *
sjallouli 0:a948f5f3904c 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sjallouli 0:a948f5f3904c 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sjallouli 0:a948f5f3904c 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sjallouli 0:a948f5f3904c 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sjallouli 0:a948f5f3904c 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sjallouli 0:a948f5f3904c 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sjallouli 0:a948f5f3904c 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sjallouli 0:a948f5f3904c 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sjallouli 0:a948f5f3904c 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sjallouli 0:a948f5f3904c 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sjallouli 0:a948f5f3904c 32 *
sjallouli 0:a948f5f3904c 33 ******************************************************************************
sjallouli 0:a948f5f3904c 34 */
sjallouli 0:a948f5f3904c 35 /* Includes ------------------------------------------------------------------*/
sjallouli 0:a948f5f3904c 36
sjallouli 0:a948f5f3904c 37 #include "hci.h"
sjallouli 0:a948f5f3904c 38 #include "spi_api.h"
sjallouli 0:a948f5f3904c 39 #include "gpio_irq_api.h"
sjallouli 0:a948f5f3904c 40 #include "gpio_api.h"
sjallouli 0:a948f5f3904c 41 #include "wait_api.h"
sjallouli 0:a948f5f3904c 42 #include "pinmap.h"
sjallouli 0:a948f5f3904c 43 #include "bluenrg_shield_bsp.h"
sjallouli 2:905715088a9b 44 //#include "Utils.h"
sjallouli 0:a948f5f3904c 45
sjallouli 0:a948f5f3904c 46 spi_t __spi;
sjallouli 0:a948f5f3904c 47 gpio_irq_t irq_exti;
sjallouli 2:905715088a9b 48 gpio_t gpio_pin_A0;
sjallouli 2:905715088a9b 49
sjallouli 2:905715088a9b 50 gpio_irq_t irq_exti_UB;
sjallouli 2:905715088a9b 51 gpio_t gpio_pin_UB;
sjallouli 2:905715088a9b 52
sjallouli 2:905715088a9b 53 gpio_t gpio_pin_CS;
sjallouli 2:905715088a9b 54 gpio_t gpio_pin_MOSI;
sjallouli 2:905715088a9b 55 gpio_t gpio_pin_MISO;
sjallouli 2:905715088a9b 56 gpio_t gpio_pin_SCLK;
sjallouli 2:905715088a9b 57 gpio_t gpio_pin_RESET;
sjallouli 2:905715088a9b 58
sjallouli 0:a948f5f3904c 59 void EXTI_irq_handler(uint32_t id, gpio_irq_event event);
sjallouli 2:905715088a9b 60
sjallouli 0:a948f5f3904c 61 /** @addtogroup BlueNRG_Shield
sjallouli 0:a948f5f3904c 62 * @{
sjallouli 0:a948f5f3904c 63 */
sjallouli 0:a948f5f3904c 64
sjallouli 0:a948f5f3904c 65 /** @defgroup BlueNRG_Shield_Driver
sjallouli 0:a948f5f3904c 66 * @brief BlueNRG Shield driver based on mbed HAL
sjallouli 0:a948f5f3904c 67 * @{
sjallouli 0:a948f5f3904c 68 */
sjallouli 0:a948f5f3904c 69
sjallouli 2:905715088a9b 70
sjallouli 0:a948f5f3904c 71 /*
sjallouli 0:a948f5f3904c 72 * mbed EXTI IRQ Handler
sjallouli 0:a948f5f3904c 73 *
sjallouli 0:a948f5f3904c 74 */
sjallouli 2:905715088a9b 75 bool user_button_pressed = false;
sjallouli 2:905715088a9b 76 void USER_BUTTON_EXTI_irq_handler(uint32_t id, gpio_irq_event event)
sjallouli 2:905715088a9b 77 {
sjallouli 2:905715088a9b 78 user_button_pressed = true;
sjallouli 2:905715088a9b 79 }
sjallouli 2:905715088a9b 80
sjallouli 0:a948f5f3904c 81 void EXTI_irq_handler(uint32_t id, gpio_irq_event event)
sjallouli 0:a948f5f3904c 82 {
sjallouli 2:905715088a9b 83 tHciDataPacket * hciReadPacket = NULL;
sjallouli 0:a948f5f3904c 84 uint8_t data_len;
sjallouli 0:a948f5f3904c 85
sjallouli 2:905715088a9b 86 if(id == (uint32_t)BNRG_SPI_INSTANCE) //Check id of the IRQ
sjallouli 2:905715088a9b 87 {
sjallouli 2:905715088a9b 88 while (gpio_read(&gpio_pin_A0) == 1)
sjallouli 2:905715088a9b 89 {
sjallouli 2:905715088a9b 90 if (list_is_empty (&hciReadPktPool) == FALSE)
sjallouli 2:905715088a9b 91 {
sjallouli 0:a948f5f3904c 92 /* enqueueing a packet for read */
sjallouli 0:a948f5f3904c 93 list_remove_head (&hciReadPktPool, (tListNode **)&hciReadPacket);
sjallouli 0:a948f5f3904c 94 data_len = BlueNRG_SPI_Read_All(hciReadPacket->dataBuff, HCI_PACKET_SIZE);
sjallouli 0:a948f5f3904c 95
sjallouli 2:905715088a9b 96 if(data_len > 0)
sjallouli 2:905715088a9b 97 {
sjallouli 2:905715088a9b 98 HCI_Input(hciReadPacket);/* Packet will be inserted to the correct queue */
sjallouli 2:905715088a9b 99 }
sjallouli 2:905715088a9b 100 else
sjallouli 2:905715088a9b 101 {
sjallouli 2:905715088a9b 102 list_insert_head(&hciReadPktPool, (tListNode *)hciReadPacket);/* Insert the packet back into the pool */
sjallouli 0:a948f5f3904c 103 }
sjallouli 2:905715088a9b 104 }
sjallouli 2:905715088a9b 105 else
sjallouli 2:905715088a9b 106 {
sjallouli 0:a948f5f3904c 107 /* TODO: HCI Read Packet Pool is empty, wait for a free packet */
sjallouli 0:a948f5f3904c 108 }
sjallouli 0:a948f5f3904c 109 }
sjallouli 0:a948f5f3904c 110 }
sjallouli 2:905715088a9b 111 else if(id == (uint32_t)BNRG_SPI_INSTANCE + 1) //Check id of the IRQ
sjallouli 2:905715088a9b 112 {
sjallouli 2:905715088a9b 113 user_button_pressed = true;
sjallouli 2:905715088a9b 114 }
sjallouli 0:a948f5f3904c 115 }
sjallouli 0:a948f5f3904c 116
sjallouli 0:a948f5f3904c 117 /**
sjallouli 0:a948f5f3904c 118 * @brief This function is used to initialize the SPI communication with
sjallouli 0:a948f5f3904c 119 * the BlueNRG Shield. All params should come from the User
sjallouli 1:be1cb4be316f 120 * @param SPI_MOSI : PA_7 (Nucleo), D11 (Generic Arduino Pin)
sjallouli 1:be1cb4be316f 121 * @param SPI_MISO : PA_6, D12
sjallouli 1:be1cb4be316f 122 * @param SPI_SCLK : PA_5, D13
sjallouli 1:be1cb4be316f 123 * @param SPI_CS : PA_1, A1
sjallouli 1:be1cb4be316f 124 * @param EXTI_IRQ : PA_0, A0
sjallouli 0:a948f5f3904c 125 * @param BlueNRG_RESET : PA_8, D7
sjallouli 0:a948f5f3904c 126 * @retval None
sjallouli 0:a948f5f3904c 127 */
sjallouli 0:a948f5f3904c 128 void BNRG_SPI_Init(void)
sjallouli 2:905715088a9b 129 {
sjallouli 0:a948f5f3904c 130 int ret;
sjallouli 2:905715088a9b 131 spi_init(&__spi, D11, D12, D13, NC);
sjallouli 2:905715088a9b 132
sjallouli 2:905715088a9b 133 #if 1
sjallouli 2:905715088a9b 134 ret = gpio_irq_init(&irq_exti_UB, USER_BUTTON, USER_BUTTON_EXTI_irq_handler,(uint32_t)(BNRG_SPI_INSTANCE+1));
sjallouli 2:905715088a9b 135 gpio_irq_set (&irq_exti_UB, IRQ_FALL, 1);//Set mode to IRQ_RISE
sjallouli 2:905715088a9b 136 gpio_init_in(&gpio_pin_UB, USER_BUTTON);//User Button in Nucleo//Configure the GPIO Pin as Input pin and PullDefault
sjallouli 2:905715088a9b 137 #endif
sjallouli 0:a948f5f3904c 138
sjallouli 2:905715088a9b 139 /*Init IRQ for EXTI Interrupt*/
sjallouli 2:905715088a9b 140 ret = gpio_irq_init(&irq_exti, A0, EXTI_irq_handler,(uint32_t)BNRG_SPI_INSTANCE);
sjallouli 2:905715088a9b 141 gpio_irq_set (&irq_exti, IRQ_RISE, 1);//Set mode to IRQ_RISE
sjallouli 2:905715088a9b 142 gpio_init_in(&gpio_pin_A0, A0);//PA_0 in Nucleo//Configure the GPIO Pin as Input pin and PullDefault
sjallouli 2:905715088a9b 143
sjallouli 2:905715088a9b 144 /* Reset Pin Config */
sjallouli 2:905715088a9b 145 gpio_init (&gpio_pin_RESET, D7);//PA_8 in Nucleo
sjallouli 2:905715088a9b 146 gpio_mode (&gpio_pin_RESET, PullNone);
sjallouli 2:905715088a9b 147 gpio_dir (&gpio_pin_RESET, PIN_OUTPUT);
sjallouli 2:905715088a9b 148 gpio_write(&gpio_pin_RESET, 1);
sjallouli 0:a948f5f3904c 149
sjallouli 2:905715088a9b 150 /* NSS/CSN/CS - PA_1*/
sjallouli 2:905715088a9b 151 gpio_init (&gpio_pin_CS, A1);//PA_1 in Nucleo
sjallouli 2:905715088a9b 152 gpio_mode (&gpio_pin_CS, PullNone);
sjallouli 2:905715088a9b 153 gpio_dir (&gpio_pin_CS, PIN_OUTPUT);
sjallouli 2:905715088a9b 154 gpio_write(&gpio_pin_CS, 1);
sjallouli 0:a948f5f3904c 155 }
sjallouli 0:a948f5f3904c 156
sjallouli 0:a948f5f3904c 157 /**
sjallouli 0:a948f5f3904c 158 * @brief Read from BlueNRG SPI buffer and store data into local buffer
sjallouli 0:a948f5f3904c 159 * @param buffer: buffer where data from SPI are stored
sjallouli 0:a948f5f3904c 160 * @param buff_size: buffer size
sjallouli 0:a948f5f3904c 161 * @retval number of read bytes
sjallouli 0:a948f5f3904c 162 */
sjallouli 0:a948f5f3904c 163 int32_t BlueNRG_SPI_Read_All(uint8_t *buffer, uint8_t buff_size)
sjallouli 0:a948f5f3904c 164 {
sjallouli 0:a948f5f3904c 165 uint16_t byte_count;
sjallouli 0:a948f5f3904c 166 uint8_t len = 0;
sjallouli 0:a948f5f3904c 167 uint8_t i = 0;
sjallouli 0:a948f5f3904c 168 uint8_t char_ff = 0xff;
sjallouli 0:a948f5f3904c 169 volatile uint8_t read_char, tmpreg;
sjallouli 0:a948f5f3904c 170
sjallouli 0:a948f5f3904c 171 uint8_t header_master[5] = {0x0b, 0x00, 0x00, 0x00, 0x00};
sjallouli 0:a948f5f3904c 172 uint8_t header_slave[5];
sjallouli 0:a948f5f3904c 173
sjallouli 0:a948f5f3904c 174 /* CS reset */
sjallouli 0:a948f5f3904c 175 gpio_write(&gpio_pin_CS, 0);
sjallouli 0:a948f5f3904c 176
sjallouli 0:a948f5f3904c 177 /* Read the header */
sjallouli 0:a948f5f3904c 178 for (i = 0; i < 5; i++)
sjallouli 0:a948f5f3904c 179 {
sjallouli 0:a948f5f3904c 180 tmpreg = spi_master_write(&__spi, header_master[i]);
sjallouli 0:a948f5f3904c 181 header_slave[i] = (uint8_t)(tmpreg);
sjallouli 0:a948f5f3904c 182 }
sjallouli 0:a948f5f3904c 183
sjallouli 0:a948f5f3904c 184
sjallouli 0:a948f5f3904c 185 if (header_slave[0] == 0x02) {
sjallouli 0:a948f5f3904c 186 /* device is ready */
sjallouli 0:a948f5f3904c 187 byte_count = (header_slave[4]<<8)|header_slave[3];
sjallouli 0:a948f5f3904c 188
sjallouli 0:a948f5f3904c 189 if (byte_count > 0) {
sjallouli 0:a948f5f3904c 190 /* avoid to read more data that size of the buffer */
sjallouli 0:a948f5f3904c 191 if (byte_count > buff_size){
sjallouli 0:a948f5f3904c 192 byte_count = buff_size;
sjallouli 0:a948f5f3904c 193 }
sjallouli 0:a948f5f3904c 194
sjallouli 0:a948f5f3904c 195 for (len = 0; len < byte_count; len++){
sjallouli 0:a948f5f3904c 196 read_char = spi_master_write(&__spi, char_ff);
sjallouli 0:a948f5f3904c 197 buffer[len] = read_char;
sjallouli 0:a948f5f3904c 198 }
sjallouli 0:a948f5f3904c 199 }
sjallouli 0:a948f5f3904c 200 }
sjallouli 0:a948f5f3904c 201 /* Release CS line */
sjallouli 0:a948f5f3904c 202 gpio_write(&gpio_pin_CS, 1);
sjallouli 0:a948f5f3904c 203
sjallouli 0:a948f5f3904c 204 return len;
sjallouli 0:a948f5f3904c 205 }
sjallouli 0:a948f5f3904c 206
sjallouli 0:a948f5f3904c 207 /**
sjallouli 0:a948f5f3904c 208 * @brief Write data from local buffer to SPI
sjallouli 0:a948f5f3904c 209 * @param data1: first data buffer to be written
sjallouli 0:a948f5f3904c 210 * @param data2: second data buffer to be written
sjallouli 0:a948f5f3904c 211 * @param Nb_bytes1: size of first data buffer to be written
sjallouli 0:a948f5f3904c 212 * @param Nb_bytes2: size of second data buffer to be written
sjallouli 0:a948f5f3904c 213 * @retval number of read bytes
sjallouli 0:a948f5f3904c 214 */
sjallouli 0:a948f5f3904c 215 int32_t BlueNRG_SPI_Write(uint8_t* data1, uint8_t* data2, uint8_t Nb_bytes1, uint8_t Nb_bytes2)
sjallouli 0:a948f5f3904c 216 {
sjallouli 0:a948f5f3904c 217 uint32_t i;
sjallouli 0:a948f5f3904c 218 volatile uint8_t read_char;
sjallouli 0:a948f5f3904c 219 int32_t result = 0;
sjallouli 0:a948f5f3904c 220 volatile uint8_t tmpreg;
sjallouli 0:a948f5f3904c 221
sjallouli 0:a948f5f3904c 222 unsigned char header_master[5] = {0x0a, 0x00, 0x00, 0x00, 0x00};
sjallouli 0:a948f5f3904c 223 unsigned char header_slave[5] = {0xaa, 0x00, 0x00, 0x00, 0x00};
sjallouli 0:a948f5f3904c 224
sjallouli 0:a948f5f3904c 225 Disable_SPI_IRQ();
sjallouli 0:a948f5f3904c 226
sjallouli 0:a948f5f3904c 227 /* CS reset */
sjallouli 0:a948f5f3904c 228 gpio_write(&gpio_pin_CS, 0);
sjallouli 0:a948f5f3904c 229
sjallouli 0:a948f5f3904c 230 /* Exchange header */
sjallouli 0:a948f5f3904c 231 for (i = 0; i < 5; i++)
sjallouli 0:a948f5f3904c 232 {
sjallouli 0:a948f5f3904c 233 tmpreg = spi_master_write(&__spi, header_master[i]);
sjallouli 0:a948f5f3904c 234 header_slave[i] = tmpreg;
sjallouli 0:a948f5f3904c 235 }
sjallouli 0:a948f5f3904c 236
sjallouli 0:a948f5f3904c 237 if (header_slave[0] == 0x02) {
sjallouli 0:a948f5f3904c 238 /* SPI is ready */
sjallouli 0:a948f5f3904c 239 if (header_slave[1] >= (Nb_bytes1+Nb_bytes2)) {
sjallouli 0:a948f5f3904c 240 /* Buffer is big enough */
sjallouli 0:a948f5f3904c 241 for (i = 0; i < Nb_bytes1; i++) {
sjallouli 0:a948f5f3904c 242 read_char = spi_master_write(&__spi, *(data1 + i));
sjallouli 0:a948f5f3904c 243 }
sjallouli 0:a948f5f3904c 244 for (i = 0; i < Nb_bytes2; i++) {
sjallouli 0:a948f5f3904c 245 read_char = spi_master_write(&__spi, *(data2 + i));
sjallouli 0:a948f5f3904c 246 }
sjallouli 0:a948f5f3904c 247 } else {
sjallouli 0:a948f5f3904c 248 /* Buffer is too small */
sjallouli 0:a948f5f3904c 249 result = -2;
sjallouli 0:a948f5f3904c 250 }
sjallouli 0:a948f5f3904c 251 } else {
sjallouli 0:a948f5f3904c 252 /* SPI is not ready */
sjallouli 0:a948f5f3904c 253 result = -1;
sjallouli 0:a948f5f3904c 254 }
sjallouli 0:a948f5f3904c 255
sjallouli 0:a948f5f3904c 256 /* Release CS line */
sjallouli 0:a948f5f3904c 257 gpio_write(&gpio_pin_CS, 1);
sjallouli 0:a948f5f3904c 258
sjallouli 0:a948f5f3904c 259 Enable_SPI_IRQ();
sjallouli 0:a948f5f3904c 260
sjallouli 0:a948f5f3904c 261 return result;
sjallouli 0:a948f5f3904c 262 }
sjallouli 0:a948f5f3904c 263
sjallouli 0:a948f5f3904c 264 /**
sjallouli 0:a948f5f3904c 265 * Writes data to a serial interface. *
sjallouli 0:a948f5f3904c 266 * @param data1 1st buffer
sjallouli 0:a948f5f3904c 267 * @param data2 2nd buffer
sjallouli 0:a948f5f3904c 268 * @param n_bytes1 number of bytes in 1st buffer
sjallouli 0:a948f5f3904c 269 * @param n_bytes2 number of bytes in 2nd buffer
sjallouli 0:a948f5f3904c 270 */
sjallouli 0:a948f5f3904c 271 void Hal_Write_Serial(const void* data1, const void* data2, int32_t n_bytes1, int32_t n_bytes2)
sjallouli 0:a948f5f3904c 272 {
sjallouli 0:a948f5f3904c 273 struct timer t;
sjallouli 0:a948f5f3904c 274
sjallouli 0:a948f5f3904c 275 Timer_Set(&t, CLOCK_SECOND/10);
sjallouli 0:a948f5f3904c 276
sjallouli 0:a948f5f3904c 277 while(1){
sjallouli 0:a948f5f3904c 278 if(BlueNRG_SPI_Write((uint8_t *)data1,(uint8_t *)data2, n_bytes1, n_bytes2)==0) break;
sjallouli 0:a948f5f3904c 279 if(Timer_Expired(&t)){
sjallouli 0:a948f5f3904c 280 break;
sjallouli 0:a948f5f3904c 281 }
sjallouli 0:a948f5f3904c 282 }
sjallouli 0:a948f5f3904c 283 }
sjallouli 0:a948f5f3904c 284
sjallouli 0:a948f5f3904c 285 /**
sjallouli 0:a948f5f3904c 286 * @brief Disable SPI IRQ
sjallouli 0:a948f5f3904c 287 * @param None
sjallouli 0:a948f5f3904c 288 * @retval None
sjallouli 0:a948f5f3904c 289 */
sjallouli 0:a948f5f3904c 290 void Disable_SPI_IRQ(void)
sjallouli 0:a948f5f3904c 291 {
sjallouli 0:a948f5f3904c 292 gpio_irq_disable(&irq_exti);
sjallouli 0:a948f5f3904c 293 }
sjallouli 0:a948f5f3904c 294
sjallouli 0:a948f5f3904c 295 /**
sjallouli 0:a948f5f3904c 296 * @brief Enable SPI IRQ
sjallouli 0:a948f5f3904c 297 * @param None
sjallouli 0:a948f5f3904c 298 * @retval None
sjallouli 0:a948f5f3904c 299 */
sjallouli 0:a948f5f3904c 300 void Enable_SPI_IRQ(void)
sjallouli 0:a948f5f3904c 301 {
sjallouli 0:a948f5f3904c 302 gpio_irq_enable(&irq_exti);
sjallouli 0:a948f5f3904c 303 }
sjallouli 0:a948f5f3904c 304
sjallouli 0:a948f5f3904c 305 /**
sjallouli 0:a948f5f3904c 306 * @brief Clear Pending SPI IRQ
sjallouli 0:a948f5f3904c 307 * @param None
sjallouli 0:a948f5f3904c 308 * @retval None
sjallouli 0:a948f5f3904c 309 */
sjallouli 0:a948f5f3904c 310 void Clear_SPI_IRQ(void)
sjallouli 0:a948f5f3904c 311 {
sjallouli 0:a948f5f3904c 312 //Not Used
sjallouli 0:a948f5f3904c 313 }
sjallouli 0:a948f5f3904c 314
sjallouli 0:a948f5f3904c 315 /**
sjallouli 0:a948f5f3904c 316 * @brief Clear EXTI (External Interrupt) line for SPI IRQ
sjallouli 0:a948f5f3904c 317 * @param None
sjallouli 0:a948f5f3904c 318 * @retval None
sjallouli 0:a948f5f3904c 319 */
sjallouli 0:a948f5f3904c 320 void Clear_SPI_EXTI_Flag(void)
sjallouli 0:a948f5f3904c 321 {
sjallouli 0:a948f5f3904c 322 //Not Used
sjallouli 0:a948f5f3904c 323 }
sjallouli 0:a948f5f3904c 324
sjallouli 0:a948f5f3904c 325 /**
sjallouli 0:a948f5f3904c 326 * @brief Reset the BlueNRG
sjallouli 0:a948f5f3904c 327 * @param None
sjallouli 0:a948f5f3904c 328 * @retval None
sjallouli 0:a948f5f3904c 329 */
sjallouli 0:a948f5f3904c 330 void BlueNRG_RST(void)
sjallouli 0:a948f5f3904c 331 {
sjallouli 2:905715088a9b 332 gpio_write(&gpio_pin_RESET, 0);
sjallouli 2:905715088a9b 333 wait_us(5);
sjallouli 2:905715088a9b 334
sjallouli 2:905715088a9b 335 gpio_write(&gpio_pin_RESET, 1);
sjallouli 2:905715088a9b 336 wait_us(5);
sjallouli 0:a948f5f3904c 337 }
sjallouli 0:a948f5f3904c 338
sjallouli 0:a948f5f3904c 339 /**
sjallouli 0:a948f5f3904c 340 * @}
sjallouli 0:a948f5f3904c 341 */
sjallouli 0:a948f5f3904c 342
sjallouli 0:a948f5f3904c 343 /**
sjallouli 0:a948f5f3904c 344 * @}
sjallouli 0:a948f5f3904c 345 */
sjallouli 0:a948f5f3904c 346
sjallouli 0:a948f5f3904c 347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/