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mbed SDK library sources

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Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_dma.c@84:f54042cbc282, 2014-02-03 (annotated)

Committer:
mbed_official
Date:
Mon Feb 03 09:30:05 2014 +0000
Revision:
84:f54042cbc282
Parent:
70:c1fbde68b492 
Synchronized with git revision bbbd8699601c42149ccf0c37bc42bb6856ccc4c6



Full URL: https://github.com/mbedmicro/mbed/commit/bbbd8699601c42149ccf0c37bc42bb6856ccc4c6/



[NUCLEO_L152RE/F030_R8] SPI, I2C, Ticker, PWM updates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 52:a51c77007319 1 /**
mbed_official 52:a51c77007319 2 ******************************************************************************
mbed_official 52:a51c77007319 3 * @file stm32f10x_dma.c
mbed_official 52:a51c77007319 4 * @author MCD Application Team
mbed_official 84:f54042cbc282 5 * @version V3.6.1
mbed_official 84:f54042cbc282 6 * @date 05-March-2012
mbed_official 52:a51c77007319 7 * @brief This file provides all the DMA firmware functions.
mbed_official 70:c1fbde68b492 8 *******************************************************************************
mbed_official 70:c1fbde68b492 9 * Copyright (c) 2014, STMicroelectronics
mbed_official 70:c1fbde68b492 10 * All rights reserved.
mbed_official 70:c1fbde68b492 11 *
mbed_official 70:c1fbde68b492 12 * Redistribution and use in source and binary forms, with or without
mbed_official 70:c1fbde68b492 13 * modification, are permitted provided that the following conditions are met:
mbed_official 70:c1fbde68b492 14 *
mbed_official 70:c1fbde68b492 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 70:c1fbde68b492 16 * this list of conditions and the following disclaimer.
mbed_official 70:c1fbde68b492 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 70:c1fbde68b492 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 70:c1fbde68b492 19 * and/or other materials provided with the distribution.
mbed_official 70:c1fbde68b492 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 70:c1fbde68b492 21 * may be used to endorse or promote products derived from this software
mbed_official 70:c1fbde68b492 22 * without specific prior written permission.
mbed_official 70:c1fbde68b492 23 *
mbed_official 70:c1fbde68b492 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 70:c1fbde68b492 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 70:c1fbde68b492 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 70:c1fbde68b492 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 70:c1fbde68b492 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 70:c1fbde68b492 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 70:c1fbde68b492 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 70:c1fbde68b492 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 70:c1fbde68b492 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 70:c1fbde68b492 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 70:c1fbde68b492 34 *******************************************************************************
mbed_official 70:c1fbde68b492 35 */
mbed_official 52:a51c77007319 36
mbed_official 52:a51c77007319 37 /* Includes ------------------------------------------------------------------*/
mbed_official 52:a51c77007319 38 #include "stm32f10x_dma.h"
mbed_official 52:a51c77007319 39 #include "stm32f10x_rcc.h"
mbed_official 52:a51c77007319 40
mbed_official 52:a51c77007319 41 /** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official 52:a51c77007319 42 * @{
mbed_official 52:a51c77007319 43 */
mbed_official 52:a51c77007319 44
mbed_official 52:a51c77007319 45 /** @defgroup DMA
mbed_official 52:a51c77007319 46 * @brief DMA driver modules
mbed_official 52:a51c77007319 47 * @{
mbed_official 52:a51c77007319 48 */
mbed_official 52:a51c77007319 49
mbed_official 52:a51c77007319 50 /** @defgroup DMA_Private_TypesDefinitions
mbed_official 52:a51c77007319 51 * @{
mbed_official 52:a51c77007319 52 */
mbed_official 52:a51c77007319 53 /**
mbed_official 52:a51c77007319 54 * @}
mbed_official 52:a51c77007319 55 */
mbed_official 52:a51c77007319 56
mbed_official 52:a51c77007319 57 /** @defgroup DMA_Private_Defines
mbed_official 52:a51c77007319 58 * @{
mbed_official 52:a51c77007319 59 */
mbed_official 52:a51c77007319 60
mbed_official 52:a51c77007319 61
mbed_official 52:a51c77007319 62 /* DMA1 Channelx interrupt pending bit masks */
mbed_official 52:a51c77007319 63 #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
mbed_official 52:a51c77007319 64 #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
mbed_official 52:a51c77007319 65 #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
mbed_official 52:a51c77007319 66 #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
mbed_official 52:a51c77007319 67 #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
mbed_official 52:a51c77007319 68 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
mbed_official 52:a51c77007319 69 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
mbed_official 52:a51c77007319 70
mbed_official 52:a51c77007319 71 /* DMA2 Channelx interrupt pending bit masks */
mbed_official 52:a51c77007319 72 #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
mbed_official 52:a51c77007319 73 #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
mbed_official 52:a51c77007319 74 #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
mbed_official 52:a51c77007319 75 #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
mbed_official 52:a51c77007319 76 #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
mbed_official 52:a51c77007319 77
mbed_official 52:a51c77007319 78 /* DMA2 FLAG mask */
mbed_official 52:a51c77007319 79 #define FLAG_Mask ((uint32_t)0x10000000)
mbed_official 52:a51c77007319 80
mbed_official 52:a51c77007319 81 /* DMA registers Masks */
mbed_official 52:a51c77007319 82 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
mbed_official 52:a51c77007319 83
mbed_official 52:a51c77007319 84 /**
mbed_official 52:a51c77007319 85 * @}
mbed_official 52:a51c77007319 86 */
mbed_official 52:a51c77007319 87
mbed_official 52:a51c77007319 88 /** @defgroup DMA_Private_Macros
mbed_official 52:a51c77007319 89 * @{
mbed_official 52:a51c77007319 90 */
mbed_official 52:a51c77007319 91
mbed_official 52:a51c77007319 92 /**
mbed_official 52:a51c77007319 93 * @}
mbed_official 52:a51c77007319 94 */
mbed_official 52:a51c77007319 95
mbed_official 52:a51c77007319 96 /** @defgroup DMA_Private_Variables
mbed_official 52:a51c77007319 97 * @{
mbed_official 52:a51c77007319 98 */
mbed_official 52:a51c77007319 99
mbed_official 52:a51c77007319 100 /**
mbed_official 52:a51c77007319 101 * @}
mbed_official 52:a51c77007319 102 */
mbed_official 52:a51c77007319 103
mbed_official 52:a51c77007319 104 /** @defgroup DMA_Private_FunctionPrototypes
mbed_official 52:a51c77007319 105 * @{
mbed_official 52:a51c77007319 106 */
mbed_official 52:a51c77007319 107
mbed_official 52:a51c77007319 108 /**
mbed_official 52:a51c77007319 109 * @}
mbed_official 52:a51c77007319 110 */
mbed_official 52:a51c77007319 111
mbed_official 52:a51c77007319 112 /** @defgroup DMA_Private_Functions
mbed_official 52:a51c77007319 113 * @{
mbed_official 52:a51c77007319 114 */
mbed_official 52:a51c77007319 115
mbed_official 52:a51c77007319 116 /**
mbed_official 52:a51c77007319 117 * @brief Deinitializes the DMAy Channelx registers to their default reset
mbed_official 52:a51c77007319 118 * values.
mbed_official 52:a51c77007319 119 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
mbed_official 52:a51c77007319 120 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
mbed_official 52:a51c77007319 121 * @retval None
mbed_official 52:a51c77007319 122 */
mbed_official 52:a51c77007319 123 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
mbed_official 52:a51c77007319 124 {
mbed_official 52:a51c77007319 125 /* Check the parameters */
mbed_official 52:a51c77007319 126 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 52:a51c77007319 127
mbed_official 52:a51c77007319 128 /* Disable the selected DMAy Channelx */
mbed_official 52:a51c77007319 129 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
mbed_official 52:a51c77007319 130
mbed_official 52:a51c77007319 131 /* Reset DMAy Channelx control register */
mbed_official 52:a51c77007319 132 DMAy_Channelx->CCR = 0;
mbed_official 52:a51c77007319 133
mbed_official 52:a51c77007319 134 /* Reset DMAy Channelx remaining bytes register */
mbed_official 52:a51c77007319 135 DMAy_Channelx->CNDTR = 0;
mbed_official 52:a51c77007319 136
mbed_official 52:a51c77007319 137 /* Reset DMAy Channelx peripheral address register */
mbed_official 52:a51c77007319 138 DMAy_Channelx->CPAR = 0;
mbed_official 52:a51c77007319 139
mbed_official 52:a51c77007319 140 /* Reset DMAy Channelx memory address register */
mbed_official 52:a51c77007319 141 DMAy_Channelx->CMAR = 0;
mbed_official 52:a51c77007319 142
mbed_official 52:a51c77007319 143 if (DMAy_Channelx == DMA1_Channel1)
mbed_official 52:a51c77007319 144 {
mbed_official 52:a51c77007319 145 /* Reset interrupt pending bits for DMA1 Channel1 */
mbed_official 52:a51c77007319 146 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
mbed_official 52:a51c77007319 147 }
mbed_official 52:a51c77007319 148 else if (DMAy_Channelx == DMA1_Channel2)
mbed_official 52:a51c77007319 149 {
mbed_official 52:a51c77007319 150 /* Reset interrupt pending bits for DMA1 Channel2 */
mbed_official 52:a51c77007319 151 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
mbed_official 52:a51c77007319 152 }
mbed_official 52:a51c77007319 153 else if (DMAy_Channelx == DMA1_Channel3)
mbed_official 52:a51c77007319 154 {
mbed_official 52:a51c77007319 155 /* Reset interrupt pending bits for DMA1 Channel3 */
mbed_official 52:a51c77007319 156 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
mbed_official 52:a51c77007319 157 }
mbed_official 52:a51c77007319 158 else if (DMAy_Channelx == DMA1_Channel4)
mbed_official 52:a51c77007319 159 {
mbed_official 52:a51c77007319 160 /* Reset interrupt pending bits for DMA1 Channel4 */
mbed_official 52:a51c77007319 161 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
mbed_official 52:a51c77007319 162 }
mbed_official 52:a51c77007319 163 else if (DMAy_Channelx == DMA1_Channel5)
mbed_official 52:a51c77007319 164 {
mbed_official 52:a51c77007319 165 /* Reset interrupt pending bits for DMA1 Channel5 */
mbed_official 52:a51c77007319 166 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
mbed_official 52:a51c77007319 167 }
mbed_official 52:a51c77007319 168 else if (DMAy_Channelx == DMA1_Channel6)
mbed_official 52:a51c77007319 169 {
mbed_official 52:a51c77007319 170 /* Reset interrupt pending bits for DMA1 Channel6 */
mbed_official 52:a51c77007319 171 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
mbed_official 52:a51c77007319 172 }
mbed_official 52:a51c77007319 173 else if (DMAy_Channelx == DMA1_Channel7)
mbed_official 52:a51c77007319 174 {
mbed_official 52:a51c77007319 175 /* Reset interrupt pending bits for DMA1 Channel7 */
mbed_official 52:a51c77007319 176 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
mbed_official 52:a51c77007319 177 }
mbed_official 52:a51c77007319 178 else if (DMAy_Channelx == DMA2_Channel1)
mbed_official 52:a51c77007319 179 {
mbed_official 52:a51c77007319 180 /* Reset interrupt pending bits for DMA2 Channel1 */
mbed_official 52:a51c77007319 181 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
mbed_official 52:a51c77007319 182 }
mbed_official 52:a51c77007319 183 else if (DMAy_Channelx == DMA2_Channel2)
mbed_official 52:a51c77007319 184 {
mbed_official 52:a51c77007319 185 /* Reset interrupt pending bits for DMA2 Channel2 */
mbed_official 52:a51c77007319 186 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
mbed_official 52:a51c77007319 187 }
mbed_official 52:a51c77007319 188 else if (DMAy_Channelx == DMA2_Channel3)
mbed_official 52:a51c77007319 189 {
mbed_official 52:a51c77007319 190 /* Reset interrupt pending bits for DMA2 Channel3 */
mbed_official 52:a51c77007319 191 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
mbed_official 52:a51c77007319 192 }
mbed_official 52:a51c77007319 193 else if (DMAy_Channelx == DMA2_Channel4)
mbed_official 52:a51c77007319 194 {
mbed_official 52:a51c77007319 195 /* Reset interrupt pending bits for DMA2 Channel4 */
mbed_official 52:a51c77007319 196 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
mbed_official 52:a51c77007319 197 }
mbed_official 52:a51c77007319 198 else
mbed_official 52:a51c77007319 199 {
mbed_official 52:a51c77007319 200 if (DMAy_Channelx == DMA2_Channel5)
mbed_official 52:a51c77007319 201 {
mbed_official 52:a51c77007319 202 /* Reset interrupt pending bits for DMA2 Channel5 */
mbed_official 52:a51c77007319 203 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
mbed_official 52:a51c77007319 204 }
mbed_official 52:a51c77007319 205 }
mbed_official 52:a51c77007319 206 }
mbed_official 52:a51c77007319 207
mbed_official 52:a51c77007319 208 /**
mbed_official 52:a51c77007319 209 * @brief Initializes the DMAy Channelx according to the specified
mbed_official 52:a51c77007319 210 * parameters in the DMA_InitStruct.
mbed_official 52:a51c77007319 211 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
mbed_official 52:a51c77007319 212 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
mbed_official 52:a51c77007319 213 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
mbed_official 52:a51c77007319 214 * contains the configuration information for the specified DMA Channel.
mbed_official 52:a51c77007319 215 * @retval None
mbed_official 52:a51c77007319 216 */
mbed_official 52:a51c77007319 217 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
mbed_official 52:a51c77007319 218 {
mbed_official 52:a51c77007319 219 uint32_t tmpreg = 0;
mbed_official 52:a51c77007319 220
mbed_official 52:a51c77007319 221 /* Check the parameters */
mbed_official 52:a51c77007319 222 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 52:a51c77007319 223 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
mbed_official 52:a51c77007319 224 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
mbed_official 52:a51c77007319 225 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
mbed_official 52:a51c77007319 226 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
mbed_official 52:a51c77007319 227 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
mbed_official 52:a51c77007319 228 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
mbed_official 52:a51c77007319 229 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
mbed_official 52:a51c77007319 230 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
mbed_official 52:a51c77007319 231 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
mbed_official 52:a51c77007319 232
mbed_official 52:a51c77007319 233 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
mbed_official 52:a51c77007319 234 /* Get the DMAy_Channelx CCR value */
mbed_official 52:a51c77007319 235 tmpreg = DMAy_Channelx->CCR;
mbed_official 52:a51c77007319 236 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
mbed_official 52:a51c77007319 237 tmpreg &= CCR_CLEAR_Mask;
mbed_official 52:a51c77007319 238 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
mbed_official 52:a51c77007319 239 /* Set DIR bit according to DMA_DIR value */
mbed_official 52:a51c77007319 240 /* Set CIRC bit according to DMA_Mode value */
mbed_official 52:a51c77007319 241 /* Set PINC bit according to DMA_PeripheralInc value */
mbed_official 52:a51c77007319 242 /* Set MINC bit according to DMA_MemoryInc value */
mbed_official 52:a51c77007319 243 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
mbed_official 52:a51c77007319 244 /* Set MSIZE bits according to DMA_MemoryDataSize value */
mbed_official 52:a51c77007319 245 /* Set PL bits according to DMA_Priority value */
mbed_official 52:a51c77007319 246 /* Set the MEM2MEM bit according to DMA_M2M value */
mbed_official 52:a51c77007319 247 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
mbed_official 52:a51c77007319 248 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
mbed_official 52:a51c77007319 249 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
mbed_official 52:a51c77007319 250 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
mbed_official 52:a51c77007319 251
mbed_official 52:a51c77007319 252 /* Write to DMAy Channelx CCR */
mbed_official 52:a51c77007319 253 DMAy_Channelx->CCR = tmpreg;
mbed_official 52:a51c77007319 254
mbed_official 52:a51c77007319 255 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
mbed_official 52:a51c77007319 256 /* Write to DMAy Channelx CNDTR */
mbed_official 52:a51c77007319 257 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
mbed_official 52:a51c77007319 258
mbed_official 52:a51c77007319 259 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
mbed_official 52:a51c77007319 260 /* Write to DMAy Channelx CPAR */
mbed_official 52:a51c77007319 261 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
mbed_official 52:a51c77007319 262
mbed_official 52:a51c77007319 263 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
mbed_official 52:a51c77007319 264 /* Write to DMAy Channelx CMAR */
mbed_official 52:a51c77007319 265 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
mbed_official 52:a51c77007319 266 }
mbed_official 52:a51c77007319 267
mbed_official 52:a51c77007319 268 /**
mbed_official 52:a51c77007319 269 * @brief Fills each DMA_InitStruct member with its default value.
mbed_official 52:a51c77007319 270 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
mbed_official 52:a51c77007319 271 * be initialized.
mbed_official 52:a51c77007319 272 * @retval None
mbed_official 52:a51c77007319 273 */
mbed_official 52:a51c77007319 274 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
mbed_official 52:a51c77007319 275 {
mbed_official 52:a51c77007319 276 /*-------------- Reset DMA init structure parameters values ------------------*/
mbed_official 52:a51c77007319 277 /* Initialize the DMA_PeripheralBaseAddr member */
mbed_official 52:a51c77007319 278 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
mbed_official 52:a51c77007319 279 /* Initialize the DMA_MemoryBaseAddr member */
mbed_official 52:a51c77007319 280 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
mbed_official 52:a51c77007319 281 /* Initialize the DMA_DIR member */
mbed_official 52:a51c77007319 282 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
mbed_official 52:a51c77007319 283 /* Initialize the DMA_BufferSize member */
mbed_official 52:a51c77007319 284 DMA_InitStruct->DMA_BufferSize = 0;
mbed_official 52:a51c77007319 285 /* Initialize the DMA_PeripheralInc member */
mbed_official 52:a51c77007319 286 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
mbed_official 52:a51c77007319 287 /* Initialize the DMA_MemoryInc member */
mbed_official 52:a51c77007319 288 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
mbed_official 52:a51c77007319 289 /* Initialize the DMA_PeripheralDataSize member */
mbed_official 52:a51c77007319 290 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
mbed_official 52:a51c77007319 291 /* Initialize the DMA_MemoryDataSize member */
mbed_official 52:a51c77007319 292 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
mbed_official 52:a51c77007319 293 /* Initialize the DMA_Mode member */
mbed_official 52:a51c77007319 294 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
mbed_official 52:a51c77007319 295 /* Initialize the DMA_Priority member */
mbed_official 52:a51c77007319 296 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
mbed_official 52:a51c77007319 297 /* Initialize the DMA_M2M member */
mbed_official 52:a51c77007319 298 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
mbed_official 52:a51c77007319 299 }
mbed_official 52:a51c77007319 300
mbed_official 52:a51c77007319 301 /**
mbed_official 52:a51c77007319 302 * @brief Enables or disables the specified DMAy Channelx.
mbed_official 52:a51c77007319 303 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
mbed_official 52:a51c77007319 304 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
mbed_official 52:a51c77007319 305 * @param NewState: new state of the DMAy Channelx.
mbed_official 52:a51c77007319 306 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 307 * @retval None
mbed_official 52:a51c77007319 308 */
mbed_official 52:a51c77007319 309 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
mbed_official 52:a51c77007319 310 {
mbed_official 52:a51c77007319 311 /* Check the parameters */
mbed_official 52:a51c77007319 312 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 52:a51c77007319 313 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 314
mbed_official 52:a51c77007319 315 if (NewState != DISABLE)
mbed_official 52:a51c77007319 316 {
mbed_official 52:a51c77007319 317 /* Enable the selected DMAy Channelx */
mbed_official 52:a51c77007319 318 DMAy_Channelx->CCR |= DMA_CCR1_EN;
mbed_official 52:a51c77007319 319 }
mbed_official 52:a51c77007319 320 else
mbed_official 52:a51c77007319 321 {
mbed_official 52:a51c77007319 322 /* Disable the selected DMAy Channelx */
mbed_official 52:a51c77007319 323 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
mbed_official 52:a51c77007319 324 }
mbed_official 52:a51c77007319 325 }
mbed_official 52:a51c77007319 326
mbed_official 52:a51c77007319 327 /**
mbed_official 52:a51c77007319 328 * @brief Enables or disables the specified DMAy Channelx interrupts.
mbed_official 52:a51c77007319 329 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
mbed_official 52:a51c77007319 330 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
mbed_official 52:a51c77007319 331 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
mbed_official 52:a51c77007319 332 * or disabled.
mbed_official 52:a51c77007319 333 * This parameter can be any combination of the following values:
mbed_official 52:a51c77007319 334 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 52:a51c77007319 335 * @arg DMA_IT_HT: Half transfer interrupt mask
mbed_official 52:a51c77007319 336 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 52:a51c77007319 337 * @param NewState: new state of the specified DMA interrupts.
mbed_official 52:a51c77007319 338 * This parameter can be: ENABLE or DISABLE.
mbed_official 52:a51c77007319 339 * @retval None
mbed_official 52:a51c77007319 340 */
mbed_official 52:a51c77007319 341 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
mbed_official 52:a51c77007319 342 {
mbed_official 52:a51c77007319 343 /* Check the parameters */
mbed_official 52:a51c77007319 344 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 52:a51c77007319 345 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
mbed_official 52:a51c77007319 346 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 52:a51c77007319 347 if (NewState != DISABLE)
mbed_official 52:a51c77007319 348 {
mbed_official 52:a51c77007319 349 /* Enable the selected DMA interrupts */
mbed_official 52:a51c77007319 350 DMAy_Channelx->CCR |= DMA_IT;
mbed_official 52:a51c77007319 351 }
mbed_official 52:a51c77007319 352 else
mbed_official 52:a51c77007319 353 {
mbed_official 52:a51c77007319 354 /* Disable the selected DMA interrupts */
mbed_official 52:a51c77007319 355 DMAy_Channelx->CCR &= ~DMA_IT;
mbed_official 52:a51c77007319 356 }
mbed_official 52:a51c77007319 357 }
mbed_official 52:a51c77007319 358
mbed_official 52:a51c77007319 359 /**
mbed_official 52:a51c77007319 360 * @brief Sets the number of data units in the current DMAy Channelx transfer.
mbed_official 52:a51c77007319 361 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
mbed_official 52:a51c77007319 362 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
mbed_official 52:a51c77007319 363 * @param DataNumber: The number of data units in the current DMAy Channelx
mbed_official 52:a51c77007319 364 * transfer.
mbed_official 52:a51c77007319 365 * @note This function can only be used when the DMAy_Channelx is disabled.
mbed_official 52:a51c77007319 366 * @retval None.
mbed_official 52:a51c77007319 367 */
mbed_official 52:a51c77007319 368 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
mbed_official 52:a51c77007319 369 {
mbed_official 52:a51c77007319 370 /* Check the parameters */
mbed_official 52:a51c77007319 371 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 52:a51c77007319 372
mbed_official 52:a51c77007319 373 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
mbed_official 52:a51c77007319 374 /* Write to DMAy Channelx CNDTR */
mbed_official 52:a51c77007319 375 DMAy_Channelx->CNDTR = DataNumber;
mbed_official 52:a51c77007319 376 }
mbed_official 52:a51c77007319 377
mbed_official 52:a51c77007319 378 /**
mbed_official 52:a51c77007319 379 * @brief Returns the number of remaining data units in the current
mbed_official 52:a51c77007319 380 * DMAy Channelx transfer.
mbed_official 52:a51c77007319 381 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
mbed_official 52:a51c77007319 382 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
mbed_official 52:a51c77007319 383 * @retval The number of remaining data units in the current DMAy Channelx
mbed_official 52:a51c77007319 384 * transfer.
mbed_official 52:a51c77007319 385 */
mbed_official 52:a51c77007319 386 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
mbed_official 52:a51c77007319 387 {
mbed_official 52:a51c77007319 388 /* Check the parameters */
mbed_official 52:a51c77007319 389 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 52:a51c77007319 390 /* Return the number of remaining data units for DMAy Channelx */
mbed_official 52:a51c77007319 391 return ((uint16_t)(DMAy_Channelx->CNDTR));
mbed_official 52:a51c77007319 392 }
mbed_official 52:a51c77007319 393
mbed_official 52:a51c77007319 394 /**
mbed_official 52:a51c77007319 395 * @brief Checks whether the specified DMAy Channelx flag is set or not.
mbed_official 52:a51c77007319 396 * @param DMAy_FLAG: specifies the flag to check.
mbed_official 52:a51c77007319 397 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 398 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
mbed_official 52:a51c77007319 399 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
mbed_official 52:a51c77007319 400 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
mbed_official 52:a51c77007319 401 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
mbed_official 52:a51c77007319 402 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
mbed_official 52:a51c77007319 403 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
mbed_official 52:a51c77007319 404 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
mbed_official 52:a51c77007319 405 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
mbed_official 52:a51c77007319 406 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
mbed_official 52:a51c77007319 407 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
mbed_official 52:a51c77007319 408 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
mbed_official 52:a51c77007319 409 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
mbed_official 52:a51c77007319 410 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
mbed_official 52:a51c77007319 411 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
mbed_official 52:a51c77007319 412 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
mbed_official 52:a51c77007319 413 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
mbed_official 52:a51c77007319 414 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
mbed_official 52:a51c77007319 415 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
mbed_official 52:a51c77007319 416 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
mbed_official 52:a51c77007319 417 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
mbed_official 52:a51c77007319 418 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
mbed_official 52:a51c77007319 419 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
mbed_official 52:a51c77007319 420 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
mbed_official 52:a51c77007319 421 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
mbed_official 52:a51c77007319 422 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
mbed_official 52:a51c77007319 423 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
mbed_official 52:a51c77007319 424 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
mbed_official 52:a51c77007319 425 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
mbed_official 52:a51c77007319 426 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
mbed_official 52:a51c77007319 427 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
mbed_official 52:a51c77007319 428 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
mbed_official 52:a51c77007319 429 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
mbed_official 52:a51c77007319 430 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
mbed_official 52:a51c77007319 431 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
mbed_official 52:a51c77007319 432 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
mbed_official 52:a51c77007319 433 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
mbed_official 52:a51c77007319 434 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
mbed_official 52:a51c77007319 435 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
mbed_official 52:a51c77007319 436 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
mbed_official 52:a51c77007319 437 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
mbed_official 52:a51c77007319 438 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
mbed_official 52:a51c77007319 439 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
mbed_official 52:a51c77007319 440 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
mbed_official 52:a51c77007319 441 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
mbed_official 52:a51c77007319 442 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
mbed_official 52:a51c77007319 443 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
mbed_official 52:a51c77007319 444 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
mbed_official 52:a51c77007319 445 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
mbed_official 52:a51c77007319 446 * @retval The new state of DMAy_FLAG (SET or RESET).
mbed_official 52:a51c77007319 447 */
mbed_official 52:a51c77007319 448 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
mbed_official 52:a51c77007319 449 {
mbed_official 52:a51c77007319 450 FlagStatus bitstatus = RESET;
mbed_official 52:a51c77007319 451 uint32_t tmpreg = 0;
mbed_official 52:a51c77007319 452
mbed_official 52:a51c77007319 453 /* Check the parameters */
mbed_official 52:a51c77007319 454 assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
mbed_official 52:a51c77007319 455
mbed_official 52:a51c77007319 456 /* Calculate the used DMAy */
mbed_official 52:a51c77007319 457 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
mbed_official 52:a51c77007319 458 {
mbed_official 52:a51c77007319 459 /* Get DMA2 ISR register value */
mbed_official 52:a51c77007319 460 tmpreg = DMA2->ISR ;
mbed_official 52:a51c77007319 461 }
mbed_official 52:a51c77007319 462 else
mbed_official 52:a51c77007319 463 {
mbed_official 52:a51c77007319 464 /* Get DMA1 ISR register value */
mbed_official 52:a51c77007319 465 tmpreg = DMA1->ISR ;
mbed_official 52:a51c77007319 466 }
mbed_official 52:a51c77007319 467
mbed_official 52:a51c77007319 468 /* Check the status of the specified DMAy flag */
mbed_official 52:a51c77007319 469 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
mbed_official 52:a51c77007319 470 {
mbed_official 52:a51c77007319 471 /* DMAy_FLAG is set */
mbed_official 52:a51c77007319 472 bitstatus = SET;
mbed_official 52:a51c77007319 473 }
mbed_official 52:a51c77007319 474 else
mbed_official 52:a51c77007319 475 {
mbed_official 52:a51c77007319 476 /* DMAy_FLAG is reset */
mbed_official 52:a51c77007319 477 bitstatus = RESET;
mbed_official 52:a51c77007319 478 }
mbed_official 52:a51c77007319 479
mbed_official 52:a51c77007319 480 /* Return the DMAy_FLAG status */
mbed_official 52:a51c77007319 481 return bitstatus;
mbed_official 52:a51c77007319 482 }
mbed_official 52:a51c77007319 483
mbed_official 52:a51c77007319 484 /**
mbed_official 52:a51c77007319 485 * @brief Clears the DMAy Channelx's pending flags.
mbed_official 52:a51c77007319 486 * @param DMAy_FLAG: specifies the flag to clear.
mbed_official 52:a51c77007319 487 * This parameter can be any combination (for the same DMA) of the following values:
mbed_official 52:a51c77007319 488 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
mbed_official 52:a51c77007319 489 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
mbed_official 52:a51c77007319 490 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
mbed_official 52:a51c77007319 491 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
mbed_official 52:a51c77007319 492 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
mbed_official 52:a51c77007319 493 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
mbed_official 52:a51c77007319 494 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
mbed_official 52:a51c77007319 495 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
mbed_official 52:a51c77007319 496 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
mbed_official 52:a51c77007319 497 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
mbed_official 52:a51c77007319 498 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
mbed_official 52:a51c77007319 499 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
mbed_official 52:a51c77007319 500 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
mbed_official 52:a51c77007319 501 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
mbed_official 52:a51c77007319 502 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
mbed_official 52:a51c77007319 503 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
mbed_official 52:a51c77007319 504 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
mbed_official 52:a51c77007319 505 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
mbed_official 52:a51c77007319 506 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
mbed_official 52:a51c77007319 507 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
mbed_official 52:a51c77007319 508 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
mbed_official 52:a51c77007319 509 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
mbed_official 52:a51c77007319 510 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
mbed_official 52:a51c77007319 511 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
mbed_official 52:a51c77007319 512 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
mbed_official 52:a51c77007319 513 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
mbed_official 52:a51c77007319 514 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
mbed_official 52:a51c77007319 515 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
mbed_official 52:a51c77007319 516 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
mbed_official 52:a51c77007319 517 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
mbed_official 52:a51c77007319 518 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
mbed_official 52:a51c77007319 519 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
mbed_official 52:a51c77007319 520 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
mbed_official 52:a51c77007319 521 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
mbed_official 52:a51c77007319 522 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
mbed_official 52:a51c77007319 523 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
mbed_official 52:a51c77007319 524 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
mbed_official 52:a51c77007319 525 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
mbed_official 52:a51c77007319 526 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
mbed_official 52:a51c77007319 527 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
mbed_official 52:a51c77007319 528 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
mbed_official 52:a51c77007319 529 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
mbed_official 52:a51c77007319 530 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
mbed_official 52:a51c77007319 531 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
mbed_official 52:a51c77007319 532 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
mbed_official 52:a51c77007319 533 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
mbed_official 52:a51c77007319 534 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
mbed_official 52:a51c77007319 535 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
mbed_official 52:a51c77007319 536 * @retval None
mbed_official 52:a51c77007319 537 */
mbed_official 52:a51c77007319 538 void DMA_ClearFlag(uint32_t DMAy_FLAG)
mbed_official 52:a51c77007319 539 {
mbed_official 52:a51c77007319 540 /* Check the parameters */
mbed_official 52:a51c77007319 541 assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
mbed_official 52:a51c77007319 542
mbed_official 52:a51c77007319 543 /* Calculate the used DMAy */
mbed_official 52:a51c77007319 544 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
mbed_official 52:a51c77007319 545 {
mbed_official 52:a51c77007319 546 /* Clear the selected DMAy flags */
mbed_official 52:a51c77007319 547 DMA2->IFCR = DMAy_FLAG;
mbed_official 52:a51c77007319 548 }
mbed_official 52:a51c77007319 549 else
mbed_official 52:a51c77007319 550 {
mbed_official 52:a51c77007319 551 /* Clear the selected DMAy flags */
mbed_official 52:a51c77007319 552 DMA1->IFCR = DMAy_FLAG;
mbed_official 52:a51c77007319 553 }
mbed_official 52:a51c77007319 554 }
mbed_official 52:a51c77007319 555
mbed_official 52:a51c77007319 556 /**
mbed_official 52:a51c77007319 557 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
mbed_official 52:a51c77007319 558 * @param DMAy_IT: specifies the DMAy interrupt source to check.
mbed_official 52:a51c77007319 559 * This parameter can be one of the following values:
mbed_official 52:a51c77007319 560 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
mbed_official 52:a51c77007319 561 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
mbed_official 52:a51c77007319 562 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
mbed_official 52:a51c77007319 563 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
mbed_official 52:a51c77007319 564 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
mbed_official 52:a51c77007319 565 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
mbed_official 52:a51c77007319 566 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
mbed_official 52:a51c77007319 567 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
mbed_official 52:a51c77007319 568 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
mbed_official 52:a51c77007319 569 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
mbed_official 52:a51c77007319 570 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
mbed_official 52:a51c77007319 571 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
mbed_official 52:a51c77007319 572 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
mbed_official 52:a51c77007319 573 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
mbed_official 52:a51c77007319 574 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
mbed_official 52:a51c77007319 575 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
mbed_official 52:a51c77007319 576 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
mbed_official 52:a51c77007319 577 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
mbed_official 52:a51c77007319 578 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
mbed_official 52:a51c77007319 579 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
mbed_official 52:a51c77007319 580 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
mbed_official 52:a51c77007319 581 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
mbed_official 52:a51c77007319 582 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
mbed_official 52:a51c77007319 583 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
mbed_official 52:a51c77007319 584 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
mbed_official 52:a51c77007319 585 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
mbed_official 52:a51c77007319 586 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
mbed_official 52:a51c77007319 587 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
mbed_official 52:a51c77007319 588 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
mbed_official 52:a51c77007319 589 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
mbed_official 52:a51c77007319 590 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
mbed_official 52:a51c77007319 591 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
mbed_official 52:a51c77007319 592 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
mbed_official 52:a51c77007319 593 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
mbed_official 52:a51c77007319 594 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
mbed_official 52:a51c77007319 595 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
mbed_official 52:a51c77007319 596 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
mbed_official 52:a51c77007319 597 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
mbed_official 52:a51c77007319 598 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
mbed_official 52:a51c77007319 599 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
mbed_official 52:a51c77007319 600 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
mbed_official 52:a51c77007319 601 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
mbed_official 52:a51c77007319 602 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
mbed_official 52:a51c77007319 603 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
mbed_official 52:a51c77007319 604 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
mbed_official 52:a51c77007319 605 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
mbed_official 52:a51c77007319 606 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
mbed_official 52:a51c77007319 607 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
mbed_official 52:a51c77007319 608 * @retval The new state of DMAy_IT (SET or RESET).
mbed_official 52:a51c77007319 609 */
mbed_official 52:a51c77007319 610 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
mbed_official 52:a51c77007319 611 {
mbed_official 52:a51c77007319 612 ITStatus bitstatus = RESET;
mbed_official 52:a51c77007319 613 uint32_t tmpreg = 0;
mbed_official 52:a51c77007319 614
mbed_official 52:a51c77007319 615 /* Check the parameters */
mbed_official 52:a51c77007319 616 assert_param(IS_DMA_GET_IT(DMAy_IT));
mbed_official 52:a51c77007319 617
mbed_official 52:a51c77007319 618 /* Calculate the used DMA */
mbed_official 52:a51c77007319 619 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
mbed_official 52:a51c77007319 620 {
mbed_official 52:a51c77007319 621 /* Get DMA2 ISR register value */
mbed_official 52:a51c77007319 622 tmpreg = DMA2->ISR;
mbed_official 52:a51c77007319 623 }
mbed_official 52:a51c77007319 624 else
mbed_official 52:a51c77007319 625 {
mbed_official 52:a51c77007319 626 /* Get DMA1 ISR register value */
mbed_official 52:a51c77007319 627 tmpreg = DMA1->ISR;
mbed_official 52:a51c77007319 628 }
mbed_official 52:a51c77007319 629
mbed_official 52:a51c77007319 630 /* Check the status of the specified DMAy interrupt */
mbed_official 52:a51c77007319 631 if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
mbed_official 52:a51c77007319 632 {
mbed_official 52:a51c77007319 633 /* DMAy_IT is set */
mbed_official 52:a51c77007319 634 bitstatus = SET;
mbed_official 52:a51c77007319 635 }
mbed_official 52:a51c77007319 636 else
mbed_official 52:a51c77007319 637 {
mbed_official 52:a51c77007319 638 /* DMAy_IT is reset */
mbed_official 52:a51c77007319 639 bitstatus = RESET;
mbed_official 52:a51c77007319 640 }
mbed_official 52:a51c77007319 641 /* Return the DMA_IT status */
mbed_official 52:a51c77007319 642 return bitstatus;
mbed_official 52:a51c77007319 643 }
mbed_official 52:a51c77007319 644
mbed_official 52:a51c77007319 645 /**
mbed_official 52:a51c77007319 646 * @brief Clears the DMAy Channelx's interrupt pending bits.
mbed_official 52:a51c77007319 647 * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
mbed_official 52:a51c77007319 648 * This parameter can be any combination (for the same DMA) of the following values:
mbed_official 52:a51c77007319 649 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
mbed_official 52:a51c77007319 650 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
mbed_official 52:a51c77007319 651 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
mbed_official 52:a51c77007319 652 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
mbed_official 52:a51c77007319 653 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
mbed_official 52:a51c77007319 654 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
mbed_official 52:a51c77007319 655 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
mbed_official 52:a51c77007319 656 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
mbed_official 52:a51c77007319 657 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
mbed_official 52:a51c77007319 658 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
mbed_official 52:a51c77007319 659 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
mbed_official 52:a51c77007319 660 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
mbed_official 52:a51c77007319 661 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
mbed_official 52:a51c77007319 662 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
mbed_official 52:a51c77007319 663 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
mbed_official 52:a51c77007319 664 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
mbed_official 52:a51c77007319 665 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
mbed_official 52:a51c77007319 666 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
mbed_official 52:a51c77007319 667 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
mbed_official 52:a51c77007319 668 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
mbed_official 52:a51c77007319 669 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
mbed_official 52:a51c77007319 670 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
mbed_official 52:a51c77007319 671 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
mbed_official 52:a51c77007319 672 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
mbed_official 52:a51c77007319 673 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
mbed_official 52:a51c77007319 674 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
mbed_official 52:a51c77007319 675 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
mbed_official 52:a51c77007319 676 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
mbed_official 52:a51c77007319 677 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
mbed_official 52:a51c77007319 678 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
mbed_official 52:a51c77007319 679 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
mbed_official 52:a51c77007319 680 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
mbed_official 52:a51c77007319 681 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
mbed_official 52:a51c77007319 682 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
mbed_official 52:a51c77007319 683 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
mbed_official 52:a51c77007319 684 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
mbed_official 52:a51c77007319 685 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
mbed_official 52:a51c77007319 686 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
mbed_official 52:a51c77007319 687 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
mbed_official 52:a51c77007319 688 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
mbed_official 52:a51c77007319 689 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
mbed_official 52:a51c77007319 690 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
mbed_official 52:a51c77007319 691 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
mbed_official 52:a51c77007319 692 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
mbed_official 52:a51c77007319 693 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
mbed_official 52:a51c77007319 694 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
mbed_official 52:a51c77007319 695 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
mbed_official 52:a51c77007319 696 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
mbed_official 52:a51c77007319 697 * @retval None
mbed_official 52:a51c77007319 698 */
mbed_official 52:a51c77007319 699 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
mbed_official 52:a51c77007319 700 {
mbed_official 52:a51c77007319 701 /* Check the parameters */
mbed_official 52:a51c77007319 702 assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
mbed_official 52:a51c77007319 703
mbed_official 52:a51c77007319 704 /* Calculate the used DMAy */
mbed_official 52:a51c77007319 705 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
mbed_official 52:a51c77007319 706 {
mbed_official 52:a51c77007319 707 /* Clear the selected DMAy interrupt pending bits */
mbed_official 52:a51c77007319 708 DMA2->IFCR = DMAy_IT;
mbed_official 52:a51c77007319 709 }
mbed_official 52:a51c77007319 710 else
mbed_official 52:a51c77007319 711 {
mbed_official 52:a51c77007319 712 /* Clear the selected DMAy interrupt pending bits */
mbed_official 52:a51c77007319 713 DMA1->IFCR = DMAy_IT;
mbed_official 52:a51c77007319 714 }
mbed_official 52:a51c77007319 715 }
mbed_official 52:a51c77007319 716
mbed_official 52:a51c77007319 717 /**
mbed_official 52:a51c77007319 718 * @}
mbed_official 52:a51c77007319 719 */
mbed_official 52:a51c77007319 720
mbed_official 52:a51c77007319 721 /**
mbed_official 52:a51c77007319 722 * @}
mbed_official 52:a51c77007319 723 */
mbed_official 52:a51c77007319 724
mbed_official 52:a51c77007319 725 /**
mbed_official 52:a51c77007319 726 * @}
mbed_official 52:a51c77007319 727 */
mbed_official 52:a51c77007319 728
mbed_official 84:f54042cbc282 729 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/