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mbed SDK library sources

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Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/core_cm4.h@89:9655231f5786, 2014-02-11 (annotated)

Committer:
mbed_official
Date:
Tue Feb 11 15:00:06 2014 +0000
Revision:
89:9655231f5786
Parent:
13:0645d8841f51 
Synchronized with git revision 17499c34d273f02497e0706d3abc516b12f3fc62



Full URL: https://github.com/mbedmicro/mbed/commit/17499c34d273f02497e0706d3abc516b12f3fc62/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 13:0645d8841f51 1 /**************************************************************************//**
bogdanm 13:0645d8841f51 2 * @file core_cm4.h
bogdanm 13:0645d8841f51 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
bogdanm 13:0645d8841f51 4 * @version V3.20
bogdanm 13:0645d8841f51 5 * @date 25. February 2013
bogdanm 13:0645d8841f51 6 *
bogdanm 13:0645d8841f51 7 * @note
bogdanm 13:0645d8841f51 8 *
bogdanm 13:0645d8841f51 9 ******************************************************************************/
bogdanm 13:0645d8841f51 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 13:0645d8841f51 11
bogdanm 13:0645d8841f51 12 All rights reserved.
bogdanm 13:0645d8841f51 13 Redistribution and use in source and binary forms, with or without
bogdanm 13:0645d8841f51 14 modification, are permitted provided that the following conditions are met:
bogdanm 13:0645d8841f51 15 - Redistributions of source code must retain the above copyright
bogdanm 13:0645d8841f51 16 notice, this list of conditions and the following disclaimer.
bogdanm 13:0645d8841f51 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 13:0645d8841f51 18 notice, this list of conditions and the following disclaimer in the
bogdanm 13:0645d8841f51 19 documentation and/or other materials provided with the distribution.
bogdanm 13:0645d8841f51 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 13:0645d8841f51 21 to endorse or promote products derived from this software without
bogdanm 13:0645d8841f51 22 specific prior written permission.
bogdanm 13:0645d8841f51 23 *
bogdanm 13:0645d8841f51 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 13:0645d8841f51 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 13:0645d8841f51 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 13:0645d8841f51 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 13:0645d8841f51 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 13:0645d8841f51 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 13:0645d8841f51 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 13:0645d8841f51 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 13:0645d8841f51 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 13:0645d8841f51 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 13:0645d8841f51 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 13:0645d8841f51 35 ---------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 36
bogdanm 13:0645d8841f51 37
bogdanm 13:0645d8841f51 38 #if defined ( __ICCARM__ )
bogdanm 13:0645d8841f51 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 13:0645d8841f51 40 #endif
bogdanm 13:0645d8841f51 41
bogdanm 13:0645d8841f51 42 #ifdef __cplusplus
bogdanm 13:0645d8841f51 43 extern "C" {
bogdanm 13:0645d8841f51 44 #endif
bogdanm 13:0645d8841f51 45
bogdanm 13:0645d8841f51 46 #ifndef __CORE_CM4_H_GENERIC
bogdanm 13:0645d8841f51 47 #define __CORE_CM4_H_GENERIC
bogdanm 13:0645d8841f51 48
bogdanm 13:0645d8841f51 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 13:0645d8841f51 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 13:0645d8841f51 51
bogdanm 13:0645d8841f51 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 13:0645d8841f51 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 13:0645d8841f51 54
bogdanm 13:0645d8841f51 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 13:0645d8841f51 56 Unions are used for effective representation of core registers.
bogdanm 13:0645d8841f51 57
bogdanm 13:0645d8841f51 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 13:0645d8841f51 59 Function-like macros are used to allow more efficient code.
bogdanm 13:0645d8841f51 60 */
bogdanm 13:0645d8841f51 61
bogdanm 13:0645d8841f51 62
bogdanm 13:0645d8841f51 63 /*******************************************************************************
bogdanm 13:0645d8841f51 64 * CMSIS definitions
bogdanm 13:0645d8841f51 65 ******************************************************************************/
bogdanm 13:0645d8841f51 66 /** \ingroup Cortex_M4
bogdanm 13:0645d8841f51 67 @{
bogdanm 13:0645d8841f51 68 */
bogdanm 13:0645d8841f51 69
bogdanm 13:0645d8841f51 70 /* CMSIS CM4 definitions */
bogdanm 13:0645d8841f51 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 13:0645d8841f51 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 13:0645d8841f51 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
bogdanm 13:0645d8841f51 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 13:0645d8841f51 75
bogdanm 13:0645d8841f51 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
bogdanm 13:0645d8841f51 77
bogdanm 13:0645d8841f51 78
bogdanm 13:0645d8841f51 79 #if defined ( __CC_ARM )
bogdanm 13:0645d8841f51 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 13:0645d8841f51 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 13:0645d8841f51 82 #define __STATIC_INLINE static __inline
bogdanm 13:0645d8841f51 83
bogdanm 13:0645d8841f51 84 #elif defined ( __ICCARM__ )
bogdanm 13:0645d8841f51 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 13:0645d8841f51 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 13:0645d8841f51 87 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 88
bogdanm 13:0645d8841f51 89 #elif defined ( __TMS470__ )
bogdanm 13:0645d8841f51 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 13:0645d8841f51 91 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 92
bogdanm 13:0645d8841f51 93 #elif defined ( __GNUC__ )
bogdanm 13:0645d8841f51 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 13:0645d8841f51 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 13:0645d8841f51 96 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 97
bogdanm 13:0645d8841f51 98 #elif defined ( __TASKING__ )
bogdanm 13:0645d8841f51 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 13:0645d8841f51 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 13:0645d8841f51 101 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 102
bogdanm 13:0645d8841f51 103 #endif
bogdanm 13:0645d8841f51 104
bogdanm 13:0645d8841f51 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
bogdanm 13:0645d8841f51 106 */
bogdanm 13:0645d8841f51 107 #if defined ( __CC_ARM )
bogdanm 13:0645d8841f51 108 #if defined __TARGET_FPU_VFP
bogdanm 13:0645d8841f51 109 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 110 #define __FPU_USED 1
bogdanm 13:0645d8841f51 111 #else
bogdanm 13:0645d8841f51 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 113 #define __FPU_USED 0
bogdanm 13:0645d8841f51 114 #endif
bogdanm 13:0645d8841f51 115 #else
bogdanm 13:0645d8841f51 116 #define __FPU_USED 0
bogdanm 13:0645d8841f51 117 #endif
bogdanm 13:0645d8841f51 118
bogdanm 13:0645d8841f51 119 #elif defined ( __ICCARM__ )
bogdanm 13:0645d8841f51 120 #if defined __ARMVFP__
bogdanm 13:0645d8841f51 121 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 122 #define __FPU_USED 1
bogdanm 13:0645d8841f51 123 #else
bogdanm 13:0645d8841f51 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 125 #define __FPU_USED 0
bogdanm 13:0645d8841f51 126 #endif
bogdanm 13:0645d8841f51 127 #else
bogdanm 13:0645d8841f51 128 #define __FPU_USED 0
bogdanm 13:0645d8841f51 129 #endif
bogdanm 13:0645d8841f51 130
bogdanm 13:0645d8841f51 131 #elif defined ( __TMS470__ )
bogdanm 13:0645d8841f51 132 #if defined __TI_VFP_SUPPORT__
bogdanm 13:0645d8841f51 133 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 134 #define __FPU_USED 1
bogdanm 13:0645d8841f51 135 #else
bogdanm 13:0645d8841f51 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 137 #define __FPU_USED 0
bogdanm 13:0645d8841f51 138 #endif
bogdanm 13:0645d8841f51 139 #else
bogdanm 13:0645d8841f51 140 #define __FPU_USED 0
bogdanm 13:0645d8841f51 141 #endif
bogdanm 13:0645d8841f51 142
bogdanm 13:0645d8841f51 143 #elif defined ( __GNUC__ )
bogdanm 13:0645d8841f51 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 13:0645d8841f51 145 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 146 #define __FPU_USED 1
bogdanm 13:0645d8841f51 147 #else
bogdanm 13:0645d8841f51 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 149 #define __FPU_USED 0
bogdanm 13:0645d8841f51 150 #endif
bogdanm 13:0645d8841f51 151 #else
bogdanm 13:0645d8841f51 152 #define __FPU_USED 0
bogdanm 13:0645d8841f51 153 #endif
bogdanm 13:0645d8841f51 154
bogdanm 13:0645d8841f51 155 #elif defined ( __TASKING__ )
bogdanm 13:0645d8841f51 156 #if defined __FPU_VFP__
bogdanm 13:0645d8841f51 157 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 158 #define __FPU_USED 1
bogdanm 13:0645d8841f51 159 #else
bogdanm 13:0645d8841f51 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 161 #define __FPU_USED 0
bogdanm 13:0645d8841f51 162 #endif
bogdanm 13:0645d8841f51 163 #else
bogdanm 13:0645d8841f51 164 #define __FPU_USED 0
bogdanm 13:0645d8841f51 165 #endif
bogdanm 13:0645d8841f51 166 #endif
bogdanm 13:0645d8841f51 167
bogdanm 13:0645d8841f51 168 #include <stdint.h> /* standard types definitions */
bogdanm 13:0645d8841f51 169 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 13:0645d8841f51 170 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 13:0645d8841f51 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
bogdanm 13:0645d8841f51 172
bogdanm 13:0645d8841f51 173 #endif /* __CORE_CM4_H_GENERIC */
bogdanm 13:0645d8841f51 174
bogdanm 13:0645d8841f51 175 #ifndef __CMSIS_GENERIC
bogdanm 13:0645d8841f51 176
bogdanm 13:0645d8841f51 177 #ifndef __CORE_CM4_H_DEPENDANT
bogdanm 13:0645d8841f51 178 #define __CORE_CM4_H_DEPENDANT
bogdanm 13:0645d8841f51 179
bogdanm 13:0645d8841f51 180 /* check device defines and use defaults */
bogdanm 13:0645d8841f51 181 #if defined __CHECK_DEVICE_DEFINES
bogdanm 13:0645d8841f51 182 #ifndef __CM4_REV
bogdanm 13:0645d8841f51 183 #define __CM4_REV 0x0000
bogdanm 13:0645d8841f51 184 #warning "__CM4_REV not defined in device header file; using default!"
bogdanm 13:0645d8841f51 185 #endif
bogdanm 13:0645d8841f51 186
bogdanm 13:0645d8841f51 187 #ifndef __FPU_PRESENT
bogdanm 13:0645d8841f51 188 #define __FPU_PRESENT 0
bogdanm 13:0645d8841f51 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
bogdanm 13:0645d8841f51 190 #endif
bogdanm 13:0645d8841f51 191
bogdanm 13:0645d8841f51 192 #ifndef __MPU_PRESENT
bogdanm 13:0645d8841f51 193 #define __MPU_PRESENT 0
bogdanm 13:0645d8841f51 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 13:0645d8841f51 195 #endif
bogdanm 13:0645d8841f51 196
bogdanm 13:0645d8841f51 197 #ifndef __NVIC_PRIO_BITS
bogdanm 13:0645d8841f51 198 #define __NVIC_PRIO_BITS 4
bogdanm 13:0645d8841f51 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 13:0645d8841f51 200 #endif
bogdanm 13:0645d8841f51 201
bogdanm 13:0645d8841f51 202 #ifndef __Vendor_SysTickConfig
bogdanm 13:0645d8841f51 203 #define __Vendor_SysTickConfig 0
bogdanm 13:0645d8841f51 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 13:0645d8841f51 205 #endif
bogdanm 13:0645d8841f51 206 #endif
bogdanm 13:0645d8841f51 207
bogdanm 13:0645d8841f51 208 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 13:0645d8841f51 209 /**
bogdanm 13:0645d8841f51 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 13:0645d8841f51 211
bogdanm 13:0645d8841f51 212 <strong>IO Type Qualifiers</strong> are used
bogdanm 13:0645d8841f51 213 \li to specify the access to peripheral variables.
bogdanm 13:0645d8841f51 214 \li for automatic generation of peripheral register debug information.
bogdanm 13:0645d8841f51 215 */
bogdanm 13:0645d8841f51 216 #ifdef __cplusplus
bogdanm 13:0645d8841f51 217 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 13:0645d8841f51 218 #else
bogdanm 13:0645d8841f51 219 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 13:0645d8841f51 220 #endif
bogdanm 13:0645d8841f51 221 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 13:0645d8841f51 222 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 13:0645d8841f51 223
bogdanm 13:0645d8841f51 224 /*@} end of group Cortex_M4 */
bogdanm 13:0645d8841f51 225
bogdanm 13:0645d8841f51 226
bogdanm 13:0645d8841f51 227
bogdanm 13:0645d8841f51 228 /*******************************************************************************
bogdanm 13:0645d8841f51 229 * Register Abstraction
bogdanm 13:0645d8841f51 230 Core Register contain:
bogdanm 13:0645d8841f51 231 - Core Register
bogdanm 13:0645d8841f51 232 - Core NVIC Register
bogdanm 13:0645d8841f51 233 - Core SCB Register
bogdanm 13:0645d8841f51 234 - Core SysTick Register
bogdanm 13:0645d8841f51 235 - Core Debug Register
bogdanm 13:0645d8841f51 236 - Core MPU Register
bogdanm 13:0645d8841f51 237 - Core FPU Register
bogdanm 13:0645d8841f51 238 ******************************************************************************/
bogdanm 13:0645d8841f51 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 13:0645d8841f51 240 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 13:0645d8841f51 241 */
bogdanm 13:0645d8841f51 242
bogdanm 13:0645d8841f51 243 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 244 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 13:0645d8841f51 245 \brief Core Register type definitions.
bogdanm 13:0645d8841f51 246 @{
bogdanm 13:0645d8841f51 247 */
bogdanm 13:0645d8841f51 248
bogdanm 13:0645d8841f51 249 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 13:0645d8841f51 250 */
bogdanm 13:0645d8841f51 251 typedef union
bogdanm 13:0645d8841f51 252 {
bogdanm 13:0645d8841f51 253 struct
bogdanm 13:0645d8841f51 254 {
bogdanm 13:0645d8841f51 255 #if (__CORTEX_M != 0x04)
bogdanm 13:0645d8841f51 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 13:0645d8841f51 257 #else
bogdanm 13:0645d8841f51 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 13:0645d8841f51 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 13:0645d8841f51 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 13:0645d8841f51 261 #endif
bogdanm 13:0645d8841f51 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 13:0645d8841f51 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 13:0645d8841f51 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 13:0645d8841f51 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 13:0645d8841f51 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 13:0645d8841f51 267 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 268 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 269 } APSR_Type;
bogdanm 13:0645d8841f51 270
bogdanm 13:0645d8841f51 271
bogdanm 13:0645d8841f51 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 13:0645d8841f51 273 */
bogdanm 13:0645d8841f51 274 typedef union
bogdanm 13:0645d8841f51 275 {
bogdanm 13:0645d8841f51 276 struct
bogdanm 13:0645d8841f51 277 {
bogdanm 13:0645d8841f51 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 13:0645d8841f51 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 13:0645d8841f51 280 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 281 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 282 } IPSR_Type;
bogdanm 13:0645d8841f51 283
bogdanm 13:0645d8841f51 284
bogdanm 13:0645d8841f51 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 13:0645d8841f51 286 */
bogdanm 13:0645d8841f51 287 typedef union
bogdanm 13:0645d8841f51 288 {
bogdanm 13:0645d8841f51 289 struct
bogdanm 13:0645d8841f51 290 {
bogdanm 13:0645d8841f51 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 13:0645d8841f51 292 #if (__CORTEX_M != 0x04)
bogdanm 13:0645d8841f51 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 13:0645d8841f51 294 #else
bogdanm 13:0645d8841f51 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 13:0645d8841f51 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 13:0645d8841f51 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 13:0645d8841f51 298 #endif
bogdanm 13:0645d8841f51 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 13:0645d8841f51 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 13:0645d8841f51 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 13:0645d8841f51 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 13:0645d8841f51 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 13:0645d8841f51 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 13:0645d8841f51 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 13:0645d8841f51 306 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 307 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 308 } xPSR_Type;
bogdanm 13:0645d8841f51 309
bogdanm 13:0645d8841f51 310
bogdanm 13:0645d8841f51 311 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 13:0645d8841f51 312 */
bogdanm 13:0645d8841f51 313 typedef union
bogdanm 13:0645d8841f51 314 {
bogdanm 13:0645d8841f51 315 struct
bogdanm 13:0645d8841f51 316 {
bogdanm 13:0645d8841f51 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 13:0645d8841f51 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 13:0645d8841f51 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 13:0645d8841f51 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 13:0645d8841f51 321 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 322 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 323 } CONTROL_Type;
bogdanm 13:0645d8841f51 324
bogdanm 13:0645d8841f51 325 /*@} end of group CMSIS_CORE */
bogdanm 13:0645d8841f51 326
bogdanm 13:0645d8841f51 327
bogdanm 13:0645d8841f51 328 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 13:0645d8841f51 330 \brief Type definitions for the NVIC Registers
bogdanm 13:0645d8841f51 331 @{
bogdanm 13:0645d8841f51 332 */
bogdanm 13:0645d8841f51 333
bogdanm 13:0645d8841f51 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 13:0645d8841f51 335 */
bogdanm 13:0645d8841f51 336 typedef struct
bogdanm 13:0645d8841f51 337 {
bogdanm 13:0645d8841f51 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 13:0645d8841f51 339 uint32_t RESERVED0[24];
bogdanm 13:0645d8841f51 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 13:0645d8841f51 341 uint32_t RSERVED1[24];
bogdanm 13:0645d8841f51 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 13:0645d8841f51 343 uint32_t RESERVED2[24];
bogdanm 13:0645d8841f51 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 13:0645d8841f51 345 uint32_t RESERVED3[24];
bogdanm 13:0645d8841f51 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
bogdanm 13:0645d8841f51 347 uint32_t RESERVED4[56];
bogdanm 13:0645d8841f51 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
bogdanm 13:0645d8841f51 349 uint32_t RESERVED5[644];
bogdanm 13:0645d8841f51 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 13:0645d8841f51 351 } NVIC_Type;
bogdanm 13:0645d8841f51 352
bogdanm 13:0645d8841f51 353 /* Software Triggered Interrupt Register Definitions */
bogdanm 13:0645d8841f51 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
bogdanm 13:0645d8841f51 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
bogdanm 13:0645d8841f51 356
bogdanm 13:0645d8841f51 357 /*@} end of group CMSIS_NVIC */
bogdanm 13:0645d8841f51 358
bogdanm 13:0645d8841f51 359
bogdanm 13:0645d8841f51 360 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 361 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 13:0645d8841f51 362 \brief Type definitions for the System Control Block Registers
bogdanm 13:0645d8841f51 363 @{
bogdanm 13:0645d8841f51 364 */
bogdanm 13:0645d8841f51 365
bogdanm 13:0645d8841f51 366 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 13:0645d8841f51 367 */
bogdanm 13:0645d8841f51 368 typedef struct
bogdanm 13:0645d8841f51 369 {
bogdanm 13:0645d8841f51 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 13:0645d8841f51 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 13:0645d8841f51 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 13:0645d8841f51 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 13:0645d8841f51 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 13:0645d8841f51 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 13:0645d8841f51 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
bogdanm 13:0645d8841f51 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 13:0645d8841f51 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
bogdanm 13:0645d8841f51 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
bogdanm 13:0645d8841f51 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
bogdanm 13:0645d8841f51 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
bogdanm 13:0645d8841f51 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
bogdanm 13:0645d8841f51 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
bogdanm 13:0645d8841f51 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
bogdanm 13:0645d8841f51 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
bogdanm 13:0645d8841f51 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
bogdanm 13:0645d8841f51 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
bogdanm 13:0645d8841f51 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
bogdanm 13:0645d8841f51 389 uint32_t RESERVED0[5];
bogdanm 13:0645d8841f51 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 13:0645d8841f51 391 } SCB_Type;
bogdanm 13:0645d8841f51 392
bogdanm 13:0645d8841f51 393 /* SCB CPUID Register Definitions */
bogdanm 13:0645d8841f51 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 13:0645d8841f51 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 13:0645d8841f51 396
bogdanm 13:0645d8841f51 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 13:0645d8841f51 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 13:0645d8841f51 399
bogdanm 13:0645d8841f51 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 13:0645d8841f51 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 13:0645d8841f51 402
bogdanm 13:0645d8841f51 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 13:0645d8841f51 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 13:0645d8841f51 405
bogdanm 13:0645d8841f51 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 13:0645d8841f51 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 13:0645d8841f51 408
bogdanm 13:0645d8841f51 409 /* SCB Interrupt Control State Register Definitions */
bogdanm 13:0645d8841f51 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 13:0645d8841f51 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 13:0645d8841f51 412
bogdanm 13:0645d8841f51 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 13:0645d8841f51 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 13:0645d8841f51 415
bogdanm 13:0645d8841f51 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 13:0645d8841f51 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 13:0645d8841f51 418
bogdanm 13:0645d8841f51 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 13:0645d8841f51 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 13:0645d8841f51 421
bogdanm 13:0645d8841f51 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 13:0645d8841f51 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 13:0645d8841f51 424
bogdanm 13:0645d8841f51 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 13:0645d8841f51 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 13:0645d8841f51 427
bogdanm 13:0645d8841f51 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 13:0645d8841f51 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 13:0645d8841f51 430
bogdanm 13:0645d8841f51 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 13:0645d8841f51 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 13:0645d8841f51 433
bogdanm 13:0645d8841f51 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
bogdanm 13:0645d8841f51 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 13:0645d8841f51 436
bogdanm 13:0645d8841f51 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 13:0645d8841f51 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 13:0645d8841f51 439
bogdanm 13:0645d8841f51 440 /* SCB Vector Table Offset Register Definitions */
bogdanm 13:0645d8841f51 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 13:0645d8841f51 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 13:0645d8841f51 443
bogdanm 13:0645d8841f51 444 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 13:0645d8841f51 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 13:0645d8841f51 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 13:0645d8841f51 447
bogdanm 13:0645d8841f51 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 13:0645d8841f51 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 13:0645d8841f51 450
bogdanm 13:0645d8841f51 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 13:0645d8841f51 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 13:0645d8841f51 453
bogdanm 13:0645d8841f51 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 13:0645d8841f51 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 13:0645d8841f51 456
bogdanm 13:0645d8841f51 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 13:0645d8841f51 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 13:0645d8841f51 459
bogdanm 13:0645d8841f51 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 13:0645d8841f51 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 13:0645d8841f51 462
bogdanm 13:0645d8841f51 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
bogdanm 13:0645d8841f51 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 13:0645d8841f51 465
bogdanm 13:0645d8841f51 466 /* SCB System Control Register Definitions */
bogdanm 13:0645d8841f51 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 13:0645d8841f51 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 13:0645d8841f51 469
bogdanm 13:0645d8841f51 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 13:0645d8841f51 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 13:0645d8841f51 472
bogdanm 13:0645d8841f51 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 13:0645d8841f51 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 13:0645d8841f51 475
bogdanm 13:0645d8841f51 476 /* SCB Configuration Control Register Definitions */
bogdanm 13:0645d8841f51 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 13:0645d8841f51 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 13:0645d8841f51 479
bogdanm 13:0645d8841f51 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 13:0645d8841f51 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 13:0645d8841f51 482
bogdanm 13:0645d8841f51 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 13:0645d8841f51 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 13:0645d8841f51 485
bogdanm 13:0645d8841f51 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 13:0645d8841f51 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 13:0645d8841f51 488
bogdanm 13:0645d8841f51 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
bogdanm 13:0645d8841f51 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 13:0645d8841f51 491
bogdanm 13:0645d8841f51 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
bogdanm 13:0645d8841f51 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 13:0645d8841f51 494
bogdanm 13:0645d8841f51 495 /* SCB System Handler Control and State Register Definitions */
bogdanm 13:0645d8841f51 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 13:0645d8841f51 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 13:0645d8841f51 498
bogdanm 13:0645d8841f51 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 13:0645d8841f51 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 13:0645d8841f51 501
bogdanm 13:0645d8841f51 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 13:0645d8841f51 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 13:0645d8841f51 504
bogdanm 13:0645d8841f51 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 13:0645d8841f51 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 13:0645d8841f51 507
bogdanm 13:0645d8841f51 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 13:0645d8841f51 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 13:0645d8841f51 510
bogdanm 13:0645d8841f51 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 13:0645d8841f51 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 13:0645d8841f51 513
bogdanm 13:0645d8841f51 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 13:0645d8841f51 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 13:0645d8841f51 516
bogdanm 13:0645d8841f51 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 13:0645d8841f51 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 13:0645d8841f51 519
bogdanm 13:0645d8841f51 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 13:0645d8841f51 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 13:0645d8841f51 522
bogdanm 13:0645d8841f51 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
bogdanm 13:0645d8841f51 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 13:0645d8841f51 525
bogdanm 13:0645d8841f51 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 13:0645d8841f51 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 13:0645d8841f51 528
bogdanm 13:0645d8841f51 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 13:0645d8841f51 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 13:0645d8841f51 531
bogdanm 13:0645d8841f51 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 13:0645d8841f51 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 13:0645d8841f51 534
bogdanm 13:0645d8841f51 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
bogdanm 13:0645d8841f51 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 13:0645d8841f51 537
bogdanm 13:0645d8841f51 538 /* SCB Configurable Fault Status Registers Definitions */
bogdanm 13:0645d8841f51 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 13:0645d8841f51 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 13:0645d8841f51 541
bogdanm 13:0645d8841f51 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 13:0645d8841f51 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 13:0645d8841f51 544
bogdanm 13:0645d8841f51 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
bogdanm 13:0645d8841f51 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 13:0645d8841f51 547
bogdanm 13:0645d8841f51 548 /* SCB Hard Fault Status Registers Definitions */
bogdanm 13:0645d8841f51 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 13:0645d8841f51 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 13:0645d8841f51 551
bogdanm 13:0645d8841f51 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
bogdanm 13:0645d8841f51 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 13:0645d8841f51 554
bogdanm 13:0645d8841f51 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
bogdanm 13:0645d8841f51 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 13:0645d8841f51 557
bogdanm 13:0645d8841f51 558 /* SCB Debug Fault Status Register Definitions */
bogdanm 13:0645d8841f51 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
bogdanm 13:0645d8841f51 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 13:0645d8841f51 561
bogdanm 13:0645d8841f51 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
bogdanm 13:0645d8841f51 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 13:0645d8841f51 564
bogdanm 13:0645d8841f51 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
bogdanm 13:0645d8841f51 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 13:0645d8841f51 567
bogdanm 13:0645d8841f51 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
bogdanm 13:0645d8841f51 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 13:0645d8841f51 570
bogdanm 13:0645d8841f51 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
bogdanm 13:0645d8841f51 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
bogdanm 13:0645d8841f51 573
bogdanm 13:0645d8841f51 574 /*@} end of group CMSIS_SCB */
bogdanm 13:0645d8841f51 575
bogdanm 13:0645d8841f51 576
bogdanm 13:0645d8841f51 577 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm 13:0645d8841f51 579 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 13:0645d8841f51 580 @{
bogdanm 13:0645d8841f51 581 */
bogdanm 13:0645d8841f51 582
bogdanm 13:0645d8841f51 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 13:0645d8841f51 584 */
bogdanm 13:0645d8841f51 585 typedef struct
bogdanm 13:0645d8841f51 586 {
bogdanm 13:0645d8841f51 587 uint32_t RESERVED0[1];
bogdanm 13:0645d8841f51 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
bogdanm 13:0645d8841f51 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 13:0645d8841f51 590 } SCnSCB_Type;
bogdanm 13:0645d8841f51 591
bogdanm 13:0645d8841f51 592 /* Interrupt Controller Type Register Definitions */
bogdanm 13:0645d8841f51 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
bogdanm 13:0645d8841f51 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
bogdanm 13:0645d8841f51 595
bogdanm 13:0645d8841f51 596 /* Auxiliary Control Register Definitions */
bogdanm 13:0645d8841f51 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
bogdanm 13:0645d8841f51 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
bogdanm 13:0645d8841f51 599
bogdanm 13:0645d8841f51 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
bogdanm 13:0645d8841f51 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
bogdanm 13:0645d8841f51 602
bogdanm 13:0645d8841f51 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
bogdanm 13:0645d8841f51 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 13:0645d8841f51 605
bogdanm 13:0645d8841f51 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
bogdanm 13:0645d8841f51 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 13:0645d8841f51 608
bogdanm 13:0645d8841f51 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
bogdanm 13:0645d8841f51 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 13:0645d8841f51 611
bogdanm 13:0645d8841f51 612 /*@} end of group CMSIS_SCnotSCB */
bogdanm 13:0645d8841f51 613
bogdanm 13:0645d8841f51 614
bogdanm 13:0645d8841f51 615 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 13:0645d8841f51 617 \brief Type definitions for the System Timer Registers.
bogdanm 13:0645d8841f51 618 @{
bogdanm 13:0645d8841f51 619 */
bogdanm 13:0645d8841f51 620
bogdanm 13:0645d8841f51 621 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 13:0645d8841f51 622 */
bogdanm 13:0645d8841f51 623 typedef struct
bogdanm 13:0645d8841f51 624 {
bogdanm 13:0645d8841f51 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 13:0645d8841f51 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 13:0645d8841f51 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 13:0645d8841f51 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 13:0645d8841f51 629 } SysTick_Type;
bogdanm 13:0645d8841f51 630
bogdanm 13:0645d8841f51 631 /* SysTick Control / Status Register Definitions */
bogdanm 13:0645d8841f51 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 13:0645d8841f51 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 13:0645d8841f51 634
bogdanm 13:0645d8841f51 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 13:0645d8841f51 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 13:0645d8841f51 637
bogdanm 13:0645d8841f51 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 13:0645d8841f51 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 13:0645d8841f51 640
bogdanm 13:0645d8841f51 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 13:0645d8841f51 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 13:0645d8841f51 643
bogdanm 13:0645d8841f51 644 /* SysTick Reload Register Definitions */
bogdanm 13:0645d8841f51 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 13:0645d8841f51 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 13:0645d8841f51 647
bogdanm 13:0645d8841f51 648 /* SysTick Current Register Definitions */
bogdanm 13:0645d8841f51 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 13:0645d8841f51 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 13:0645d8841f51 651
bogdanm 13:0645d8841f51 652 /* SysTick Calibration Register Definitions */
bogdanm 13:0645d8841f51 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 13:0645d8841f51 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 13:0645d8841f51 655
bogdanm 13:0645d8841f51 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 13:0645d8841f51 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 13:0645d8841f51 658
bogdanm 13:0645d8841f51 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 13:0645d8841f51 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 13:0645d8841f51 661
bogdanm 13:0645d8841f51 662 /*@} end of group CMSIS_SysTick */
bogdanm 13:0645d8841f51 663
bogdanm 13:0645d8841f51 664
bogdanm 13:0645d8841f51 665 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm 13:0645d8841f51 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 13:0645d8841f51 668 @{
bogdanm 13:0645d8841f51 669 */
bogdanm 13:0645d8841f51 670
bogdanm 13:0645d8841f51 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 13:0645d8841f51 672 */
bogdanm 13:0645d8841f51 673 typedef struct
bogdanm 13:0645d8841f51 674 {
bogdanm 13:0645d8841f51 675 __O union
bogdanm 13:0645d8841f51 676 {
bogdanm 13:0645d8841f51 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
bogdanm 13:0645d8841f51 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
bogdanm 13:0645d8841f51 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
bogdanm 13:0645d8841f51 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
bogdanm 13:0645d8841f51 681 uint32_t RESERVED0[864];
bogdanm 13:0645d8841f51 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
bogdanm 13:0645d8841f51 683 uint32_t RESERVED1[15];
bogdanm 13:0645d8841f51 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
bogdanm 13:0645d8841f51 685 uint32_t RESERVED2[15];
bogdanm 13:0645d8841f51 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
bogdanm 13:0645d8841f51 687 uint32_t RESERVED3[29];
bogdanm 13:0645d8841f51 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
bogdanm 13:0645d8841f51 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
bogdanm 13:0645d8841f51 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
bogdanm 13:0645d8841f51 691 uint32_t RESERVED4[43];
bogdanm 13:0645d8841f51 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
bogdanm 13:0645d8841f51 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
bogdanm 13:0645d8841f51 694 uint32_t RESERVED5[6];
bogdanm 13:0645d8841f51 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
bogdanm 13:0645d8841f51 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
bogdanm 13:0645d8841f51 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
bogdanm 13:0645d8841f51 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
bogdanm 13:0645d8841f51 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
bogdanm 13:0645d8841f51 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
bogdanm 13:0645d8841f51 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
bogdanm 13:0645d8841f51 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
bogdanm 13:0645d8841f51 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
bogdanm 13:0645d8841f51 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
bogdanm 13:0645d8841f51 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
bogdanm 13:0645d8841f51 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 13:0645d8841f51 707 } ITM_Type;
bogdanm 13:0645d8841f51 708
bogdanm 13:0645d8841f51 709 /* ITM Trace Privilege Register Definitions */
bogdanm 13:0645d8841f51 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
bogdanm 13:0645d8841f51 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 13:0645d8841f51 712
bogdanm 13:0645d8841f51 713 /* ITM Trace Control Register Definitions */
bogdanm 13:0645d8841f51 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
bogdanm 13:0645d8841f51 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 13:0645d8841f51 716
bogdanm 13:0645d8841f51 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
bogdanm 13:0645d8841f51 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 13:0645d8841f51 719
bogdanm 13:0645d8841f51 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 13:0645d8841f51 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 13:0645d8841f51 722
bogdanm 13:0645d8841f51 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
bogdanm 13:0645d8841f51 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 13:0645d8841f51 725
bogdanm 13:0645d8841f51 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
bogdanm 13:0645d8841f51 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 13:0645d8841f51 728
bogdanm 13:0645d8841f51 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
bogdanm 13:0645d8841f51 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 13:0645d8841f51 731
bogdanm 13:0645d8841f51 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
bogdanm 13:0645d8841f51 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 13:0645d8841f51 734
bogdanm 13:0645d8841f51 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
bogdanm 13:0645d8841f51 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 13:0645d8841f51 737
bogdanm 13:0645d8841f51 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
bogdanm 13:0645d8841f51 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 13:0645d8841f51 740
bogdanm 13:0645d8841f51 741 /* ITM Integration Write Register Definitions */
bogdanm 13:0645d8841f51 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
bogdanm 13:0645d8841f51 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 13:0645d8841f51 744
bogdanm 13:0645d8841f51 745 /* ITM Integration Read Register Definitions */
bogdanm 13:0645d8841f51 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
bogdanm 13:0645d8841f51 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
bogdanm 13:0645d8841f51 748
bogdanm 13:0645d8841f51 749 /* ITM Integration Mode Control Register Definitions */
bogdanm 13:0645d8841f51 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
bogdanm 13:0645d8841f51 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 13:0645d8841f51 752
bogdanm 13:0645d8841f51 753 /* ITM Lock Status Register Definitions */
bogdanm 13:0645d8841f51 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
bogdanm 13:0645d8841f51 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 13:0645d8841f51 756
bogdanm 13:0645d8841f51 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
bogdanm 13:0645d8841f51 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 13:0645d8841f51 759
bogdanm 13:0645d8841f51 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
bogdanm 13:0645d8841f51 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
bogdanm 13:0645d8841f51 762
bogdanm 13:0645d8841f51 763 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 13:0645d8841f51 764
bogdanm 13:0645d8841f51 765
bogdanm 13:0645d8841f51 766 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm 13:0645d8841f51 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 13:0645d8841f51 769 @{
bogdanm 13:0645d8841f51 770 */
bogdanm 13:0645d8841f51 771
bogdanm 13:0645d8841f51 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 13:0645d8841f51 773 */
bogdanm 13:0645d8841f51 774 typedef struct
bogdanm 13:0645d8841f51 775 {
bogdanm 13:0645d8841f51 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
bogdanm 13:0645d8841f51 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
bogdanm 13:0645d8841f51 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
bogdanm 13:0645d8841f51 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
bogdanm 13:0645d8841f51 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
bogdanm 13:0645d8841f51 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
bogdanm 13:0645d8841f51 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
bogdanm 13:0645d8841f51 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
bogdanm 13:0645d8841f51 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
bogdanm 13:0645d8841f51 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
bogdanm 13:0645d8841f51 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
bogdanm 13:0645d8841f51 787 uint32_t RESERVED0[1];
bogdanm 13:0645d8841f51 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
bogdanm 13:0645d8841f51 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
bogdanm 13:0645d8841f51 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
bogdanm 13:0645d8841f51 791 uint32_t RESERVED1[1];
bogdanm 13:0645d8841f51 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
bogdanm 13:0645d8841f51 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
bogdanm 13:0645d8841f51 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
bogdanm 13:0645d8841f51 795 uint32_t RESERVED2[1];
bogdanm 13:0645d8841f51 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
bogdanm 13:0645d8841f51 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
bogdanm 13:0645d8841f51 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 13:0645d8841f51 799 } DWT_Type;
bogdanm 13:0645d8841f51 800
bogdanm 13:0645d8841f51 801 /* DWT Control Register Definitions */
bogdanm 13:0645d8841f51 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
bogdanm 13:0645d8841f51 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 13:0645d8841f51 804
bogdanm 13:0645d8841f51 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 13:0645d8841f51 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 13:0645d8841f51 807
bogdanm 13:0645d8841f51 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 13:0645d8841f51 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 13:0645d8841f51 810
bogdanm 13:0645d8841f51 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 13:0645d8841f51 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 13:0645d8841f51 813
bogdanm 13:0645d8841f51 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 13:0645d8841f51 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 13:0645d8841f51 816
bogdanm 13:0645d8841f51 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 13:0645d8841f51 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 13:0645d8841f51 819
bogdanm 13:0645d8841f51 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 13:0645d8841f51 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 13:0645d8841f51 822
bogdanm 13:0645d8841f51 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 13:0645d8841f51 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 13:0645d8841f51 825
bogdanm 13:0645d8841f51 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 13:0645d8841f51 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 13:0645d8841f51 828
bogdanm 13:0645d8841f51 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 13:0645d8841f51 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 13:0645d8841f51 831
bogdanm 13:0645d8841f51 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 13:0645d8841f51 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 13:0645d8841f51 834
bogdanm 13:0645d8841f51 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 13:0645d8841f51 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 13:0645d8841f51 837
bogdanm 13:0645d8841f51 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 13:0645d8841f51 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 13:0645d8841f51 840
bogdanm 13:0645d8841f51 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
bogdanm 13:0645d8841f51 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 13:0645d8841f51 843
bogdanm 13:0645d8841f51 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
bogdanm 13:0645d8841f51 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 13:0645d8841f51 846
bogdanm 13:0645d8841f51 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
bogdanm 13:0645d8841f51 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 13:0645d8841f51 849
bogdanm 13:0645d8841f51 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
bogdanm 13:0645d8841f51 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 13:0645d8841f51 852
bogdanm 13:0645d8841f51 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
bogdanm 13:0645d8841f51 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 13:0645d8841f51 855
bogdanm 13:0645d8841f51 856 /* DWT CPI Count Register Definitions */
bogdanm 13:0645d8841f51 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
bogdanm 13:0645d8841f51 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 13:0645d8841f51 859
bogdanm 13:0645d8841f51 860 /* DWT Exception Overhead Count Register Definitions */
bogdanm 13:0645d8841f51 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
bogdanm 13:0645d8841f51 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 13:0645d8841f51 863
bogdanm 13:0645d8841f51 864 /* DWT Sleep Count Register Definitions */
bogdanm 13:0645d8841f51 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
bogdanm 13:0645d8841f51 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 13:0645d8841f51 867
bogdanm 13:0645d8841f51 868 /* DWT LSU Count Register Definitions */
bogdanm 13:0645d8841f51 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
bogdanm 13:0645d8841f51 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 13:0645d8841f51 871
bogdanm 13:0645d8841f51 872 /* DWT Folded-instruction Count Register Definitions */
bogdanm 13:0645d8841f51 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
bogdanm 13:0645d8841f51 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 13:0645d8841f51 875
bogdanm 13:0645d8841f51 876 /* DWT Comparator Mask Register Definitions */
bogdanm 13:0645d8841f51 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
bogdanm 13:0645d8841f51 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
bogdanm 13:0645d8841f51 879
bogdanm 13:0645d8841f51 880 /* DWT Comparator Function Register Definitions */
bogdanm 13:0645d8841f51 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
bogdanm 13:0645d8841f51 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 13:0645d8841f51 883
bogdanm 13:0645d8841f51 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 13:0645d8841f51 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 13:0645d8841f51 886
bogdanm 13:0645d8841f51 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 13:0645d8841f51 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 13:0645d8841f51 889
bogdanm 13:0645d8841f51 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 13:0645d8841f51 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 13:0645d8841f51 892
bogdanm 13:0645d8841f51 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 13:0645d8841f51 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 13:0645d8841f51 895
bogdanm 13:0645d8841f51 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 13:0645d8841f51 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 13:0645d8841f51 898
bogdanm 13:0645d8841f51 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 13:0645d8841f51 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 13:0645d8841f51 901
bogdanm 13:0645d8841f51 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 13:0645d8841f51 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 13:0645d8841f51 904
bogdanm 13:0645d8841f51 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
bogdanm 13:0645d8841f51 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 13:0645d8841f51 907
bogdanm 13:0645d8841f51 908 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 13:0645d8841f51 909
bogdanm 13:0645d8841f51 910
bogdanm 13:0645d8841f51 911 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm 13:0645d8841f51 913 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 13:0645d8841f51 914 @{
bogdanm 13:0645d8841f51 915 */
bogdanm 13:0645d8841f51 916
bogdanm 13:0645d8841f51 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 13:0645d8841f51 918 */
bogdanm 13:0645d8841f51 919 typedef struct
bogdanm 13:0645d8841f51 920 {
bogdanm 13:0645d8841f51 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
bogdanm 13:0645d8841f51 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
bogdanm 13:0645d8841f51 923 uint32_t RESERVED0[2];
bogdanm 13:0645d8841f51 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
bogdanm 13:0645d8841f51 925 uint32_t RESERVED1[55];
bogdanm 13:0645d8841f51 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
bogdanm 13:0645d8841f51 927 uint32_t RESERVED2[131];
bogdanm 13:0645d8841f51 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
bogdanm 13:0645d8841f51 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
bogdanm 13:0645d8841f51 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
bogdanm 13:0645d8841f51 931 uint32_t RESERVED3[759];
bogdanm 13:0645d8841f51 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
bogdanm 13:0645d8841f51 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
bogdanm 13:0645d8841f51 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
bogdanm 13:0645d8841f51 935 uint32_t RESERVED4[1];
bogdanm 13:0645d8841f51 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
bogdanm 13:0645d8841f51 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
bogdanm 13:0645d8841f51 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
bogdanm 13:0645d8841f51 939 uint32_t RESERVED5[39];
bogdanm 13:0645d8841f51 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
bogdanm 13:0645d8841f51 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
bogdanm 13:0645d8841f51 942 uint32_t RESERVED7[8];
bogdanm 13:0645d8841f51 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
bogdanm 13:0645d8841f51 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 13:0645d8841f51 945 } TPI_Type;
bogdanm 13:0645d8841f51 946
bogdanm 13:0645d8841f51 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm 13:0645d8841f51 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
bogdanm 13:0645d8841f51 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 13:0645d8841f51 950
bogdanm 13:0645d8841f51 951 /* TPI Selected Pin Protocol Register Definitions */
bogdanm 13:0645d8841f51 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
bogdanm 13:0645d8841f51 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
bogdanm 13:0645d8841f51 954
bogdanm 13:0645d8841f51 955 /* TPI Formatter and Flush Status Register Definitions */
bogdanm 13:0645d8841f51 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
bogdanm 13:0645d8841f51 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 13:0645d8841f51 958
bogdanm 13:0645d8841f51 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
bogdanm 13:0645d8841f51 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 13:0645d8841f51 961
bogdanm 13:0645d8841f51 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
bogdanm 13:0645d8841f51 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 13:0645d8841f51 964
bogdanm 13:0645d8841f51 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
bogdanm 13:0645d8841f51 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
bogdanm 13:0645d8841f51 967
bogdanm 13:0645d8841f51 968 /* TPI Formatter and Flush Control Register Definitions */
bogdanm 13:0645d8841f51 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
bogdanm 13:0645d8841f51 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 13:0645d8841f51 971
bogdanm 13:0645d8841f51 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
bogdanm 13:0645d8841f51 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 13:0645d8841f51 974
bogdanm 13:0645d8841f51 975 /* TPI TRIGGER Register Definitions */
bogdanm 13:0645d8841f51 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
bogdanm 13:0645d8841f51 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 13:0645d8841f51 978
bogdanm 13:0645d8841f51 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm 13:0645d8841f51 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 13:0645d8841f51 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 13:0645d8841f51 982
bogdanm 13:0645d8841f51 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 13:0645d8841f51 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 13:0645d8841f51 985
bogdanm 13:0645d8841f51 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 13:0645d8841f51 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 13:0645d8841f51 988
bogdanm 13:0645d8841f51 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 13:0645d8841f51 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 13:0645d8841f51 991
bogdanm 13:0645d8841f51 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
bogdanm 13:0645d8841f51 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 13:0645d8841f51 994
bogdanm 13:0645d8841f51 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
bogdanm 13:0645d8841f51 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 13:0645d8841f51 997
bogdanm 13:0645d8841f51 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
bogdanm 13:0645d8841f51 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 13:0645d8841f51 1000
bogdanm 13:0645d8841f51 1001 /* TPI ITATBCTR2 Register Definitions */
bogdanm 13:0645d8841f51 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
bogdanm 13:0645d8841f51 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 13:0645d8841f51 1004
bogdanm 13:0645d8841f51 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm 13:0645d8841f51 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 13:0645d8841f51 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 13:0645d8841f51 1008
bogdanm 13:0645d8841f51 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 13:0645d8841f51 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 13:0645d8841f51 1011
bogdanm 13:0645d8841f51 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 13:0645d8841f51 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 13:0645d8841f51 1014
bogdanm 13:0645d8841f51 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 13:0645d8841f51 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 13:0645d8841f51 1017
bogdanm 13:0645d8841f51 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
bogdanm 13:0645d8841f51 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 13:0645d8841f51 1020
bogdanm 13:0645d8841f51 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
bogdanm 13:0645d8841f51 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 13:0645d8841f51 1023
bogdanm 13:0645d8841f51 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
bogdanm 13:0645d8841f51 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 13:0645d8841f51 1026
bogdanm 13:0645d8841f51 1027 /* TPI ITATBCTR0 Register Definitions */
bogdanm 13:0645d8841f51 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
bogdanm 13:0645d8841f51 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 13:0645d8841f51 1030
bogdanm 13:0645d8841f51 1031 /* TPI Integration Mode Control Register Definitions */
bogdanm 13:0645d8841f51 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
bogdanm 13:0645d8841f51 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
bogdanm 13:0645d8841f51 1034
bogdanm 13:0645d8841f51 1035 /* TPI DEVID Register Definitions */
bogdanm 13:0645d8841f51 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
bogdanm 13:0645d8841f51 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 13:0645d8841f51 1038
bogdanm 13:0645d8841f51 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
bogdanm 13:0645d8841f51 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 13:0645d8841f51 1041
bogdanm 13:0645d8841f51 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
bogdanm 13:0645d8841f51 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 13:0645d8841f51 1044
bogdanm 13:0645d8841f51 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
bogdanm 13:0645d8841f51 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 13:0645d8841f51 1047
bogdanm 13:0645d8841f51 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
bogdanm 13:0645d8841f51 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 13:0645d8841f51 1050
bogdanm 13:0645d8841f51 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
bogdanm 13:0645d8841f51 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 13:0645d8841f51 1053
bogdanm 13:0645d8841f51 1054 /* TPI DEVTYPE Register Definitions */
bogdanm 13:0645d8841f51 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
bogdanm 13:0645d8841f51 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
bogdanm 13:0645d8841f51 1057
bogdanm 13:0645d8841f51 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
bogdanm 13:0645d8841f51 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 13:0645d8841f51 1060
bogdanm 13:0645d8841f51 1061 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 13:0645d8841f51 1062
bogdanm 13:0645d8841f51 1063
bogdanm 13:0645d8841f51 1064 #if (__MPU_PRESENT == 1)
bogdanm 13:0645d8841f51 1065 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 13:0645d8841f51 1067 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 13:0645d8841f51 1068 @{
bogdanm 13:0645d8841f51 1069 */
bogdanm 13:0645d8841f51 1070
bogdanm 13:0645d8841f51 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 13:0645d8841f51 1072 */
bogdanm 13:0645d8841f51 1073 typedef struct
bogdanm 13:0645d8841f51 1074 {
bogdanm 13:0645d8841f51 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 13:0645d8841f51 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 13:0645d8841f51 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 13:0645d8841f51 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 13:0645d8841f51 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 13:0645d8841f51 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
bogdanm 13:0645d8841f51 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
bogdanm 13:0645d8841f51 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
bogdanm 13:0645d8841f51 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
bogdanm 13:0645d8841f51 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
bogdanm 13:0645d8841f51 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 13:0645d8841f51 1086 } MPU_Type;
bogdanm 13:0645d8841f51 1087
bogdanm 13:0645d8841f51 1088 /* MPU Type Register */
bogdanm 13:0645d8841f51 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 13:0645d8841f51 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 13:0645d8841f51 1091
bogdanm 13:0645d8841f51 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 13:0645d8841f51 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 13:0645d8841f51 1094
bogdanm 13:0645d8841f51 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 13:0645d8841f51 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 13:0645d8841f51 1097
bogdanm 13:0645d8841f51 1098 /* MPU Control Register */
bogdanm 13:0645d8841f51 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 13:0645d8841f51 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 13:0645d8841f51 1101
bogdanm 13:0645d8841f51 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 13:0645d8841f51 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 13:0645d8841f51 1104
bogdanm 13:0645d8841f51 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 13:0645d8841f51 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 13:0645d8841f51 1107
bogdanm 13:0645d8841f51 1108 /* MPU Region Number Register */
bogdanm 13:0645d8841f51 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 13:0645d8841f51 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 13:0645d8841f51 1111
bogdanm 13:0645d8841f51 1112 /* MPU Region Base Address Register */
bogdanm 13:0645d8841f51 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
bogdanm 13:0645d8841f51 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 13:0645d8841f51 1115
bogdanm 13:0645d8841f51 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 13:0645d8841f51 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 13:0645d8841f51 1118
bogdanm 13:0645d8841f51 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 13:0645d8841f51 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 13:0645d8841f51 1121
bogdanm 13:0645d8841f51 1122 /* MPU Region Attribute and Size Register */
bogdanm 13:0645d8841f51 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 13:0645d8841f51 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 13:0645d8841f51 1125
bogdanm 13:0645d8841f51 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 13:0645d8841f51 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 13:0645d8841f51 1128
bogdanm 13:0645d8841f51 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 13:0645d8841f51 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 13:0645d8841f51 1131
bogdanm 13:0645d8841f51 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 13:0645d8841f51 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 13:0645d8841f51 1134
bogdanm 13:0645d8841f51 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 13:0645d8841f51 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 13:0645d8841f51 1137
bogdanm 13:0645d8841f51 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 13:0645d8841f51 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 13:0645d8841f51 1140
bogdanm 13:0645d8841f51 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 13:0645d8841f51 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 13:0645d8841f51 1143
bogdanm 13:0645d8841f51 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 13:0645d8841f51 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 13:0645d8841f51 1146
bogdanm 13:0645d8841f51 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 13:0645d8841f51 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 13:0645d8841f51 1149
bogdanm 13:0645d8841f51 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 13:0645d8841f51 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 13:0645d8841f51 1152
bogdanm 13:0645d8841f51 1153 /*@} end of group CMSIS_MPU */
bogdanm 13:0645d8841f51 1154 #endif
bogdanm 13:0645d8841f51 1155
bogdanm 13:0645d8841f51 1156
bogdanm 13:0645d8841f51 1157 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 1158 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
bogdanm 13:0645d8841f51 1160 \brief Type definitions for the Floating Point Unit (FPU)
bogdanm 13:0645d8841f51 1161 @{
bogdanm 13:0645d8841f51 1162 */
bogdanm 13:0645d8841f51 1163
bogdanm 13:0645d8841f51 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
bogdanm 13:0645d8841f51 1165 */
bogdanm 13:0645d8841f51 1166 typedef struct
bogdanm 13:0645d8841f51 1167 {
bogdanm 13:0645d8841f51 1168 uint32_t RESERVED0[1];
bogdanm 13:0645d8841f51 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
bogdanm 13:0645d8841f51 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
bogdanm 13:0645d8841f51 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
bogdanm 13:0645d8841f51 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
bogdanm 13:0645d8841f51 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
bogdanm 13:0645d8841f51 1174 } FPU_Type;
bogdanm 13:0645d8841f51 1175
bogdanm 13:0645d8841f51 1176 /* Floating-Point Context Control Register */
bogdanm 13:0645d8841f51 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
bogdanm 13:0645d8841f51 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
bogdanm 13:0645d8841f51 1179
bogdanm 13:0645d8841f51 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
bogdanm 13:0645d8841f51 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
bogdanm 13:0645d8841f51 1182
bogdanm 13:0645d8841f51 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
bogdanm 13:0645d8841f51 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
bogdanm 13:0645d8841f51 1185
bogdanm 13:0645d8841f51 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
bogdanm 13:0645d8841f51 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
bogdanm 13:0645d8841f51 1188
bogdanm 13:0645d8841f51 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
bogdanm 13:0645d8841f51 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
bogdanm 13:0645d8841f51 1191
bogdanm 13:0645d8841f51 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
bogdanm 13:0645d8841f51 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
bogdanm 13:0645d8841f51 1194
bogdanm 13:0645d8841f51 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
bogdanm 13:0645d8841f51 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
bogdanm 13:0645d8841f51 1197
bogdanm 13:0645d8841f51 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
bogdanm 13:0645d8841f51 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
bogdanm 13:0645d8841f51 1200
bogdanm 13:0645d8841f51 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
bogdanm 13:0645d8841f51 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
bogdanm 13:0645d8841f51 1203
bogdanm 13:0645d8841f51 1204 /* Floating-Point Context Address Register */
bogdanm 13:0645d8841f51 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
bogdanm 13:0645d8841f51 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
bogdanm 13:0645d8841f51 1207
bogdanm 13:0645d8841f51 1208 /* Floating-Point Default Status Control Register */
bogdanm 13:0645d8841f51 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
bogdanm 13:0645d8841f51 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
bogdanm 13:0645d8841f51 1211
bogdanm 13:0645d8841f51 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
bogdanm 13:0645d8841f51 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
bogdanm 13:0645d8841f51 1214
bogdanm 13:0645d8841f51 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
bogdanm 13:0645d8841f51 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
bogdanm 13:0645d8841f51 1217
bogdanm 13:0645d8841f51 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
bogdanm 13:0645d8841f51 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
bogdanm 13:0645d8841f51 1220
bogdanm 13:0645d8841f51 1221 /* Media and FP Feature Register 0 */
bogdanm 13:0645d8841f51 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
bogdanm 13:0645d8841f51 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
bogdanm 13:0645d8841f51 1224
bogdanm 13:0645d8841f51 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
bogdanm 13:0645d8841f51 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
bogdanm 13:0645d8841f51 1227
bogdanm 13:0645d8841f51 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
bogdanm 13:0645d8841f51 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
bogdanm 13:0645d8841f51 1230
bogdanm 13:0645d8841f51 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
bogdanm 13:0645d8841f51 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
bogdanm 13:0645d8841f51 1233
bogdanm 13:0645d8841f51 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
bogdanm 13:0645d8841f51 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
bogdanm 13:0645d8841f51 1236
bogdanm 13:0645d8841f51 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
bogdanm 13:0645d8841f51 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
bogdanm 13:0645d8841f51 1239
bogdanm 13:0645d8841f51 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
bogdanm 13:0645d8841f51 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
bogdanm 13:0645d8841f51 1242
bogdanm 13:0645d8841f51 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
bogdanm 13:0645d8841f51 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
bogdanm 13:0645d8841f51 1245
bogdanm 13:0645d8841f51 1246 /* Media and FP Feature Register 1 */
bogdanm 13:0645d8841f51 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
bogdanm 13:0645d8841f51 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
bogdanm 13:0645d8841f51 1249
bogdanm 13:0645d8841f51 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
bogdanm 13:0645d8841f51 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
bogdanm 13:0645d8841f51 1252
bogdanm 13:0645d8841f51 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
bogdanm 13:0645d8841f51 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
bogdanm 13:0645d8841f51 1255
bogdanm 13:0645d8841f51 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
bogdanm 13:0645d8841f51 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
bogdanm 13:0645d8841f51 1258
bogdanm 13:0645d8841f51 1259 /*@} end of group CMSIS_FPU */
bogdanm 13:0645d8841f51 1260 #endif
bogdanm 13:0645d8841f51 1261
bogdanm 13:0645d8841f51 1262
bogdanm 13:0645d8841f51 1263 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 13:0645d8841f51 1265 \brief Type definitions for the Core Debug Registers
bogdanm 13:0645d8841f51 1266 @{
bogdanm 13:0645d8841f51 1267 */
bogdanm 13:0645d8841f51 1268
bogdanm 13:0645d8841f51 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 13:0645d8841f51 1270 */
bogdanm 13:0645d8841f51 1271 typedef struct
bogdanm 13:0645d8841f51 1272 {
bogdanm 13:0645d8841f51 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
bogdanm 13:0645d8841f51 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
bogdanm 13:0645d8841f51 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
bogdanm 13:0645d8841f51 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 13:0645d8841f51 1277 } CoreDebug_Type;
bogdanm 13:0645d8841f51 1278
bogdanm 13:0645d8841f51 1279 /* Debug Halting Control and Status Register */
bogdanm 13:0645d8841f51 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 13:0645d8841f51 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 13:0645d8841f51 1282
bogdanm 13:0645d8841f51 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 13:0645d8841f51 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 13:0645d8841f51 1285
bogdanm 13:0645d8841f51 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 13:0645d8841f51 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 13:0645d8841f51 1288
bogdanm 13:0645d8841f51 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 13:0645d8841f51 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 13:0645d8841f51 1291
bogdanm 13:0645d8841f51 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 13:0645d8841f51 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 13:0645d8841f51 1294
bogdanm 13:0645d8841f51 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 13:0645d8841f51 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 13:0645d8841f51 1297
bogdanm 13:0645d8841f51 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 13:0645d8841f51 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 13:0645d8841f51 1300
bogdanm 13:0645d8841f51 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 13:0645d8841f51 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 13:0645d8841f51 1303
bogdanm 13:0645d8841f51 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 13:0645d8841f51 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 13:0645d8841f51 1306
bogdanm 13:0645d8841f51 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 13:0645d8841f51 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 13:0645d8841f51 1309
bogdanm 13:0645d8841f51 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 13:0645d8841f51 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 13:0645d8841f51 1312
bogdanm 13:0645d8841f51 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
bogdanm 13:0645d8841f51 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 13:0645d8841f51 1315
bogdanm 13:0645d8841f51 1316 /* Debug Core Register Selector Register */
bogdanm 13:0645d8841f51 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 13:0645d8841f51 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 13:0645d8841f51 1319
bogdanm 13:0645d8841f51 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
bogdanm 13:0645d8841f51 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 13:0645d8841f51 1322
bogdanm 13:0645d8841f51 1323 /* Debug Exception and Monitor Control Register */
bogdanm 13:0645d8841f51 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 13:0645d8841f51 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 13:0645d8841f51 1326
bogdanm 13:0645d8841f51 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 13:0645d8841f51 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 13:0645d8841f51 1329
bogdanm 13:0645d8841f51 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 13:0645d8841f51 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 13:0645d8841f51 1332
bogdanm 13:0645d8841f51 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 13:0645d8841f51 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 13:0645d8841f51 1335
bogdanm 13:0645d8841f51 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 13:0645d8841f51 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 13:0645d8841f51 1338
bogdanm 13:0645d8841f51 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 13:0645d8841f51 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 13:0645d8841f51 1341
bogdanm 13:0645d8841f51 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 13:0645d8841f51 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 13:0645d8841f51 1344
bogdanm 13:0645d8841f51 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 13:0645d8841f51 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 13:0645d8841f51 1347
bogdanm 13:0645d8841f51 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 13:0645d8841f51 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 13:0645d8841f51 1350
bogdanm 13:0645d8841f51 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 13:0645d8841f51 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 13:0645d8841f51 1353
bogdanm 13:0645d8841f51 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 13:0645d8841f51 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 13:0645d8841f51 1356
bogdanm 13:0645d8841f51 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 13:0645d8841f51 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 13:0645d8841f51 1359
bogdanm 13:0645d8841f51 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
bogdanm 13:0645d8841f51 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 13:0645d8841f51 1362
bogdanm 13:0645d8841f51 1363 /*@} end of group CMSIS_CoreDebug */
bogdanm 13:0645d8841f51 1364
bogdanm 13:0645d8841f51 1365
bogdanm 13:0645d8841f51 1366 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 1367 \defgroup CMSIS_core_base Core Definitions
bogdanm 13:0645d8841f51 1368 \brief Definitions for base addresses, unions, and structures.
bogdanm 13:0645d8841f51 1369 @{
bogdanm 13:0645d8841f51 1370 */
bogdanm 13:0645d8841f51 1371
bogdanm 13:0645d8841f51 1372 /* Memory mapping of Cortex-M4 Hardware */
bogdanm 13:0645d8841f51 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 13:0645d8841f51 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
bogdanm 13:0645d8841f51 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
bogdanm 13:0645d8841f51 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
bogdanm 13:0645d8841f51 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
bogdanm 13:0645d8841f51 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 13:0645d8841f51 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 13:0645d8841f51 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 13:0645d8841f51 1381
bogdanm 13:0645d8841f51 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
bogdanm 13:0645d8841f51 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 13:0645d8841f51 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 13:0645d8841f51 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 13:0645d8841f51 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
bogdanm 13:0645d8841f51 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
bogdanm 13:0645d8841f51 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
bogdanm 13:0645d8841f51 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 13:0645d8841f51 1390
bogdanm 13:0645d8841f51 1391 #if (__MPU_PRESENT == 1)
bogdanm 13:0645d8841f51 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 13:0645d8841f51 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 13:0645d8841f51 1394 #endif
bogdanm 13:0645d8841f51 1395
bogdanm 13:0645d8841f51 1396 #if (__FPU_PRESENT == 1)
bogdanm 13:0645d8841f51 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
bogdanm 13:0645d8841f51 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
bogdanm 13:0645d8841f51 1399 #endif
bogdanm 13:0645d8841f51 1400
bogdanm 13:0645d8841f51 1401 /*@} */
bogdanm 13:0645d8841f51 1402
bogdanm 13:0645d8841f51 1403
bogdanm 13:0645d8841f51 1404
bogdanm 13:0645d8841f51 1405 /*******************************************************************************
bogdanm 13:0645d8841f51 1406 * Hardware Abstraction Layer
bogdanm 13:0645d8841f51 1407 Core Function Interface contains:
bogdanm 13:0645d8841f51 1408 - Core NVIC Functions
bogdanm 13:0645d8841f51 1409 - Core SysTick Functions
bogdanm 13:0645d8841f51 1410 - Core Debug Functions
bogdanm 13:0645d8841f51 1411 - Core Register Access Functions
bogdanm 13:0645d8841f51 1412 ******************************************************************************/
bogdanm 13:0645d8841f51 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 13:0645d8841f51 1414 */
bogdanm 13:0645d8841f51 1415
bogdanm 13:0645d8841f51 1416
bogdanm 13:0645d8841f51 1417
bogdanm 13:0645d8841f51 1418 /* ########################## NVIC functions #################################### */
bogdanm 13:0645d8841f51 1419 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 13:0645d8841f51 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 13:0645d8841f51 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 13:0645d8841f51 1422 @{
bogdanm 13:0645d8841f51 1423 */
bogdanm 13:0645d8841f51 1424
bogdanm 13:0645d8841f51 1425 /** \brief Set Priority Grouping
bogdanm 13:0645d8841f51 1426
bogdanm 13:0645d8841f51 1427 The function sets the priority grouping field using the required unlock sequence.
bogdanm 13:0645d8841f51 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm 13:0645d8841f51 1429 Only values from 0..7 are used.
bogdanm 13:0645d8841f51 1430 In case of a conflict between priority grouping and available
bogdanm 13:0645d8841f51 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 13:0645d8841f51 1432
bogdanm 13:0645d8841f51 1433 \param [in] PriorityGroup Priority grouping field.
bogdanm 13:0645d8841f51 1434 */
bogdanm 13:0645d8841f51 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 13:0645d8841f51 1436 {
bogdanm 13:0645d8841f51 1437 uint32_t reg_value;
bogdanm 13:0645d8841f51 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
bogdanm 13:0645d8841f51 1439
bogdanm 13:0645d8841f51 1440 reg_value = SCB->AIRCR; /* read old register configuration */
bogdanm 13:0645d8841f51 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
bogdanm 13:0645d8841f51 1442 reg_value = (reg_value |
bogdanm 13:0645d8841f51 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 13:0645d8841f51 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
bogdanm 13:0645d8841f51 1445 SCB->AIRCR = reg_value;
bogdanm 13:0645d8841f51 1446 }
bogdanm 13:0645d8841f51 1447
bogdanm 13:0645d8841f51 1448
bogdanm 13:0645d8841f51 1449 /** \brief Get Priority Grouping
bogdanm 13:0645d8841f51 1450
bogdanm 13:0645d8841f51 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm 13:0645d8841f51 1452
bogdanm 13:0645d8841f51 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 13:0645d8841f51 1454 */
bogdanm 13:0645d8841f51 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
bogdanm 13:0645d8841f51 1456 {
bogdanm 13:0645d8841f51 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
bogdanm 13:0645d8841f51 1458 }
bogdanm 13:0645d8841f51 1459
bogdanm 13:0645d8841f51 1460
bogdanm 13:0645d8841f51 1461 /** \brief Enable External Interrupt
bogdanm 13:0645d8841f51 1462
bogdanm 13:0645d8841f51 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 13:0645d8841f51 1464
bogdanm 13:0645d8841f51 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 1466 */
bogdanm 13:0645d8841f51 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1468 {
bogdanm 13:0645d8841f51 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
bogdanm 13:0645d8841f51 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
bogdanm 13:0645d8841f51 1471 }
bogdanm 13:0645d8841f51 1472
bogdanm 13:0645d8841f51 1473
bogdanm 13:0645d8841f51 1474 /** \brief Disable External Interrupt
bogdanm 13:0645d8841f51 1475
bogdanm 13:0645d8841f51 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 13:0645d8841f51 1477
bogdanm 13:0645d8841f51 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 1479 */
bogdanm 13:0645d8841f51 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1481 {
bogdanm 13:0645d8841f51 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
bogdanm 13:0645d8841f51 1483 }
bogdanm 13:0645d8841f51 1484
bogdanm 13:0645d8841f51 1485
bogdanm 13:0645d8841f51 1486 /** \brief Get Pending Interrupt
bogdanm 13:0645d8841f51 1487
bogdanm 13:0645d8841f51 1488 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 13:0645d8841f51 1489 for the specified interrupt.
bogdanm 13:0645d8841f51 1490
bogdanm 13:0645d8841f51 1491 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 1492
bogdanm 13:0645d8841f51 1493 \return 0 Interrupt status is not pending.
bogdanm 13:0645d8841f51 1494 \return 1 Interrupt status is pending.
bogdanm 13:0645d8841f51 1495 */
bogdanm 13:0645d8841f51 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1497 {
bogdanm 13:0645d8841f51 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
bogdanm 13:0645d8841f51 1499 }
bogdanm 13:0645d8841f51 1500
bogdanm 13:0645d8841f51 1501
bogdanm 13:0645d8841f51 1502 /** \brief Set Pending Interrupt
bogdanm 13:0645d8841f51 1503
bogdanm 13:0645d8841f51 1504 The function sets the pending bit of an external interrupt.
bogdanm 13:0645d8841f51 1505
bogdanm 13:0645d8841f51 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 1507 */
bogdanm 13:0645d8841f51 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1509 {
bogdanm 13:0645d8841f51 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
bogdanm 13:0645d8841f51 1511 }
bogdanm 13:0645d8841f51 1512
bogdanm 13:0645d8841f51 1513
bogdanm 13:0645d8841f51 1514 /** \brief Clear Pending Interrupt
bogdanm 13:0645d8841f51 1515
bogdanm 13:0645d8841f51 1516 The function clears the pending bit of an external interrupt.
bogdanm 13:0645d8841f51 1517
bogdanm 13:0645d8841f51 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 1519 */
bogdanm 13:0645d8841f51 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1521 {
bogdanm 13:0645d8841f51 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 13:0645d8841f51 1523 }
bogdanm 13:0645d8841f51 1524
bogdanm 13:0645d8841f51 1525
bogdanm 13:0645d8841f51 1526 /** \brief Get Active Interrupt
bogdanm 13:0645d8841f51 1527
bogdanm 13:0645d8841f51 1528 The function reads the active register in NVIC and returns the active bit.
bogdanm 13:0645d8841f51 1529
bogdanm 13:0645d8841f51 1530 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 1531
bogdanm 13:0645d8841f51 1532 \return 0 Interrupt status is not active.
bogdanm 13:0645d8841f51 1533 \return 1 Interrupt status is active.
bogdanm 13:0645d8841f51 1534 */
bogdanm 13:0645d8841f51 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1536 {
bogdanm 13:0645d8841f51 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
bogdanm 13:0645d8841f51 1538 }
bogdanm 13:0645d8841f51 1539
bogdanm 13:0645d8841f51 1540
bogdanm 13:0645d8841f51 1541 /** \brief Set Interrupt Priority
bogdanm 13:0645d8841f51 1542
bogdanm 13:0645d8841f51 1543 The function sets the priority of an interrupt.
bogdanm 13:0645d8841f51 1544
bogdanm 13:0645d8841f51 1545 \note The priority cannot be set for every core interrupt.
bogdanm 13:0645d8841f51 1546
bogdanm 13:0645d8841f51 1547 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 1548 \param [in] priority Priority to set.
bogdanm 13:0645d8841f51 1549 */
bogdanm 13:0645d8841f51 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 13:0645d8841f51 1551 {
bogdanm 13:0645d8841f51 1552 if(IRQn < 0) {
bogdanm 13:0645d8841f51 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
bogdanm 13:0645d8841f51 1554 else {
bogdanm 13:0645d8841f51 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
bogdanm 13:0645d8841f51 1556 }
bogdanm 13:0645d8841f51 1557
bogdanm 13:0645d8841f51 1558
bogdanm 13:0645d8841f51 1559 /** \brief Get Interrupt Priority
bogdanm 13:0645d8841f51 1560
bogdanm 13:0645d8841f51 1561 The function reads the priority of an interrupt. The interrupt
bogdanm 13:0645d8841f51 1562 number can be positive to specify an external (device specific)
bogdanm 13:0645d8841f51 1563 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 13:0645d8841f51 1564
bogdanm 13:0645d8841f51 1565
bogdanm 13:0645d8841f51 1566 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 13:0645d8841f51 1568 priority bits of the microcontroller.
bogdanm 13:0645d8841f51 1569 */
bogdanm 13:0645d8841f51 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 1571 {
bogdanm 13:0645d8841f51 1572
bogdanm 13:0645d8841f51 1573 if(IRQn < 0) {
bogdanm 13:0645d8841f51 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
bogdanm 13:0645d8841f51 1575 else {
bogdanm 13:0645d8841f51 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 13:0645d8841f51 1577 }
bogdanm 13:0645d8841f51 1578
bogdanm 13:0645d8841f51 1579
bogdanm 13:0645d8841f51 1580 /** \brief Encode Priority
bogdanm 13:0645d8841f51 1581
bogdanm 13:0645d8841f51 1582 The function encodes the priority for an interrupt with the given priority group,
bogdanm 13:0645d8841f51 1583 preemptive priority value, and subpriority value.
bogdanm 13:0645d8841f51 1584 In case of a conflict between priority grouping and available
bogdanm 13:0645d8841f51 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
bogdanm 13:0645d8841f51 1586
bogdanm 13:0645d8841f51 1587 \param [in] PriorityGroup Used priority group.
bogdanm 13:0645d8841f51 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm 13:0645d8841f51 1589 \param [in] SubPriority Subpriority value (starting from 0).
bogdanm 13:0645d8841f51 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 13:0645d8841f51 1591 */
bogdanm 13:0645d8841f51 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 13:0645d8841f51 1593 {
bogdanm 13:0645d8841f51 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 13:0645d8841f51 1595 uint32_t PreemptPriorityBits;
bogdanm 13:0645d8841f51 1596 uint32_t SubPriorityBits;
bogdanm 13:0645d8841f51 1597
bogdanm 13:0645d8841f51 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 13:0645d8841f51 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 13:0645d8841f51 1600
bogdanm 13:0645d8841f51 1601 return (
bogdanm 13:0645d8841f51 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
bogdanm 13:0645d8841f51 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
bogdanm 13:0645d8841f51 1604 );
bogdanm 13:0645d8841f51 1605 }
bogdanm 13:0645d8841f51 1606
bogdanm 13:0645d8841f51 1607
bogdanm 13:0645d8841f51 1608 /** \brief Decode Priority
bogdanm 13:0645d8841f51 1609
bogdanm 13:0645d8841f51 1610 The function decodes an interrupt priority value with a given priority group to
bogdanm 13:0645d8841f51 1611 preemptive priority value and subpriority value.
bogdanm 13:0645d8841f51 1612 In case of a conflict between priority grouping and available
bogdanm 13:0645d8841f51 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
bogdanm 13:0645d8841f51 1614
bogdanm 13:0645d8841f51 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm 13:0645d8841f51 1616 \param [in] PriorityGroup Used priority group.
bogdanm 13:0645d8841f51 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm 13:0645d8841f51 1618 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 13:0645d8841f51 1619 */
bogdanm 13:0645d8841f51 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm 13:0645d8841f51 1621 {
bogdanm 13:0645d8841f51 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 13:0645d8841f51 1623 uint32_t PreemptPriorityBits;
bogdanm 13:0645d8841f51 1624 uint32_t SubPriorityBits;
bogdanm 13:0645d8841f51 1625
bogdanm 13:0645d8841f51 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 13:0645d8841f51 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 13:0645d8841f51 1628
bogdanm 13:0645d8841f51 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
bogdanm 13:0645d8841f51 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
bogdanm 13:0645d8841f51 1631 }
bogdanm 13:0645d8841f51 1632
bogdanm 13:0645d8841f51 1633
bogdanm 13:0645d8841f51 1634 /** \brief System Reset
bogdanm 13:0645d8841f51 1635
bogdanm 13:0645d8841f51 1636 The function initiates a system reset request to reset the MCU.
bogdanm 13:0645d8841f51 1637 */
bogdanm 13:0645d8841f51 1638 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 13:0645d8841f51 1639 {
bogdanm 13:0645d8841f51 1640 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 13:0645d8841f51 1641 buffered write are completed before reset */
bogdanm 13:0645d8841f51 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 13:0645d8841f51 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
bogdanm 13:0645d8841f51 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
bogdanm 13:0645d8841f51 1645 __DSB(); /* Ensure completion of memory access */
bogdanm 13:0645d8841f51 1646 while(1); /* wait until reset */
bogdanm 13:0645d8841f51 1647 }
bogdanm 13:0645d8841f51 1648
bogdanm 13:0645d8841f51 1649 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 13:0645d8841f51 1650
bogdanm 13:0645d8841f51 1651
bogdanm 13:0645d8841f51 1652
bogdanm 13:0645d8841f51 1653 /* ################################## SysTick function ############################################ */
bogdanm 13:0645d8841f51 1654 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 13:0645d8841f51 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 13:0645d8841f51 1656 \brief Functions that configure the System.
bogdanm 13:0645d8841f51 1657 @{
bogdanm 13:0645d8841f51 1658 */
bogdanm 13:0645d8841f51 1659
bogdanm 13:0645d8841f51 1660 #if (__Vendor_SysTickConfig == 0)
bogdanm 13:0645d8841f51 1661
bogdanm 13:0645d8841f51 1662 /** \brief System Tick Configuration
bogdanm 13:0645d8841f51 1663
bogdanm 13:0645d8841f51 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 13:0645d8841f51 1665 Counter is in free running mode to generate periodic interrupts.
bogdanm 13:0645d8841f51 1666
bogdanm 13:0645d8841f51 1667 \param [in] ticks Number of ticks between two interrupts.
bogdanm 13:0645d8841f51 1668
bogdanm 13:0645d8841f51 1669 \return 0 Function succeeded.
bogdanm 13:0645d8841f51 1670 \return 1 Function failed.
bogdanm 13:0645d8841f51 1671
bogdanm 13:0645d8841f51 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 13:0645d8841f51 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 13:0645d8841f51 1674 must contain a vendor-specific implementation of this function.
bogdanm 13:0645d8841f51 1675
bogdanm 13:0645d8841f51 1676 */
bogdanm 13:0645d8841f51 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 13:0645d8841f51 1678 {
bogdanm 13:0645d8841f51 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 13:0645d8841f51 1680
bogdanm 13:0645d8841f51 1681 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 13:0645d8841f51 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 13:0645d8841f51 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 13:0645d8841f51 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 13:0645d8841f51 1685 SysTick_CTRL_TICKINT_Msk |
bogdanm 13:0645d8841f51 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 13:0645d8841f51 1687 return (0); /* Function successful */
bogdanm 13:0645d8841f51 1688 }
bogdanm 13:0645d8841f51 1689
bogdanm 13:0645d8841f51 1690 #endif
bogdanm 13:0645d8841f51 1691
bogdanm 13:0645d8841f51 1692 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 13:0645d8841f51 1693
bogdanm 13:0645d8841f51 1694
bogdanm 13:0645d8841f51 1695
bogdanm 13:0645d8841f51 1696 /* ##################################### Debug In/Output function ########################################### */
bogdanm 13:0645d8841f51 1697 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 13:0645d8841f51 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm 13:0645d8841f51 1699 \brief Functions that access the ITM debug interface.
bogdanm 13:0645d8841f51 1700 @{
bogdanm 13:0645d8841f51 1701 */
bogdanm 13:0645d8841f51 1702
bogdanm 13:0645d8841f51 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
bogdanm 13:0645d8841f51 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 13:0645d8841f51 1705
bogdanm 13:0645d8841f51 1706
bogdanm 13:0645d8841f51 1707 /** \brief ITM Send Character
bogdanm 13:0645d8841f51 1708
bogdanm 13:0645d8841f51 1709 The function transmits a character via the ITM channel 0, and
bogdanm 13:0645d8841f51 1710 \li Just returns when no debugger is connected that has booked the output.
bogdanm 13:0645d8841f51 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm 13:0645d8841f51 1712
bogdanm 13:0645d8841f51 1713 \param [in] ch Character to transmit.
bogdanm 13:0645d8841f51 1714
bogdanm 13:0645d8841f51 1715 \returns Character to transmit.
bogdanm 13:0645d8841f51 1716 */
bogdanm 13:0645d8841f51 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 13:0645d8841f51 1718 {
bogdanm 13:0645d8841f51 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
bogdanm 13:0645d8841f51 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
bogdanm 13:0645d8841f51 1721 {
bogdanm 13:0645d8841f51 1722 while (ITM->PORT[0].u32 == 0);
bogdanm 13:0645d8841f51 1723 ITM->PORT[0].u8 = (uint8_t) ch;
bogdanm 13:0645d8841f51 1724 }
bogdanm 13:0645d8841f51 1725 return (ch);
bogdanm 13:0645d8841f51 1726 }
bogdanm 13:0645d8841f51 1727
bogdanm 13:0645d8841f51 1728
bogdanm 13:0645d8841f51 1729 /** \brief ITM Receive Character
bogdanm 13:0645d8841f51 1730
bogdanm 13:0645d8841f51 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm 13:0645d8841f51 1732
bogdanm 13:0645d8841f51 1733 \return Received character.
bogdanm 13:0645d8841f51 1734 \return -1 No character pending.
bogdanm 13:0645d8841f51 1735 */
bogdanm 13:0645d8841f51 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm 13:0645d8841f51 1737 int32_t ch = -1; /* no character available */
bogdanm 13:0645d8841f51 1738
bogdanm 13:0645d8841f51 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm 13:0645d8841f51 1740 ch = ITM_RxBuffer;
bogdanm 13:0645d8841f51 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 13:0645d8841f51 1742 }
bogdanm 13:0645d8841f51 1743
bogdanm 13:0645d8841f51 1744 return (ch);
bogdanm 13:0645d8841f51 1745 }
bogdanm 13:0645d8841f51 1746
bogdanm 13:0645d8841f51 1747
bogdanm 13:0645d8841f51 1748 /** \brief ITM Check Character
bogdanm 13:0645d8841f51 1749
bogdanm 13:0645d8841f51 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm 13:0645d8841f51 1751
bogdanm 13:0645d8841f51 1752 \return 0 No character available.
bogdanm 13:0645d8841f51 1753 \return 1 Character available.
bogdanm 13:0645d8841f51 1754 */
bogdanm 13:0645d8841f51 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm 13:0645d8841f51 1756
bogdanm 13:0645d8841f51 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm 13:0645d8841f51 1758 return (0); /* no character available */
bogdanm 13:0645d8841f51 1759 } else {
bogdanm 13:0645d8841f51 1760 return (1); /* character available */
bogdanm 13:0645d8841f51 1761 }
bogdanm 13:0645d8841f51 1762 }
bogdanm 13:0645d8841f51 1763
bogdanm 13:0645d8841f51 1764 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 13:0645d8841f51 1765
bogdanm 13:0645d8841f51 1766 #endif /* __CORE_CM4_H_DEPENDANT */
bogdanm 13:0645d8841f51 1767
bogdanm 13:0645d8841f51 1768 #endif /* __CMSIS_GENERIC */
bogdanm 13:0645d8841f51 1769
bogdanm 13:0645d8841f51 1770 #ifdef __cplusplus
bogdanm 13:0645d8841f51 1771 }
bogdanm 13:0645d8841f51 1772 #endif