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mbed SDK library sources

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Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h@89:9655231f5786, 2014-02-11 (annotated)

Committer:
mbed_official
Date:
Tue Feb 11 15:00:06 2014 +0000
Revision:
89:9655231f5786
Parent:
13:0645d8841f51 
Synchronized with git revision 17499c34d273f02497e0706d3abc516b12f3fc62



Full URL: https://github.com/mbedmicro/mbed/commit/17499c34d273f02497e0706d3abc516b12f3fc62/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file LPC17xx.h
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
emilmont 10:3bc89ef62ce7 4 * NXP LPC17xx Device Series
emilmont 10:3bc89ef62ce7 5 * @version: V1.09
emilmont 10:3bc89ef62ce7 6 * @date: 17. March 2010
emilmont 10:3bc89ef62ce7 7
emilmont 10:3bc89ef62ce7 8 *
emilmont 10:3bc89ef62ce7 9 * @note
emilmont 10:3bc89ef62ce7 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 11 *
emilmont 10:3bc89ef62ce7 12 * @par
emilmont 10:3bc89ef62ce7 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 14 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 15 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 16 *
emilmont 10:3bc89ef62ce7 17 * @par
emilmont 10:3bc89ef62ce7 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 23 *
emilmont 10:3bc89ef62ce7 24 ******************************************************************************/
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 #ifndef __LPC17xx_H__
emilmont 10:3bc89ef62ce7 28 #define __LPC17xx_H__
emilmont 10:3bc89ef62ce7 29
emilmont 10:3bc89ef62ce7 30 /*
emilmont 10:3bc89ef62ce7 31 * ==========================================================================
emilmont 10:3bc89ef62ce7 32 * ---------- Interrupt Number Definition -----------------------------------
emilmont 10:3bc89ef62ce7 33 * ==========================================================================
emilmont 10:3bc89ef62ce7 34 */
emilmont 10:3bc89ef62ce7 35
emilmont 10:3bc89ef62ce7 36 typedef enum IRQn
emilmont 10:3bc89ef62ce7 37 {
emilmont 10:3bc89ef62ce7 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
emilmont 10:3bc89ef62ce7 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
emilmont 10:3bc89ef62ce7 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
emilmont 10:3bc89ef62ce7 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
emilmont 10:3bc89ef62ce7 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
emilmont 10:3bc89ef62ce7 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
emilmont 10:3bc89ef62ce7 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
emilmont 10:3bc89ef62ce7 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
emilmont 10:3bc89ef62ce7 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
emilmont 10:3bc89ef62ce7 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
emilmont 10:3bc89ef62ce7 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
emilmont 10:3bc89ef62ce7 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
emilmont 10:3bc89ef62ce7 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
emilmont 10:3bc89ef62ce7 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
emilmont 10:3bc89ef62ce7 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
emilmont 10:3bc89ef62ce7 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
emilmont 10:3bc89ef62ce7 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
emilmont 10:3bc89ef62ce7 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
emilmont 10:3bc89ef62ce7 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
emilmont 10:3bc89ef62ce7 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
emilmont 10:3bc89ef62ce7 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
emilmont 10:3bc89ef62ce7 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
emilmont 10:3bc89ef62ce7 62 SPI_IRQn = 13, /*!< SPI Interrupt */
emilmont 10:3bc89ef62ce7 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
emilmont 10:3bc89ef62ce7 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
emilmont 10:3bc89ef62ce7 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
emilmont 10:3bc89ef62ce7 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
emilmont 10:3bc89ef62ce7 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
emilmont 10:3bc89ef62ce7 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
emilmont 10:3bc89ef62ce7 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
emilmont 10:3bc89ef62ce7 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
emilmont 10:3bc89ef62ce7 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
emilmont 10:3bc89ef62ce7 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
emilmont 10:3bc89ef62ce7 73 USB_IRQn = 24, /*!< USB Interrupt */
emilmont 10:3bc89ef62ce7 74 CAN_IRQn = 25, /*!< CAN Interrupt */
emilmont 10:3bc89ef62ce7 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
emilmont 10:3bc89ef62ce7 76 I2S_IRQn = 27, /*!< I2S Interrupt */
emilmont 10:3bc89ef62ce7 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
emilmont 10:3bc89ef62ce7 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
emilmont 10:3bc89ef62ce7 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
emilmont 10:3bc89ef62ce7 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
emilmont 10:3bc89ef62ce7 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
emilmont 10:3bc89ef62ce7 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
emilmont 10:3bc89ef62ce7 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
emilmont 10:3bc89ef62ce7 84 } IRQn_Type;
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86
emilmont 10:3bc89ef62ce7 87 /*
emilmont 10:3bc89ef62ce7 88 * ==========================================================================
emilmont 10:3bc89ef62ce7 89 * ----------- Processor and Core Peripheral Section ------------------------
emilmont 10:3bc89ef62ce7 90 * ==========================================================================
emilmont 10:3bc89ef62ce7 91 */
emilmont 10:3bc89ef62ce7 92
emilmont 10:3bc89ef62ce7 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
emilmont 10:3bc89ef62ce7 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
emilmont 10:3bc89ef62ce7 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
emilmont 10:3bc89ef62ce7 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 10:3bc89ef62ce7 97
emilmont 10:3bc89ef62ce7 98
emilmont 10:3bc89ef62ce7 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
emilmont 10:3bc89ef62ce7 100 #include "system_LPC17xx.h" /* System Header */
emilmont 10:3bc89ef62ce7 101
emilmont 10:3bc89ef62ce7 102
emilmont 10:3bc89ef62ce7 103 /******************************************************************************/
emilmont 10:3bc89ef62ce7 104 /* Device Specific Peripheral registers structures */
emilmont 10:3bc89ef62ce7 105 /******************************************************************************/
emilmont 10:3bc89ef62ce7 106
emilmont 10:3bc89ef62ce7 107 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 108 #pragma anon_unions
emilmont 10:3bc89ef62ce7 109 #endif
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 /*------------- System Control (SC) ------------------------------------------*/
emilmont 10:3bc89ef62ce7 112 typedef struct
emilmont 10:3bc89ef62ce7 113 {
emilmont 10:3bc89ef62ce7 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
emilmont 10:3bc89ef62ce7 115 uint32_t RESERVED0[31];
emilmont 10:3bc89ef62ce7 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
emilmont 10:3bc89ef62ce7 117 __IO uint32_t PLL0CFG;
emilmont 10:3bc89ef62ce7 118 __I uint32_t PLL0STAT;
emilmont 10:3bc89ef62ce7 119 __O uint32_t PLL0FEED;
emilmont 10:3bc89ef62ce7 120 uint32_t RESERVED1[4];
emilmont 10:3bc89ef62ce7 121 __IO uint32_t PLL1CON;
emilmont 10:3bc89ef62ce7 122 __IO uint32_t PLL1CFG;
emilmont 10:3bc89ef62ce7 123 __I uint32_t PLL1STAT;
emilmont 10:3bc89ef62ce7 124 __O uint32_t PLL1FEED;
emilmont 10:3bc89ef62ce7 125 uint32_t RESERVED2[4];
emilmont 10:3bc89ef62ce7 126 __IO uint32_t PCON;
emilmont 10:3bc89ef62ce7 127 __IO uint32_t PCONP;
emilmont 10:3bc89ef62ce7 128 uint32_t RESERVED3[15];
emilmont 10:3bc89ef62ce7 129 __IO uint32_t CCLKCFG;
emilmont 10:3bc89ef62ce7 130 __IO uint32_t USBCLKCFG;
emilmont 10:3bc89ef62ce7 131 __IO uint32_t CLKSRCSEL;
emilmont 10:3bc89ef62ce7 132 __IO uint32_t CANSLEEPCLR;
emilmont 10:3bc89ef62ce7 133 __IO uint32_t CANWAKEFLAGS;
emilmont 10:3bc89ef62ce7 134 uint32_t RESERVED4[10];
emilmont 10:3bc89ef62ce7 135 __IO uint32_t EXTINT; /* External Interrupts */
emilmont 10:3bc89ef62ce7 136 uint32_t RESERVED5;
emilmont 10:3bc89ef62ce7 137 __IO uint32_t EXTMODE;
emilmont 10:3bc89ef62ce7 138 __IO uint32_t EXTPOLAR;
emilmont 10:3bc89ef62ce7 139 uint32_t RESERVED6[12];
emilmont 10:3bc89ef62ce7 140 __IO uint32_t RSID; /* Reset */
emilmont 10:3bc89ef62ce7 141 uint32_t RESERVED7[7];
emilmont 10:3bc89ef62ce7 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
emilmont 10:3bc89ef62ce7 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
emilmont 10:3bc89ef62ce7 144 __IO uint32_t PCLKSEL0;
emilmont 10:3bc89ef62ce7 145 __IO uint32_t PCLKSEL1;
emilmont 10:3bc89ef62ce7 146 uint32_t RESERVED8[4];
emilmont 10:3bc89ef62ce7 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
emilmont 10:3bc89ef62ce7 148 __IO uint32_t DMAREQSEL;
emilmont 10:3bc89ef62ce7 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
emilmont 10:3bc89ef62ce7 150 } LPC_SC_TypeDef;
emilmont 10:3bc89ef62ce7 151
emilmont 10:3bc89ef62ce7 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
emilmont 10:3bc89ef62ce7 153 typedef struct
emilmont 10:3bc89ef62ce7 154 {
emilmont 10:3bc89ef62ce7 155 __IO uint32_t PINSEL0;
emilmont 10:3bc89ef62ce7 156 __IO uint32_t PINSEL1;
emilmont 10:3bc89ef62ce7 157 __IO uint32_t PINSEL2;
emilmont 10:3bc89ef62ce7 158 __IO uint32_t PINSEL3;
emilmont 10:3bc89ef62ce7 159 __IO uint32_t PINSEL4;
emilmont 10:3bc89ef62ce7 160 __IO uint32_t PINSEL5;
emilmont 10:3bc89ef62ce7 161 __IO uint32_t PINSEL6;
emilmont 10:3bc89ef62ce7 162 __IO uint32_t PINSEL7;
emilmont 10:3bc89ef62ce7 163 __IO uint32_t PINSEL8;
emilmont 10:3bc89ef62ce7 164 __IO uint32_t PINSEL9;
emilmont 10:3bc89ef62ce7 165 __IO uint32_t PINSEL10;
emilmont 10:3bc89ef62ce7 166 uint32_t RESERVED0[5];
emilmont 10:3bc89ef62ce7 167 __IO uint32_t PINMODE0;
emilmont 10:3bc89ef62ce7 168 __IO uint32_t PINMODE1;
emilmont 10:3bc89ef62ce7 169 __IO uint32_t PINMODE2;
emilmont 10:3bc89ef62ce7 170 __IO uint32_t PINMODE3;
emilmont 10:3bc89ef62ce7 171 __IO uint32_t PINMODE4;
emilmont 10:3bc89ef62ce7 172 __IO uint32_t PINMODE5;
emilmont 10:3bc89ef62ce7 173 __IO uint32_t PINMODE6;
emilmont 10:3bc89ef62ce7 174 __IO uint32_t PINMODE7;
emilmont 10:3bc89ef62ce7 175 __IO uint32_t PINMODE8;
emilmont 10:3bc89ef62ce7 176 __IO uint32_t PINMODE9;
emilmont 10:3bc89ef62ce7 177 __IO uint32_t PINMODE_OD0;
emilmont 10:3bc89ef62ce7 178 __IO uint32_t PINMODE_OD1;
emilmont 10:3bc89ef62ce7 179 __IO uint32_t PINMODE_OD2;
emilmont 10:3bc89ef62ce7 180 __IO uint32_t PINMODE_OD3;
emilmont 10:3bc89ef62ce7 181 __IO uint32_t PINMODE_OD4;
emilmont 10:3bc89ef62ce7 182 __IO uint32_t I2CPADCFG;
emilmont 10:3bc89ef62ce7 183 } LPC_PINCON_TypeDef;
emilmont 10:3bc89ef62ce7 184
emilmont 10:3bc89ef62ce7 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
emilmont 10:3bc89ef62ce7 186 typedef struct
emilmont 10:3bc89ef62ce7 187 {
emilmont 10:3bc89ef62ce7 188 union {
emilmont 10:3bc89ef62ce7 189 __IO uint32_t FIODIR;
emilmont 10:3bc89ef62ce7 190 struct {
emilmont 10:3bc89ef62ce7 191 __IO uint16_t FIODIRL;
emilmont 10:3bc89ef62ce7 192 __IO uint16_t FIODIRH;
emilmont 10:3bc89ef62ce7 193 };
emilmont 10:3bc89ef62ce7 194 struct {
emilmont 10:3bc89ef62ce7 195 __IO uint8_t FIODIR0;
emilmont 10:3bc89ef62ce7 196 __IO uint8_t FIODIR1;
emilmont 10:3bc89ef62ce7 197 __IO uint8_t FIODIR2;
emilmont 10:3bc89ef62ce7 198 __IO uint8_t FIODIR3;
emilmont 10:3bc89ef62ce7 199 };
emilmont 10:3bc89ef62ce7 200 };
emilmont 10:3bc89ef62ce7 201 uint32_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 202 union {
emilmont 10:3bc89ef62ce7 203 __IO uint32_t FIOMASK;
emilmont 10:3bc89ef62ce7 204 struct {
emilmont 10:3bc89ef62ce7 205 __IO uint16_t FIOMASKL;
emilmont 10:3bc89ef62ce7 206 __IO uint16_t FIOMASKH;
emilmont 10:3bc89ef62ce7 207 };
emilmont 10:3bc89ef62ce7 208 struct {
emilmont 10:3bc89ef62ce7 209 __IO uint8_t FIOMASK0;
emilmont 10:3bc89ef62ce7 210 __IO uint8_t FIOMASK1;
emilmont 10:3bc89ef62ce7 211 __IO uint8_t FIOMASK2;
emilmont 10:3bc89ef62ce7 212 __IO uint8_t FIOMASK3;
emilmont 10:3bc89ef62ce7 213 };
emilmont 10:3bc89ef62ce7 214 };
emilmont 10:3bc89ef62ce7 215 union {
emilmont 10:3bc89ef62ce7 216 __IO uint32_t FIOPIN;
emilmont 10:3bc89ef62ce7 217 struct {
emilmont 10:3bc89ef62ce7 218 __IO uint16_t FIOPINL;
emilmont 10:3bc89ef62ce7 219 __IO uint16_t FIOPINH;
emilmont 10:3bc89ef62ce7 220 };
emilmont 10:3bc89ef62ce7 221 struct {
emilmont 10:3bc89ef62ce7 222 __IO uint8_t FIOPIN0;
emilmont 10:3bc89ef62ce7 223 __IO uint8_t FIOPIN1;
emilmont 10:3bc89ef62ce7 224 __IO uint8_t FIOPIN2;
emilmont 10:3bc89ef62ce7 225 __IO uint8_t FIOPIN3;
emilmont 10:3bc89ef62ce7 226 };
emilmont 10:3bc89ef62ce7 227 };
emilmont 10:3bc89ef62ce7 228 union {
emilmont 10:3bc89ef62ce7 229 __IO uint32_t FIOSET;
emilmont 10:3bc89ef62ce7 230 struct {
emilmont 10:3bc89ef62ce7 231 __IO uint16_t FIOSETL;
emilmont 10:3bc89ef62ce7 232 __IO uint16_t FIOSETH;
emilmont 10:3bc89ef62ce7 233 };
emilmont 10:3bc89ef62ce7 234 struct {
emilmont 10:3bc89ef62ce7 235 __IO uint8_t FIOSET0;
emilmont 10:3bc89ef62ce7 236 __IO uint8_t FIOSET1;
emilmont 10:3bc89ef62ce7 237 __IO uint8_t FIOSET2;
emilmont 10:3bc89ef62ce7 238 __IO uint8_t FIOSET3;
emilmont 10:3bc89ef62ce7 239 };
emilmont 10:3bc89ef62ce7 240 };
emilmont 10:3bc89ef62ce7 241 union {
emilmont 10:3bc89ef62ce7 242 __O uint32_t FIOCLR;
emilmont 10:3bc89ef62ce7 243 struct {
emilmont 10:3bc89ef62ce7 244 __O uint16_t FIOCLRL;
emilmont 10:3bc89ef62ce7 245 __O uint16_t FIOCLRH;
emilmont 10:3bc89ef62ce7 246 };
emilmont 10:3bc89ef62ce7 247 struct {
emilmont 10:3bc89ef62ce7 248 __O uint8_t FIOCLR0;
emilmont 10:3bc89ef62ce7 249 __O uint8_t FIOCLR1;
emilmont 10:3bc89ef62ce7 250 __O uint8_t FIOCLR2;
emilmont 10:3bc89ef62ce7 251 __O uint8_t FIOCLR3;
emilmont 10:3bc89ef62ce7 252 };
emilmont 10:3bc89ef62ce7 253 };
emilmont 10:3bc89ef62ce7 254 } LPC_GPIO_TypeDef;
emilmont 10:3bc89ef62ce7 255
emilmont 10:3bc89ef62ce7 256 typedef struct
emilmont 10:3bc89ef62ce7 257 {
emilmont 10:3bc89ef62ce7 258 __I uint32_t IntStatus;
emilmont 10:3bc89ef62ce7 259 __I uint32_t IO0IntStatR;
emilmont 10:3bc89ef62ce7 260 __I uint32_t IO0IntStatF;
emilmont 10:3bc89ef62ce7 261 __O uint32_t IO0IntClr;
emilmont 10:3bc89ef62ce7 262 __IO uint32_t IO0IntEnR;
emilmont 10:3bc89ef62ce7 263 __IO uint32_t IO0IntEnF;
emilmont 10:3bc89ef62ce7 264 uint32_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 265 __I uint32_t IO2IntStatR;
emilmont 10:3bc89ef62ce7 266 __I uint32_t IO2IntStatF;
emilmont 10:3bc89ef62ce7 267 __O uint32_t IO2IntClr;
emilmont 10:3bc89ef62ce7 268 __IO uint32_t IO2IntEnR;
emilmont 10:3bc89ef62ce7 269 __IO uint32_t IO2IntEnF;
emilmont 10:3bc89ef62ce7 270 } LPC_GPIOINT_TypeDef;
emilmont 10:3bc89ef62ce7 271
emilmont 10:3bc89ef62ce7 272 /*------------- Timer (TIM) --------------------------------------------------*/
emilmont 10:3bc89ef62ce7 273 typedef struct
emilmont 10:3bc89ef62ce7 274 {
emilmont 10:3bc89ef62ce7 275 __IO uint32_t IR;
emilmont 10:3bc89ef62ce7 276 __IO uint32_t TCR;
emilmont 10:3bc89ef62ce7 277 __IO uint32_t TC;
emilmont 10:3bc89ef62ce7 278 __IO uint32_t PR;
emilmont 10:3bc89ef62ce7 279 __IO uint32_t PC;
emilmont 10:3bc89ef62ce7 280 __IO uint32_t MCR;
emilmont 10:3bc89ef62ce7 281 __IO uint32_t MR0;
emilmont 10:3bc89ef62ce7 282 __IO uint32_t MR1;
emilmont 10:3bc89ef62ce7 283 __IO uint32_t MR2;
emilmont 10:3bc89ef62ce7 284 __IO uint32_t MR3;
emilmont 10:3bc89ef62ce7 285 __IO uint32_t CCR;
emilmont 10:3bc89ef62ce7 286 __I uint32_t CR0;
emilmont 10:3bc89ef62ce7 287 __I uint32_t CR1;
emilmont 10:3bc89ef62ce7 288 uint32_t RESERVED0[2];
emilmont 10:3bc89ef62ce7 289 __IO uint32_t EMR;
emilmont 10:3bc89ef62ce7 290 uint32_t RESERVED1[12];
emilmont 10:3bc89ef62ce7 291 __IO uint32_t CTCR;
emilmont 10:3bc89ef62ce7 292 } LPC_TIM_TypeDef;
emilmont 10:3bc89ef62ce7 293
emilmont 10:3bc89ef62ce7 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
emilmont 10:3bc89ef62ce7 295 typedef struct
emilmont 10:3bc89ef62ce7 296 {
emilmont 10:3bc89ef62ce7 297 __IO uint32_t IR;
emilmont 10:3bc89ef62ce7 298 __IO uint32_t TCR;
emilmont 10:3bc89ef62ce7 299 __IO uint32_t TC;
emilmont 10:3bc89ef62ce7 300 __IO uint32_t PR;
emilmont 10:3bc89ef62ce7 301 __IO uint32_t PC;
emilmont 10:3bc89ef62ce7 302 __IO uint32_t MCR;
emilmont 10:3bc89ef62ce7 303 __IO uint32_t MR0;
emilmont 10:3bc89ef62ce7 304 __IO uint32_t MR1;
emilmont 10:3bc89ef62ce7 305 __IO uint32_t MR2;
emilmont 10:3bc89ef62ce7 306 __IO uint32_t MR3;
emilmont 10:3bc89ef62ce7 307 __IO uint32_t CCR;
emilmont 10:3bc89ef62ce7 308 __I uint32_t CR0;
emilmont 10:3bc89ef62ce7 309 __I uint32_t CR1;
emilmont 10:3bc89ef62ce7 310 __I uint32_t CR2;
emilmont 10:3bc89ef62ce7 311 __I uint32_t CR3;
emilmont 10:3bc89ef62ce7 312 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 313 __IO uint32_t MR4;
emilmont 10:3bc89ef62ce7 314 __IO uint32_t MR5;
emilmont 10:3bc89ef62ce7 315 __IO uint32_t MR6;
emilmont 10:3bc89ef62ce7 316 __IO uint32_t PCR;
emilmont 10:3bc89ef62ce7 317 __IO uint32_t LER;
emilmont 10:3bc89ef62ce7 318 uint32_t RESERVED1[7];
emilmont 10:3bc89ef62ce7 319 __IO uint32_t CTCR;
emilmont 10:3bc89ef62ce7 320 } LPC_PWM_TypeDef;
emilmont 10:3bc89ef62ce7 321
emilmont 10:3bc89ef62ce7 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
emilmont 10:3bc89ef62ce7 323 typedef struct
emilmont 10:3bc89ef62ce7 324 {
emilmont 10:3bc89ef62ce7 325 union {
emilmont 10:3bc89ef62ce7 326 __I uint8_t RBR;
emilmont 10:3bc89ef62ce7 327 __O uint8_t THR;
emilmont 10:3bc89ef62ce7 328 __IO uint8_t DLL;
emilmont 10:3bc89ef62ce7 329 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 330 };
emilmont 10:3bc89ef62ce7 331 union {
emilmont 10:3bc89ef62ce7 332 __IO uint8_t DLM;
emilmont 10:3bc89ef62ce7 333 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 334 };
emilmont 10:3bc89ef62ce7 335 union {
emilmont 10:3bc89ef62ce7 336 __I uint32_t IIR;
emilmont 10:3bc89ef62ce7 337 __O uint8_t FCR;
emilmont 10:3bc89ef62ce7 338 };
emilmont 10:3bc89ef62ce7 339 __IO uint8_t LCR;
emilmont 10:3bc89ef62ce7 340 uint8_t RESERVED1[7];
emilmont 10:3bc89ef62ce7 341 __I uint8_t LSR;
emilmont 10:3bc89ef62ce7 342 uint8_t RESERVED2[7];
emilmont 10:3bc89ef62ce7 343 __IO uint8_t SCR;
emilmont 10:3bc89ef62ce7 344 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 345 __IO uint32_t ACR;
emilmont 10:3bc89ef62ce7 346 __IO uint8_t ICR;
emilmont 10:3bc89ef62ce7 347 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 348 __IO uint8_t FDR;
emilmont 10:3bc89ef62ce7 349 uint8_t RESERVED5[7];
emilmont 10:3bc89ef62ce7 350 __IO uint8_t TER;
emilmont 10:3bc89ef62ce7 351 uint8_t RESERVED6[39];
emilmont 10:3bc89ef62ce7 352 __IO uint32_t FIFOLVL;
emilmont 10:3bc89ef62ce7 353 } LPC_UART_TypeDef;
emilmont 10:3bc89ef62ce7 354
emilmont 10:3bc89ef62ce7 355 typedef struct
emilmont 10:3bc89ef62ce7 356 {
emilmont 10:3bc89ef62ce7 357 union {
emilmont 10:3bc89ef62ce7 358 __I uint8_t RBR;
emilmont 10:3bc89ef62ce7 359 __O uint8_t THR;
emilmont 10:3bc89ef62ce7 360 __IO uint8_t DLL;
emilmont 10:3bc89ef62ce7 361 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 362 };
emilmont 10:3bc89ef62ce7 363 union {
emilmont 10:3bc89ef62ce7 364 __IO uint8_t DLM;
emilmont 10:3bc89ef62ce7 365 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 366 };
emilmont 10:3bc89ef62ce7 367 union {
emilmont 10:3bc89ef62ce7 368 __I uint32_t IIR;
emilmont 10:3bc89ef62ce7 369 __O uint8_t FCR;
emilmont 10:3bc89ef62ce7 370 };
emilmont 10:3bc89ef62ce7 371 __IO uint8_t LCR;
emilmont 10:3bc89ef62ce7 372 uint8_t RESERVED1[7];
emilmont 10:3bc89ef62ce7 373 __I uint8_t LSR;
emilmont 10:3bc89ef62ce7 374 uint8_t RESERVED2[7];
emilmont 10:3bc89ef62ce7 375 __IO uint8_t SCR;
emilmont 10:3bc89ef62ce7 376 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 377 __IO uint32_t ACR;
emilmont 10:3bc89ef62ce7 378 __IO uint8_t ICR;
emilmont 10:3bc89ef62ce7 379 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 380 __IO uint8_t FDR;
emilmont 10:3bc89ef62ce7 381 uint8_t RESERVED5[7];
emilmont 10:3bc89ef62ce7 382 __IO uint8_t TER;
emilmont 10:3bc89ef62ce7 383 uint8_t RESERVED6[39];
emilmont 10:3bc89ef62ce7 384 __IO uint32_t FIFOLVL;
emilmont 10:3bc89ef62ce7 385 } LPC_UART0_TypeDef;
emilmont 10:3bc89ef62ce7 386
emilmont 10:3bc89ef62ce7 387 typedef struct
emilmont 10:3bc89ef62ce7 388 {
emilmont 10:3bc89ef62ce7 389 union {
emilmont 10:3bc89ef62ce7 390 __I uint8_t RBR;
emilmont 10:3bc89ef62ce7 391 __O uint8_t THR;
emilmont 10:3bc89ef62ce7 392 __IO uint8_t DLL;
emilmont 10:3bc89ef62ce7 393 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 394 };
emilmont 10:3bc89ef62ce7 395 union {
emilmont 10:3bc89ef62ce7 396 __IO uint8_t DLM;
emilmont 10:3bc89ef62ce7 397 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 398 };
emilmont 10:3bc89ef62ce7 399 union {
emilmont 10:3bc89ef62ce7 400 __I uint32_t IIR;
emilmont 10:3bc89ef62ce7 401 __O uint8_t FCR;
emilmont 10:3bc89ef62ce7 402 };
emilmont 10:3bc89ef62ce7 403 __IO uint8_t LCR;
emilmont 10:3bc89ef62ce7 404 uint8_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 405 __IO uint8_t MCR;
emilmont 10:3bc89ef62ce7 406 uint8_t RESERVED2[3];
emilmont 10:3bc89ef62ce7 407 __I uint8_t LSR;
emilmont 10:3bc89ef62ce7 408 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 409 __I uint8_t MSR;
emilmont 10:3bc89ef62ce7 410 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 411 __IO uint8_t SCR;
emilmont 10:3bc89ef62ce7 412 uint8_t RESERVED5[3];
emilmont 10:3bc89ef62ce7 413 __IO uint32_t ACR;
emilmont 10:3bc89ef62ce7 414 uint32_t RESERVED6;
emilmont 10:3bc89ef62ce7 415 __IO uint32_t FDR;
emilmont 10:3bc89ef62ce7 416 uint32_t RESERVED7;
emilmont 10:3bc89ef62ce7 417 __IO uint8_t TER;
emilmont 10:3bc89ef62ce7 418 uint8_t RESERVED8[27];
emilmont 10:3bc89ef62ce7 419 __IO uint8_t RS485CTRL;
emilmont 10:3bc89ef62ce7 420 uint8_t RESERVED9[3];
emilmont 10:3bc89ef62ce7 421 __IO uint8_t ADRMATCH;
emilmont 10:3bc89ef62ce7 422 uint8_t RESERVED10[3];
emilmont 10:3bc89ef62ce7 423 __IO uint8_t RS485DLY;
emilmont 10:3bc89ef62ce7 424 uint8_t RESERVED11[3];
emilmont 10:3bc89ef62ce7 425 __IO uint32_t FIFOLVL;
emilmont 10:3bc89ef62ce7 426 } LPC_UART1_TypeDef;
emilmont 10:3bc89ef62ce7 427
emilmont 10:3bc89ef62ce7 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
emilmont 10:3bc89ef62ce7 429 typedef struct
emilmont 10:3bc89ef62ce7 430 {
emilmont 10:3bc89ef62ce7 431 __IO uint32_t SPCR;
emilmont 10:3bc89ef62ce7 432 __I uint32_t SPSR;
emilmont 10:3bc89ef62ce7 433 __IO uint32_t SPDR;
emilmont 10:3bc89ef62ce7 434 __IO uint32_t SPCCR;
emilmont 10:3bc89ef62ce7 435 uint32_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 436 __IO uint32_t SPINT;
emilmont 10:3bc89ef62ce7 437 } LPC_SPI_TypeDef;
emilmont 10:3bc89ef62ce7 438
emilmont 10:3bc89ef62ce7 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
emilmont 10:3bc89ef62ce7 440 typedef struct
emilmont 10:3bc89ef62ce7 441 {
emilmont 10:3bc89ef62ce7 442 __IO uint32_t CR0;
emilmont 10:3bc89ef62ce7 443 __IO uint32_t CR1;
emilmont 10:3bc89ef62ce7 444 __IO uint32_t DR;
emilmont 10:3bc89ef62ce7 445 __I uint32_t SR;
emilmont 10:3bc89ef62ce7 446 __IO uint32_t CPSR;
emilmont 10:3bc89ef62ce7 447 __IO uint32_t IMSC;
emilmont 10:3bc89ef62ce7 448 __IO uint32_t RIS;
emilmont 10:3bc89ef62ce7 449 __IO uint32_t MIS;
emilmont 10:3bc89ef62ce7 450 __IO uint32_t ICR;
emilmont 10:3bc89ef62ce7 451 __IO uint32_t DMACR;
emilmont 10:3bc89ef62ce7 452 } LPC_SSP_TypeDef;
emilmont 10:3bc89ef62ce7 453
emilmont 10:3bc89ef62ce7 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
emilmont 10:3bc89ef62ce7 455 typedef struct
emilmont 10:3bc89ef62ce7 456 {
emilmont 10:3bc89ef62ce7 457 __IO uint32_t I2CONSET;
emilmont 10:3bc89ef62ce7 458 __I uint32_t I2STAT;
emilmont 10:3bc89ef62ce7 459 __IO uint32_t I2DAT;
emilmont 10:3bc89ef62ce7 460 __IO uint32_t I2ADR0;
emilmont 10:3bc89ef62ce7 461 __IO uint32_t I2SCLH;
emilmont 10:3bc89ef62ce7 462 __IO uint32_t I2SCLL;
emilmont 10:3bc89ef62ce7 463 __O uint32_t I2CONCLR;
emilmont 10:3bc89ef62ce7 464 __IO uint32_t MMCTRL;
emilmont 10:3bc89ef62ce7 465 __IO uint32_t I2ADR1;
emilmont 10:3bc89ef62ce7 466 __IO uint32_t I2ADR2;
emilmont 10:3bc89ef62ce7 467 __IO uint32_t I2ADR3;
emilmont 10:3bc89ef62ce7 468 __I uint32_t I2DATA_BUFFER;
emilmont 10:3bc89ef62ce7 469 __IO uint32_t I2MASK0;
emilmont 10:3bc89ef62ce7 470 __IO uint32_t I2MASK1;
emilmont 10:3bc89ef62ce7 471 __IO uint32_t I2MASK2;
emilmont 10:3bc89ef62ce7 472 __IO uint32_t I2MASK3;
emilmont 10:3bc89ef62ce7 473 } LPC_I2C_TypeDef;
emilmont 10:3bc89ef62ce7 474
emilmont 10:3bc89ef62ce7 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
emilmont 10:3bc89ef62ce7 476 typedef struct
emilmont 10:3bc89ef62ce7 477 {
emilmont 10:3bc89ef62ce7 478 __IO uint32_t I2SDAO;
emilmont 10:3bc89ef62ce7 479 __IO uint32_t I2SDAI;
emilmont 10:3bc89ef62ce7 480 __O uint32_t I2STXFIFO;
emilmont 10:3bc89ef62ce7 481 __I uint32_t I2SRXFIFO;
emilmont 10:3bc89ef62ce7 482 __I uint32_t I2SSTATE;
emilmont 10:3bc89ef62ce7 483 __IO uint32_t I2SDMA1;
emilmont 10:3bc89ef62ce7 484 __IO uint32_t I2SDMA2;
emilmont 10:3bc89ef62ce7 485 __IO uint32_t I2SIRQ;
emilmont 10:3bc89ef62ce7 486 __IO uint32_t I2STXRATE;
emilmont 10:3bc89ef62ce7 487 __IO uint32_t I2SRXRATE;
emilmont 10:3bc89ef62ce7 488 __IO uint32_t I2STXBITRATE;
emilmont 10:3bc89ef62ce7 489 __IO uint32_t I2SRXBITRATE;
emilmont 10:3bc89ef62ce7 490 __IO uint32_t I2STXMODE;
emilmont 10:3bc89ef62ce7 491 __IO uint32_t I2SRXMODE;
emilmont 10:3bc89ef62ce7 492 } LPC_I2S_TypeDef;
emilmont 10:3bc89ef62ce7 493
emilmont 10:3bc89ef62ce7 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
emilmont 10:3bc89ef62ce7 495 typedef struct
emilmont 10:3bc89ef62ce7 496 {
emilmont 10:3bc89ef62ce7 497 __IO uint32_t RICOMPVAL;
emilmont 10:3bc89ef62ce7 498 __IO uint32_t RIMASK;
emilmont 10:3bc89ef62ce7 499 __IO uint8_t RICTRL;
emilmont 10:3bc89ef62ce7 500 uint8_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 501 __IO uint32_t RICOUNTER;
emilmont 10:3bc89ef62ce7 502 } LPC_RIT_TypeDef;
emilmont 10:3bc89ef62ce7 503
emilmont 10:3bc89ef62ce7 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
emilmont 10:3bc89ef62ce7 505 typedef struct
emilmont 10:3bc89ef62ce7 506 {
emilmont 10:3bc89ef62ce7 507 __IO uint8_t ILR;
emilmont 10:3bc89ef62ce7 508 uint8_t RESERVED0[7];
emilmont 10:3bc89ef62ce7 509 __IO uint8_t CCR;
emilmont 10:3bc89ef62ce7 510 uint8_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 511 __IO uint8_t CIIR;
emilmont 10:3bc89ef62ce7 512 uint8_t RESERVED2[3];
emilmont 10:3bc89ef62ce7 513 __IO uint8_t AMR;
emilmont 10:3bc89ef62ce7 514 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 515 __I uint32_t CTIME0;
emilmont 10:3bc89ef62ce7 516 __I uint32_t CTIME1;
emilmont 10:3bc89ef62ce7 517 __I uint32_t CTIME2;
emilmont 10:3bc89ef62ce7 518 __IO uint8_t SEC;
emilmont 10:3bc89ef62ce7 519 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 520 __IO uint8_t MIN;
emilmont 10:3bc89ef62ce7 521 uint8_t RESERVED5[3];
emilmont 10:3bc89ef62ce7 522 __IO uint8_t HOUR;
emilmont 10:3bc89ef62ce7 523 uint8_t RESERVED6[3];
emilmont 10:3bc89ef62ce7 524 __IO uint8_t DOM;
emilmont 10:3bc89ef62ce7 525 uint8_t RESERVED7[3];
emilmont 10:3bc89ef62ce7 526 __IO uint8_t DOW;
emilmont 10:3bc89ef62ce7 527 uint8_t RESERVED8[3];
emilmont 10:3bc89ef62ce7 528 __IO uint16_t DOY;
emilmont 10:3bc89ef62ce7 529 uint16_t RESERVED9;
emilmont 10:3bc89ef62ce7 530 __IO uint8_t MONTH;
emilmont 10:3bc89ef62ce7 531 uint8_t RESERVED10[3];
emilmont 10:3bc89ef62ce7 532 __IO uint16_t YEAR;
emilmont 10:3bc89ef62ce7 533 uint16_t RESERVED11;
emilmont 10:3bc89ef62ce7 534 __IO uint32_t CALIBRATION;
emilmont 10:3bc89ef62ce7 535 __IO uint32_t GPREG0;
emilmont 10:3bc89ef62ce7 536 __IO uint32_t GPREG1;
emilmont 10:3bc89ef62ce7 537 __IO uint32_t GPREG2;
emilmont 10:3bc89ef62ce7 538 __IO uint32_t GPREG3;
emilmont 10:3bc89ef62ce7 539 __IO uint32_t GPREG4;
emilmont 10:3bc89ef62ce7 540 __IO uint8_t RTC_AUXEN;
emilmont 10:3bc89ef62ce7 541 uint8_t RESERVED12[3];
emilmont 10:3bc89ef62ce7 542 __IO uint8_t RTC_AUX;
emilmont 10:3bc89ef62ce7 543 uint8_t RESERVED13[3];
emilmont 10:3bc89ef62ce7 544 __IO uint8_t ALSEC;
emilmont 10:3bc89ef62ce7 545 uint8_t RESERVED14[3];
emilmont 10:3bc89ef62ce7 546 __IO uint8_t ALMIN;
emilmont 10:3bc89ef62ce7 547 uint8_t RESERVED15[3];
emilmont 10:3bc89ef62ce7 548 __IO uint8_t ALHOUR;
emilmont 10:3bc89ef62ce7 549 uint8_t RESERVED16[3];
emilmont 10:3bc89ef62ce7 550 __IO uint8_t ALDOM;
emilmont 10:3bc89ef62ce7 551 uint8_t RESERVED17[3];
emilmont 10:3bc89ef62ce7 552 __IO uint8_t ALDOW;
emilmont 10:3bc89ef62ce7 553 uint8_t RESERVED18[3];
emilmont 10:3bc89ef62ce7 554 __IO uint16_t ALDOY;
emilmont 10:3bc89ef62ce7 555 uint16_t RESERVED19;
emilmont 10:3bc89ef62ce7 556 __IO uint8_t ALMON;
emilmont 10:3bc89ef62ce7 557 uint8_t RESERVED20[3];
emilmont 10:3bc89ef62ce7 558 __IO uint16_t ALYEAR;
emilmont 10:3bc89ef62ce7 559 uint16_t RESERVED21;
emilmont 10:3bc89ef62ce7 560 } LPC_RTC_TypeDef;
emilmont 10:3bc89ef62ce7 561
emilmont 10:3bc89ef62ce7 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
emilmont 10:3bc89ef62ce7 563 typedef struct
emilmont 10:3bc89ef62ce7 564 {
emilmont 10:3bc89ef62ce7 565 __IO uint8_t WDMOD;
emilmont 10:3bc89ef62ce7 566 uint8_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 567 __IO uint32_t WDTC;
emilmont 10:3bc89ef62ce7 568 __O uint8_t WDFEED;
emilmont 10:3bc89ef62ce7 569 uint8_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 570 __I uint32_t WDTV;
emilmont 10:3bc89ef62ce7 571 __IO uint32_t WDCLKSEL;
emilmont 10:3bc89ef62ce7 572 } LPC_WDT_TypeDef;
emilmont 10:3bc89ef62ce7 573
emilmont 10:3bc89ef62ce7 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
emilmont 10:3bc89ef62ce7 575 typedef struct
emilmont 10:3bc89ef62ce7 576 {
emilmont 10:3bc89ef62ce7 577 __IO uint32_t ADCR;
emilmont 10:3bc89ef62ce7 578 __IO uint32_t ADGDR;
emilmont 10:3bc89ef62ce7 579 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 580 __IO uint32_t ADINTEN;
emilmont 10:3bc89ef62ce7 581 __I uint32_t ADDR0;
emilmont 10:3bc89ef62ce7 582 __I uint32_t ADDR1;
emilmont 10:3bc89ef62ce7 583 __I uint32_t ADDR2;
emilmont 10:3bc89ef62ce7 584 __I uint32_t ADDR3;
emilmont 10:3bc89ef62ce7 585 __I uint32_t ADDR4;
emilmont 10:3bc89ef62ce7 586 __I uint32_t ADDR5;
emilmont 10:3bc89ef62ce7 587 __I uint32_t ADDR6;
emilmont 10:3bc89ef62ce7 588 __I uint32_t ADDR7;
emilmont 10:3bc89ef62ce7 589 __I uint32_t ADSTAT;
emilmont 10:3bc89ef62ce7 590 __IO uint32_t ADTRM;
emilmont 10:3bc89ef62ce7 591 } LPC_ADC_TypeDef;
emilmont 10:3bc89ef62ce7 592
emilmont 10:3bc89ef62ce7 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
emilmont 10:3bc89ef62ce7 594 typedef struct
emilmont 10:3bc89ef62ce7 595 {
emilmont 10:3bc89ef62ce7 596 __IO uint32_t DACR;
emilmont 10:3bc89ef62ce7 597 __IO uint32_t DACCTRL;
emilmont 10:3bc89ef62ce7 598 __IO uint16_t DACCNTVAL;
emilmont 10:3bc89ef62ce7 599 } LPC_DAC_TypeDef;
emilmont 10:3bc89ef62ce7 600
emilmont 10:3bc89ef62ce7 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
emilmont 10:3bc89ef62ce7 602 typedef struct
emilmont 10:3bc89ef62ce7 603 {
emilmont 10:3bc89ef62ce7 604 __I uint32_t MCCON;
emilmont 10:3bc89ef62ce7 605 __O uint32_t MCCON_SET;
emilmont 10:3bc89ef62ce7 606 __O uint32_t MCCON_CLR;
emilmont 10:3bc89ef62ce7 607 __I uint32_t MCCAPCON;
emilmont 10:3bc89ef62ce7 608 __O uint32_t MCCAPCON_SET;
emilmont 10:3bc89ef62ce7 609 __O uint32_t MCCAPCON_CLR;
emilmont 10:3bc89ef62ce7 610 __IO uint32_t MCTIM0;
emilmont 10:3bc89ef62ce7 611 __IO uint32_t MCTIM1;
emilmont 10:3bc89ef62ce7 612 __IO uint32_t MCTIM2;
emilmont 10:3bc89ef62ce7 613 __IO uint32_t MCPER0;
emilmont 10:3bc89ef62ce7 614 __IO uint32_t MCPER1;
emilmont 10:3bc89ef62ce7 615 __IO uint32_t MCPER2;
emilmont 10:3bc89ef62ce7 616 __IO uint32_t MCPW0;
emilmont 10:3bc89ef62ce7 617 __IO uint32_t MCPW1;
emilmont 10:3bc89ef62ce7 618 __IO uint32_t MCPW2;
emilmont 10:3bc89ef62ce7 619 __IO uint32_t MCDEADTIME;
emilmont 10:3bc89ef62ce7 620 __IO uint32_t MCCCP;
emilmont 10:3bc89ef62ce7 621 __IO uint32_t MCCR0;
emilmont 10:3bc89ef62ce7 622 __IO uint32_t MCCR1;
emilmont 10:3bc89ef62ce7 623 __IO uint32_t MCCR2;
emilmont 10:3bc89ef62ce7 624 __I uint32_t MCINTEN;
emilmont 10:3bc89ef62ce7 625 __O uint32_t MCINTEN_SET;
emilmont 10:3bc89ef62ce7 626 __O uint32_t MCINTEN_CLR;
emilmont 10:3bc89ef62ce7 627 __I uint32_t MCCNTCON;
emilmont 10:3bc89ef62ce7 628 __O uint32_t MCCNTCON_SET;
emilmont 10:3bc89ef62ce7 629 __O uint32_t MCCNTCON_CLR;
emilmont 10:3bc89ef62ce7 630 __I uint32_t MCINTFLAG;
emilmont 10:3bc89ef62ce7 631 __O uint32_t MCINTFLAG_SET;
emilmont 10:3bc89ef62ce7 632 __O uint32_t MCINTFLAG_CLR;
emilmont 10:3bc89ef62ce7 633 __O uint32_t MCCAP_CLR;
emilmont 10:3bc89ef62ce7 634 } LPC_MCPWM_TypeDef;
emilmont 10:3bc89ef62ce7 635
emilmont 10:3bc89ef62ce7 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
emilmont 10:3bc89ef62ce7 637 typedef struct
emilmont 10:3bc89ef62ce7 638 {
emilmont 10:3bc89ef62ce7 639 __O uint32_t QEICON;
emilmont 10:3bc89ef62ce7 640 __I uint32_t QEISTAT;
emilmont 10:3bc89ef62ce7 641 __IO uint32_t QEICONF;
emilmont 10:3bc89ef62ce7 642 __I uint32_t QEIPOS;
emilmont 10:3bc89ef62ce7 643 __IO uint32_t QEIMAXPOS;
emilmont 10:3bc89ef62ce7 644 __IO uint32_t CMPOS0;
emilmont 10:3bc89ef62ce7 645 __IO uint32_t CMPOS1;
emilmont 10:3bc89ef62ce7 646 __IO uint32_t CMPOS2;
emilmont 10:3bc89ef62ce7 647 __I uint32_t INXCNT;
emilmont 10:3bc89ef62ce7 648 __IO uint32_t INXCMP;
emilmont 10:3bc89ef62ce7 649 __IO uint32_t QEILOAD;
emilmont 10:3bc89ef62ce7 650 __I uint32_t QEITIME;
emilmont 10:3bc89ef62ce7 651 __I uint32_t QEIVEL;
emilmont 10:3bc89ef62ce7 652 __I uint32_t QEICAP;
emilmont 10:3bc89ef62ce7 653 __IO uint32_t VELCOMP;
emilmont 10:3bc89ef62ce7 654 __IO uint32_t FILTER;
emilmont 10:3bc89ef62ce7 655 uint32_t RESERVED0[998];
emilmont 10:3bc89ef62ce7 656 __O uint32_t QEIIEC;
emilmont 10:3bc89ef62ce7 657 __O uint32_t QEIIES;
emilmont 10:3bc89ef62ce7 658 __I uint32_t QEIINTSTAT;
emilmont 10:3bc89ef62ce7 659 __I uint32_t QEIIE;
emilmont 10:3bc89ef62ce7 660 __O uint32_t QEICLR;
emilmont 10:3bc89ef62ce7 661 __O uint32_t QEISET;
emilmont 10:3bc89ef62ce7 662 } LPC_QEI_TypeDef;
emilmont 10:3bc89ef62ce7 663
emilmont 10:3bc89ef62ce7 664 /*------------- Controller Area Network (CAN) --------------------------------*/
emilmont 10:3bc89ef62ce7 665 typedef struct
emilmont 10:3bc89ef62ce7 666 {
emilmont 10:3bc89ef62ce7 667 __IO uint32_t mask[512]; /* ID Masks */
emilmont 10:3bc89ef62ce7 668 } LPC_CANAF_RAM_TypeDef;
emilmont 10:3bc89ef62ce7 669
emilmont 10:3bc89ef62ce7 670 typedef struct /* Acceptance Filter Registers */
emilmont 10:3bc89ef62ce7 671 {
emilmont 10:3bc89ef62ce7 672 __IO uint32_t AFMR;
emilmont 10:3bc89ef62ce7 673 __IO uint32_t SFF_sa;
emilmont 10:3bc89ef62ce7 674 __IO uint32_t SFF_GRP_sa;
emilmont 10:3bc89ef62ce7 675 __IO uint32_t EFF_sa;
emilmont 10:3bc89ef62ce7 676 __IO uint32_t EFF_GRP_sa;
emilmont 10:3bc89ef62ce7 677 __IO uint32_t ENDofTable;
emilmont 10:3bc89ef62ce7 678 __I uint32_t LUTerrAd;
emilmont 10:3bc89ef62ce7 679 __I uint32_t LUTerr;
emilmont 10:3bc89ef62ce7 680 __IO uint32_t FCANIE;
emilmont 10:3bc89ef62ce7 681 __IO uint32_t FCANIC0;
emilmont 10:3bc89ef62ce7 682 __IO uint32_t FCANIC1;
emilmont 10:3bc89ef62ce7 683 } LPC_CANAF_TypeDef;
emilmont 10:3bc89ef62ce7 684
emilmont 10:3bc89ef62ce7 685 typedef struct /* Central Registers */
emilmont 10:3bc89ef62ce7 686 {
emilmont 10:3bc89ef62ce7 687 __I uint32_t CANTxSR;
emilmont 10:3bc89ef62ce7 688 __I uint32_t CANRxSR;
emilmont 10:3bc89ef62ce7 689 __I uint32_t CANMSR;
emilmont 10:3bc89ef62ce7 690 } LPC_CANCR_TypeDef;
emilmont 10:3bc89ef62ce7 691
emilmont 10:3bc89ef62ce7 692 typedef struct /* Controller Registers */
emilmont 10:3bc89ef62ce7 693 {
emilmont 10:3bc89ef62ce7 694 __IO uint32_t MOD;
emilmont 10:3bc89ef62ce7 695 __O uint32_t CMR;
emilmont 10:3bc89ef62ce7 696 __IO uint32_t GSR;
emilmont 10:3bc89ef62ce7 697 __I uint32_t ICR;
emilmont 10:3bc89ef62ce7 698 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 699 __IO uint32_t BTR;
emilmont 10:3bc89ef62ce7 700 __IO uint32_t EWL;
emilmont 10:3bc89ef62ce7 701 __I uint32_t SR;
emilmont 10:3bc89ef62ce7 702 __IO uint32_t RFS;
emilmont 10:3bc89ef62ce7 703 __IO uint32_t RID;
emilmont 10:3bc89ef62ce7 704 __IO uint32_t RDA;
emilmont 10:3bc89ef62ce7 705 __IO uint32_t RDB;
emilmont 10:3bc89ef62ce7 706 __IO uint32_t TFI1;
emilmont 10:3bc89ef62ce7 707 __IO uint32_t TID1;
emilmont 10:3bc89ef62ce7 708 __IO uint32_t TDA1;
emilmont 10:3bc89ef62ce7 709 __IO uint32_t TDB1;
emilmont 10:3bc89ef62ce7 710 __IO uint32_t TFI2;
emilmont 10:3bc89ef62ce7 711 __IO uint32_t TID2;
emilmont 10:3bc89ef62ce7 712 __IO uint32_t TDA2;
emilmont 10:3bc89ef62ce7 713 __IO uint32_t TDB2;
emilmont 10:3bc89ef62ce7 714 __IO uint32_t TFI3;
emilmont 10:3bc89ef62ce7 715 __IO uint32_t TID3;
emilmont 10:3bc89ef62ce7 716 __IO uint32_t TDA3;
emilmont 10:3bc89ef62ce7 717 __IO uint32_t TDB3;
emilmont 10:3bc89ef62ce7 718 } LPC_CAN_TypeDef;
emilmont 10:3bc89ef62ce7 719
emilmont 10:3bc89ef62ce7 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
emilmont 10:3bc89ef62ce7 721 typedef struct /* Common Registers */
emilmont 10:3bc89ef62ce7 722 {
emilmont 10:3bc89ef62ce7 723 __I uint32_t DMACIntStat;
emilmont 10:3bc89ef62ce7 724 __I uint32_t DMACIntTCStat;
emilmont 10:3bc89ef62ce7 725 __O uint32_t DMACIntTCClear;
emilmont 10:3bc89ef62ce7 726 __I uint32_t DMACIntErrStat;
emilmont 10:3bc89ef62ce7 727 __O uint32_t DMACIntErrClr;
emilmont 10:3bc89ef62ce7 728 __I uint32_t DMACRawIntTCStat;
emilmont 10:3bc89ef62ce7 729 __I uint32_t DMACRawIntErrStat;
emilmont 10:3bc89ef62ce7 730 __I uint32_t DMACEnbldChns;
emilmont 10:3bc89ef62ce7 731 __IO uint32_t DMACSoftBReq;
emilmont 10:3bc89ef62ce7 732 __IO uint32_t DMACSoftSReq;
emilmont 10:3bc89ef62ce7 733 __IO uint32_t DMACSoftLBReq;
emilmont 10:3bc89ef62ce7 734 __IO uint32_t DMACSoftLSReq;
emilmont 10:3bc89ef62ce7 735 __IO uint32_t DMACConfig;
emilmont 10:3bc89ef62ce7 736 __IO uint32_t DMACSync;
emilmont 10:3bc89ef62ce7 737 } LPC_GPDMA_TypeDef;
emilmont 10:3bc89ef62ce7 738
emilmont 10:3bc89ef62ce7 739 typedef struct /* Channel Registers */
emilmont 10:3bc89ef62ce7 740 {
emilmont 10:3bc89ef62ce7 741 __IO uint32_t DMACCSrcAddr;
emilmont 10:3bc89ef62ce7 742 __IO uint32_t DMACCDestAddr;
emilmont 10:3bc89ef62ce7 743 __IO uint32_t DMACCLLI;
emilmont 10:3bc89ef62ce7 744 __IO uint32_t DMACCControl;
emilmont 10:3bc89ef62ce7 745 __IO uint32_t DMACCConfig;
emilmont 10:3bc89ef62ce7 746 } LPC_GPDMACH_TypeDef;
emilmont 10:3bc89ef62ce7 747
emilmont 10:3bc89ef62ce7 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
emilmont 10:3bc89ef62ce7 749 typedef struct
emilmont 10:3bc89ef62ce7 750 {
emilmont 10:3bc89ef62ce7 751 __I uint32_t HcRevision; /* USB Host Registers */
emilmont 10:3bc89ef62ce7 752 __IO uint32_t HcControl;
emilmont 10:3bc89ef62ce7 753 __IO uint32_t HcCommandStatus;
emilmont 10:3bc89ef62ce7 754 __IO uint32_t HcInterruptStatus;
emilmont 10:3bc89ef62ce7 755 __IO uint32_t HcInterruptEnable;
emilmont 10:3bc89ef62ce7 756 __IO uint32_t HcInterruptDisable;
emilmont 10:3bc89ef62ce7 757 __IO uint32_t HcHCCA;
emilmont 10:3bc89ef62ce7 758 __I uint32_t HcPeriodCurrentED;
emilmont 10:3bc89ef62ce7 759 __IO uint32_t HcControlHeadED;
emilmont 10:3bc89ef62ce7 760 __IO uint32_t HcControlCurrentED;
emilmont 10:3bc89ef62ce7 761 __IO uint32_t HcBulkHeadED;
emilmont 10:3bc89ef62ce7 762 __IO uint32_t HcBulkCurrentED;
emilmont 10:3bc89ef62ce7 763 __I uint32_t HcDoneHead;
emilmont 10:3bc89ef62ce7 764 __IO uint32_t HcFmInterval;
emilmont 10:3bc89ef62ce7 765 __I uint32_t HcFmRemaining;
emilmont 10:3bc89ef62ce7 766 __I uint32_t HcFmNumber;
emilmont 10:3bc89ef62ce7 767 __IO uint32_t HcPeriodicStart;
emilmont 10:3bc89ef62ce7 768 __IO uint32_t HcLSTreshold;
emilmont 10:3bc89ef62ce7 769 __IO uint32_t HcRhDescriptorA;
emilmont 10:3bc89ef62ce7 770 __IO uint32_t HcRhDescriptorB;
emilmont 10:3bc89ef62ce7 771 __IO uint32_t HcRhStatus;
emilmont 10:3bc89ef62ce7 772 __IO uint32_t HcRhPortStatus1;
emilmont 10:3bc89ef62ce7 773 __IO uint32_t HcRhPortStatus2;
emilmont 10:3bc89ef62ce7 774 uint32_t RESERVED0[40];
emilmont 10:3bc89ef62ce7 775 __I uint32_t Module_ID;
emilmont 10:3bc89ef62ce7 776
emilmont 10:3bc89ef62ce7 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
emilmont 10:3bc89ef62ce7 778 __IO uint32_t OTGIntEn;
emilmont 10:3bc89ef62ce7 779 __O uint32_t OTGIntSet;
emilmont 10:3bc89ef62ce7 780 __O uint32_t OTGIntClr;
emilmont 10:3bc89ef62ce7 781 __IO uint32_t OTGStCtrl;
emilmont 10:3bc89ef62ce7 782 __IO uint32_t OTGTmr;
emilmont 10:3bc89ef62ce7 783 uint32_t RESERVED1[58];
emilmont 10:3bc89ef62ce7 784
emilmont 10:3bc89ef62ce7 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
emilmont 10:3bc89ef62ce7 786 __IO uint32_t USBDevIntEn;
emilmont 10:3bc89ef62ce7 787 __O uint32_t USBDevIntClr;
emilmont 10:3bc89ef62ce7 788 __O uint32_t USBDevIntSet;
emilmont 10:3bc89ef62ce7 789
emilmont 10:3bc89ef62ce7 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
emilmont 10:3bc89ef62ce7 791 __I uint32_t USBCmdData;
emilmont 10:3bc89ef62ce7 792
emilmont 10:3bc89ef62ce7 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
emilmont 10:3bc89ef62ce7 794 __O uint32_t USBTxData;
emilmont 10:3bc89ef62ce7 795 __I uint32_t USBRxPLen;
emilmont 10:3bc89ef62ce7 796 __O uint32_t USBTxPLen;
emilmont 10:3bc89ef62ce7 797 __IO uint32_t USBCtrl;
emilmont 10:3bc89ef62ce7 798 __O uint32_t USBDevIntPri;
emilmont 10:3bc89ef62ce7 799
emilmont 10:3bc89ef62ce7 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
emilmont 10:3bc89ef62ce7 801 __IO uint32_t USBEpIntEn;
emilmont 10:3bc89ef62ce7 802 __O uint32_t USBEpIntClr;
emilmont 10:3bc89ef62ce7 803 __O uint32_t USBEpIntSet;
emilmont 10:3bc89ef62ce7 804 __O uint32_t USBEpIntPri;
emilmont 10:3bc89ef62ce7 805
emilmont 10:3bc89ef62ce7 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
emilmont 10:3bc89ef62ce7 807 __O uint32_t USBEpInd;
emilmont 10:3bc89ef62ce7 808 __IO uint32_t USBMaxPSize;
emilmont 10:3bc89ef62ce7 809
emilmont 10:3bc89ef62ce7 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
emilmont 10:3bc89ef62ce7 811 __O uint32_t USBDMARClr;
emilmont 10:3bc89ef62ce7 812 __O uint32_t USBDMARSet;
emilmont 10:3bc89ef62ce7 813 uint32_t RESERVED2[9];
emilmont 10:3bc89ef62ce7 814 __IO uint32_t USBUDCAH;
emilmont 10:3bc89ef62ce7 815 __I uint32_t USBEpDMASt;
emilmont 10:3bc89ef62ce7 816 __O uint32_t USBEpDMAEn;
emilmont 10:3bc89ef62ce7 817 __O uint32_t USBEpDMADis;
emilmont 10:3bc89ef62ce7 818 __I uint32_t USBDMAIntSt;
emilmont 10:3bc89ef62ce7 819 __IO uint32_t USBDMAIntEn;
emilmont 10:3bc89ef62ce7 820 uint32_t RESERVED3[2];
emilmont 10:3bc89ef62ce7 821 __I uint32_t USBEoTIntSt;
emilmont 10:3bc89ef62ce7 822 __O uint32_t USBEoTIntClr;
emilmont 10:3bc89ef62ce7 823 __O uint32_t USBEoTIntSet;
emilmont 10:3bc89ef62ce7 824 __I uint32_t USBNDDRIntSt;
emilmont 10:3bc89ef62ce7 825 __O uint32_t USBNDDRIntClr;
emilmont 10:3bc89ef62ce7 826 __O uint32_t USBNDDRIntSet;
emilmont 10:3bc89ef62ce7 827 __I uint32_t USBSysErrIntSt;
emilmont 10:3bc89ef62ce7 828 __O uint32_t USBSysErrIntClr;
emilmont 10:3bc89ef62ce7 829 __O uint32_t USBSysErrIntSet;
emilmont 10:3bc89ef62ce7 830 uint32_t RESERVED4[15];
emilmont 10:3bc89ef62ce7 831
emilmont 10:3bc89ef62ce7 832 union {
emilmont 10:3bc89ef62ce7 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
emilmont 10:3bc89ef62ce7 834 __O uint32_t I2C_TX;
emilmont 10:3bc89ef62ce7 835 };
emilmont 10:3bc89ef62ce7 836 __I uint32_t I2C_STS;
emilmont 10:3bc89ef62ce7 837 __IO uint32_t I2C_CTL;
emilmont 10:3bc89ef62ce7 838 __IO uint32_t I2C_CLKHI;
emilmont 10:3bc89ef62ce7 839 __O uint32_t I2C_CLKLO;
emilmont 10:3bc89ef62ce7 840 uint32_t RESERVED5[824];
emilmont 10:3bc89ef62ce7 841
emilmont 10:3bc89ef62ce7 842 union {
emilmont 10:3bc89ef62ce7 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
emilmont 10:3bc89ef62ce7 844 __IO uint32_t OTGClkCtrl;
emilmont 10:3bc89ef62ce7 845 };
emilmont 10:3bc89ef62ce7 846 union {
emilmont 10:3bc89ef62ce7 847 __I uint32_t USBClkSt;
emilmont 10:3bc89ef62ce7 848 __I uint32_t OTGClkSt;
emilmont 10:3bc89ef62ce7 849 };
emilmont 10:3bc89ef62ce7 850 } LPC_USB_TypeDef;
emilmont 10:3bc89ef62ce7 851
emilmont 10:3bc89ef62ce7 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
emilmont 10:3bc89ef62ce7 853 typedef struct
emilmont 10:3bc89ef62ce7 854 {
emilmont 10:3bc89ef62ce7 855 __IO uint32_t MAC1; /* MAC Registers */
emilmont 10:3bc89ef62ce7 856 __IO uint32_t MAC2;
emilmont 10:3bc89ef62ce7 857 __IO uint32_t IPGT;
emilmont 10:3bc89ef62ce7 858 __IO uint32_t IPGR;
emilmont 10:3bc89ef62ce7 859 __IO uint32_t CLRT;
emilmont 10:3bc89ef62ce7 860 __IO uint32_t MAXF;
emilmont 10:3bc89ef62ce7 861 __IO uint32_t SUPP;
emilmont 10:3bc89ef62ce7 862 __IO uint32_t TEST;
emilmont 10:3bc89ef62ce7 863 __IO uint32_t MCFG;
emilmont 10:3bc89ef62ce7 864 __IO uint32_t MCMD;
emilmont 10:3bc89ef62ce7 865 __IO uint32_t MADR;
emilmont 10:3bc89ef62ce7 866 __O uint32_t MWTD;
emilmont 10:3bc89ef62ce7 867 __I uint32_t MRDD;
emilmont 10:3bc89ef62ce7 868 __I uint32_t MIND;
emilmont 10:3bc89ef62ce7 869 uint32_t RESERVED0[2];
emilmont 10:3bc89ef62ce7 870 __IO uint32_t SA0;
emilmont 10:3bc89ef62ce7 871 __IO uint32_t SA1;
emilmont 10:3bc89ef62ce7 872 __IO uint32_t SA2;
emilmont 10:3bc89ef62ce7 873 uint32_t RESERVED1[45];
emilmont 10:3bc89ef62ce7 874 __IO uint32_t Command; /* Control Registers */
emilmont 10:3bc89ef62ce7 875 __I uint32_t Status;
emilmont 10:3bc89ef62ce7 876 __IO uint32_t RxDescriptor;
emilmont 10:3bc89ef62ce7 877 __IO uint32_t RxStatus;
emilmont 10:3bc89ef62ce7 878 __IO uint32_t RxDescriptorNumber;
emilmont 10:3bc89ef62ce7 879 __I uint32_t RxProduceIndex;
emilmont 10:3bc89ef62ce7 880 __IO uint32_t RxConsumeIndex;
emilmont 10:3bc89ef62ce7 881 __IO uint32_t TxDescriptor;
emilmont 10:3bc89ef62ce7 882 __IO uint32_t TxStatus;
emilmont 10:3bc89ef62ce7 883 __IO uint32_t TxDescriptorNumber;
emilmont 10:3bc89ef62ce7 884 __IO uint32_t TxProduceIndex;
emilmont 10:3bc89ef62ce7 885 __I uint32_t TxConsumeIndex;
emilmont 10:3bc89ef62ce7 886 uint32_t RESERVED2[10];
emilmont 10:3bc89ef62ce7 887 __I uint32_t TSV0;
emilmont 10:3bc89ef62ce7 888 __I uint32_t TSV1;
emilmont 10:3bc89ef62ce7 889 __I uint32_t RSV;
emilmont 10:3bc89ef62ce7 890 uint32_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 891 __IO uint32_t FlowControlCounter;
emilmont 10:3bc89ef62ce7 892 __I uint32_t FlowControlStatus;
emilmont 10:3bc89ef62ce7 893 uint32_t RESERVED4[34];
emilmont 10:3bc89ef62ce7 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
emilmont 10:3bc89ef62ce7 895 __IO uint32_t RxFilterWoLStatus;
emilmont 10:3bc89ef62ce7 896 __IO uint32_t RxFilterWoLClear;
emilmont 10:3bc89ef62ce7 897 uint32_t RESERVED5;
emilmont 10:3bc89ef62ce7 898 __IO uint32_t HashFilterL;
emilmont 10:3bc89ef62ce7 899 __IO uint32_t HashFilterH;
emilmont 10:3bc89ef62ce7 900 uint32_t RESERVED6[882];
emilmont 10:3bc89ef62ce7 901 __I uint32_t IntStatus; /* Module Control Registers */
emilmont 10:3bc89ef62ce7 902 __IO uint32_t IntEnable;
emilmont 10:3bc89ef62ce7 903 __O uint32_t IntClear;
emilmont 10:3bc89ef62ce7 904 __O uint32_t IntSet;
emilmont 10:3bc89ef62ce7 905 uint32_t RESERVED7;
emilmont 10:3bc89ef62ce7 906 __IO uint32_t PowerDown;
emilmont 10:3bc89ef62ce7 907 uint32_t RESERVED8;
emilmont 10:3bc89ef62ce7 908 __IO uint32_t Module_ID;
emilmont 10:3bc89ef62ce7 909 } LPC_EMAC_TypeDef;
emilmont 10:3bc89ef62ce7 910
emilmont 10:3bc89ef62ce7 911 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 912 #pragma no_anon_unions
emilmont 10:3bc89ef62ce7 913 #endif
emilmont 10:3bc89ef62ce7 914
emilmont 10:3bc89ef62ce7 915
emilmont 10:3bc89ef62ce7 916 /******************************************************************************/
emilmont 10:3bc89ef62ce7 917 /* Peripheral memory map */
emilmont 10:3bc89ef62ce7 918 /******************************************************************************/
emilmont 10:3bc89ef62ce7 919 /* Base addresses */
emilmont 10:3bc89ef62ce7 920 #define LPC_FLASH_BASE (0x00000000UL)
emilmont 10:3bc89ef62ce7 921 #define LPC_RAM_BASE (0x10000000UL)
emilmont 10:3bc89ef62ce7 922 #define LPC_GPIO_BASE (0x2009C000UL)
emilmont 10:3bc89ef62ce7 923 #define LPC_APB0_BASE (0x40000000UL)
emilmont 10:3bc89ef62ce7 924 #define LPC_APB1_BASE (0x40080000UL)
emilmont 10:3bc89ef62ce7 925 #define LPC_AHB_BASE (0x50000000UL)
emilmont 10:3bc89ef62ce7 926 #define LPC_CM3_BASE (0xE0000000UL)
emilmont 10:3bc89ef62ce7 927
emilmont 10:3bc89ef62ce7 928 /* APB0 peripherals */
emilmont 10:3bc89ef62ce7 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
emilmont 10:3bc89ef62ce7 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
emilmont 10:3bc89ef62ce7 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
emilmont 10:3bc89ef62ce7 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
emilmont 10:3bc89ef62ce7 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
emilmont 10:3bc89ef62ce7 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
emilmont 10:3bc89ef62ce7 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
emilmont 10:3bc89ef62ce7 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
emilmont 10:3bc89ef62ce7 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
emilmont 10:3bc89ef62ce7 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
emilmont 10:3bc89ef62ce7 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
emilmont 10:3bc89ef62ce7 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
emilmont 10:3bc89ef62ce7 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
emilmont 10:3bc89ef62ce7 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
emilmont 10:3bc89ef62ce7 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
emilmont 10:3bc89ef62ce7 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
emilmont 10:3bc89ef62ce7 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
emilmont 10:3bc89ef62ce7 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
emilmont 10:3bc89ef62ce7 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
emilmont 10:3bc89ef62ce7 948
emilmont 10:3bc89ef62ce7 949 /* APB1 peripherals */
emilmont 10:3bc89ef62ce7 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
emilmont 10:3bc89ef62ce7 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
emilmont 10:3bc89ef62ce7 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
emilmont 10:3bc89ef62ce7 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
emilmont 10:3bc89ef62ce7 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
emilmont 10:3bc89ef62ce7 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
emilmont 10:3bc89ef62ce7 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
emilmont 10:3bc89ef62ce7 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
emilmont 10:3bc89ef62ce7 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
emilmont 10:3bc89ef62ce7 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
emilmont 10:3bc89ef62ce7 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
emilmont 10:3bc89ef62ce7 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
emilmont 10:3bc89ef62ce7 962
emilmont 10:3bc89ef62ce7 963 /* AHB peripherals */
emilmont 10:3bc89ef62ce7 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
emilmont 10:3bc89ef62ce7 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
emilmont 10:3bc89ef62ce7 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
emilmont 10:3bc89ef62ce7 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
emilmont 10:3bc89ef62ce7 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
emilmont 10:3bc89ef62ce7 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
emilmont 10:3bc89ef62ce7 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
emilmont 10:3bc89ef62ce7 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
emilmont 10:3bc89ef62ce7 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
emilmont 10:3bc89ef62ce7 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
emilmont 10:3bc89ef62ce7 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
emilmont 10:3bc89ef62ce7 975
emilmont 10:3bc89ef62ce7 976 /* GPIOs */
emilmont 10:3bc89ef62ce7 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
emilmont 10:3bc89ef62ce7 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
emilmont 10:3bc89ef62ce7 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
emilmont 10:3bc89ef62ce7 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
emilmont 10:3bc89ef62ce7 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
emilmont 10:3bc89ef62ce7 982
emilmont 10:3bc89ef62ce7 983
emilmont 10:3bc89ef62ce7 984 /******************************************************************************/
emilmont 10:3bc89ef62ce7 985 /* Peripheral declaration */
emilmont 10:3bc89ef62ce7 986 /******************************************************************************/
emilmont 10:3bc89ef62ce7 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
emilmont 10:3bc89ef62ce7 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
emilmont 10:3bc89ef62ce7 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
emilmont 10:3bc89ef62ce7 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
emilmont 10:3bc89ef62ce7 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
emilmont 10:3bc89ef62ce7 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
emilmont 10:3bc89ef62ce7 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
emilmont 10:3bc89ef62ce7 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
emilmont 10:3bc89ef62ce7 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
emilmont 10:3bc89ef62ce7 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
emilmont 10:3bc89ef62ce7 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
emilmont 10:3bc89ef62ce7 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
emilmont 10:3bc89ef62ce7 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
emilmont 10:3bc89ef62ce7 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
emilmont 10:3bc89ef62ce7 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
emilmont 10:3bc89ef62ce7 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
emilmont 10:3bc89ef62ce7 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
emilmont 10:3bc89ef62ce7 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
emilmont 10:3bc89ef62ce7 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
emilmont 10:3bc89ef62ce7 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
emilmont 10:3bc89ef62ce7 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
emilmont 10:3bc89ef62ce7 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
emilmont 10:3bc89ef62ce7 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
emilmont 10:3bc89ef62ce7 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
emilmont 10:3bc89ef62ce7 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
emilmont 10:3bc89ef62ce7 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
emilmont 10:3bc89ef62ce7 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
emilmont 10:3bc89ef62ce7 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
emilmont 10:3bc89ef62ce7 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
emilmont 10:3bc89ef62ce7 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
emilmont 10:3bc89ef62ce7 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
emilmont 10:3bc89ef62ce7 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
emilmont 10:3bc89ef62ce7 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
emilmont 10:3bc89ef62ce7 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
emilmont 10:3bc89ef62ce7 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
emilmont 10:3bc89ef62ce7 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
emilmont 10:3bc89ef62ce7 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
emilmont 10:3bc89ef62ce7 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
emilmont 10:3bc89ef62ce7 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
emilmont 10:3bc89ef62ce7 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
emilmont 10:3bc89ef62ce7 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
emilmont 10:3bc89ef62ce7 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
emilmont 10:3bc89ef62ce7 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
emilmont 10:3bc89ef62ce7 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
emilmont 10:3bc89ef62ce7 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
emilmont 10:3bc89ef62ce7 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
emilmont 10:3bc89ef62ce7 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
emilmont 10:3bc89ef62ce7 1034
emilmont 10:3bc89ef62ce7 1035 #endif // __LPC17xx_H__