Rigado / mbed-src-bmd-200

mbed-src updated for BMD-200 evaluation board. Just pin numbers are updated.

Dependents:   mbed_blinky-bmd-200 bmd-200_accel_demo firstRig

Fork of mbed-src by mbed official

Replacement for the "mbed" or "mbed-src" library when using the BMD-200 Evaluation kit. This library only remaps the pin names (i.e. LED1 points to p0.01 instead of p0.18, etc) as used by the BMD-200 Evaluation board (select the nRF51822_mkit platform). All other code is untouched.

targets/cmsis/core_caFunc.h@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Child:
485:d9a48e768ce0
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 2 * @file core_caFunc.h
mbed_official 390:35c2c1cf29cd 3 * @brief CMSIS Cortex-A Core Function Access Header File
mbed_official 390:35c2c1cf29cd 4 * @version V3.10
mbed_official 390:35c2c1cf29cd 5 * @date 9 May 2013
mbed_official 390:35c2c1cf29cd 6 *
mbed_official 390:35c2c1cf29cd 7 * @note
mbed_official 390:35c2c1cf29cd 8 *
mbed_official 390:35c2c1cf29cd 9 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
mbed_official 390:35c2c1cf29cd 11
mbed_official 390:35c2c1cf29cd 12 All rights reserved.
mbed_official 390:35c2c1cf29cd 13 Redistribution and use in source and binary forms, with or without
mbed_official 390:35c2c1cf29cd 14 modification, are permitted provided that the following conditions are met:
mbed_official 390:35c2c1cf29cd 15 - Redistributions of source code must retain the above copyright
mbed_official 390:35c2c1cf29cd 16 notice, this list of conditions and the following disclaimer.
mbed_official 390:35c2c1cf29cd 17 - Redistributions in binary form must reproduce the above copyright
mbed_official 390:35c2c1cf29cd 18 notice, this list of conditions and the following disclaimer in the
mbed_official 390:35c2c1cf29cd 19 documentation and/or other materials provided with the distribution.
mbed_official 390:35c2c1cf29cd 20 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 390:35c2c1cf29cd 21 to endorse or promote products derived from this software without
mbed_official 390:35c2c1cf29cd 22 specific prior written permission.
mbed_official 390:35c2c1cf29cd 23 *
mbed_official 390:35c2c1cf29cd 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 390:35c2c1cf29cd 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 390:35c2c1cf29cd 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 390:35c2c1cf29cd 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 390:35c2c1cf29cd 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 390:35c2c1cf29cd 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 390:35c2c1cf29cd 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 390:35c2c1cf29cd 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 390:35c2c1cf29cd 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 390:35c2c1cf29cd 34 POSSIBILITY OF SUCH DAMAGE.
mbed_official 390:35c2c1cf29cd 35 ---------------------------------------------------------------------------*/
mbed_official 390:35c2c1cf29cd 36
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38 #ifndef __CORE_CAFUNC_H__
mbed_official 390:35c2c1cf29cd 39 #define __CORE_CAFUNC_H__
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41
mbed_official 390:35c2c1cf29cd 42 /* ########################### Core Function Access ########################### */
mbed_official 390:35c2c1cf29cd 43 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 390:35c2c1cf29cd 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mbed_official 390:35c2c1cf29cd 45 @{
mbed_official 390:35c2c1cf29cd 46 */
mbed_official 390:35c2c1cf29cd 47
mbed_official 390:35c2c1cf29cd 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mbed_official 390:35c2c1cf29cd 49 /* ARM armcc specific functions */
mbed_official 390:35c2c1cf29cd 50
mbed_official 390:35c2c1cf29cd 51 #if (__ARMCC_VERSION < 400677)
mbed_official 390:35c2c1cf29cd 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mbed_official 390:35c2c1cf29cd 53 #endif
mbed_official 390:35c2c1cf29cd 54
mbed_official 390:35c2c1cf29cd 55 #define MODE_USR 0x10
mbed_official 390:35c2c1cf29cd 56 #define MODE_FIQ 0x11
mbed_official 390:35c2c1cf29cd 57 #define MODE_IRQ 0x12
mbed_official 390:35c2c1cf29cd 58 #define MODE_SVC 0x13
mbed_official 390:35c2c1cf29cd 59 #define MODE_MON 0x16
mbed_official 390:35c2c1cf29cd 60 #define MODE_ABT 0x17
mbed_official 390:35c2c1cf29cd 61 #define MODE_HYP 0x1A
mbed_official 390:35c2c1cf29cd 62 #define MODE_UND 0x1B
mbed_official 390:35c2c1cf29cd 63 #define MODE_SYS 0x1F
mbed_official 390:35c2c1cf29cd 64
mbed_official 390:35c2c1cf29cd 65 /** \brief Get APSR Register
mbed_official 390:35c2c1cf29cd 66
mbed_official 390:35c2c1cf29cd 67 This function returns the content of the APSR Register.
mbed_official 390:35c2c1cf29cd 68
mbed_official 390:35c2c1cf29cd 69 \return APSR Register value
mbed_official 390:35c2c1cf29cd 70 */
mbed_official 390:35c2c1cf29cd 71 __STATIC_INLINE uint32_t __get_APSR(void)
mbed_official 390:35c2c1cf29cd 72 {
mbed_official 390:35c2c1cf29cd 73 register uint32_t __regAPSR __ASM("apsr");
mbed_official 390:35c2c1cf29cd 74 return(__regAPSR);
mbed_official 390:35c2c1cf29cd 75 }
mbed_official 390:35c2c1cf29cd 76
mbed_official 390:35c2c1cf29cd 77
mbed_official 390:35c2c1cf29cd 78 /** \brief Get CPSR Register
mbed_official 390:35c2c1cf29cd 79
mbed_official 390:35c2c1cf29cd 80 This function returns the content of the CPSR Register.
mbed_official 390:35c2c1cf29cd 81
mbed_official 390:35c2c1cf29cd 82 \return CPSR Register value
mbed_official 390:35c2c1cf29cd 83 */
mbed_official 390:35c2c1cf29cd 84 __STATIC_INLINE uint32_t __get_CPSR(void)
mbed_official 390:35c2c1cf29cd 85 {
mbed_official 390:35c2c1cf29cd 86 register uint32_t __regCPSR __ASM("cpsr");
mbed_official 390:35c2c1cf29cd 87 return(__regCPSR);
mbed_official 390:35c2c1cf29cd 88 }
mbed_official 390:35c2c1cf29cd 89
mbed_official 390:35c2c1cf29cd 90 /** \brief Set Stack Pointer
mbed_official 390:35c2c1cf29cd 91
mbed_official 390:35c2c1cf29cd 92 This function assigns the given value to the current stack pointer.
mbed_official 390:35c2c1cf29cd 93
mbed_official 390:35c2c1cf29cd 94 \param [in] topOfStack Stack Pointer value to set
mbed_official 390:35c2c1cf29cd 95 */
mbed_official 390:35c2c1cf29cd 96 register uint32_t __regSP __ASM("sp");
mbed_official 390:35c2c1cf29cd 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mbed_official 390:35c2c1cf29cd 98 {
mbed_official 390:35c2c1cf29cd 99 __regSP = topOfStack;
mbed_official 390:35c2c1cf29cd 100 }
mbed_official 390:35c2c1cf29cd 101
mbed_official 390:35c2c1cf29cd 102
mbed_official 390:35c2c1cf29cd 103 /** \brief Get link register
mbed_official 390:35c2c1cf29cd 104
mbed_official 390:35c2c1cf29cd 105 This function returns the value of the link register
mbed_official 390:35c2c1cf29cd 106
mbed_official 390:35c2c1cf29cd 107 \return Value of link register
mbed_official 390:35c2c1cf29cd 108 */
mbed_official 390:35c2c1cf29cd 109 register uint32_t __reglr __ASM("lr");
mbed_official 390:35c2c1cf29cd 110 __STATIC_INLINE uint32_t __get_LR(void)
mbed_official 390:35c2c1cf29cd 111 {
mbed_official 390:35c2c1cf29cd 112 return(__reglr);
mbed_official 390:35c2c1cf29cd 113 }
mbed_official 390:35c2c1cf29cd 114
mbed_official 390:35c2c1cf29cd 115 /** \brief Set link register
mbed_official 390:35c2c1cf29cd 116
mbed_official 390:35c2c1cf29cd 117 This function sets the value of the link register
mbed_official 390:35c2c1cf29cd 118
mbed_official 390:35c2c1cf29cd 119 \param [in] lr LR value to set
mbed_official 390:35c2c1cf29cd 120 */
mbed_official 390:35c2c1cf29cd 121 __STATIC_INLINE void __set_LR(uint32_t lr)
mbed_official 390:35c2c1cf29cd 122 {
mbed_official 390:35c2c1cf29cd 123 __reglr = lr;
mbed_official 390:35c2c1cf29cd 124 }
mbed_official 390:35c2c1cf29cd 125
mbed_official 390:35c2c1cf29cd 126 /** \brief Set Process Stack Pointer
mbed_official 390:35c2c1cf29cd 127
mbed_official 390:35c2c1cf29cd 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mbed_official 390:35c2c1cf29cd 129
mbed_official 390:35c2c1cf29cd 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mbed_official 390:35c2c1cf29cd 131 */
mbed_official 390:35c2c1cf29cd 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
mbed_official 390:35c2c1cf29cd 133 {
mbed_official 390:35c2c1cf29cd 134 ARM
mbed_official 390:35c2c1cf29cd 135 PRESERVE8
mbed_official 390:35c2c1cf29cd 136
mbed_official 390:35c2c1cf29cd 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
mbed_official 390:35c2c1cf29cd 138 MRS R1, CPSR
mbed_official 390:35c2c1cf29cd 139 CPS #MODE_SYS ;no effect in USR mode
mbed_official 390:35c2c1cf29cd 140 MOV SP, R0
mbed_official 390:35c2c1cf29cd 141 MSR CPSR_c, R1 ;no effect in USR mode
mbed_official 390:35c2c1cf29cd 142 ISB
mbed_official 390:35c2c1cf29cd 143 BX LR
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145 }
mbed_official 390:35c2c1cf29cd 146
mbed_official 390:35c2c1cf29cd 147 /** \brief Set User Mode
mbed_official 390:35c2c1cf29cd 148
mbed_official 390:35c2c1cf29cd 149 This function changes the processor state to User Mode
mbed_official 390:35c2c1cf29cd 150
mbed_official 390:35c2c1cf29cd 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mbed_official 390:35c2c1cf29cd 152 */
mbed_official 390:35c2c1cf29cd 153 __STATIC_ASM void __set_CPS_USR(void)
mbed_official 390:35c2c1cf29cd 154 {
mbed_official 390:35c2c1cf29cd 155 ARM
mbed_official 390:35c2c1cf29cd 156
mbed_official 390:35c2c1cf29cd 157 CPS #MODE_USR
mbed_official 390:35c2c1cf29cd 158 BX LR
mbed_official 390:35c2c1cf29cd 159 }
mbed_official 390:35c2c1cf29cd 160
mbed_official 390:35c2c1cf29cd 161
mbed_official 390:35c2c1cf29cd 162 /** \brief Enable FIQ
mbed_official 390:35c2c1cf29cd 163
mbed_official 390:35c2c1cf29cd 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mbed_official 390:35c2c1cf29cd 165 Can only be executed in Privileged modes.
mbed_official 390:35c2c1cf29cd 166 */
mbed_official 390:35c2c1cf29cd 167 #define __enable_fault_irq __enable_fiq
mbed_official 390:35c2c1cf29cd 168
mbed_official 390:35c2c1cf29cd 169
mbed_official 390:35c2c1cf29cd 170 /** \brief Disable FIQ
mbed_official 390:35c2c1cf29cd 171
mbed_official 390:35c2c1cf29cd 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mbed_official 390:35c2c1cf29cd 173 Can only be executed in Privileged modes.
mbed_official 390:35c2c1cf29cd 174 */
mbed_official 390:35c2c1cf29cd 175 #define __disable_fault_irq __disable_fiq
mbed_official 390:35c2c1cf29cd 176
mbed_official 390:35c2c1cf29cd 177
mbed_official 390:35c2c1cf29cd 178 /** \brief Get FPSCR
mbed_official 390:35c2c1cf29cd 179
mbed_official 390:35c2c1cf29cd 180 This function returns the current value of the Floating Point Status/Control register.
mbed_official 390:35c2c1cf29cd 181
mbed_official 390:35c2c1cf29cd 182 \return Floating Point Status/Control register value
mbed_official 390:35c2c1cf29cd 183 */
mbed_official 390:35c2c1cf29cd 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
mbed_official 390:35c2c1cf29cd 185 {
mbed_official 390:35c2c1cf29cd 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 390:35c2c1cf29cd 187 register uint32_t __regfpscr __ASM("fpscr");
mbed_official 390:35c2c1cf29cd 188 return(__regfpscr);
mbed_official 390:35c2c1cf29cd 189 #else
mbed_official 390:35c2c1cf29cd 190 return(0);
mbed_official 390:35c2c1cf29cd 191 #endif
mbed_official 390:35c2c1cf29cd 192 }
mbed_official 390:35c2c1cf29cd 193
mbed_official 390:35c2c1cf29cd 194
mbed_official 390:35c2c1cf29cd 195 /** \brief Set FPSCR
mbed_official 390:35c2c1cf29cd 196
mbed_official 390:35c2c1cf29cd 197 This function assigns the given value to the Floating Point Status/Control register.
mbed_official 390:35c2c1cf29cd 198
mbed_official 390:35c2c1cf29cd 199 \param [in] fpscr Floating Point Status/Control value to set
mbed_official 390:35c2c1cf29cd 200 */
mbed_official 390:35c2c1cf29cd 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mbed_official 390:35c2c1cf29cd 202 {
mbed_official 390:35c2c1cf29cd 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 390:35c2c1cf29cd 204 register uint32_t __regfpscr __ASM("fpscr");
mbed_official 390:35c2c1cf29cd 205 __regfpscr = (fpscr);
mbed_official 390:35c2c1cf29cd 206 #endif
mbed_official 390:35c2c1cf29cd 207 }
mbed_official 390:35c2c1cf29cd 208
mbed_official 390:35c2c1cf29cd 209 /** \brief Get FPEXC
mbed_official 390:35c2c1cf29cd 210
mbed_official 390:35c2c1cf29cd 211 This function returns the current value of the Floating Point Exception Control register.
mbed_official 390:35c2c1cf29cd 212
mbed_official 390:35c2c1cf29cd 213 \return Floating Point Exception Control register value
mbed_official 390:35c2c1cf29cd 214 */
mbed_official 390:35c2c1cf29cd 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
mbed_official 390:35c2c1cf29cd 216 {
mbed_official 390:35c2c1cf29cd 217 #if (__FPU_PRESENT == 1)
mbed_official 390:35c2c1cf29cd 218 register uint32_t __regfpexc __ASM("fpexc");
mbed_official 390:35c2c1cf29cd 219 return(__regfpexc);
mbed_official 390:35c2c1cf29cd 220 #else
mbed_official 390:35c2c1cf29cd 221 return(0);
mbed_official 390:35c2c1cf29cd 222 #endif
mbed_official 390:35c2c1cf29cd 223 }
mbed_official 390:35c2c1cf29cd 224
mbed_official 390:35c2c1cf29cd 225
mbed_official 390:35c2c1cf29cd 226 /** \brief Set FPEXC
mbed_official 390:35c2c1cf29cd 227
mbed_official 390:35c2c1cf29cd 228 This function assigns the given value to the Floating Point Exception Control register.
mbed_official 390:35c2c1cf29cd 229
mbed_official 390:35c2c1cf29cd 230 \param [in] fpscr Floating Point Exception Control value to set
mbed_official 390:35c2c1cf29cd 231 */
mbed_official 390:35c2c1cf29cd 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mbed_official 390:35c2c1cf29cd 233 {
mbed_official 390:35c2c1cf29cd 234 #if (__FPU_PRESENT == 1)
mbed_official 390:35c2c1cf29cd 235 register uint32_t __regfpexc __ASM("fpexc");
mbed_official 390:35c2c1cf29cd 236 __regfpexc = (fpexc);
mbed_official 390:35c2c1cf29cd 237 #endif
mbed_official 390:35c2c1cf29cd 238 }
mbed_official 390:35c2c1cf29cd 239
mbed_official 390:35c2c1cf29cd 240 /** \brief Get CPACR
mbed_official 390:35c2c1cf29cd 241
mbed_official 390:35c2c1cf29cd 242 This function returns the current value of the Coprocessor Access Control register.
mbed_official 390:35c2c1cf29cd 243
mbed_official 390:35c2c1cf29cd 244 \return Coprocessor Access Control register value
mbed_official 390:35c2c1cf29cd 245 */
mbed_official 390:35c2c1cf29cd 246 __STATIC_INLINE uint32_t __get_CPACR(void)
mbed_official 390:35c2c1cf29cd 247 {
mbed_official 390:35c2c1cf29cd 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbed_official 390:35c2c1cf29cd 249 return __regCPACR;
mbed_official 390:35c2c1cf29cd 250 }
mbed_official 390:35c2c1cf29cd 251
mbed_official 390:35c2c1cf29cd 252 /** \brief Set CPACR
mbed_official 390:35c2c1cf29cd 253
mbed_official 390:35c2c1cf29cd 254 This function assigns the given value to the Coprocessor Access Control register.
mbed_official 390:35c2c1cf29cd 255
mbed_official 390:35c2c1cf29cd 256 \param [in] cpacr Coporcessor Acccess Control value to set
mbed_official 390:35c2c1cf29cd 257 */
mbed_official 390:35c2c1cf29cd 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mbed_official 390:35c2c1cf29cd 259 {
mbed_official 390:35c2c1cf29cd 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbed_official 390:35c2c1cf29cd 261 __regCPACR = cpacr;
mbed_official 390:35c2c1cf29cd 262 __ISB();
mbed_official 390:35c2c1cf29cd 263 }
mbed_official 390:35c2c1cf29cd 264
mbed_official 390:35c2c1cf29cd 265 /** \brief Get CBAR
mbed_official 390:35c2c1cf29cd 266
mbed_official 390:35c2c1cf29cd 267 This function returns the value of the Configuration Base Address register.
mbed_official 390:35c2c1cf29cd 268
mbed_official 390:35c2c1cf29cd 269 \return Configuration Base Address register value
mbed_official 390:35c2c1cf29cd 270 */
mbed_official 390:35c2c1cf29cd 271 __STATIC_INLINE uint32_t __get_CBAR() {
mbed_official 390:35c2c1cf29cd 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mbed_official 390:35c2c1cf29cd 273 return(__regCBAR);
mbed_official 390:35c2c1cf29cd 274 }
mbed_official 390:35c2c1cf29cd 275
mbed_official 390:35c2c1cf29cd 276 /** \brief Get TTBR0
mbed_official 390:35c2c1cf29cd 277
mbed_official 390:35c2c1cf29cd 278 This function returns the value of the Configuration Base Address register.
mbed_official 390:35c2c1cf29cd 279
mbed_official 390:35c2c1cf29cd 280 \return Translation Table Base Register 0 value
mbed_official 390:35c2c1cf29cd 281 */
mbed_official 390:35c2c1cf29cd 282 __STATIC_INLINE uint32_t __get_TTBR0() {
mbed_official 390:35c2c1cf29cd 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbed_official 390:35c2c1cf29cd 284 return(__regTTBR0);
mbed_official 390:35c2c1cf29cd 285 }
mbed_official 390:35c2c1cf29cd 286
mbed_official 390:35c2c1cf29cd 287 /** \brief Set TTBR0
mbed_official 390:35c2c1cf29cd 288
mbed_official 390:35c2c1cf29cd 289 This function assigns the given value to the Coprocessor Access Control register.
mbed_official 390:35c2c1cf29cd 290
mbed_official 390:35c2c1cf29cd 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
mbed_official 390:35c2c1cf29cd 292 */
mbed_official 390:35c2c1cf29cd 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mbed_official 390:35c2c1cf29cd 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbed_official 390:35c2c1cf29cd 295 __regTTBR0 = ttbr0;
mbed_official 390:35c2c1cf29cd 296 __ISB();
mbed_official 390:35c2c1cf29cd 297 }
mbed_official 390:35c2c1cf29cd 298
mbed_official 390:35c2c1cf29cd 299 /** \brief Get DACR
mbed_official 390:35c2c1cf29cd 300
mbed_official 390:35c2c1cf29cd 301 This function returns the value of the Domain Access Control Register.
mbed_official 390:35c2c1cf29cd 302
mbed_official 390:35c2c1cf29cd 303 \return Domain Access Control Register value
mbed_official 390:35c2c1cf29cd 304 */
mbed_official 390:35c2c1cf29cd 305 __STATIC_INLINE uint32_t __get_DACR() {
mbed_official 390:35c2c1cf29cd 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbed_official 390:35c2c1cf29cd 307 return(__regDACR);
mbed_official 390:35c2c1cf29cd 308 }
mbed_official 390:35c2c1cf29cd 309
mbed_official 390:35c2c1cf29cd 310 /** \brief Set DACR
mbed_official 390:35c2c1cf29cd 311
mbed_official 390:35c2c1cf29cd 312 This function assigns the given value to the Coprocessor Access Control register.
mbed_official 390:35c2c1cf29cd 313
mbed_official 390:35c2c1cf29cd 314 \param [in] dacr Domain Access Control Register value to set
mbed_official 390:35c2c1cf29cd 315 */
mbed_official 390:35c2c1cf29cd 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mbed_official 390:35c2c1cf29cd 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbed_official 390:35c2c1cf29cd 318 __regDACR = dacr;
mbed_official 390:35c2c1cf29cd 319 __ISB();
mbed_official 390:35c2c1cf29cd 320 }
mbed_official 390:35c2c1cf29cd 321
mbed_official 390:35c2c1cf29cd 322 /******************************** Cache and BTAC enable ****************************************************/
mbed_official 390:35c2c1cf29cd 323
mbed_official 390:35c2c1cf29cd 324 /** \brief Set SCTLR
mbed_official 390:35c2c1cf29cd 325
mbed_official 390:35c2c1cf29cd 326 This function assigns the given value to the System Control Register.
mbed_official 390:35c2c1cf29cd 327
mbed_official 390:35c2c1cf29cd 328 \param [in] sctlr System Control Register, value to set
mbed_official 390:35c2c1cf29cd 329 */
mbed_official 390:35c2c1cf29cd 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mbed_official 390:35c2c1cf29cd 331 {
mbed_official 390:35c2c1cf29cd 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbed_official 390:35c2c1cf29cd 333 __regSCTLR = sctlr;
mbed_official 390:35c2c1cf29cd 334 }
mbed_official 390:35c2c1cf29cd 335
mbed_official 390:35c2c1cf29cd 336 /** \brief Get SCTLR
mbed_official 390:35c2c1cf29cd 337
mbed_official 390:35c2c1cf29cd 338 This function returns the value of the System Control Register.
mbed_official 390:35c2c1cf29cd 339
mbed_official 390:35c2c1cf29cd 340 \return System Control Register value
mbed_official 390:35c2c1cf29cd 341 */
mbed_official 390:35c2c1cf29cd 342 __STATIC_INLINE uint32_t __get_SCTLR() {
mbed_official 390:35c2c1cf29cd 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbed_official 390:35c2c1cf29cd 344 return(__regSCTLR);
mbed_official 390:35c2c1cf29cd 345 }
mbed_official 390:35c2c1cf29cd 346
mbed_official 390:35c2c1cf29cd 347 /** \brief Enable Caches
mbed_official 390:35c2c1cf29cd 348
mbed_official 390:35c2c1cf29cd 349 Enable Caches
mbed_official 390:35c2c1cf29cd 350 */
mbed_official 390:35c2c1cf29cd 351 __STATIC_INLINE void __enable_caches(void) {
mbed_official 390:35c2c1cf29cd 352 // Set I bit 12 to enable I Cache
mbed_official 390:35c2c1cf29cd 353 // Set C bit 2 to enable D Cache
mbed_official 390:35c2c1cf29cd 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mbed_official 390:35c2c1cf29cd 355 }
mbed_official 390:35c2c1cf29cd 356
mbed_official 390:35c2c1cf29cd 357 /** \brief Disable Caches
mbed_official 390:35c2c1cf29cd 358
mbed_official 390:35c2c1cf29cd 359 Disable Caches
mbed_official 390:35c2c1cf29cd 360 */
mbed_official 390:35c2c1cf29cd 361 __STATIC_INLINE void __disable_caches(void) {
mbed_official 390:35c2c1cf29cd 362 // Clear I bit 12 to disable I Cache
mbed_official 390:35c2c1cf29cd 363 // Clear C bit 2 to disable D Cache
mbed_official 390:35c2c1cf29cd 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mbed_official 390:35c2c1cf29cd 365 __ISB();
mbed_official 390:35c2c1cf29cd 366 }
mbed_official 390:35c2c1cf29cd 367
mbed_official 390:35c2c1cf29cd 368 /** \brief Enable BTAC
mbed_official 390:35c2c1cf29cd 369
mbed_official 390:35c2c1cf29cd 370 Enable BTAC
mbed_official 390:35c2c1cf29cd 371 */
mbed_official 390:35c2c1cf29cd 372 __STATIC_INLINE void __enable_btac(void) {
mbed_official 390:35c2c1cf29cd 373 // Set Z bit 11 to enable branch prediction
mbed_official 390:35c2c1cf29cd 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
mbed_official 390:35c2c1cf29cd 375 __ISB();
mbed_official 390:35c2c1cf29cd 376 }
mbed_official 390:35c2c1cf29cd 377
mbed_official 390:35c2c1cf29cd 378 /** \brief Disable BTAC
mbed_official 390:35c2c1cf29cd 379
mbed_official 390:35c2c1cf29cd 380 Disable BTAC
mbed_official 390:35c2c1cf29cd 381 */
mbed_official 390:35c2c1cf29cd 382 __STATIC_INLINE void __disable_btac(void) {
mbed_official 390:35c2c1cf29cd 383 // Clear Z bit 11 to disable branch prediction
mbed_official 390:35c2c1cf29cd 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mbed_official 390:35c2c1cf29cd 385 }
mbed_official 390:35c2c1cf29cd 386
mbed_official 390:35c2c1cf29cd 387
mbed_official 390:35c2c1cf29cd 388 /** \brief Enable MMU
mbed_official 390:35c2c1cf29cd 389
mbed_official 390:35c2c1cf29cd 390 Enable MMU
mbed_official 390:35c2c1cf29cd 391 */
mbed_official 390:35c2c1cf29cd 392 __STATIC_INLINE void __enable_mmu(void) {
mbed_official 390:35c2c1cf29cd 393 // Set M bit 0 to enable the MMU
mbed_official 390:35c2c1cf29cd 394 // Set AFE bit to enable simplified access permissions model
mbed_official 390:35c2c1cf29cd 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mbed_official 390:35c2c1cf29cd 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mbed_official 390:35c2c1cf29cd 397 __ISB();
mbed_official 390:35c2c1cf29cd 398 }
mbed_official 390:35c2c1cf29cd 399
mbed_official 390:35c2c1cf29cd 400 /** \brief Enable MMU
mbed_official 390:35c2c1cf29cd 401
mbed_official 390:35c2c1cf29cd 402 Enable MMU
mbed_official 390:35c2c1cf29cd 403 */
mbed_official 390:35c2c1cf29cd 404 __STATIC_INLINE void __disable_mmu(void) {
mbed_official 390:35c2c1cf29cd 405 // Clear M bit 0 to disable the MMU
mbed_official 390:35c2c1cf29cd 406 __set_SCTLR( __get_SCTLR() & ~1);
mbed_official 390:35c2c1cf29cd 407 __ISB();
mbed_official 390:35c2c1cf29cd 408 }
mbed_official 390:35c2c1cf29cd 409
mbed_official 390:35c2c1cf29cd 410 /******************************** TLB maintenance operations ************************************************/
mbed_official 390:35c2c1cf29cd 411 /** \brief Invalidate the whole tlb
mbed_official 390:35c2c1cf29cd 412
mbed_official 390:35c2c1cf29cd 413 TLBIALL. Invalidate the whole tlb
mbed_official 390:35c2c1cf29cd 414 */
mbed_official 390:35c2c1cf29cd 415
mbed_official 390:35c2c1cf29cd 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mbed_official 390:35c2c1cf29cd 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mbed_official 390:35c2c1cf29cd 418 __TLBIALL = 0;
mbed_official 390:35c2c1cf29cd 419 __DSB();
mbed_official 390:35c2c1cf29cd 420 __ISB();
mbed_official 390:35c2c1cf29cd 421 }
mbed_official 390:35c2c1cf29cd 422
mbed_official 390:35c2c1cf29cd 423 /******************************** BTB maintenance operations ************************************************/
mbed_official 390:35c2c1cf29cd 424 /** \brief Invalidate entire branch predictor array
mbed_official 390:35c2c1cf29cd 425
mbed_official 390:35c2c1cf29cd 426 BPIALL. Branch Predictor Invalidate All.
mbed_official 390:35c2c1cf29cd 427 */
mbed_official 390:35c2c1cf29cd 428
mbed_official 390:35c2c1cf29cd 429 __STATIC_INLINE void __v7_inv_btac(void) {
mbed_official 390:35c2c1cf29cd 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mbed_official 390:35c2c1cf29cd 431 __BPIALL = 0;
mbed_official 390:35c2c1cf29cd 432 __DSB(); //ensure completion of the invalidation
mbed_official 390:35c2c1cf29cd 433 __ISB(); //ensure instruction fetch path sees new state
mbed_official 390:35c2c1cf29cd 434 }
mbed_official 390:35c2c1cf29cd 435
mbed_official 390:35c2c1cf29cd 436
mbed_official 390:35c2c1cf29cd 437 /******************************** L1 cache operations ******************************************************/
mbed_official 390:35c2c1cf29cd 438
mbed_official 390:35c2c1cf29cd 439 /** \brief Invalidate the whole I$
mbed_official 390:35c2c1cf29cd 440
mbed_official 390:35c2c1cf29cd 441 ICIALLU. Instruction Cache Invalidate All to PoU
mbed_official 390:35c2c1cf29cd 442 */
mbed_official 390:35c2c1cf29cd 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
mbed_official 390:35c2c1cf29cd 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mbed_official 390:35c2c1cf29cd 445 __ICIALLU = 0;
mbed_official 390:35c2c1cf29cd 446 __DSB(); //ensure completion of the invalidation
mbed_official 390:35c2c1cf29cd 447 __ISB(); //ensure instruction fetch path sees new I cache state
mbed_official 390:35c2c1cf29cd 448 }
mbed_official 390:35c2c1cf29cd 449
mbed_official 390:35c2c1cf29cd 450 /** \brief Clean D$ by MVA
mbed_official 390:35c2c1cf29cd 451
mbed_official 390:35c2c1cf29cd 452 DCCMVAC. Data cache clean by MVA to PoC
mbed_official 390:35c2c1cf29cd 453 */
mbed_official 390:35c2c1cf29cd 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mbed_official 390:35c2c1cf29cd 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mbed_official 390:35c2c1cf29cd 456 __DCCMVAC = (uint32_t)va;
mbed_official 390:35c2c1cf29cd 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 390:35c2c1cf29cd 458 }
mbed_official 390:35c2c1cf29cd 459
mbed_official 390:35c2c1cf29cd 460 /** \brief Invalidate D$ by MVA
mbed_official 390:35c2c1cf29cd 461
mbed_official 390:35c2c1cf29cd 462 DCIMVAC. Data cache invalidate by MVA to PoC
mbed_official 390:35c2c1cf29cd 463 */
mbed_official 390:35c2c1cf29cd 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mbed_official 390:35c2c1cf29cd 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mbed_official 390:35c2c1cf29cd 466 __DCIMVAC = (uint32_t)va;
mbed_official 390:35c2c1cf29cd 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 390:35c2c1cf29cd 468 }
mbed_official 390:35c2c1cf29cd 469
mbed_official 390:35c2c1cf29cd 470 /** \brief Clean and Invalidate D$ by MVA
mbed_official 390:35c2c1cf29cd 471
mbed_official 390:35c2c1cf29cd 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mbed_official 390:35c2c1cf29cd 473 */
mbed_official 390:35c2c1cf29cd 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mbed_official 390:35c2c1cf29cd 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mbed_official 390:35c2c1cf29cd 476 __DCCIMVAC = (uint32_t)va;
mbed_official 390:35c2c1cf29cd 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 390:35c2c1cf29cd 478 }
mbed_official 390:35c2c1cf29cd 479
mbed_official 390:35c2c1cf29cd 480 /** \brief
mbed_official 390:35c2c1cf29cd 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mbed_official 390:35c2c1cf29cd 482 */
mbed_official 390:35c2c1cf29cd 483 #pragma push
mbed_official 390:35c2c1cf29cd 484 #pragma arm
mbed_official 390:35c2c1cf29cd 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
mbed_official 390:35c2c1cf29cd 486 ARM
mbed_official 390:35c2c1cf29cd 487
mbed_official 390:35c2c1cf29cd 488 PUSH {R4-R11}
mbed_official 390:35c2c1cf29cd 489
mbed_official 390:35c2c1cf29cd 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
mbed_official 390:35c2c1cf29cd 491 ANDS R3, R6, #0x07000000 // Extract coherency level
mbed_official 390:35c2c1cf29cd 492 MOV R3, R3, LSR #23 // Total cache levels << 1
mbed_official 390:35c2c1cf29cd 493 BEQ Finished // If 0, no need to clean
mbed_official 390:35c2c1cf29cd 494
mbed_official 390:35c2c1cf29cd 495 MOV R10, #0 // R10 holds current cache level << 1
mbed_official 390:35c2c1cf29cd 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
mbed_official 390:35c2c1cf29cd 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
mbed_official 390:35c2c1cf29cd 498 AND R1, R1, #7 // Isolate those lower 3 bits
mbed_official 390:35c2c1cf29cd 499 CMP R1, #2
mbed_official 390:35c2c1cf29cd 500 BLT Skip // No cache or only instruction cache at this level
mbed_official 390:35c2c1cf29cd 501
mbed_official 390:35c2c1cf29cd 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
mbed_official 390:35c2c1cf29cd 503 ISB // ISB to sync the change to the CacheSizeID reg
mbed_official 390:35c2c1cf29cd 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
mbed_official 390:35c2c1cf29cd 505 AND R2, R1, #7 // Extract the line length field
mbed_official 390:35c2c1cf29cd 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
mbed_official 390:35c2c1cf29cd 507 LDR R4, =0x3FF
mbed_official 390:35c2c1cf29cd 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
mbed_official 390:35c2c1cf29cd 509 CLZ R5, R4 // R5 is the bit position of the way size increment
mbed_official 390:35c2c1cf29cd 510 LDR R7, =0x7FFF
mbed_official 390:35c2c1cf29cd 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
mbed_official 390:35c2c1cf29cd 512
mbed_official 390:35c2c1cf29cd 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
mbed_official 390:35c2c1cf29cd 514
mbed_official 390:35c2c1cf29cd 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
mbed_official 390:35c2c1cf29cd 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
mbed_official 390:35c2c1cf29cd 517 CMP R0, #0
mbed_official 390:35c2c1cf29cd 518 BNE Dccsw
mbed_official 390:35c2c1cf29cd 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 520 B cont
mbed_official 390:35c2c1cf29cd 521 Dccsw CMP R0, #1
mbed_official 390:35c2c1cf29cd 522 BNE Dccisw
mbed_official 390:35c2c1cf29cd 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
mbed_official 390:35c2c1cf29cd 524 B cont
mbed_official 390:35c2c1cf29cd 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 526 cont SUBS R9, R9, #1 // Decrement the Way number
mbed_official 390:35c2c1cf29cd 527 BGE Loop3
mbed_official 390:35c2c1cf29cd 528 SUBS R7, R7, #1 // Decrement the Set number
mbed_official 390:35c2c1cf29cd 529 BGE Loop2
mbed_official 390:35c2c1cf29cd 530 Skip ADD R10, R10, #2 // increment the cache number
mbed_official 390:35c2c1cf29cd 531 CMP R3, R10
mbed_official 390:35c2c1cf29cd 532 BGT Loop1
mbed_official 390:35c2c1cf29cd 533
mbed_official 390:35c2c1cf29cd 534 Finished
mbed_official 390:35c2c1cf29cd 535 DSB
mbed_official 390:35c2c1cf29cd 536 POP {R4-R11}
mbed_official 390:35c2c1cf29cd 537 BX lr
mbed_official 390:35c2c1cf29cd 538
mbed_official 390:35c2c1cf29cd 539 }
mbed_official 390:35c2c1cf29cd 540 #pragma pop
mbed_official 390:35c2c1cf29cd 541
mbed_official 390:35c2c1cf29cd 542 /** \brief __v7_all_cache - helper function
mbed_official 390:35c2c1cf29cd 543
mbed_official 390:35c2c1cf29cd 544 */
mbed_official 390:35c2c1cf29cd 545
mbed_official 390:35c2c1cf29cd 546 /** \brief Invalidate the whole D$
mbed_official 390:35c2c1cf29cd 547
mbed_official 390:35c2c1cf29cd 548 DCISW. Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 549 */
mbed_official 390:35c2c1cf29cd 550
mbed_official 390:35c2c1cf29cd 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mbed_official 390:35c2c1cf29cd 552 __v7_all_cache(0);
mbed_official 390:35c2c1cf29cd 553 }
mbed_official 390:35c2c1cf29cd 554
mbed_official 390:35c2c1cf29cd 555 /** \brief Clean the whole D$
mbed_official 390:35c2c1cf29cd 556
mbed_official 390:35c2c1cf29cd 557 DCCSW. Clean by Set/Way
mbed_official 390:35c2c1cf29cd 558 */
mbed_official 390:35c2c1cf29cd 559
mbed_official 390:35c2c1cf29cd 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
mbed_official 390:35c2c1cf29cd 561 __v7_all_cache(1);
mbed_official 390:35c2c1cf29cd 562 }
mbed_official 390:35c2c1cf29cd 563
mbed_official 390:35c2c1cf29cd 564 /** \brief Clean and invalidate the whole D$
mbed_official 390:35c2c1cf29cd 565
mbed_official 390:35c2c1cf29cd 566 DCCISW. Clean and Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 567 */
mbed_official 390:35c2c1cf29cd 568
mbed_official 390:35c2c1cf29cd 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mbed_official 390:35c2c1cf29cd 570 __v7_all_cache(2);
mbed_official 390:35c2c1cf29cd 571 }
mbed_official 390:35c2c1cf29cd 572
mbed_official 390:35c2c1cf29cd 573 #include "core_ca_mmu.h"
mbed_official 390:35c2c1cf29cd 574
mbed_official 390:35c2c1cf29cd 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
mbed_official 390:35c2c1cf29cd 576
mbed_official 390:35c2c1cf29cd 577 #error IAR Compiler support not implemented for Cortex-A
mbed_official 390:35c2c1cf29cd 578
mbed_official 390:35c2c1cf29cd 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
mbed_official 390:35c2c1cf29cd 580
mbed_official 390:35c2c1cf29cd 581 //#error GNU Compiler support not implemented for Cortex-A
mbed_official 390:35c2c1cf29cd 582
mbed_official 390:35c2c1cf29cd 583 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
mbed_official 390:35c2c1cf29cd 584
mbed_official 390:35c2c1cf29cd 585 #error TASKING Compiler support not implemented for Cortex-A
mbed_official 390:35c2c1cf29cd 586
mbed_official 390:35c2c1cf29cd 587 #endif
mbed_official 390:35c2c1cf29cd 588
mbed_official 390:35c2c1cf29cd 589 /*@} end of CMSIS_Core_RegAccFunctions */
mbed_official 390:35c2c1cf29cd 590
mbed_official 390:35c2c1cf29cd 591
mbed_official 390:35c2c1cf29cd 592 #endif /* __CORE_CAFUNC_H__ */