Renesas / mbed-src_GR-PEACH_rev_b

mbed library sources for GR-PEACH rev.B.

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c@514:cf59050bad8e, 2015-04-15 (annotated)

Committer:
RyoheiHagimoto
Date:
Wed Apr 15 01:34:29 2015 +0000
Revision:
514:cf59050bad8e
Parent:
82:0b31dbcd4769 
mbed library sources for GR-PEACH rev.B.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 31:42176bc3c368 1 /*
mbed_official 31:42176bc3c368 2 ** ###################################################################
mbed_official 44:2ce89a25b635 3 ** Processors: MKL46Z256VLH4
mbed_official 44:2ce89a25b635 4 ** MKL46Z128VLH4
mbed_official 44:2ce89a25b635 5 ** MKL46Z256VLL4
mbed_official 44:2ce89a25b635 6 ** MKL46Z128VLL4
mbed_official 44:2ce89a25b635 7 ** MKL46Z256VMC4
mbed_official 44:2ce89a25b635 8 ** MKL46Z128VMC4
mbed_official 44:2ce89a25b635 9 **
mbed_official 31:42176bc3c368 10 ** Compilers: ARM Compiler
mbed_official 31:42176bc3c368 11 ** Freescale C/C++ for Embedded ARM
mbed_official 31:42176bc3c368 12 ** GNU C Compiler
mbed_official 31:42176bc3c368 13 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 31:42176bc3c368 14 **
mbed_official 44:2ce89a25b635 15 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
mbed_official 44:2ce89a25b635 16 ** Version: rev. 2.0, 2012-12-12
mbed_official 31:42176bc3c368 17 **
mbed_official 31:42176bc3c368 18 ** Abstract:
mbed_official 31:42176bc3c368 19 ** Provides a system configuration function and a global variable that
mbed_official 31:42176bc3c368 20 ** contains the system frequency. It configures the device and initializes
mbed_official 31:42176bc3c368 21 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 31:42176bc3c368 22 **
mbed_official 44:2ce89a25b635 23 ** Copyright: 2012 Freescale, Inc. All Rights Reserved.
mbed_official 31:42176bc3c368 24 **
mbed_official 31:42176bc3c368 25 ** http: www.freescale.com
mbed_official 31:42176bc3c368 26 ** mail: support@freescale.com
mbed_official 31:42176bc3c368 27 **
mbed_official 31:42176bc3c368 28 ** Revisions:
mbed_official 44:2ce89a25b635 29 ** - rev. 1.0 (2012-10-16)
mbed_official 31:42176bc3c368 30 ** Initial version.
mbed_official 44:2ce89a25b635 31 ** - rev. 2.0 (2012-12-12)
mbed_official 44:2ce89a25b635 32 ** Update to reference manual rev. 1.
mbed_official 31:42176bc3c368 33 **
mbed_official 31:42176bc3c368 34 ** ###################################################################
mbed_official 31:42176bc3c368 35 */
mbed_official 31:42176bc3c368 36
mbed_official 31:42176bc3c368 37 /**
mbed_official 31:42176bc3c368 38 * @file MKL46Z4
mbed_official 44:2ce89a25b635 39 * @version 2.0
mbed_official 44:2ce89a25b635 40 * @date 2012-12-12
mbed_official 31:42176bc3c368 41 * @brief Device specific configuration file for MKL46Z4 (implementation file)
mbed_official 31:42176bc3c368 42 *
mbed_official 31:42176bc3c368 43 * Provides a system configuration function and a global variable that contains
mbed_official 31:42176bc3c368 44 * the system frequency. It configures the device and initializes the oscillator
mbed_official 31:42176bc3c368 45 * (PLL) that is part of the microcontroller device.
mbed_official 31:42176bc3c368 46 */
mbed_official 31:42176bc3c368 47
mbed_official 31:42176bc3c368 48 #include <stdint.h>
mbed_official 31:42176bc3c368 49 #include "MKL46Z4.h"
mbed_official 31:42176bc3c368 50
mbed_official 31:42176bc3c368 51 #define DISABLE_WDOG 1
mbed_official 31:42176bc3c368 52
mbed_official 33:e214068ab66c 53 #define CLOCK_SETUP 1
mbed_official 31:42176bc3c368 54 /* Predefined clock setups
mbed_official 31:42176bc3c368 55 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 31:42176bc3c368 56 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 31:42176bc3c368 57 Core clock = 41.94MHz, BusClock = 13.98MHz
mbed_official 31:42176bc3c368 58 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 31:42176bc3c368 59 Reference clock source for MCG module is an external crystal 8MHz
mbed_official 31:42176bc3c368 60 Core clock = 48MHz, BusClock = 24MHz
mbed_official 31:42176bc3c368 61 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
mbed_official 31:42176bc3c368 62 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
mbed_official 31:42176bc3c368 63 Core clock = 8MHz, BusClock = 8MHz
mbed_official 31:42176bc3c368 64 */
mbed_official 31:42176bc3c368 65
mbed_official 31:42176bc3c368 66 /*----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 67 Define clock source values
mbed_official 31:42176bc3c368 68 *----------------------------------------------------------------------------*/
mbed_official 31:42176bc3c368 69 #if (CLOCK_SETUP == 0)
mbed_official 31:42176bc3c368 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 71 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 72 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 73 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
mbed_official 31:42176bc3c368 74 #elif (CLOCK_SETUP == 1)
mbed_official 31:42176bc3c368 75 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 76 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 77 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 78 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
mbed_official 31:42176bc3c368 79 #elif (CLOCK_SETUP == 2)
mbed_official 31:42176bc3c368 80 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 81 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 82 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 83 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
mbed_official 31:42176bc3c368 84 #endif /* (CLOCK_SETUP == 2) */
mbed_official 31:42176bc3c368 85
mbed_official 31:42176bc3c368 86
mbed_official 31:42176bc3c368 87 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 88 -- Core clock
mbed_official 31:42176bc3c368 89 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 90
mbed_official 31:42176bc3c368 91 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 31:42176bc3c368 92
mbed_official 31:42176bc3c368 93 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 94 -- SystemInit()
mbed_official 31:42176bc3c368 95 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 96
mbed_official 31:42176bc3c368 97 void SystemInit (void) {
mbed_official 31:42176bc3c368 98 #if (DISABLE_WDOG)
mbed_official 31:42176bc3c368 99 /* Disable the WDOG module */
mbed_official 31:42176bc3c368 100 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
mbed_official 31:42176bc3c368 101 SIM->COPC = (uint32_t)0x00u;
mbed_official 31:42176bc3c368 102 #endif /* (DISABLE_WDOG) */
mbed_official 31:42176bc3c368 103 #if (CLOCK_SETUP == 0)
mbed_official 31:42176bc3c368 104 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 31:42176bc3c368 105 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
mbed_official 31:42176bc3c368 106 /* Switch to FEI Mode */
mbed_official 31:42176bc3c368 107 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 108 MCG->C1 = (uint8_t)0x06U;
mbed_official 44:2ce89a25b635 109 /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
mbed_official 44:2ce89a25b635 110 MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
mbed_official 31:42176bc3c368 111 /* MCG->C4: DMX32=0,DRST_DRS=1 */
mbed_official 31:42176bc3c368 112 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
mbed_official 31:42176bc3c368 113 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 31:42176bc3c368 114 OSC0->CR = (uint8_t)0x80U;
mbed_official 31:42176bc3c368 115 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 31:42176bc3c368 116 MCG->C5 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 117 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 118 MCG->C6 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 119 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 31:42176bc3c368 120 }
mbed_official 31:42176bc3c368 121 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 31:42176bc3c368 122 }
mbed_official 31:42176bc3c368 123 #elif (CLOCK_SETUP == 1)
mbed_official 31:42176bc3c368 124 /* SIM->SCGC5: PORTA=1 */
mbed_official 31:42176bc3c368 125 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 31:42176bc3c368 126 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 31:42176bc3c368 127 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
mbed_official 31:42176bc3c368 128 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 129 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 130 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 131 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 132 /* Switch to FBE Mode */
mbed_official 44:2ce89a25b635 133 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 44:2ce89a25b635 134 MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
mbed_official 44:2ce89a25b635 135 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 44:2ce89a25b635 136 OSC0->CR = (uint8_t)0x80U;
mbed_official 44:2ce89a25b635 137 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 138 MCG->C1 = (uint8_t)0x9AU;
mbed_official 31:42176bc3c368 139 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 31:42176bc3c368 140 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 31:42176bc3c368 141 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
mbed_official 31:42176bc3c368 142 MCG->C5 = (uint8_t)0x01U;
mbed_official 31:42176bc3c368 143 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 144 MCG->C6 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 145 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 31:42176bc3c368 146 }
mbed_official 31:42176bc3c368 147 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 148 }
mbed_official 31:42176bc3c368 149 /* Switch to PBE Mode */
mbed_official 31:42176bc3c368 150 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 151 MCG->C6 = (uint8_t)0x40U;
mbed_official 31:42176bc3c368 152 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 153 }
mbed_official 31:42176bc3c368 154 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
mbed_official 31:42176bc3c368 155 }
mbed_official 31:42176bc3c368 156 /* Switch to PEE Mode */
mbed_official 31:42176bc3c368 157 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 158 MCG->C1 = (uint8_t)0x1AU;
mbed_official 31:42176bc3c368 159 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 31:42176bc3c368 160 }
mbed_official 31:42176bc3c368 161 #elif (CLOCK_SETUP == 2)
mbed_official 31:42176bc3c368 162 /* SIM->SCGC5: PORTA=1 */
mbed_official 31:42176bc3c368 163 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 31:42176bc3c368 164 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 31:42176bc3c368 165 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
mbed_official 31:42176bc3c368 166 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 167 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 168 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 169 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 170 /* Switch to FBE Mode */
mbed_official 31:42176bc3c368 171 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 31:42176bc3c368 172 MCG->C2 = (uint8_t)0x24U;
mbed_official 44:2ce89a25b635 173 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 44:2ce89a25b635 174 OSC0->CR = (uint8_t)0x80U;
mbed_official 31:42176bc3c368 175 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 176 MCG->C1 = (uint8_t)0x9AU;
mbed_official 31:42176bc3c368 177 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 31:42176bc3c368 178 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 31:42176bc3c368 179 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 31:42176bc3c368 180 MCG->C5 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 181 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 182 MCG->C6 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 183 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 31:42176bc3c368 184 }
mbed_official 31:42176bc3c368 185 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 186 }
mbed_official 31:42176bc3c368 187 /* Switch to BLPE Mode */
mbed_official 44:2ce89a25b635 188 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
mbed_official 44:2ce89a25b635 189 MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
mbed_official 31:42176bc3c368 190 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 191 }
mbed_official 31:42176bc3c368 192 #endif /* (CLOCK_SETUP == 2) */
mbed_official 31:42176bc3c368 193 }
mbed_official 31:42176bc3c368 194
mbed_official 31:42176bc3c368 195 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 196 -- SystemCoreClockUpdate()
mbed_official 31:42176bc3c368 197 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 198
mbed_official 31:42176bc3c368 199 void SystemCoreClockUpdate (void) {
mbed_official 31:42176bc3c368 200 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 31:42176bc3c368 201 uint8_t Divider;
mbed_official 31:42176bc3c368 202
mbed_official 31:42176bc3c368 203 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 204 /* Output of FLL or PLL is selected */
mbed_official 31:42176bc3c368 205 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 206 /* FLL is selected */
mbed_official 31:42176bc3c368 207 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 208 /* External reference clock is selected */
mbed_official 31:42176bc3c368 209 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 31:42176bc3c368 210 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 31:42176bc3c368 211 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 31:42176bc3c368 212 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 31:42176bc3c368 213 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 31:42176bc3c368 214 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
mbed_official 31:42176bc3c368 215 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 216 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 31:42176bc3c368 217 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 218 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 31:42176bc3c368 219 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 31:42176bc3c368 220 case 0x0u:
mbed_official 31:42176bc3c368 221 MCGOUTClock *= 640u;
mbed_official 31:42176bc3c368 222 break;
mbed_official 31:42176bc3c368 223 case 0x20u:
mbed_official 31:42176bc3c368 224 MCGOUTClock *= 1280u;
mbed_official 31:42176bc3c368 225 break;
mbed_official 31:42176bc3c368 226 case 0x40u:
mbed_official 31:42176bc3c368 227 MCGOUTClock *= 1920u;
mbed_official 31:42176bc3c368 228 break;
mbed_official 31:42176bc3c368 229 case 0x60u:
mbed_official 31:42176bc3c368 230 MCGOUTClock *= 2560u;
mbed_official 31:42176bc3c368 231 break;
mbed_official 31:42176bc3c368 232 case 0x80u:
mbed_official 31:42176bc3c368 233 MCGOUTClock *= 732u;
mbed_official 31:42176bc3c368 234 break;
mbed_official 31:42176bc3c368 235 case 0xA0u:
mbed_official 31:42176bc3c368 236 MCGOUTClock *= 1464u;
mbed_official 31:42176bc3c368 237 break;
mbed_official 31:42176bc3c368 238 case 0xC0u:
mbed_official 31:42176bc3c368 239 MCGOUTClock *= 2197u;
mbed_official 31:42176bc3c368 240 break;
mbed_official 31:42176bc3c368 241 case 0xE0u:
mbed_official 31:42176bc3c368 242 MCGOUTClock *= 2929u;
mbed_official 31:42176bc3c368 243 break;
mbed_official 31:42176bc3c368 244 default:
mbed_official 31:42176bc3c368 245 break;
mbed_official 31:42176bc3c368 246 }
mbed_official 31:42176bc3c368 247 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 248 /* PLL is selected */
mbed_official 31:42176bc3c368 249 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 31:42176bc3c368 250 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 31:42176bc3c368 251 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 31:42176bc3c368 252 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 31:42176bc3c368 253 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 254 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 31:42176bc3c368 255 /* Internal reference clock is selected */
mbed_official 31:42176bc3c368 256 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 257 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 31:42176bc3c368 258 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 259 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 31:42176bc3c368 260 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 261 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 31:42176bc3c368 262 /* External reference clock is selected */
mbed_official 31:42176bc3c368 263 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 31:42176bc3c368 264 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 31:42176bc3c368 265 /* Reserved value */
mbed_official 31:42176bc3c368 266 return;
mbed_official 31:42176bc3c368 267 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 31:42176bc3c368 268 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 31:42176bc3c368 269 }