Renesas / mbed-src_GR-PEACH_rev_b

mbed library sources for GR-PEACH rev.B.

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c@33:e214068ab66c, 2013-10-07 (annotated)

Committer:
mbed_official
Date:
Mon Oct 07 09:15:08 2013 +0100
Revision:
33:e214068ab66c
Parent:
31:42176bc3c368
Child:
44:2ce89a25b635
Synchronized with git revision 53edc82f7373bbfa01a161700524765f52fdb444

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 31:42176bc3c368 1 /*
mbed_official 31:42176bc3c368 2 ** ###################################################################
mbed_official 31:42176bc3c368 3 ** Processor: MKL46Z128VLK4
mbed_official 31:42176bc3c368 4 ** Compilers: ARM Compiler
mbed_official 31:42176bc3c368 5 ** Freescale C/C++ for Embedded ARM
mbed_official 31:42176bc3c368 6 ** GNU C Compiler
mbed_official 31:42176bc3c368 7 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 31:42176bc3c368 8 **
mbed_official 31:42176bc3c368 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
mbed_official 31:42176bc3c368 10 ** Version: rev. 1.1, 2012-06-21
mbed_official 31:42176bc3c368 11 **
mbed_official 31:42176bc3c368 12 ** Abstract:
mbed_official 31:42176bc3c368 13 ** Provides a system configuration function and a global variable that
mbed_official 31:42176bc3c368 14 ** contains the system frequency. It configures the device and initializes
mbed_official 31:42176bc3c368 15 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 31:42176bc3c368 16 **
mbed_official 31:42176bc3c368 17 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
mbed_official 31:42176bc3c368 18 **
mbed_official 31:42176bc3c368 19 ** http: www.freescale.com
mbed_official 31:42176bc3c368 20 ** mail: support@freescale.com
mbed_official 31:42176bc3c368 21 **
mbed_official 31:42176bc3c368 22 ** Revisions:
mbed_official 31:42176bc3c368 23 ** - rev. 1.0 (2012-06-13)
mbed_official 31:42176bc3c368 24 ** Initial version.
mbed_official 31:42176bc3c368 25 ** - rev. 1.1 (2012-06-21)
mbed_official 31:42176bc3c368 26 ** Update according to reference manual rev. 1.
mbed_official 31:42176bc3c368 27 **
mbed_official 31:42176bc3c368 28 ** ###################################################################
mbed_official 31:42176bc3c368 29 */
mbed_official 31:42176bc3c368 30
mbed_official 31:42176bc3c368 31 /**
mbed_official 31:42176bc3c368 32 * @file MKL46Z4
mbed_official 31:42176bc3c368 33 * @version 1.1
mbed_official 31:42176bc3c368 34 * @date 2012-06-21
mbed_official 31:42176bc3c368 35 * @brief Device specific configuration file for MKL46Z4 (implementation file)
mbed_official 31:42176bc3c368 36 *
mbed_official 31:42176bc3c368 37 * Provides a system configuration function and a global variable that contains
mbed_official 31:42176bc3c368 38 * the system frequency. It configures the device and initializes the oscillator
mbed_official 31:42176bc3c368 39 * (PLL) that is part of the microcontroller device.
mbed_official 31:42176bc3c368 40 */
mbed_official 31:42176bc3c368 41
mbed_official 31:42176bc3c368 42 #include <stdint.h>
mbed_official 31:42176bc3c368 43 #include "MKL46Z4.h"
mbed_official 31:42176bc3c368 44
mbed_official 31:42176bc3c368 45 #define DISABLE_WDOG 1
mbed_official 31:42176bc3c368 46
mbed_official 33:e214068ab66c 47 #define CLOCK_SETUP 1
mbed_official 31:42176bc3c368 48 /* Predefined clock setups
mbed_official 31:42176bc3c368 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 31:42176bc3c368 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 31:42176bc3c368 51 Core clock = 41.94MHz, BusClock = 13.98MHz
mbed_official 31:42176bc3c368 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 31:42176bc3c368 53 Reference clock source for MCG module is an external crystal 8MHz
mbed_official 31:42176bc3c368 54 Core clock = 48MHz, BusClock = 24MHz
mbed_official 31:42176bc3c368 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
mbed_official 31:42176bc3c368 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
mbed_official 31:42176bc3c368 57 Core clock = 8MHz, BusClock = 8MHz
mbed_official 31:42176bc3c368 58 */
mbed_official 31:42176bc3c368 59
mbed_official 31:42176bc3c368 60 /*----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 61 Define clock source values
mbed_official 31:42176bc3c368 62 *----------------------------------------------------------------------------*/
mbed_official 31:42176bc3c368 63 #if (CLOCK_SETUP == 0)
mbed_official 31:42176bc3c368 64 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 65 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 66 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 67 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
mbed_official 31:42176bc3c368 68 #elif (CLOCK_SETUP == 1)
mbed_official 31:42176bc3c368 69 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 70 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 71 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 72 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
mbed_official 31:42176bc3c368 73 #elif (CLOCK_SETUP == 2)
mbed_official 31:42176bc3c368 74 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 75 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 76 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 31:42176bc3c368 77 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
mbed_official 31:42176bc3c368 78 #endif /* (CLOCK_SETUP == 2) */
mbed_official 31:42176bc3c368 79
mbed_official 31:42176bc3c368 80
mbed_official 31:42176bc3c368 81 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 82 -- Core clock
mbed_official 31:42176bc3c368 83 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 84
mbed_official 31:42176bc3c368 85 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 31:42176bc3c368 86
mbed_official 31:42176bc3c368 87 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 88 -- SystemInit()
mbed_official 31:42176bc3c368 89 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 90
mbed_official 31:42176bc3c368 91 void SystemInit (void) {
mbed_official 31:42176bc3c368 92 #if (DISABLE_WDOG)
mbed_official 31:42176bc3c368 93 /* Disable the WDOG module */
mbed_official 31:42176bc3c368 94 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
mbed_official 31:42176bc3c368 95 SIM->COPC = (uint32_t)0x00u;
mbed_official 31:42176bc3c368 96 #endif /* (DISABLE_WDOG) */
mbed_official 31:42176bc3c368 97 #if (CLOCK_SETUP == 0)
mbed_official 31:42176bc3c368 98 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 31:42176bc3c368 99 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
mbed_official 31:42176bc3c368 100 /* Switch to FEI Mode */
mbed_official 31:42176bc3c368 101 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 102 MCG->C1 = (uint8_t)0x06U;
mbed_official 31:42176bc3c368 103 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
mbed_official 31:42176bc3c368 104 MCG->C2 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 105 /* MCG->C4: DMX32=0,DRST_DRS=1 */
mbed_official 31:42176bc3c368 106 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
mbed_official 31:42176bc3c368 107 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 31:42176bc3c368 108 OSC0->CR = (uint8_t)0x80U;
mbed_official 31:42176bc3c368 109 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 31:42176bc3c368 110 MCG->C5 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 111 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 112 MCG->C6 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 113 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 31:42176bc3c368 114 }
mbed_official 31:42176bc3c368 115 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 31:42176bc3c368 116 }
mbed_official 31:42176bc3c368 117 #elif (CLOCK_SETUP == 1)
mbed_official 31:42176bc3c368 118 /* SIM->SCGC5: PORTA=1 */
mbed_official 31:42176bc3c368 119 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 31:42176bc3c368 120 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 31:42176bc3c368 121 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
mbed_official 31:42176bc3c368 122 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 123 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 124 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 125 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 126 /* Switch to FBE Mode */
mbed_official 31:42176bc3c368 127 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
mbed_official 31:42176bc3c368 128 OSC0->CR = (uint8_t)0x89U;
mbed_official 31:42176bc3c368 129 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 31:42176bc3c368 130 MCG->C2 = (uint8_t)0x24U;
mbed_official 31:42176bc3c368 131 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 132 MCG->C1 = (uint8_t)0x9AU;
mbed_official 31:42176bc3c368 133 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 31:42176bc3c368 134 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 31:42176bc3c368 135 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
mbed_official 31:42176bc3c368 136 MCG->C5 = (uint8_t)0x01U;
mbed_official 31:42176bc3c368 137 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 138 MCG->C6 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 139 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 31:42176bc3c368 140 }
mbed_official 31:42176bc3c368 141 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 142 }
mbed_official 31:42176bc3c368 143 /* Switch to PBE Mode */
mbed_official 31:42176bc3c368 144 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 145 MCG->C6 = (uint8_t)0x40U;
mbed_official 31:42176bc3c368 146 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 147 }
mbed_official 31:42176bc3c368 148 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
mbed_official 31:42176bc3c368 149 }
mbed_official 31:42176bc3c368 150 /* Switch to PEE Mode */
mbed_official 31:42176bc3c368 151 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 152 MCG->C1 = (uint8_t)0x1AU;
mbed_official 31:42176bc3c368 153 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 31:42176bc3c368 154 }
mbed_official 31:42176bc3c368 155 #elif (CLOCK_SETUP == 2)
mbed_official 31:42176bc3c368 156 /* SIM->SCGC5: PORTA=1 */
mbed_official 31:42176bc3c368 157 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 31:42176bc3c368 158 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 31:42176bc3c368 159 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
mbed_official 31:42176bc3c368 160 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 161 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 162 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 31:42176bc3c368 163 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 31:42176bc3c368 164 /* Switch to FBE Mode */
mbed_official 31:42176bc3c368 165 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
mbed_official 31:42176bc3c368 166 OSC0->CR = (uint8_t)0x89U;
mbed_official 31:42176bc3c368 167 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 31:42176bc3c368 168 MCG->C2 = (uint8_t)0x24U;
mbed_official 31:42176bc3c368 169 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 31:42176bc3c368 170 MCG->C1 = (uint8_t)0x9AU;
mbed_official 31:42176bc3c368 171 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 31:42176bc3c368 172 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 31:42176bc3c368 173 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 31:42176bc3c368 174 MCG->C5 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 175 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 31:42176bc3c368 176 MCG->C6 = (uint8_t)0x00U;
mbed_official 31:42176bc3c368 177 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 31:42176bc3c368 178 }
mbed_official 31:42176bc3c368 179 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 180 }
mbed_official 31:42176bc3c368 181 /* Switch to BLPE Mode */
mbed_official 31:42176bc3c368 182 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
mbed_official 31:42176bc3c368 183 MCG->C2 = (uint8_t)0x26U;
mbed_official 31:42176bc3c368 184 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 31:42176bc3c368 185 }
mbed_official 31:42176bc3c368 186 #endif /* (CLOCK_SETUP == 2) */
mbed_official 31:42176bc3c368 187 }
mbed_official 31:42176bc3c368 188
mbed_official 31:42176bc3c368 189 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 190 -- SystemCoreClockUpdate()
mbed_official 31:42176bc3c368 191 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 192
mbed_official 31:42176bc3c368 193 void SystemCoreClockUpdate (void) {
mbed_official 31:42176bc3c368 194 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 31:42176bc3c368 195 uint8_t Divider;
mbed_official 31:42176bc3c368 196
mbed_official 31:42176bc3c368 197 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 198 /* Output of FLL or PLL is selected */
mbed_official 31:42176bc3c368 199 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 200 /* FLL is selected */
mbed_official 31:42176bc3c368 201 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 202 /* External reference clock is selected */
mbed_official 31:42176bc3c368 203 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 31:42176bc3c368 204 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 31:42176bc3c368 205 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 31:42176bc3c368 206 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 31:42176bc3c368 207 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 31:42176bc3c368 208 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
mbed_official 31:42176bc3c368 209 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 210 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 31:42176bc3c368 211 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 212 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 31:42176bc3c368 213 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 31:42176bc3c368 214 case 0x0u:
mbed_official 31:42176bc3c368 215 MCGOUTClock *= 640u;
mbed_official 31:42176bc3c368 216 break;
mbed_official 31:42176bc3c368 217 case 0x20u:
mbed_official 31:42176bc3c368 218 MCGOUTClock *= 1280u;
mbed_official 31:42176bc3c368 219 break;
mbed_official 31:42176bc3c368 220 case 0x40u:
mbed_official 31:42176bc3c368 221 MCGOUTClock *= 1920u;
mbed_official 31:42176bc3c368 222 break;
mbed_official 31:42176bc3c368 223 case 0x60u:
mbed_official 31:42176bc3c368 224 MCGOUTClock *= 2560u;
mbed_official 31:42176bc3c368 225 break;
mbed_official 31:42176bc3c368 226 case 0x80u:
mbed_official 31:42176bc3c368 227 MCGOUTClock *= 732u;
mbed_official 31:42176bc3c368 228 break;
mbed_official 31:42176bc3c368 229 case 0xA0u:
mbed_official 31:42176bc3c368 230 MCGOUTClock *= 1464u;
mbed_official 31:42176bc3c368 231 break;
mbed_official 31:42176bc3c368 232 case 0xC0u:
mbed_official 31:42176bc3c368 233 MCGOUTClock *= 2197u;
mbed_official 31:42176bc3c368 234 break;
mbed_official 31:42176bc3c368 235 case 0xE0u:
mbed_official 31:42176bc3c368 236 MCGOUTClock *= 2929u;
mbed_official 31:42176bc3c368 237 break;
mbed_official 31:42176bc3c368 238 default:
mbed_official 31:42176bc3c368 239 break;
mbed_official 31:42176bc3c368 240 }
mbed_official 31:42176bc3c368 241 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 242 /* PLL is selected */
mbed_official 31:42176bc3c368 243 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 31:42176bc3c368 244 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 31:42176bc3c368 245 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 31:42176bc3c368 246 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 31:42176bc3c368 247 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 248 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 31:42176bc3c368 249 /* Internal reference clock is selected */
mbed_official 31:42176bc3c368 250 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 31:42176bc3c368 251 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 31:42176bc3c368 252 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 253 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 31:42176bc3c368 254 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 31:42176bc3c368 255 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 31:42176bc3c368 256 /* External reference clock is selected */
mbed_official 31:42176bc3c368 257 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 31:42176bc3c368 258 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 31:42176bc3c368 259 /* Reserved value */
mbed_official 31:42176bc3c368 260 return;
mbed_official 31:42176bc3c368 261 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 31:42176bc3c368 262 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 31:42176bc3c368 263 }