Renesas / mbed-dsp-neon

Fork of mbed-dsp. CMSIS-DSP library of supporting NEON

Dependents:   mbed-os-example-cmsis_dsp_neon

Fork of mbed-dsp by mbed official

Information

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CMSIS-DSP of supporting NEON

What is this ?

A library for CMSIS-DSP of supporting NEON.
We supported the NEON to CMSIS-DSP Ver1.4.3(CMSIS V4.1) that ARM supplied, has achieved the processing speed improvement.
If you use the mbed-dsp library, you can use to replace this library.
CMSIS-DSP of supporting NEON is provied as a library.

Library Creation environment

CMSIS-DSP library of supporting NEON was created by the following environment.

  • Compiler
    ARMCC Version 5.03
  • Compile option switch[C Compiler]
   -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -O3 -Otime --cpu=Cortex-A9 --littleend --arm 
   --apcs=/interwork --no_unaligned_access --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp 
   --vectorize --asm
  • Compile option switch[Assembler]
   --cpreproc --cpu=Cortex-A9 --littleend --arm --apcs=/interwork --no_unaligned_access 
   --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp


Effects of NEON support

In the data which passes to each function, large size will be expected more effective than small size.
Also if the data is a multiple of 16, effect will be expected in every function in the CMSIS-DSP.


NEON対応CMSIS-DSP

概要

NEON対応したCMSIS-DSPのライブラリです。
ARM社提供のCMSIS-DSP Ver1.4.3(CMSIS V4.1)をターゲットにNEON対応を行ない、処理速度向上を実現しております。
mbed-dspライブラリを使用している場合は、本ライブラリに置き換えて使用することができます。
NEON対応したCMSIS-DSPはライブラリで提供します。

ライブラリ作成環境

NEON対応CMSIS-DSPライブラリは、以下の環境で作成しています。

  • コンパイラ
    ARMCC Version 5.03
  • コンパイルオプションスイッチ[C Compiler]
   -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -O3 -Otime --cpu=Cortex-A9 --littleend --arm 
   --apcs=/interwork --no_unaligned_access --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp 
   --vectorize --asm
  • コンパイルオプションスイッチ[Assembler]
   --cpreproc --cpu=Cortex-A9 --littleend --arm --apcs=/interwork --no_unaligned_access 
   --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp


NEON対応による効果について

CMSIS-DSP内の各関数へ渡すデータは、小さいサイズよりも大きいサイズの方が効果が見込めます。
また、16の倍数のデータであれば、CMSIS-DSP内のどの関数でも効果が見込めます。


cmsis_dsp/StatisticsFunctions/arm_rms_q31.c@2:da51fb522205, 2013-05-30 (annotated)

Committer:
emilmont
Date:
Thu May 30 17:10:11 2013 +0100
Revision:
2:da51fb522205
Parent:
1:fdd22bb7aa52
Child:
3:7a284390b0ce
Keep "cmsis-dsp" module in synch with its source

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
emilmont 1:fdd22bb7aa52 2 * Copyright (C) 2010 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
emilmont 1:fdd22bb7aa52 4 * $Date: 15. February 2012
emilmont 2:da51fb522205 5 * $Revision: V1.1.0
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_rms_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Root Mean Square of the elements of a Q31 vector.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
emilmont 1:fdd22bb7aa52 14 * Version 1.1.0 2012/02/15
emilmont 1:fdd22bb7aa52 15 * Updated with more optimizations, bug fixes and minor API changes.
emilmont 1:fdd22bb7aa52 16 *
emilmont 1:fdd22bb7aa52 17 * Version 1.0.10 2011/7/15
emilmont 1:fdd22bb7aa52 18 * Big Endian support added and Merged M0 and M3/M4 Source code.
emilmont 1:fdd22bb7aa52 19 *
emilmont 1:fdd22bb7aa52 20 * Version 1.0.3 2010/11/29
emilmont 1:fdd22bb7aa52 21 * Re-organized the CMSIS folders and updated documentation.
emilmont 1:fdd22bb7aa52 22 *
emilmont 1:fdd22bb7aa52 23 * Version 1.0.2 2010/11/11
emilmont 1:fdd22bb7aa52 24 * Documentation updated.
emilmont 1:fdd22bb7aa52 25 *
emilmont 1:fdd22bb7aa52 26 * Version 1.0.1 2010/10/05
emilmont 1:fdd22bb7aa52 27 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 28 *
emilmont 1:fdd22bb7aa52 29 * Version 1.0.0 2010/09/20
emilmont 1:fdd22bb7aa52 30 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 31 * ---------------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 32
emilmont 1:fdd22bb7aa52 33 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 34
emilmont 1:fdd22bb7aa52 35 /**
emilmont 1:fdd22bb7aa52 36 * @addtogroup RMS
emilmont 1:fdd22bb7aa52 37 * @{
emilmont 1:fdd22bb7aa52 38 */
emilmont 1:fdd22bb7aa52 39
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 /**
emilmont 1:fdd22bb7aa52 42 * @brief Root Mean Square of the elements of a Q31 vector.
emilmont 1:fdd22bb7aa52 43 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 44 * @param[in] blockSize length of the input vector
emilmont 1:fdd22bb7aa52 45 * @param[out] *pResult rms value returned here
emilmont 1:fdd22bb7aa52 46 * @return none.
emilmont 1:fdd22bb7aa52 47 *
emilmont 1:fdd22bb7aa52 48 * @details
emilmont 1:fdd22bb7aa52 49 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 50 *
emilmont 1:fdd22bb7aa52 51 *\par
emilmont 1:fdd22bb7aa52 52 * The function is implemented using an internal 64-bit accumulator.
emilmont 1:fdd22bb7aa52 53 * The input is represented in 1.31 format, and intermediate multiplication
emilmont 1:fdd22bb7aa52 54 * yields a 2.62 format.
emilmont 1:fdd22bb7aa52 55 * The accumulator maintains full precision of the intermediate multiplication results,
emilmont 1:fdd22bb7aa52 56 * but provides only a single guard bit.
emilmont 1:fdd22bb7aa52 57 * There is no saturation on intermediate additions.
emilmont 1:fdd22bb7aa52 58 * If the accumulator overflows, it wraps around and distorts the result.
emilmont 1:fdd22bb7aa52 59 * In order to avoid overflows completely, the input signal must be scaled down by
emilmont 1:fdd22bb7aa52 60 * log2(blockSize) bits, as a total of blockSize additions are performed internally.
emilmont 1:fdd22bb7aa52 61 * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
emilmont 1:fdd22bb7aa52 62 *
emilmont 1:fdd22bb7aa52 63 */
emilmont 1:fdd22bb7aa52 64
emilmont 1:fdd22bb7aa52 65 void arm_rms_q31(
emilmont 1:fdd22bb7aa52 66 q31_t * pSrc,
emilmont 1:fdd22bb7aa52 67 uint32_t blockSize,
emilmont 1:fdd22bb7aa52 68 q31_t * pResult)
emilmont 1:fdd22bb7aa52 69 {
emilmont 1:fdd22bb7aa52 70 q63_t sum = 0; /* accumulator */
emilmont 1:fdd22bb7aa52 71 q31_t in; /* Temporary variable to store the input */
emilmont 1:fdd22bb7aa52 72 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 73
emilmont 1:fdd22bb7aa52 74 #ifndef ARM_MATH_CM0
emilmont 1:fdd22bb7aa52 75
emilmont 1:fdd22bb7aa52 76 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 77
emilmont 1:fdd22bb7aa52 78 q31_t in1, in2, in3, in4; /* Temporary input variables */
emilmont 1:fdd22bb7aa52 79
emilmont 1:fdd22bb7aa52 80 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 81 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83 /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
emilmont 1:fdd22bb7aa52 84 ** a second loop below computes the remaining 1 to 7 samples. */
emilmont 1:fdd22bb7aa52 85 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 86 {
emilmont 1:fdd22bb7aa52 87 /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
emilmont 1:fdd22bb7aa52 88 /* Compute sum of the squares and then store the result in a temporary variable, sum */
emilmont 1:fdd22bb7aa52 89 /* read two samples from source buffer */
emilmont 1:fdd22bb7aa52 90 in1 = pSrc[0];
emilmont 1:fdd22bb7aa52 91 in2 = pSrc[1];
emilmont 1:fdd22bb7aa52 92
emilmont 1:fdd22bb7aa52 93 /* calculate power and accumulate to accumulator */
emilmont 1:fdd22bb7aa52 94 sum += (q63_t) in1 *in1;
emilmont 1:fdd22bb7aa52 95 sum += (q63_t) in2 *in2;
emilmont 1:fdd22bb7aa52 96
emilmont 1:fdd22bb7aa52 97 /* read two samples from source buffer */
emilmont 1:fdd22bb7aa52 98 in3 = pSrc[2];
emilmont 1:fdd22bb7aa52 99 in4 = pSrc[3];
emilmont 1:fdd22bb7aa52 100
emilmont 1:fdd22bb7aa52 101 /* calculate power and accumulate to accumulator */
emilmont 1:fdd22bb7aa52 102 sum += (q63_t) in3 *in3;
emilmont 1:fdd22bb7aa52 103 sum += (q63_t) in4 *in4;
emilmont 1:fdd22bb7aa52 104
emilmont 1:fdd22bb7aa52 105
emilmont 1:fdd22bb7aa52 106 /* update source buffer to process next samples */
emilmont 1:fdd22bb7aa52 107 pSrc += 4u;
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 110 blkCnt--;
emilmont 1:fdd22bb7aa52 111 }
emilmont 1:fdd22bb7aa52 112
emilmont 1:fdd22bb7aa52 113 /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 114 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 115 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 116
emilmont 1:fdd22bb7aa52 117 #else
emilmont 1:fdd22bb7aa52 118
emilmont 1:fdd22bb7aa52 119 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 120 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 121
emilmont 1:fdd22bb7aa52 122 #endif /* #ifndef ARM_MATH_CM0 */
emilmont 1:fdd22bb7aa52 123
emilmont 1:fdd22bb7aa52 124 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 125 {
emilmont 1:fdd22bb7aa52 126 /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
emilmont 1:fdd22bb7aa52 127 /* Compute sum of the squares and then store the results in a temporary variable, sum */
emilmont 1:fdd22bb7aa52 128 in = *pSrc++;
emilmont 1:fdd22bb7aa52 129 sum += (q63_t) in *in;
emilmont 1:fdd22bb7aa52 130
emilmont 1:fdd22bb7aa52 131 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 132 blkCnt--;
emilmont 1:fdd22bb7aa52 133 }
emilmont 1:fdd22bb7aa52 134
emilmont 1:fdd22bb7aa52 135 /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
emilmont 1:fdd22bb7aa52 136
emilmont 1:fdd22bb7aa52 137 sum = __SSAT(sum >> 31, 31);
emilmont 1:fdd22bb7aa52 138
emilmont 1:fdd22bb7aa52 139
emilmont 1:fdd22bb7aa52 140 /* Compute Rms and store the result in the destination vector */
emilmont 1:fdd22bb7aa52 141 arm_sqrt_q31((q31_t) ((q31_t) sum / (int32_t) blockSize), pResult);
emilmont 1:fdd22bb7aa52 142 }
emilmont 1:fdd22bb7aa52 143
emilmont 1:fdd22bb7aa52 144 /**
emilmont 1:fdd22bb7aa52 145 * @} end of RMS group
emilmont 1:fdd22bb7aa52 146 */