Fork of mbed-dsp. CMSIS-DSP library of supporting NEON
Dependents: mbed-os-example-cmsis_dsp_neon
Fork of mbed-dsp by
Information
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このページの後半に日本語版が用意されています.
CMSIS-DSP of supporting NEON
What is this ?
A library for CMSIS-DSP of supporting NEON.
We supported the NEON to CMSIS-DSP Ver1.4.3(CMSIS V4.1) that ARM supplied, has achieved the processing speed improvement.
If you use the mbed-dsp library, you can use to replace this library.
CMSIS-DSP of supporting NEON is provied as a library.
Library Creation environment
CMSIS-DSP library of supporting NEON was created by the following environment.
- Compiler
ARMCC Version 5.03 - Compile option switch[C Compiler]
-DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -O3 -Otime --cpu=Cortex-A9 --littleend --arm --apcs=/interwork --no_unaligned_access --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp --vectorize --asm
- Compile option switch[Assembler]
--cpreproc --cpu=Cortex-A9 --littleend --arm --apcs=/interwork --no_unaligned_access --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp
Effects of NEON support
In the data which passes to each function, large size will be expected more effective than small size.
Also if the data is a multiple of 16, effect will be expected in every function in the CMSIS-DSP.
NEON対応CMSIS-DSP
概要
NEON対応したCMSIS-DSPのライブラリです。
ARM社提供のCMSIS-DSP Ver1.4.3(CMSIS V4.1)をターゲットにNEON対応を行ない、処理速度向上を実現しております。
mbed-dspライブラリを使用している場合は、本ライブラリに置き換えて使用することができます。
NEON対応したCMSIS-DSPはライブラリで提供します。
ライブラリ作成環境
NEON対応CMSIS-DSPライブラリは、以下の環境で作成しています。
- コンパイラ
ARMCC Version 5.03 - コンパイルオプションスイッチ[C Compiler]
-DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -O3 -Otime --cpu=Cortex-A9 --littleend --arm --apcs=/interwork --no_unaligned_access --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp --vectorize --asm
- コンパイルオプションスイッチ[Assembler]
--cpreproc --cpu=Cortex-A9 --littleend --arm --apcs=/interwork --no_unaligned_access --fpu=vfpv3_fp16 --fpmode=fast --apcs=/hardfp
NEON対応による効果について
CMSIS-DSP内の各関数へ渡すデータは、小さいサイズよりも大きいサイズの方が効果が見込めます。
また、16の倍数のデータであれば、CMSIS-DSP内のどの関数でも効果が見込めます。
cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c
- Committer:
- emilmont
- Date:
- 2012-11-28
- Revision:
- 1:fdd22bb7aa52
- Child:
- 2:da51fb522205
File content as of revision 1:fdd22bb7aa52:
/* ---------------------------------------------------------------------- * Copyright (C) 2010 ARM Limited. All rights reserved. * * $Date: 15. February 2012 * $Revision: V1.1.0 * * Project: CMSIS DSP Library * Title: arm_cmplx_mag_q15.c * * Description: Q15 complex magnitude. * * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * * Version 1.1.0 2012/02/15 * Updated with more optimizations, bug fixes and minor API changes. * * Version 1.0.10 2011/7/15 * Big Endian support added and Merged M0 and M3/M4 Source code. * * Version 1.0.3 2010/11/29 * Re-organized the CMSIS folders and updated documentation. * * Version 1.0.2 2010/11/11 * Documentation updated. * * Version 1.0.1 2010/10/05 * Production release and review comments incorporated. * * Version 1.0.0 2010/09/20 * Production release and review comments incorporated. * ---------------------------------------------------------------------------- */ #include "arm_math.h" /** * @ingroup groupCmplxMath */ /** * @addtogroup cmplx_mag * @{ */ /** * @brief Q15 complex magnitude * @param *pSrc points to the complex input vector * @param *pDst points to the real output vector * @param numSamples number of complex samples in the input vector * @return none. * * <b>Scaling and Overflow Behavior:</b> * \par * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. */ void arm_cmplx_mag_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples) { q31_t acc0, acc1; /* Accumulators */ #ifndef ARM_MATH_CM0 /* Run the below code for Cortex-M4 and Cortex-M3 */ uint32_t blkCnt; /* loop counter */ q31_t in1, in2, in3, in4; q31_t acc2, acc3; /*loop Unrolling */ blkCnt = numSamples >> 2u; /* First part of the processing with loop unrolling. Compute 4 outputs at a time. ** a second loop below computes the remaining 1 to 3 samples. */ while(blkCnt > 0u) { /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ in1 = *__SIMD32(pSrc)++; in2 = *__SIMD32(pSrc)++; in3 = *__SIMD32(pSrc)++; in4 = *__SIMD32(pSrc)++; acc0 = __SMUAD(in1, in1); acc1 = __SMUAD(in2, in2); acc2 = __SMUAD(in3, in3); acc3 = __SMUAD(in4, in4); /* store the result in 2.14 format in the destination buffer. */ arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++); arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++); arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++); arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++); /* Decrement the loop counter */ blkCnt--; } /* If the numSamples is not a multiple of 4, compute any remaining output samples here. ** No loop unrolling is used. */ blkCnt = numSamples % 0x4u; while(blkCnt > 0u) { /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ in1 = *__SIMD32(pSrc)++; acc0 = __SMUAD(in1, in1); /* store the result in 2.14 format in the destination buffer. */ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); /* Decrement the loop counter */ blkCnt--; } #else /* Run the below code for Cortex-M0 */ q15_t real, imag; /* Temporary variables to hold input values */ while(numSamples > 0u) { /* out = sqrt(real * real + imag * imag) */ real = *pSrc++; imag = *pSrc++; acc0 = (real * real); acc1 = (imag * imag); /* store the result in 2.14 format in the destination buffer. */ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); /* Decrement the loop counter */ numSamples--; } #endif /* #ifndef ARM_MATH_CM0 */ } /** * @} end of cmplx_mag group */