RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.
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SSIF
The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.
Hello World!
Import program
00001 #include "mbed.h" 00002 #include "R_BSP_Ssif.h" 00003 #include "sine_data_tbl.h" 00004 00005 //I2S send only, The upper limit of write buffer is 8. 00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0); 00007 00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) { 00009 if (result < 0) { 00010 printf("ssif write callback error %d\n", result); 00011 } 00012 } 00013 00014 int main() { 00015 rbsp_data_conf_t ssif_write_end_conf = {&callback_ssif_write_end, NULL}; 00016 ssif_channel_cfg_t ssif_cfg; 00017 int32_t result; 00018 00019 //I2S Master, 44.1kHz, 16bit, 2ch 00020 ssif_cfg.enabled = true; 00021 ssif_cfg.int_level = 0x78; 00022 ssif_cfg.slave_mode = false; 00023 ssif_cfg.sample_freq = 44100u; 00024 ssif_cfg.clk_select = SSIF_CFG_CKS_AUDIO_X1; 00025 ssif_cfg.multi_ch = SSIF_CFG_MULTI_CH_1; 00026 ssif_cfg.data_word = SSIF_CFG_DATA_WORD_16; 00027 ssif_cfg.system_word = SSIF_CFG_SYSTEM_WORD_32; 00028 ssif_cfg.bclk_pol = SSIF_CFG_FALLING; 00029 ssif_cfg.ws_pol = SSIF_CFG_WS_LOW; 00030 ssif_cfg.padding_pol = SSIF_CFG_PADDING_LOW; 00031 ssif_cfg.serial_alignment = SSIF_CFG_DATA_FIRST; 00032 ssif_cfg.parallel_alignment = SSIF_CFG_LEFT; 00033 ssif_cfg.ws_delay = SSIF_CFG_DELAY; 00034 ssif_cfg.noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL; 00035 ssif_cfg.tdm_mode = SSIF_CFG_DISABLE_TDM; 00036 ssif_cfg.romdec_direct.mode = SSIF_CFG_DISABLE_ROMDEC_DIRECT; 00037 ssif_cfg.romdec_direct.p_cbfunc = NULL; 00038 result = ssif.ConfigChannel(&ssif_cfg); 00039 if (result < 0) { 00040 printf("ssif config error %d\n", result); 00041 } 00042 00043 while (1) { 00044 //The upper limit of write buffer is 8. 00045 result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 00046 sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf); 00047 if (result < 0) { 00048 printf("ssif write api error %d\n", result); 00049 } 00050 } 00051 }
API
Import library
Public Member Functions |
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R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16) | |
Constructor.
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virtual | ~R_BSP_Ssif () |
Destructor.
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int32_t | GetSsifChNo (void) |
Get a value of SSIF channel number.
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bool | ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg) |
Save configuration to the SSIF driver.
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bool | GetStatus (uint32_t *const p_status) |
Get a value of SSISR register.
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int32_t | write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Write count bytes to the file associated.
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int32_t | read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Read count bytes to the file associated.
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Protected Member Functions |
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void | write_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Write init.
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void | read_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Read init.
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Interface
See the Pinout page for more details
SCUX
The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.
Hello World!
Import program
00001 #include "mbed.h" 00002 #include "R_BSP_Scux.h" 00003 #include "USBHostMSD.h" 00004 00005 R_BSP_Scux scux(SCUX_CH_0); 00006 00007 #define WRITE_SAMPLE_NUM (128) 00008 #define READ_SAMPLE_NUM (2048) 00009 00010 const short sin_data[WRITE_SAMPLE_NUM] = { 00011 0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528 00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133 00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2 00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61 00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C 00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1 00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56 00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C 00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8 00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD 00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E 00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F 00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584 00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F 00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA 00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374 00027 }; 00028 00029 #if defined(__ICCARM__) 00030 #pragma data_alignment=4 00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram"; 00032 #pragma data_alignment=4 00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram"; 00034 #else 00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4))); 00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4))); 00037 #endif 00038 00039 void scux_setup(void); 00040 void write_task(void const*); 00041 void file_output_to_usb(void); 00042 00043 int main(void) { 00044 // set up SRC parameters. 00045 scux_setup(); 00046 00047 printf("Sampling rate conversion Start.\n"); 00048 // start accepting transmit/receive requests. 00049 scux.TransStart(); 00050 00051 // create a new thread to write to SCUX. 00052 Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4); 00053 00054 // receive request to the SCUX driver. 00055 scux.read(read_buff, sizeof(read_buff)); 00056 printf("Sampling rate conversion End.\n"); 00057 00058 // output binary file to USB port 0. 00059 file_output_to_usb(); 00060 } 00061 00062 void scux_setup(void) { 00063 scux_src_usr_cfg_t src_cfg; 00064 00065 src_cfg.src_enable = true; 00066 src_cfg.word_len = SCUX_DATA_LEN_16; 00067 src_cfg.mode_sync = true; 00068 src_cfg.input_rate = SAMPLING_RATE_48000HZ; 00069 src_cfg.output_rate = SAMPLING_RATE_96000HZ; 00070 src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0; 00071 src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1; 00072 00073 scux.SetSrcCfg(&src_cfg); 00074 } 00075 00076 void scux_flush_callback(int scux_ch) { 00077 // do nothing 00078 } 00079 00080 void write_task(void const*) { 00081 memcpy(write_buff, sin_data, sizeof(write_buff)); 00082 // send request to the SCUX driver. 00083 scux.write(write_buff, sizeof(write_buff)); 00084 00085 // stop the acceptance of transmit/receive requests. 00086 scux.FlushStop(&scux_flush_callback); 00087 } 00088 00089 void file_output_to_usb(void) { 00090 FILE * fp = NULL; 00091 int i; 00092 00093 USBHostMSD msd("usb"); 00094 00095 // try to connect a MSD device 00096 for(i = 0; i < 10; i++) { 00097 if (msd.connect()) { 00098 break; 00099 } 00100 wait(0.5); 00101 } 00102 00103 if (msd.connected()) { 00104 fp = fopen("/usb/scux_input.dat", "rb"); 00105 if (fp == NULL) { 00106 fp = fopen("/usb/scux_input.dat", "wb"); 00107 if (fp != NULL) { 00108 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp); 00109 fclose(fp); 00110 printf("Output binary file(Input data) to USB.\n"); 00111 } else { 00112 printf("Failed to output binary file(Input data).\n"); 00113 } 00114 } else { 00115 printf("Binary file(Input data) exists.\n"); 00116 fclose(fp); 00117 } 00118 00119 fp = fopen("/usb/scux_output.dat", "rb"); 00120 if (fp == NULL) { 00121 fp = fopen("/usb/scux_output.dat", "wb"); 00122 if (fp != NULL) { 00123 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp); 00124 fclose(fp); 00125 printf("Output binary file(Output data) to USB.\n"); 00126 } else { 00127 printf("Failed to output binary file(Output data).\n"); 00128 } 00129 } else { 00130 printf("Binary file(Output data) exists.\n"); 00131 fclose(fp); 00132 } 00133 } else { 00134 printf("Failed to connect to the USB device.\n"); 00135 } 00136 }
API
Import library
Public Member Functions |
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R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16) | |
Constructor: Initializes and opens the channel designated by the SCUX driver.
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virtual | ~R_BSP_Scux (void) |
Destructor: Closes the channel designated by the SCUX driver and exits.
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bool | TransStart (void) |
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
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bool | FlushStop (void(*const callback)(int32_t)) |
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
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bool | ClearStop (void) |
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
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bool | SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param) |
Sets up SRC parameters.
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bool | GetWriteStat (uint32_t *const p_write_stat) |
Obtains the state information of the write request.
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bool | GetReadStat (uint32_t *const p_read_stat) |
Obtains the state information of the read request.
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int32_t | write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Write count bytes to the file associated.
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int32_t | read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL) |
Read count bytes to the file associated.
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Protected Member Functions |
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void | write_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Write init.
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void | read_init (void *handle, void *p_func_a, int32_t max_buff_num=16) |
Read init.
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Write request state transition diagram
Read request state transition diagram
RenesasBSP/drv_src/ssif/ssif_dma.c@11:fb9eda52224e, 2016-05-31 (annotated)
- Committer:
- dkato
- Date:
- Tue May 31 01:45:35 2016 +0000
- Revision:
- 11:fb9eda52224e
- Parent:
- 5:1390bfcb667c
"inline" of the ssif_init function is removed.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dkato | 0:702bf7b2b7d8 | 1 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 2 | * DISCLAIMER |
dkato | 0:702bf7b2b7d8 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
dkato | 0:702bf7b2b7d8 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
dkato | 0:702bf7b2b7d8 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
dkato | 0:702bf7b2b7d8 | 6 | * all applicable laws, including copyright laws. |
dkato | 0:702bf7b2b7d8 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
dkato | 0:702bf7b2b7d8 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
dkato | 0:702bf7b2b7d8 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
dkato | 0:702bf7b2b7d8 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
dkato | 0:702bf7b2b7d8 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
dkato | 0:702bf7b2b7d8 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
dkato | 0:702bf7b2b7d8 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
dkato | 0:702bf7b2b7d8 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
dkato | 0:702bf7b2b7d8 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
dkato | 0:702bf7b2b7d8 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
dkato | 0:702bf7b2b7d8 | 17 | * and to discontinue the availability of this software. By using this software, |
dkato | 0:702bf7b2b7d8 | 18 | * you agree to the additional terms and conditions found by accessing the |
dkato | 0:702bf7b2b7d8 | 19 | * following link: |
dkato | 0:702bf7b2b7d8 | 20 | * http://www.renesas.com/disclaimer |
dkato | 0:702bf7b2b7d8 | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
dkato | 0:702bf7b2b7d8 | 22 | *******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 23 | |
dkato | 0:702bf7b2b7d8 | 24 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 25 | * File Name : ssif_dma.c |
dkato | 5:1390bfcb667c | 26 | * $Rev: 1645 $ |
dkato | 5:1390bfcb667c | 27 | * $Date:: 2015-05-21 10:35:06 +0900#$ |
dkato | 0:702bf7b2b7d8 | 28 | * Description : SSIF driver DMA functions |
dkato | 0:702bf7b2b7d8 | 29 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 30 | |
dkato | 0:702bf7b2b7d8 | 31 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 32 | Includes <System Includes>, "Project Includes" |
dkato | 0:702bf7b2b7d8 | 33 | *******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 34 | #include "ssif.h" |
dkato | 0:702bf7b2b7d8 | 35 | #include "iodefine.h" |
dkato | 0:702bf7b2b7d8 | 36 | #include "ssif_int.h" |
dkato | 0:702bf7b2b7d8 | 37 | #include "dma_if.h" |
dkato | 0:702bf7b2b7d8 | 38 | #include "Renesas_RZ_A1.h" |
dkato | 0:702bf7b2b7d8 | 39 | |
dkato | 0:702bf7b2b7d8 | 40 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 41 | Macro definitions |
dkato | 0:702bf7b2b7d8 | 42 | *******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 43 | #define SSIF_DUMMY_DMA_BUF_SIZE (4096u) |
dkato | 0:702bf7b2b7d8 | 44 | #define SSIF_I2S_LR_CH (2u) |
dkato | 0:702bf7b2b7d8 | 45 | |
dkato | 0:702bf7b2b7d8 | 46 | #define SSIF_ROMDEC_DMA_SIZE (2352u) |
dkato | 0:702bf7b2b7d8 | 47 | |
dkato | 0:702bf7b2b7d8 | 48 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 49 | Typedef definitions |
dkato | 0:702bf7b2b7d8 | 50 | *******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 51 | |
dkato | 0:702bf7b2b7d8 | 52 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 53 | Exported global variables (to be accessed by other files) |
dkato | 0:702bf7b2b7d8 | 54 | *******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 55 | |
dkato | 0:702bf7b2b7d8 | 56 | /******************************************************************************* |
dkato | 0:702bf7b2b7d8 | 57 | Private global variables and functions |
dkato | 0:702bf7b2b7d8 | 58 | *******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 59 | |
dkato | 0:702bf7b2b7d8 | 60 | static void SSIF_DMA_TxCallback(union sigval param); |
dkato | 0:702bf7b2b7d8 | 61 | static void SSIF_DMA_RxCallback(union sigval param); |
dkato | 0:702bf7b2b7d8 | 62 | |
dkato | 0:702bf7b2b7d8 | 63 | static const dma_res_select_t gb_ssif_dma_tx_resource[SSIF_NUM_CHANS] = |
dkato | 0:702bf7b2b7d8 | 64 | { |
dkato | 0:702bf7b2b7d8 | 65 | DMA_RS_SSITXI0, |
dkato | 0:702bf7b2b7d8 | 66 | DMA_RS_SSITXI1, |
dkato | 0:702bf7b2b7d8 | 67 | DMA_RS_SSIRTI2, |
dkato | 0:702bf7b2b7d8 | 68 | DMA_RS_SSITXI3, |
dkato | 0:702bf7b2b7d8 | 69 | DMA_RS_SSIRTI4, |
dkato | 0:702bf7b2b7d8 | 70 | DMA_RS_SSITXI5 |
dkato | 0:702bf7b2b7d8 | 71 | }; |
dkato | 0:702bf7b2b7d8 | 72 | |
dkato | 0:702bf7b2b7d8 | 73 | static const dma_res_select_t gb_ssif_dma_rx_resource[SSIF_NUM_CHANS] = |
dkato | 0:702bf7b2b7d8 | 74 | { |
dkato | 0:702bf7b2b7d8 | 75 | DMA_RS_SSIRXI0, |
dkato | 0:702bf7b2b7d8 | 76 | DMA_RS_SSIRXI1, |
dkato | 0:702bf7b2b7d8 | 77 | DMA_RS_SSIRTI2, |
dkato | 0:702bf7b2b7d8 | 78 | DMA_RS_SSIRXI3, |
dkato | 0:702bf7b2b7d8 | 79 | DMA_RS_SSIRTI4, |
dkato | 0:702bf7b2b7d8 | 80 | DMA_RS_SSIRXI5 |
dkato | 0:702bf7b2b7d8 | 81 | }; |
dkato | 0:702bf7b2b7d8 | 82 | |
dkato | 0:702bf7b2b7d8 | 83 | static AIOCB gb_ssif_dma_tx_end_aiocb[SSIF_NUM_CHANS]; |
dkato | 0:702bf7b2b7d8 | 84 | static AIOCB gb_ssif_dma_rx_end_aiocb[SSIF_NUM_CHANS]; |
dkato | 0:702bf7b2b7d8 | 85 | |
dkato | 0:702bf7b2b7d8 | 86 | static dma_trans_data_t gb_ssif_txdma_dummy_trparam[SSIF_NUM_CHANS]; |
dkato | 0:702bf7b2b7d8 | 87 | static dma_trans_data_t gb_ssif_rxdma_dummy_trparam[SSIF_NUM_CHANS]; |
dkato | 0:702bf7b2b7d8 | 88 | |
dkato | 0:702bf7b2b7d8 | 89 | static uint32_t ssif_tx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE]; |
dkato | 0:702bf7b2b7d8 | 90 | static uint32_t ssif_rx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE]; |
dkato | 0:702bf7b2b7d8 | 91 | |
dkato | 0:702bf7b2b7d8 | 92 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 93 | * Function Name: SSIF_InitDMA |
dkato | 0:702bf7b2b7d8 | 94 | * @brief Allocate and Setup DMA_CH for specified SSIF channel. |
dkato | 0:702bf7b2b7d8 | 95 | * |
dkato | 0:702bf7b2b7d8 | 96 | * Description:<br> |
dkato | 0:702bf7b2b7d8 | 97 | * |
dkato | 0:702bf7b2b7d8 | 98 | * @param[in,out] p_info_ch :channel object. |
dkato | 0:702bf7b2b7d8 | 99 | * @retval ESUCCESS :Success. |
dkato | 0:702bf7b2b7d8 | 100 | * @retval error code :Failure. |
dkato | 0:702bf7b2b7d8 | 101 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 102 | int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch) |
dkato | 0:702bf7b2b7d8 | 103 | { |
dkato | 0:702bf7b2b7d8 | 104 | int_t ercd = ESUCCESS; |
dkato | 0:702bf7b2b7d8 | 105 | int_t dma_ret; |
dkato | 0:702bf7b2b7d8 | 106 | uint32_t ssif_ch; |
dkato | 0:702bf7b2b7d8 | 107 | int32_t dma_ercd; |
dkato | 0:702bf7b2b7d8 | 108 | dma_ch_setup_t dma_ch_setup; |
dkato | 0:702bf7b2b7d8 | 109 | uint32_t n_datawd_per_smp; |
dkato | 0:702bf7b2b7d8 | 110 | uint32_t byte_per_smp; |
dkato | 0:702bf7b2b7d8 | 111 | uint32_t dummy_smp_count; |
dkato | 0:702bf7b2b7d8 | 112 | uint32_t dummy_dma_size = 0u; |
dkato | 0:702bf7b2b7d8 | 113 | |
dkato | 0:702bf7b2b7d8 | 114 | if (NULL == p_info_ch) |
dkato | 0:702bf7b2b7d8 | 115 | { |
dkato | 0:702bf7b2b7d8 | 116 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 117 | } |
dkato | 0:702bf7b2b7d8 | 118 | else |
dkato | 0:702bf7b2b7d8 | 119 | { |
dkato | 0:702bf7b2b7d8 | 120 | ssif_ch = p_info_ch->channel; |
dkato | 0:702bf7b2b7d8 | 121 | |
dkato | 0:702bf7b2b7d8 | 122 | /* calculate dummy dma transfer size */ |
dkato | 0:702bf7b2b7d8 | 123 | n_datawd_per_smp = (uint32_t)(p_info_ch->multi_ch + 1) * SSIF_I2S_LR_CH; |
dkato | 0:702bf7b2b7d8 | 124 | byte_per_smp = n_datawd_per_smp * (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word); |
dkato | 0:702bf7b2b7d8 | 125 | |
dkato | 0:702bf7b2b7d8 | 126 | if (0u == byte_per_smp) |
dkato | 0:702bf7b2b7d8 | 127 | { |
dkato | 0:702bf7b2b7d8 | 128 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 129 | } |
dkato | 0:702bf7b2b7d8 | 130 | else |
dkato | 0:702bf7b2b7d8 | 131 | { |
dkato | 0:702bf7b2b7d8 | 132 | dummy_smp_count = SSIF_DUMMY_DMA_BUF_SIZE / byte_per_smp; |
dkato | 0:702bf7b2b7d8 | 133 | dummy_dma_size = dummy_smp_count * byte_per_smp; |
dkato | 0:702bf7b2b7d8 | 134 | |
dkato | 0:702bf7b2b7d8 | 135 | if (0u == dummy_dma_size) |
dkato | 0:702bf7b2b7d8 | 136 | { |
dkato | 0:702bf7b2b7d8 | 137 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 138 | } |
dkato | 0:702bf7b2b7d8 | 139 | } |
dkato | 0:702bf7b2b7d8 | 140 | |
dkato | 0:702bf7b2b7d8 | 141 | /* allocate DMA Channel for write(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 142 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 143 | { |
dkato | 0:702bf7b2b7d8 | 144 | if (O_RDONLY == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 145 | { |
dkato | 0:702bf7b2b7d8 | 146 | p_info_ch->dma_tx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 147 | } |
dkato | 0:702bf7b2b7d8 | 148 | else |
dkato | 0:702bf7b2b7d8 | 149 | { |
dkato | 0:702bf7b2b7d8 | 150 | dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 151 | |
dkato | 0:702bf7b2b7d8 | 152 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 153 | { |
dkato | 0:702bf7b2b7d8 | 154 | p_info_ch->dma_tx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 155 | ercd = ENOMEM; |
dkato | 0:702bf7b2b7d8 | 156 | } |
dkato | 0:702bf7b2b7d8 | 157 | else |
dkato | 0:702bf7b2b7d8 | 158 | { |
dkato | 0:702bf7b2b7d8 | 159 | p_info_ch->dma_tx_ch = dma_ret; |
dkato | 0:702bf7b2b7d8 | 160 | ercd = ESUCCESS; |
dkato | 0:702bf7b2b7d8 | 161 | } |
dkato | 0:702bf7b2b7d8 | 162 | } |
dkato | 0:702bf7b2b7d8 | 163 | } |
dkato | 0:702bf7b2b7d8 | 164 | |
dkato | 0:702bf7b2b7d8 | 165 | /* allocate DMA Channel for read(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 166 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 167 | { |
dkato | 0:702bf7b2b7d8 | 168 | if (O_WRONLY == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 169 | { |
dkato | 0:702bf7b2b7d8 | 170 | p_info_ch->dma_rx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 171 | } |
dkato | 0:702bf7b2b7d8 | 172 | else |
dkato | 0:702bf7b2b7d8 | 173 | { |
dkato | 0:702bf7b2b7d8 | 174 | dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 175 | |
dkato | 0:702bf7b2b7d8 | 176 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 177 | { |
dkato | 0:702bf7b2b7d8 | 178 | p_info_ch->dma_rx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 179 | ercd = ENOMEM; |
dkato | 0:702bf7b2b7d8 | 180 | } |
dkato | 0:702bf7b2b7d8 | 181 | else |
dkato | 0:702bf7b2b7d8 | 182 | { |
dkato | 0:702bf7b2b7d8 | 183 | p_info_ch->dma_rx_ch = dma_ret; |
dkato | 0:702bf7b2b7d8 | 184 | ercd = ESUCCESS; |
dkato | 0:702bf7b2b7d8 | 185 | } |
dkato | 0:702bf7b2b7d8 | 186 | } |
dkato | 0:702bf7b2b7d8 | 187 | } |
dkato | 0:702bf7b2b7d8 | 188 | |
dkato | 0:702bf7b2b7d8 | 189 | /* setup DMA channel for write(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 190 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 191 | { |
dkato | 0:702bf7b2b7d8 | 192 | if (O_RDONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 193 | { |
dkato | 0:702bf7b2b7d8 | 194 | AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 195 | p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD; |
dkato | 0:702bf7b2b7d8 | 196 | p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch; |
dkato | 0:702bf7b2b7d8 | 197 | p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback; |
dkato | 0:702bf7b2b7d8 | 198 | |
dkato | 0:702bf7b2b7d8 | 199 | dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 200 | dma_ch_setup.direction = DMA_REQ_DES; |
dkato | 0:702bf7b2b7d8 | 201 | dma_ch_setup.dst_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 202 | dma_ch_setup.src_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 203 | dma_ch_setup.dst_cnt = DMA_ADDR_FIX; |
dkato | 0:702bf7b2b7d8 | 204 | dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT; |
dkato | 0:702bf7b2b7d8 | 205 | dma_ch_setup.p_aio = p_tx_aio; |
dkato | 0:702bf7b2b7d8 | 206 | |
dkato | 0:702bf7b2b7d8 | 207 | dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 208 | |
dkato | 0:702bf7b2b7d8 | 209 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 210 | { |
dkato | 0:702bf7b2b7d8 | 211 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 212 | } |
dkato | 0:702bf7b2b7d8 | 213 | } |
dkato | 0:702bf7b2b7d8 | 214 | } |
dkato | 0:702bf7b2b7d8 | 215 | |
dkato | 0:702bf7b2b7d8 | 216 | /* setup DMA channel for read(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 217 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 218 | { |
dkato | 0:702bf7b2b7d8 | 219 | if (O_WRONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 220 | { |
dkato | 0:702bf7b2b7d8 | 221 | AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 222 | p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD; |
dkato | 0:702bf7b2b7d8 | 223 | p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch; |
dkato | 0:702bf7b2b7d8 | 224 | p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback; |
dkato | 0:702bf7b2b7d8 | 225 | |
dkato | 0:702bf7b2b7d8 | 226 | dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 227 | dma_ch_setup.direction = DMA_REQ_SRC; |
dkato | 0:702bf7b2b7d8 | 228 | dma_ch_setup.dst_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 229 | dma_ch_setup.src_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 230 | dma_ch_setup.src_cnt = DMA_ADDR_FIX; |
dkato | 0:702bf7b2b7d8 | 231 | dma_ch_setup.p_aio = p_rx_aio; |
dkato | 0:702bf7b2b7d8 | 232 | |
dkato | 0:702bf7b2b7d8 | 233 | if (SSIF_CFG_ENABLE_ROMDEC_DIRECT |
dkato | 0:702bf7b2b7d8 | 234 | != p_info_ch->romdec_direct.mode) |
dkato | 0:702bf7b2b7d8 | 235 | { |
dkato | 0:702bf7b2b7d8 | 236 | dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT; |
dkato | 0:702bf7b2b7d8 | 237 | } |
dkato | 0:702bf7b2b7d8 | 238 | else |
dkato | 0:702bf7b2b7d8 | 239 | { |
dkato | 0:702bf7b2b7d8 | 240 | dma_ch_setup.dst_cnt = DMA_ADDR_FIX; |
dkato | 0:702bf7b2b7d8 | 241 | } |
dkato | 0:702bf7b2b7d8 | 242 | |
dkato | 0:702bf7b2b7d8 | 243 | dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 244 | |
dkato | 0:702bf7b2b7d8 | 245 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 246 | { |
dkato | 0:702bf7b2b7d8 | 247 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 248 | } |
dkato | 0:702bf7b2b7d8 | 249 | } |
dkato | 0:702bf7b2b7d8 | 250 | } |
dkato | 0:702bf7b2b7d8 | 251 | |
dkato | 0:702bf7b2b7d8 | 252 | /* start DMA dummy transfer for write(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 253 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 254 | { |
dkato | 0:702bf7b2b7d8 | 255 | if (O_RDONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 256 | { |
dkato | 0:702bf7b2b7d8 | 257 | /* setup short dummy transfer */ |
dkato | 0:702bf7b2b7d8 | 258 | gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0]; |
dkato | 0:702bf7b2b7d8 | 259 | gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR; |
dkato | 0:702bf7b2b7d8 | 260 | gb_ssif_txdma_dummy_trparam[ssif_ch].count = dummy_dma_size; |
dkato | 0:702bf7b2b7d8 | 261 | |
dkato | 0:702bf7b2b7d8 | 262 | dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 263 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 264 | { |
dkato | 0:702bf7b2b7d8 | 265 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 266 | } |
dkato | 0:702bf7b2b7d8 | 267 | else |
dkato | 0:702bf7b2b7d8 | 268 | { |
dkato | 0:702bf7b2b7d8 | 269 | dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 270 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 271 | { |
dkato | 0:702bf7b2b7d8 | 272 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 273 | } |
dkato | 0:702bf7b2b7d8 | 274 | } |
dkato | 0:702bf7b2b7d8 | 275 | } |
dkato | 0:702bf7b2b7d8 | 276 | } |
dkato | 0:702bf7b2b7d8 | 277 | |
dkato | 0:702bf7b2b7d8 | 278 | /* start DMA dummy transfer for read(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 279 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 280 | { |
dkato | 0:702bf7b2b7d8 | 281 | if (O_WRONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 282 | { |
dkato | 0:702bf7b2b7d8 | 283 | if (SSIF_CFG_ENABLE_ROMDEC_DIRECT |
dkato | 0:702bf7b2b7d8 | 284 | != p_info_ch->romdec_direct.mode) |
dkato | 0:702bf7b2b7d8 | 285 | { |
dkato | 0:702bf7b2b7d8 | 286 | /* setup short dummy transfer */ |
dkato | 0:702bf7b2b7d8 | 287 | gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR; |
dkato | 0:702bf7b2b7d8 | 288 | gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0]; |
dkato | 0:702bf7b2b7d8 | 289 | gb_ssif_rxdma_dummy_trparam[ssif_ch].count = dummy_dma_size; |
dkato | 0:702bf7b2b7d8 | 290 | } |
dkato | 0:702bf7b2b7d8 | 291 | else |
dkato | 0:702bf7b2b7d8 | 292 | { |
dkato | 0:702bf7b2b7d8 | 293 | /* setup ROMDEC direct input transfer */ |
dkato | 0:702bf7b2b7d8 | 294 | gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR; |
dkato | 0:702bf7b2b7d8 | 295 | gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ROMDEC.STRMDIN0; |
dkato | 0:702bf7b2b7d8 | 296 | gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_ROMDEC_DMA_SIZE; |
dkato | 0:702bf7b2b7d8 | 297 | } |
dkato | 0:702bf7b2b7d8 | 298 | |
dkato | 0:702bf7b2b7d8 | 299 | dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 300 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 301 | { |
dkato | 0:702bf7b2b7d8 | 302 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 303 | } |
dkato | 0:702bf7b2b7d8 | 304 | else |
dkato | 0:702bf7b2b7d8 | 305 | { |
dkato | 0:702bf7b2b7d8 | 306 | dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 307 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 308 | { |
dkato | 0:702bf7b2b7d8 | 309 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 310 | } |
dkato | 0:702bf7b2b7d8 | 311 | } |
dkato | 0:702bf7b2b7d8 | 312 | } |
dkato | 0:702bf7b2b7d8 | 313 | } |
dkato | 0:702bf7b2b7d8 | 314 | |
dkato | 0:702bf7b2b7d8 | 315 | /* enable ssif transfer */ |
dkato | 0:702bf7b2b7d8 | 316 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 317 | { |
dkato | 0:702bf7b2b7d8 | 318 | /* clear status and enable error interrupt */ |
dkato | 0:702bf7b2b7d8 | 319 | SSIF_EnableErrorInterrupt(ssif_ch); |
dkato | 0:702bf7b2b7d8 | 320 | |
dkato | 0:702bf7b2b7d8 | 321 | /* enable end interrupt */ |
dkato | 0:702bf7b2b7d8 | 322 | g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE; |
dkato | 0:702bf7b2b7d8 | 323 | |
dkato | 0:702bf7b2b7d8 | 324 | if (O_RDWR == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 325 | { |
dkato | 0:702bf7b2b7d8 | 326 | /* start write and read DMA at the same time */ |
dkato | 0:702bf7b2b7d8 | 327 | g_ssireg[ssif_ch]->SSICR |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN; |
dkato | 0:702bf7b2b7d8 | 328 | } |
dkato | 0:702bf7b2b7d8 | 329 | else if (O_WRONLY == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 330 | { |
dkato | 0:702bf7b2b7d8 | 331 | /* start write DMA only */ |
dkato | 0:702bf7b2b7d8 | 332 | g_ssireg[ssif_ch]->SSICR |= SSIF_CR_BIT_TEN; |
dkato | 0:702bf7b2b7d8 | 333 | } |
dkato | 0:702bf7b2b7d8 | 334 | else if (O_RDONLY == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 335 | { |
dkato | 0:702bf7b2b7d8 | 336 | /* start read DMA only */ |
dkato | 0:702bf7b2b7d8 | 337 | g_ssireg[ssif_ch]->SSICR |= SSIF_CR_BIT_REN; |
dkato | 0:702bf7b2b7d8 | 338 | } |
dkato | 0:702bf7b2b7d8 | 339 | else |
dkato | 0:702bf7b2b7d8 | 340 | { |
dkato | 0:702bf7b2b7d8 | 341 | ercd = EINVAL; |
dkato | 0:702bf7b2b7d8 | 342 | } |
dkato | 0:702bf7b2b7d8 | 343 | } |
dkato | 0:702bf7b2b7d8 | 344 | |
dkato | 0:702bf7b2b7d8 | 345 | /* cleanup dma resources when error occured */ |
dkato | 0:702bf7b2b7d8 | 346 | if (ESUCCESS != ercd) |
dkato | 0:702bf7b2b7d8 | 347 | { |
dkato | 0:702bf7b2b7d8 | 348 | if (-1 != p_info_ch->dma_tx_ch) |
dkato | 0:702bf7b2b7d8 | 349 | { |
dkato | 0:702bf7b2b7d8 | 350 | uint32_t remain; |
dkato | 0:702bf7b2b7d8 | 351 | dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 352 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 353 | { |
dkato | 0:702bf7b2b7d8 | 354 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 355 | } |
dkato | 0:702bf7b2b7d8 | 356 | } |
dkato | 0:702bf7b2b7d8 | 357 | |
dkato | 0:702bf7b2b7d8 | 358 | if (-1 != p_info_ch->dma_rx_ch) |
dkato | 0:702bf7b2b7d8 | 359 | { |
dkato | 0:702bf7b2b7d8 | 360 | uint32_t remain; |
dkato | 0:702bf7b2b7d8 | 361 | dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 362 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 363 | { |
dkato | 0:702bf7b2b7d8 | 364 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 365 | } |
dkato | 0:702bf7b2b7d8 | 366 | } |
dkato | 0:702bf7b2b7d8 | 367 | |
dkato | 0:702bf7b2b7d8 | 368 | if (-1 != p_info_ch->dma_tx_ch) |
dkato | 0:702bf7b2b7d8 | 369 | { |
dkato | 0:702bf7b2b7d8 | 370 | dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 371 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 372 | { |
dkato | 0:702bf7b2b7d8 | 373 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 374 | } |
dkato | 0:702bf7b2b7d8 | 375 | p_info_ch->dma_tx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 376 | } |
dkato | 0:702bf7b2b7d8 | 377 | |
dkato | 0:702bf7b2b7d8 | 378 | if (-1 != p_info_ch->dma_rx_ch) |
dkato | 0:702bf7b2b7d8 | 379 | { |
dkato | 0:702bf7b2b7d8 | 380 | dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 381 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 382 | { |
dkato | 0:702bf7b2b7d8 | 383 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 384 | } |
dkato | 0:702bf7b2b7d8 | 385 | p_info_ch->dma_rx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 386 | } |
dkato | 0:702bf7b2b7d8 | 387 | } |
dkato | 0:702bf7b2b7d8 | 388 | } |
dkato | 0:702bf7b2b7d8 | 389 | |
dkato | 0:702bf7b2b7d8 | 390 | return ercd; |
dkato | 0:702bf7b2b7d8 | 391 | } |
dkato | 0:702bf7b2b7d8 | 392 | |
dkato | 0:702bf7b2b7d8 | 393 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 394 | * Function Name: SSIF_UnInitDMA |
dkato | 0:702bf7b2b7d8 | 395 | * @brief Free DMA_CH for specified SSIF channel. |
dkato | 0:702bf7b2b7d8 | 396 | * |
dkato | 0:702bf7b2b7d8 | 397 | * Description:<br> |
dkato | 0:702bf7b2b7d8 | 398 | * |
dkato | 0:702bf7b2b7d8 | 399 | * @param[in,out] p_info_ch :channel object. |
dkato | 0:702bf7b2b7d8 | 400 | * @retval none |
dkato | 0:702bf7b2b7d8 | 401 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 402 | void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch) |
dkato | 0:702bf7b2b7d8 | 403 | { |
dkato | 0:702bf7b2b7d8 | 404 | int_t dma_ret; |
dkato | 0:702bf7b2b7d8 | 405 | int32_t dma_ercd; |
dkato | 0:702bf7b2b7d8 | 406 | |
dkato | 0:702bf7b2b7d8 | 407 | if (NULL == p_info_ch) |
dkato | 0:702bf7b2b7d8 | 408 | { |
dkato | 0:702bf7b2b7d8 | 409 | /* NON_NOTICE_ASSERT: illegal pointer */ |
dkato | 0:702bf7b2b7d8 | 410 | } |
dkato | 0:702bf7b2b7d8 | 411 | else |
dkato | 0:702bf7b2b7d8 | 412 | { |
dkato | 0:702bf7b2b7d8 | 413 | if (-1 != p_info_ch->dma_tx_ch) |
dkato | 0:702bf7b2b7d8 | 414 | { |
dkato | 0:702bf7b2b7d8 | 415 | uint32_t remain; |
dkato | 0:702bf7b2b7d8 | 416 | dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 417 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 418 | { |
dkato | 0:702bf7b2b7d8 | 419 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 420 | } |
dkato | 0:702bf7b2b7d8 | 421 | } |
dkato | 0:702bf7b2b7d8 | 422 | |
dkato | 0:702bf7b2b7d8 | 423 | if (-1 != p_info_ch->dma_rx_ch) |
dkato | 0:702bf7b2b7d8 | 424 | { |
dkato | 0:702bf7b2b7d8 | 425 | uint32_t remain; |
dkato | 0:702bf7b2b7d8 | 426 | dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 427 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 428 | { |
dkato | 0:702bf7b2b7d8 | 429 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 430 | } |
dkato | 0:702bf7b2b7d8 | 431 | } |
dkato | 0:702bf7b2b7d8 | 432 | |
dkato | 0:702bf7b2b7d8 | 433 | if (-1 != p_info_ch->dma_tx_ch) |
dkato | 0:702bf7b2b7d8 | 434 | { |
dkato | 0:702bf7b2b7d8 | 435 | dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 436 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 437 | { |
dkato | 0:702bf7b2b7d8 | 438 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 439 | } |
dkato | 0:702bf7b2b7d8 | 440 | p_info_ch->dma_tx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 441 | } |
dkato | 0:702bf7b2b7d8 | 442 | |
dkato | 0:702bf7b2b7d8 | 443 | if (-1 != p_info_ch->dma_rx_ch) |
dkato | 0:702bf7b2b7d8 | 444 | { |
dkato | 0:702bf7b2b7d8 | 445 | dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 446 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 447 | { |
dkato | 0:702bf7b2b7d8 | 448 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 449 | } |
dkato | 0:702bf7b2b7d8 | 450 | p_info_ch->dma_rx_ch = -1; |
dkato | 0:702bf7b2b7d8 | 451 | } |
dkato | 0:702bf7b2b7d8 | 452 | } |
dkato | 0:702bf7b2b7d8 | 453 | |
dkato | 0:702bf7b2b7d8 | 454 | return; |
dkato | 0:702bf7b2b7d8 | 455 | } |
dkato | 0:702bf7b2b7d8 | 456 | |
dkato | 0:702bf7b2b7d8 | 457 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 458 | * Function Name: SSIF_RestartDMA |
dkato | 0:702bf7b2b7d8 | 459 | * @brief Setup DMA_CH for specified SSIF channel(without allocate) |
dkato | 0:702bf7b2b7d8 | 460 | * |
dkato | 0:702bf7b2b7d8 | 461 | * Description:<br> |
dkato | 0:702bf7b2b7d8 | 462 | * |
dkato | 0:702bf7b2b7d8 | 463 | * @param[in,out] p_info_ch :channel object. |
dkato | 0:702bf7b2b7d8 | 464 | * @retval ESUCCESS :Success. |
dkato | 0:702bf7b2b7d8 | 465 | * @retval error code :Failure. |
dkato | 0:702bf7b2b7d8 | 466 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 467 | int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch) |
dkato | 0:702bf7b2b7d8 | 468 | { |
dkato | 0:702bf7b2b7d8 | 469 | int_t ercd = ESUCCESS; |
dkato | 0:702bf7b2b7d8 | 470 | int_t dma_ret; |
dkato | 0:702bf7b2b7d8 | 471 | uint32_t ssif_ch; |
dkato | 0:702bf7b2b7d8 | 472 | int32_t dma_ercd; |
dkato | 0:702bf7b2b7d8 | 473 | dma_ch_setup_t dma_ch_setup; |
dkato | 0:702bf7b2b7d8 | 474 | uint32_t n_datawd_per_smp; |
dkato | 0:702bf7b2b7d8 | 475 | uint32_t byte_per_smp; |
dkato | 0:702bf7b2b7d8 | 476 | uint32_t dummy_smp_count; |
dkato | 0:702bf7b2b7d8 | 477 | uint32_t dummy_dma_size = 0u; |
dkato | 0:702bf7b2b7d8 | 478 | |
dkato | 0:702bf7b2b7d8 | 479 | if (NULL == p_info_ch) |
dkato | 0:702bf7b2b7d8 | 480 | { |
dkato | 0:702bf7b2b7d8 | 481 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 482 | } |
dkato | 0:702bf7b2b7d8 | 483 | else |
dkato | 0:702bf7b2b7d8 | 484 | { |
dkato | 0:702bf7b2b7d8 | 485 | ssif_ch = p_info_ch->channel; |
dkato | 0:702bf7b2b7d8 | 486 | |
dkato | 0:702bf7b2b7d8 | 487 | /* calculate dummy dma transfer size */ |
dkato | 0:702bf7b2b7d8 | 488 | n_datawd_per_smp = (uint32_t)(p_info_ch->multi_ch + 1) * SSIF_I2S_LR_CH; |
dkato | 0:702bf7b2b7d8 | 489 | byte_per_smp = n_datawd_per_smp * (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word); |
dkato | 0:702bf7b2b7d8 | 490 | |
dkato | 0:702bf7b2b7d8 | 491 | if (0u == byte_per_smp) |
dkato | 0:702bf7b2b7d8 | 492 | { |
dkato | 0:702bf7b2b7d8 | 493 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 494 | } |
dkato | 0:702bf7b2b7d8 | 495 | else |
dkato | 0:702bf7b2b7d8 | 496 | { |
dkato | 0:702bf7b2b7d8 | 497 | dummy_smp_count = SSIF_DUMMY_DMA_BUF_SIZE / byte_per_smp; |
dkato | 0:702bf7b2b7d8 | 498 | dummy_dma_size = dummy_smp_count * byte_per_smp; |
dkato | 0:702bf7b2b7d8 | 499 | |
dkato | 0:702bf7b2b7d8 | 500 | if (0u == dummy_dma_size) |
dkato | 0:702bf7b2b7d8 | 501 | { |
dkato | 0:702bf7b2b7d8 | 502 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 503 | } |
dkato | 0:702bf7b2b7d8 | 504 | } |
dkato | 0:702bf7b2b7d8 | 505 | |
dkato | 0:702bf7b2b7d8 | 506 | /* setup DMA channel for write(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 507 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 508 | { |
dkato | 0:702bf7b2b7d8 | 509 | if (O_RDONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 510 | { |
dkato | 0:702bf7b2b7d8 | 511 | AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 512 | p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD; |
dkato | 0:702bf7b2b7d8 | 513 | p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch; |
dkato | 0:702bf7b2b7d8 | 514 | p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback; |
dkato | 0:702bf7b2b7d8 | 515 | |
dkato | 0:702bf7b2b7d8 | 516 | dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 517 | dma_ch_setup.direction = DMA_REQ_DES; |
dkato | 0:702bf7b2b7d8 | 518 | dma_ch_setup.dst_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 519 | dma_ch_setup.src_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 520 | dma_ch_setup.dst_cnt = DMA_ADDR_FIX; |
dkato | 0:702bf7b2b7d8 | 521 | dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT; |
dkato | 0:702bf7b2b7d8 | 522 | dma_ch_setup.p_aio = p_tx_aio; |
dkato | 0:702bf7b2b7d8 | 523 | |
dkato | 0:702bf7b2b7d8 | 524 | dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 525 | |
dkato | 0:702bf7b2b7d8 | 526 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 527 | { |
dkato | 0:702bf7b2b7d8 | 528 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 529 | } |
dkato | 0:702bf7b2b7d8 | 530 | } |
dkato | 0:702bf7b2b7d8 | 531 | } |
dkato | 0:702bf7b2b7d8 | 532 | |
dkato | 0:702bf7b2b7d8 | 533 | /* setup DMA channel for read(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 534 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 535 | { |
dkato | 0:702bf7b2b7d8 | 536 | if (O_WRONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 537 | { |
dkato | 0:702bf7b2b7d8 | 538 | AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 539 | p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD; |
dkato | 0:702bf7b2b7d8 | 540 | p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch; |
dkato | 0:702bf7b2b7d8 | 541 | p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback; |
dkato | 0:702bf7b2b7d8 | 542 | |
dkato | 0:702bf7b2b7d8 | 543 | dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch]; |
dkato | 0:702bf7b2b7d8 | 544 | dma_ch_setup.direction = DMA_REQ_SRC; |
dkato | 0:702bf7b2b7d8 | 545 | dma_ch_setup.dst_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 546 | dma_ch_setup.src_width = DMA_UNIT_4; |
dkato | 0:702bf7b2b7d8 | 547 | dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT; |
dkato | 0:702bf7b2b7d8 | 548 | dma_ch_setup.src_cnt = DMA_ADDR_FIX; |
dkato | 0:702bf7b2b7d8 | 549 | dma_ch_setup.p_aio = p_rx_aio; |
dkato | 0:702bf7b2b7d8 | 550 | |
dkato | 0:702bf7b2b7d8 | 551 | dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 552 | |
dkato | 0:702bf7b2b7d8 | 553 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 554 | { |
dkato | 0:702bf7b2b7d8 | 555 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 556 | } |
dkato | 0:702bf7b2b7d8 | 557 | } |
dkato | 0:702bf7b2b7d8 | 558 | } |
dkato | 0:702bf7b2b7d8 | 559 | |
dkato | 0:702bf7b2b7d8 | 560 | /* start DMA dummy transfer for write(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 561 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 562 | { |
dkato | 0:702bf7b2b7d8 | 563 | if (O_RDONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 564 | { |
dkato | 0:702bf7b2b7d8 | 565 | /* setup short dummy transfer */ |
dkato | 0:702bf7b2b7d8 | 566 | gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0]; |
dkato | 0:702bf7b2b7d8 | 567 | gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR; |
dkato | 0:702bf7b2b7d8 | 568 | gb_ssif_txdma_dummy_trparam[ssif_ch].count = dummy_dma_size; |
dkato | 0:702bf7b2b7d8 | 569 | |
dkato | 0:702bf7b2b7d8 | 570 | dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 571 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 572 | { |
dkato | 0:702bf7b2b7d8 | 573 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 574 | } |
dkato | 0:702bf7b2b7d8 | 575 | else |
dkato | 0:702bf7b2b7d8 | 576 | { |
dkato | 0:702bf7b2b7d8 | 577 | dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 578 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 579 | { |
dkato | 0:702bf7b2b7d8 | 580 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 581 | } |
dkato | 0:702bf7b2b7d8 | 582 | } |
dkato | 0:702bf7b2b7d8 | 583 | } |
dkato | 0:702bf7b2b7d8 | 584 | } |
dkato | 0:702bf7b2b7d8 | 585 | |
dkato | 0:702bf7b2b7d8 | 586 | /* start DMA dummy transfer for read(if necessary) */ |
dkato | 0:702bf7b2b7d8 | 587 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 588 | { |
dkato | 0:702bf7b2b7d8 | 589 | if (O_WRONLY != p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 590 | { |
dkato | 0:702bf7b2b7d8 | 591 | /* setup short dummy transfer */ |
dkato | 0:702bf7b2b7d8 | 592 | gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR; |
dkato | 0:702bf7b2b7d8 | 593 | gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0]; |
dkato | 0:702bf7b2b7d8 | 594 | gb_ssif_rxdma_dummy_trparam[ssif_ch].count = dummy_dma_size; |
dkato | 0:702bf7b2b7d8 | 595 | |
dkato | 0:702bf7b2b7d8 | 596 | dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 597 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 598 | { |
dkato | 0:702bf7b2b7d8 | 599 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 600 | } |
dkato | 0:702bf7b2b7d8 | 601 | else |
dkato | 0:702bf7b2b7d8 | 602 | { |
dkato | 0:702bf7b2b7d8 | 603 | dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 604 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 605 | { |
dkato | 0:702bf7b2b7d8 | 606 | ercd = EFAULT; |
dkato | 0:702bf7b2b7d8 | 607 | } |
dkato | 0:702bf7b2b7d8 | 608 | } |
dkato | 0:702bf7b2b7d8 | 609 | } |
dkato | 0:702bf7b2b7d8 | 610 | } |
dkato | 0:702bf7b2b7d8 | 611 | |
dkato | 0:702bf7b2b7d8 | 612 | /* enable ssif transfer */ |
dkato | 0:702bf7b2b7d8 | 613 | if (ESUCCESS == ercd) |
dkato | 0:702bf7b2b7d8 | 614 | { |
dkato | 0:702bf7b2b7d8 | 615 | /* clear status and enable error interrupt */ |
dkato | 0:702bf7b2b7d8 | 616 | SSIF_EnableErrorInterrupt(ssif_ch); |
dkato | 0:702bf7b2b7d8 | 617 | |
dkato | 0:702bf7b2b7d8 | 618 | /* enable end interrupt */ |
dkato | 0:702bf7b2b7d8 | 619 | g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE; |
dkato | 0:702bf7b2b7d8 | 620 | |
dkato | 0:702bf7b2b7d8 | 621 | if (O_RDWR == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 622 | { |
dkato | 0:702bf7b2b7d8 | 623 | /* start write and read DMA at the same time */ |
dkato | 0:702bf7b2b7d8 | 624 | g_ssireg[ssif_ch]->SSICR |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN; |
dkato | 0:702bf7b2b7d8 | 625 | } |
dkato | 0:702bf7b2b7d8 | 626 | else if (O_WRONLY == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 627 | { |
dkato | 0:702bf7b2b7d8 | 628 | /* start write DMA only */ |
dkato | 0:702bf7b2b7d8 | 629 | g_ssireg[ssif_ch]->SSICR |= SSIF_CR_BIT_TEN; |
dkato | 0:702bf7b2b7d8 | 630 | } |
dkato | 0:702bf7b2b7d8 | 631 | else if (O_RDONLY == p_info_ch->openflag) |
dkato | 0:702bf7b2b7d8 | 632 | { |
dkato | 0:702bf7b2b7d8 | 633 | /* start read DMA only */ |
dkato | 0:702bf7b2b7d8 | 634 | g_ssireg[ssif_ch]->SSICR |= SSIF_CR_BIT_REN; |
dkato | 0:702bf7b2b7d8 | 635 | } |
dkato | 0:702bf7b2b7d8 | 636 | else |
dkato | 0:702bf7b2b7d8 | 637 | { |
dkato | 0:702bf7b2b7d8 | 638 | ercd = EINVAL; |
dkato | 0:702bf7b2b7d8 | 639 | } |
dkato | 0:702bf7b2b7d8 | 640 | } |
dkato | 0:702bf7b2b7d8 | 641 | } |
dkato | 0:702bf7b2b7d8 | 642 | |
dkato | 0:702bf7b2b7d8 | 643 | return ercd; |
dkato | 0:702bf7b2b7d8 | 644 | } |
dkato | 0:702bf7b2b7d8 | 645 | |
dkato | 0:702bf7b2b7d8 | 646 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 647 | * Function Name: SSIF_CancelDMA |
dkato | 0:702bf7b2b7d8 | 648 | * @brief Pause DMA transfer for specified SSIF channel. |
dkato | 0:702bf7b2b7d8 | 649 | * |
dkato | 0:702bf7b2b7d8 | 650 | * Description:<br> |
dkato | 0:702bf7b2b7d8 | 651 | * |
dkato | 0:702bf7b2b7d8 | 652 | * @param[in,out] p_info_ch :channel object. |
dkato | 0:702bf7b2b7d8 | 653 | * @retval none |
dkato | 0:702bf7b2b7d8 | 654 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 655 | void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch) |
dkato | 0:702bf7b2b7d8 | 656 | { |
dkato | 0:702bf7b2b7d8 | 657 | int_t dma_ret; |
dkato | 0:702bf7b2b7d8 | 658 | int32_t dma_ercd; |
dkato | 0:702bf7b2b7d8 | 659 | |
dkato | 0:702bf7b2b7d8 | 660 | if (NULL == p_info_ch) |
dkato | 0:702bf7b2b7d8 | 661 | { |
dkato | 0:702bf7b2b7d8 | 662 | /* NON_NOTICE_ASSERT: illegal pointer */ |
dkato | 0:702bf7b2b7d8 | 663 | } |
dkato | 0:702bf7b2b7d8 | 664 | else |
dkato | 0:702bf7b2b7d8 | 665 | { |
dkato | 0:702bf7b2b7d8 | 666 | if (-1 != p_info_ch->dma_tx_ch) |
dkato | 0:702bf7b2b7d8 | 667 | { |
dkato | 0:702bf7b2b7d8 | 668 | uint32_t remain; |
dkato | 0:702bf7b2b7d8 | 669 | dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 670 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 671 | { |
dkato | 0:702bf7b2b7d8 | 672 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 673 | } |
dkato | 0:702bf7b2b7d8 | 674 | } |
dkato | 0:702bf7b2b7d8 | 675 | |
dkato | 0:702bf7b2b7d8 | 676 | if (-1 != p_info_ch->dma_rx_ch) |
dkato | 0:702bf7b2b7d8 | 677 | { |
dkato | 0:702bf7b2b7d8 | 678 | uint32_t remain; |
dkato | 0:702bf7b2b7d8 | 679 | dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd); |
dkato | 0:702bf7b2b7d8 | 680 | if (EERROR == dma_ret) |
dkato | 0:702bf7b2b7d8 | 681 | { |
dkato | 0:702bf7b2b7d8 | 682 | /* NON_NOTICE_ASSERT: unexpected dma error */ |
dkato | 0:702bf7b2b7d8 | 683 | } |
dkato | 0:702bf7b2b7d8 | 684 | } |
dkato | 0:702bf7b2b7d8 | 685 | } |
dkato | 0:702bf7b2b7d8 | 686 | |
dkato | 0:702bf7b2b7d8 | 687 | return; |
dkato | 0:702bf7b2b7d8 | 688 | } |
dkato | 0:702bf7b2b7d8 | 689 | |
dkato | 0:702bf7b2b7d8 | 690 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 691 | Private functions |
dkato | 0:702bf7b2b7d8 | 692 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 693 | |
dkato | 0:702bf7b2b7d8 | 694 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 695 | * Function Name: SSIF_DMA_TxCallback |
dkato | 0:702bf7b2b7d8 | 696 | * @brief DMA callback function |
dkato | 0:702bf7b2b7d8 | 697 | * |
dkato | 0:702bf7b2b7d8 | 698 | * Description:<br> |
dkato | 0:702bf7b2b7d8 | 699 | * |
dkato | 0:702bf7b2b7d8 | 700 | * @param[in] param :callback param |
dkato | 0:702bf7b2b7d8 | 701 | * @retval none |
dkato | 0:702bf7b2b7d8 | 702 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 703 | static void SSIF_DMA_TxCallback(const union sigval param) |
dkato | 0:702bf7b2b7d8 | 704 | { |
dkato | 0:702bf7b2b7d8 | 705 | ssif_info_ch_t* const p_info_ch = param.sival_ptr; |
dkato | 0:702bf7b2b7d8 | 706 | uint32_t ssif_ch; |
dkato | 0:702bf7b2b7d8 | 707 | dma_trans_data_t dma_data_next; |
dkato | 0:702bf7b2b7d8 | 708 | int_t ercd = ESUCCESS; |
dkato | 0:702bf7b2b7d8 | 709 | int_t ret; |
dkato | 0:702bf7b2b7d8 | 710 | |
dkato | 0:702bf7b2b7d8 | 711 | |
dkato | 0:702bf7b2b7d8 | 712 | if (NULL == p_info_ch) |
dkato | 0:702bf7b2b7d8 | 713 | { |
dkato | 0:702bf7b2b7d8 | 714 | /* NON_NOTICE_ASSERT: illegal pointer */ |
dkato | 0:702bf7b2b7d8 | 715 | } |
dkato | 0:702bf7b2b7d8 | 716 | else |
dkato | 0:702bf7b2b7d8 | 717 | { |
dkato | 0:702bf7b2b7d8 | 718 | ssif_ch = p_info_ch->channel; |
dkato | 0:702bf7b2b7d8 | 719 | |
dkato | 0:702bf7b2b7d8 | 720 | if (NULL == p_info_ch->p_aio_tx_curr) |
dkato | 0:702bf7b2b7d8 | 721 | { |
dkato | 0:702bf7b2b7d8 | 722 | /* now complete dummy transfer, It isn't neccessary to signal. */ |
dkato | 0:702bf7b2b7d8 | 723 | } |
dkato | 0:702bf7b2b7d8 | 724 | else |
dkato | 0:702bf7b2b7d8 | 725 | { |
dkato | 0:702bf7b2b7d8 | 726 | /* now complete user request transfer, Signal to application */ |
dkato | 0:702bf7b2b7d8 | 727 | |
dkato | 0:702bf7b2b7d8 | 728 | /* return aio complete */ |
dkato | 0:702bf7b2b7d8 | 729 | p_info_ch->p_aio_tx_curr->aio_return = (ssize_t)p_info_ch->p_aio_tx_curr->aio_nbytes; |
dkato | 0:702bf7b2b7d8 | 730 | ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr); |
dkato | 0:702bf7b2b7d8 | 731 | } |
dkato | 0:702bf7b2b7d8 | 732 | |
dkato | 0:702bf7b2b7d8 | 733 | /* copy next to curr(even if it's NULL) */ |
dkato | 0:702bf7b2b7d8 | 734 | p_info_ch->p_aio_tx_curr = p_info_ch->p_aio_tx_next; |
dkato | 0:702bf7b2b7d8 | 735 | |
dkato | 0:702bf7b2b7d8 | 736 | /* get next request(It's maybe NULL) */ |
dkato | 0:702bf7b2b7d8 | 737 | p_info_ch->p_aio_tx_next = ahf_removehead(&p_info_ch->tx_que); |
dkato | 0:702bf7b2b7d8 | 738 | |
dkato | 0:702bf7b2b7d8 | 739 | if (NULL != p_info_ch->p_aio_tx_next) |
dkato | 0:702bf7b2b7d8 | 740 | { |
dkato | 0:702bf7b2b7d8 | 741 | /* add user request */ |
dkato | 0:702bf7b2b7d8 | 742 | dma_data_next.dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR; |
dkato | 0:702bf7b2b7d8 | 743 | dma_data_next.src_addr = (void*)p_info_ch->p_aio_tx_next->aio_buf; |
dkato | 0:702bf7b2b7d8 | 744 | dma_data_next.count = (uint32_t)p_info_ch->p_aio_tx_next->aio_nbytes; |
dkato | 0:702bf7b2b7d8 | 745 | |
dkato | 0:702bf7b2b7d8 | 746 | ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_data_next, &ercd); |
dkato | 0:702bf7b2b7d8 | 747 | if (EERROR == ret) |
dkato | 0:702bf7b2b7d8 | 748 | { |
dkato | 0:702bf7b2b7d8 | 749 | /* NON_NOTICE_ASSERT: unexpected DMA error */ |
dkato | 0:702bf7b2b7d8 | 750 | } |
dkato | 0:702bf7b2b7d8 | 751 | } |
dkato | 0:702bf7b2b7d8 | 752 | else |
dkato | 0:702bf7b2b7d8 | 753 | { |
dkato | 0:702bf7b2b7d8 | 754 | /* add dummy request */ |
dkato | 0:702bf7b2b7d8 | 755 | ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &ercd); |
dkato | 0:702bf7b2b7d8 | 756 | if (EERROR == ret) |
dkato | 0:702bf7b2b7d8 | 757 | { |
dkato | 0:702bf7b2b7d8 | 758 | /* NON_NOTICE_ASSERT: unexpected DMA error */ |
dkato | 0:702bf7b2b7d8 | 759 | } |
dkato | 0:702bf7b2b7d8 | 760 | } |
dkato | 0:702bf7b2b7d8 | 761 | } |
dkato | 0:702bf7b2b7d8 | 762 | |
dkato | 0:702bf7b2b7d8 | 763 | return; |
dkato | 0:702bf7b2b7d8 | 764 | } |
dkato | 0:702bf7b2b7d8 | 765 | |
dkato | 0:702bf7b2b7d8 | 766 | /****************************************************************************** |
dkato | 0:702bf7b2b7d8 | 767 | * Function Name: SSIF_DMA_RxCallback |
dkato | 0:702bf7b2b7d8 | 768 | * @brief DMA callback function |
dkato | 0:702bf7b2b7d8 | 769 | * |
dkato | 0:702bf7b2b7d8 | 770 | * Description:<br> |
dkato | 0:702bf7b2b7d8 | 771 | * |
dkato | 0:702bf7b2b7d8 | 772 | * @param[in] param :callback param |
dkato | 0:702bf7b2b7d8 | 773 | * @retval none |
dkato | 0:702bf7b2b7d8 | 774 | ******************************************************************************/ |
dkato | 0:702bf7b2b7d8 | 775 | static void SSIF_DMA_RxCallback(const union sigval param) |
dkato | 0:702bf7b2b7d8 | 776 | { |
dkato | 0:702bf7b2b7d8 | 777 | ssif_info_ch_t* const p_info_ch = param.sival_ptr; |
dkato | 0:702bf7b2b7d8 | 778 | uint32_t ssif_ch; |
dkato | 0:702bf7b2b7d8 | 779 | dma_trans_data_t dma_data_next; |
dkato | 0:702bf7b2b7d8 | 780 | int_t ercd = ESUCCESS; |
dkato | 0:702bf7b2b7d8 | 781 | int_t ret; |
dkato | 0:702bf7b2b7d8 | 782 | |
dkato | 0:702bf7b2b7d8 | 783 | if (NULL == p_info_ch) |
dkato | 0:702bf7b2b7d8 | 784 | { |
dkato | 0:702bf7b2b7d8 | 785 | /* NON_NOTICE_ASSERT: illegal pointer */ |
dkato | 0:702bf7b2b7d8 | 786 | } |
dkato | 0:702bf7b2b7d8 | 787 | else |
dkato | 0:702bf7b2b7d8 | 788 | { |
dkato | 0:702bf7b2b7d8 | 789 | ssif_ch = p_info_ch->channel; |
dkato | 0:702bf7b2b7d8 | 790 | |
dkato | 0:702bf7b2b7d8 | 791 | if (NULL == p_info_ch->p_aio_rx_curr) |
dkato | 0:702bf7b2b7d8 | 792 | { |
dkato | 0:702bf7b2b7d8 | 793 | /* now complete dummy transfer, It isn't neccessary to signal. */ |
dkato | 0:702bf7b2b7d8 | 794 | } |
dkato | 0:702bf7b2b7d8 | 795 | else |
dkato | 0:702bf7b2b7d8 | 796 | { |
dkato | 0:702bf7b2b7d8 | 797 | /* now complete user request transfer, Signal to application */ |
dkato | 0:702bf7b2b7d8 | 798 | |
dkato | 0:702bf7b2b7d8 | 799 | /* return aio complete */ |
dkato | 0:702bf7b2b7d8 | 800 | p_info_ch->p_aio_rx_curr->aio_return = (ssize_t)p_info_ch->p_aio_rx_curr->aio_nbytes; |
dkato | 0:702bf7b2b7d8 | 801 | ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr); |
dkato | 0:702bf7b2b7d8 | 802 | } |
dkato | 0:702bf7b2b7d8 | 803 | |
dkato | 0:702bf7b2b7d8 | 804 | /* copy next to curr(even if it's NULL) */ |
dkato | 0:702bf7b2b7d8 | 805 | p_info_ch->p_aio_rx_curr = p_info_ch->p_aio_rx_next; |
dkato | 0:702bf7b2b7d8 | 806 | |
dkato | 0:702bf7b2b7d8 | 807 | /* get next request(It's maybe NULL) */ |
dkato | 0:702bf7b2b7d8 | 808 | p_info_ch->p_aio_rx_next = ahf_removehead(&p_info_ch->rx_que); |
dkato | 0:702bf7b2b7d8 | 809 | |
dkato | 0:702bf7b2b7d8 | 810 | if (NULL != p_info_ch->p_aio_rx_next) |
dkato | 0:702bf7b2b7d8 | 811 | { |
dkato | 0:702bf7b2b7d8 | 812 | /* add user request */ |
dkato | 0:702bf7b2b7d8 | 813 | dma_data_next.src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR; |
dkato | 0:702bf7b2b7d8 | 814 | dma_data_next.dst_addr = (void*)p_info_ch->p_aio_rx_next->aio_buf; |
dkato | 0:702bf7b2b7d8 | 815 | dma_data_next.count = (uint32_t)p_info_ch->p_aio_rx_next->aio_nbytes; |
dkato | 0:702bf7b2b7d8 | 816 | |
dkato | 0:702bf7b2b7d8 | 817 | ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &dma_data_next, &ercd); |
dkato | 0:702bf7b2b7d8 | 818 | if (EERROR == ret) |
dkato | 0:702bf7b2b7d8 | 819 | { |
dkato | 0:702bf7b2b7d8 | 820 | /* NON_NOTICE_ASSERT: unexpected DMA error */ |
dkato | 0:702bf7b2b7d8 | 821 | } |
dkato | 0:702bf7b2b7d8 | 822 | } |
dkato | 0:702bf7b2b7d8 | 823 | else |
dkato | 0:702bf7b2b7d8 | 824 | { |
dkato | 0:702bf7b2b7d8 | 825 | /* add dummy request */ |
dkato | 0:702bf7b2b7d8 | 826 | ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &ercd); |
dkato | 0:702bf7b2b7d8 | 827 | if (EERROR == ret) |
dkato | 0:702bf7b2b7d8 | 828 | { |
dkato | 0:702bf7b2b7d8 | 829 | /* NON_NOTICE_ASSERT: unexpected DMA error */ |
dkato | 0:702bf7b2b7d8 | 830 | } |
dkato | 0:702bf7b2b7d8 | 831 | } |
dkato | 0:702bf7b2b7d8 | 832 | } |
dkato | 0:702bf7b2b7d8 | 833 | |
dkato | 0:702bf7b2b7d8 | 834 | return; |
dkato | 0:702bf7b2b7d8 | 835 | } |