RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Mon Jun 01 08:33:21 2015 +0000
Revision:
0:702bf7b2b7d8
Child:
5:1390bfcb667c
first comit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /*******************************************************************************
dkato 0:702bf7b2b7d8 25 * File Name : ssif_cfg.c
dkato 0:702bf7b2b7d8 26 * $Rev: 891 $
dkato 0:702bf7b2b7d8 27 * $Date:: 2014-06-27 10:40:52 +0900#$
dkato 0:702bf7b2b7d8 28 * Description : SSIF driver userown functions
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*******************************************************************************
dkato 0:702bf7b2b7d8 32 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 33 *******************************************************************************/
dkato 0:702bf7b2b7d8 34 #include "dma_if.h"
dkato 0:702bf7b2b7d8 35 #include "ssif_if.h"
dkato 0:702bf7b2b7d8 36 #include "iodefine.h"
dkato 0:702bf7b2b7d8 37 #include "Renesas_RZ_A1.h"
dkato 0:702bf7b2b7d8 38
dkato 0:702bf7b2b7d8 39 /*******************************************************************************
dkato 0:702bf7b2b7d8 40 Macro definitions
dkato 0:702bf7b2b7d8 41 *******************************************************************************/
dkato 0:702bf7b2b7d8 42
dkato 0:702bf7b2b7d8 43 /***** Audio Clock Source Configurations *****/
dkato 0:702bf7b2b7d8 44 /* AUDIO_X1 : Connect to CPU Board X8(22579200Hz) */
dkato 0:702bf7b2b7d8 45 #define SSIF_AUDIO_X1 (22579200u)
dkato 0:702bf7b2b7d8 46
dkato 0:702bf7b2b7d8 47 /* AUDIO_CLK: Connect to option board J7(no clock on board) */
dkato 0:702bf7b2b7d8 48 #define SSIF_AUDIO_CLK (0u)
dkato 0:702bf7b2b7d8 49
dkato 0:702bf7b2b7d8 50 /* SSICR CKDV divieded value */
dkato 0:702bf7b2b7d8 51 #define SSIF_AUDIO_CLK_DIV_1 (1u)
dkato 0:702bf7b2b7d8 52 #define SSIF_AUDIO_CLK_DIV_2 (2u)
dkato 0:702bf7b2b7d8 53 #define SSIF_AUDIO_CLK_DIV_4 (4u)
dkato 0:702bf7b2b7d8 54 #define SSIF_AUDIO_CLK_DIV_8 (8u)
dkato 0:702bf7b2b7d8 55 #define SSIF_AUDIO_CLK_DIV_16 (16u)
dkato 0:702bf7b2b7d8 56 #define SSIF_AUDIO_CLK_DIV_32 (32u)
dkato 0:702bf7b2b7d8 57 #define SSIF_AUDIO_CLK_DIV_64 (64u)
dkato 0:702bf7b2b7d8 58 #define SSIF_AUDIO_CLK_DIV_128 (128u)
dkato 0:702bf7b2b7d8 59 #define SSIF_AUDIO_CLK_DIV_6 (6u)
dkato 0:702bf7b2b7d8 60 #define SSIF_AUDIO_CLK_DIV_12 (12u)
dkato 0:702bf7b2b7d8 61 #define SSIF_AUDIO_CLK_DIV_24 (24u)
dkato 0:702bf7b2b7d8 62 #define SSIF_AUDIO_CLK_DIV_48 (48u)
dkato 0:702bf7b2b7d8 63 #define SSIF_AUDIO_CLK_DIV_96 (96u)
dkato 0:702bf7b2b7d8 64
dkato 0:702bf7b2b7d8 65 /* SSIF channel number */
dkato 0:702bf7b2b7d8 66 #define SSIF_CHNUM_0 (0u)
dkato 0:702bf7b2b7d8 67 #define SSIF_CHNUM_1 (1u)
dkato 0:702bf7b2b7d8 68 #define SSIF_CHNUM_2 (2u)
dkato 0:702bf7b2b7d8 69 #define SSIF_CHNUM_3 (3u)
dkato 0:702bf7b2b7d8 70 #define SSIF_CHNUM_4 (4u)
dkato 0:702bf7b2b7d8 71 #define SSIF_CHNUM_5 (5u)
dkato 0:702bf7b2b7d8 72
dkato 0:702bf7b2b7d8 73 /* misc constant value */
dkato 0:702bf7b2b7d8 74 #define SSIF_I2S_LR_CH (2u)
dkato 0:702bf7b2b7d8 75
dkato 0:702bf7b2b7d8 76 /*******************************************************************************
dkato 0:702bf7b2b7d8 77 Exported global variables (to be accessed by other files)
dkato 0:702bf7b2b7d8 78 *******************************************************************************/
dkato 0:702bf7b2b7d8 79
dkato 0:702bf7b2b7d8 80 /******************************************************************************
dkato 0:702bf7b2b7d8 81 * Function Name: R_SSIF_Userdef_InitPinMux
dkato 0:702bf7b2b7d8 82 * @brief This function initialise pin multiplex settings.
dkato 0:702bf7b2b7d8 83 *
dkato 0:702bf7b2b7d8 84 * Description:<br>
dkato 0:702bf7b2b7d8 85 * R7S72100 Boards depended pin connections bellow<br>
dkato 0:702bf7b2b7d8 86 * Clock settings<br>
dkato 0:702bf7b2b7d8 87 * AUDIO_X1 : Private use pin(nothing to do)<br>
dkato 0:702bf7b2b7d8 88 * AUDIO_X2 : No connection<br>
dkato 0:702bf7b2b7d8 89 * AUDIO_CLK: Working with SSIF5<br>
dkato 0:702bf7b2b7d8 90 * Channel settings<br>
dkato 0:702bf7b2b7d8 91 * SSIF0 : Fully connected to WM8978<br>
dkato 0:702bf7b2b7d8 92 * SSIF1 : Read only (NC:SSITxD1) connected to CD Deck<br>
dkato 0:702bf7b2b7d8 93 * SSIF2 : No connection<br>
dkato 0:702bf7b2b7d8 94 * SSIF3 : Write only (NC:SSIRxD3) connected to AK4353<br>
dkato 0:702bf7b2b7d8 95 * SSIF4 : Fully connected to AK4353<br>
dkato 0:702bf7b2b7d8 96 * SSIF5 : Fully connected to HCI
dkato 0:702bf7b2b7d8 97 * @param[in] ssif_ch :channel number.
dkato 0:702bf7b2b7d8 98 * @retval ESUCCESS :Success.
dkato 0:702bf7b2b7d8 99 * @retval error code :Failure.
dkato 0:702bf7b2b7d8 100 ******************************************************************************/
dkato 0:702bf7b2b7d8 101 int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
dkato 0:702bf7b2b7d8 102 {
dkato 0:702bf7b2b7d8 103 #if(1) /* mbed */
dkato 0:702bf7b2b7d8 104 UNUSED_ARG(ssif_ch);
dkato 0:702bf7b2b7d8 105
dkato 0:702bf7b2b7d8 106 return ESUCCESS;
dkato 0:702bf7b2b7d8 107 #else
dkato 0:702bf7b2b7d8 108 int_t ercd = ESUCCESS;
dkato 0:702bf7b2b7d8 109 int_t was_masked;
dkato 0:702bf7b2b7d8 110
dkato 0:702bf7b2b7d8 111 was_masked = __disable_irq();
dkato 0:702bf7b2b7d8 112
dkato 0:702bf7b2b7d8 113 /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
dkato 0:702bf7b2b7d8 114 switch (ssif_ch)
dkato 0:702bf7b2b7d8 115 {
dkato 0:702bf7b2b7d8 116 case SSIF_CHNUM_0:
dkato 0:702bf7b2b7d8 117 /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
dkato 0:702bf7b2b7d8 118 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 119 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 120 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 121 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 122 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 123
dkato 0:702bf7b2b7d8 124 GPIO.PBDC4 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 125 GPIO.PFC4 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 126 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 127 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 128
dkato 0:702bf7b2b7d8 129 GPIO.PIPC4 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 130 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 131
dkato 0:702bf7b2b7d8 132 /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
dkato 0:702bf7b2b7d8 133 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 134 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 135 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 136 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 137 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 138
dkato 0:702bf7b2b7d8 139 GPIO.PBDC4 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 140 GPIO.PFC4 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 141 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 142 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 143
dkato 0:702bf7b2b7d8 144 GPIO.PIPC4 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 145 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 146
dkato 0:702bf7b2b7d8 147 /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
dkato 0:702bf7b2b7d8 148 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 149 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 150 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 151 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 152 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 153
dkato 0:702bf7b2b7d8 154 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 155 GPIO.PFC4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 156 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 157 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 158
dkato 0:702bf7b2b7d8 159 GPIO.PIPC4 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 160 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 161
dkato 0:702bf7b2b7d8 162 /* SSITxD0(P4_7, Alternative Mode 5,Output) */
dkato 0:702bf7b2b7d8 163 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 164 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 165 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 166 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 167 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 168
dkato 0:702bf7b2b7d8 169 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 170 GPIO.PFC4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 171 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 172 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 173
dkato 0:702bf7b2b7d8 174 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 175 GPIO.PM4 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 176 break;
dkato 0:702bf7b2b7d8 177
dkato 0:702bf7b2b7d8 178 case SSIF_CHNUM_1:
dkato 0:702bf7b2b7d8 179 /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
dkato 0:702bf7b2b7d8 180 GPIO.PIBC3 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 181 GPIO.PBDC3 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 182 GPIO.PM3 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 183 GPIO.PMC3 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 184 GPIO.PIPC3 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 185
dkato 0:702bf7b2b7d8 186 GPIO.PBDC3 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 187 GPIO.PFC3 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 188 GPIO.PFCE3 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 189 GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 190
dkato 0:702bf7b2b7d8 191 GPIO.PIPC3 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 192 GPIO.PMC3 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 193
dkato 0:702bf7b2b7d8 194 /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
dkato 0:702bf7b2b7d8 195 GPIO.PIBC3 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 196 GPIO.PBDC3 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 197 GPIO.PM3 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 198 GPIO.PMC3 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 199 GPIO.PIPC3 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 200
dkato 0:702bf7b2b7d8 201 GPIO.PBDC3 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 202 GPIO.PFC3 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 203 GPIO.PFCE3 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 204 GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 205
dkato 0:702bf7b2b7d8 206 GPIO.PIPC3 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 207 GPIO.PMC3 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 208
dkato 0:702bf7b2b7d8 209 /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
dkato 0:702bf7b2b7d8 210 GPIO.PIBC3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 211 GPIO.PBDC3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 212 GPIO.PM3 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 213 GPIO.PMC3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 214 GPIO.PIPC3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 215
dkato 0:702bf7b2b7d8 216 GPIO.PBDC3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 217 GPIO.PFC3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 218 GPIO.PFCE3 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 219 GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 220
dkato 0:702bf7b2b7d8 221 GPIO.PIPC3 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 222 GPIO.PMC3 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 223
dkato 0:702bf7b2b7d8 224 /* SSITxD1: no connection */
dkato 0:702bf7b2b7d8 225 break;
dkato 0:702bf7b2b7d8 226
dkato 0:702bf7b2b7d8 227 case SSIF_CHNUM_2:
dkato 0:702bf7b2b7d8 228 /* SSISCK2: no connection */
dkato 0:702bf7b2b7d8 229 /* SSIWS2: no connection */
dkato 0:702bf7b2b7d8 230 /* SSIDATA2: no connection */
dkato 0:702bf7b2b7d8 231 break;
dkato 0:702bf7b2b7d8 232
dkato 0:702bf7b2b7d8 233 case SSIF_CHNUM_3:
dkato 0:702bf7b2b7d8 234 /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
dkato 0:702bf7b2b7d8 235 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 236 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 237 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 238 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 239 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 240
dkato 0:702bf7b2b7d8 241 GPIO.PBDC4 |= (uint16_t) (GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 242 GPIO.PFC4 |= (uint16_t) (GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 243 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 244 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 245
dkato 0:702bf7b2b7d8 246 GPIO.PIPC4 |= (uint16_t) GPIO_BIT_N12;
dkato 0:702bf7b2b7d8 247 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N12);
dkato 0:702bf7b2b7d8 248
dkato 0:702bf7b2b7d8 249 /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
dkato 0:702bf7b2b7d8 250 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 251 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 252 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 253 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 254 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 255
dkato 0:702bf7b2b7d8 256 GPIO.PBDC4 |= (uint16_t) (GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 257 GPIO.PFC4 |= (uint16_t) (GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 258 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 259 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 260
dkato 0:702bf7b2b7d8 261 GPIO.PIPC4 |= (uint16_t) (GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 262 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N13);
dkato 0:702bf7b2b7d8 263
dkato 0:702bf7b2b7d8 264 /* SSIRxD3: no connection */
dkato 0:702bf7b2b7d8 265
dkato 0:702bf7b2b7d8 266 /* SSITxD3(P4_15, Alternative Mode 6,Output) */
dkato 0:702bf7b2b7d8 267 GPIO.PIBC4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 268 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 269 GPIO.PM4 |= (uint16_t) (GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 270 GPIO.PMC4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 271 GPIO.PIPC4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 272
dkato 0:702bf7b2b7d8 273 GPIO.PBDC4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 274 GPIO.PFC4 |= (uint16_t) (GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 275 GPIO.PFCE4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 276 GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 277
dkato 0:702bf7b2b7d8 278 GPIO.PMC4 |= (uint16_t) (GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 279 GPIO.PM4 &= (uint16_t)~(GPIO_BIT_N15);
dkato 0:702bf7b2b7d8 280 break;
dkato 0:702bf7b2b7d8 281
dkato 0:702bf7b2b7d8 282 case SSIF_CHNUM_4:
dkato 0:702bf7b2b7d8 283 /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
dkato 0:702bf7b2b7d8 284 GPIO.PIBC11 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 285 GPIO.PBDC11 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 286 GPIO.PM11 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 287 GPIO.PMC11 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 288 GPIO.PIPC11 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 289
dkato 0:702bf7b2b7d8 290 GPIO.PBDC11 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 291 GPIO.PFC11 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 292 GPIO.PFCE11 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 293 GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 294
dkato 0:702bf7b2b7d8 295 GPIO.PIPC11 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 296 GPIO.PMC11 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 297
dkato 0:702bf7b2b7d8 298 /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
dkato 0:702bf7b2b7d8 299 GPIO.PIBC11 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 300 GPIO.PBDC11 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 301 GPIO.PM11 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 302 GPIO.PMC11 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 303 GPIO.PIPC11 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 304
dkato 0:702bf7b2b7d8 305 GPIO.PBDC11 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 306 GPIO.PFC11 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 307 GPIO.PFCE11 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 308 GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 309
dkato 0:702bf7b2b7d8 310 GPIO.PIPC11 |= (uint16_t) GPIO_BIT_N5;
dkato 0:702bf7b2b7d8 311 GPIO.PMC11 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 312
dkato 0:702bf7b2b7d8 313 /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
dkato 0:702bf7b2b7d8 314 GPIO.PIBC11 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 315 GPIO.PBDC11 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 316 GPIO.PM11 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 317 GPIO.PMC11 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 318 GPIO.PIPC11 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 319
dkato 0:702bf7b2b7d8 320 GPIO.PBDC11 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 321 GPIO.PFC11 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 322 GPIO.PFCE11 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 323 GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 324
dkato 0:702bf7b2b7d8 325 GPIO.PIPC11 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 326 GPIO.PMC11 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 327 break;
dkato 0:702bf7b2b7d8 328
dkato 0:702bf7b2b7d8 329 case SSIF_CHNUM_5:
dkato 0:702bf7b2b7d8 330 /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
dkato 0:702bf7b2b7d8 331 GPIO.PIBC2 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 332 GPIO.PBDC2 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 333 GPIO.PM2 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 334 GPIO.PMC2 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 335 GPIO.PIPC2 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 336
dkato 0:702bf7b2b7d8 337 GPIO.PBDC2 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 338 GPIO.PFC2 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 339 GPIO.PFCE2 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 340 GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 341
dkato 0:702bf7b2b7d8 342 GPIO.PIPC2 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 343 GPIO.PMC2 |= (uint16_t) (GPIO_BIT_N4);
dkato 0:702bf7b2b7d8 344
dkato 0:702bf7b2b7d8 345 /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
dkato 0:702bf7b2b7d8 346 GPIO.PIBC2 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 347 GPIO.PBDC2 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 348 GPIO.PM2 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 349 GPIO.PMC2 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 350 GPIO.PIPC2 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 351
dkato 0:702bf7b2b7d8 352 GPIO.PBDC2 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 353 GPIO.PFC2 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 354 GPIO.PFCE2 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 355 GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 356
dkato 0:702bf7b2b7d8 357 GPIO.PIPC2 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 358 GPIO.PMC2 |= (uint16_t) (GPIO_BIT_N5);
dkato 0:702bf7b2b7d8 359
dkato 0:702bf7b2b7d8 360 /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
dkato 0:702bf7b2b7d8 361 GPIO.PIBC2 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 362 GPIO.PBDC2 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 363 GPIO.PM2 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 364 GPIO.PMC2 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 365 GPIO.PIPC2 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 366
dkato 0:702bf7b2b7d8 367 GPIO.PBDC2 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 368 GPIO.PFC2 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 369 GPIO.PFCE2 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 370 GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 371
dkato 0:702bf7b2b7d8 372 GPIO.PIPC2 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 373 GPIO.PMC2 |= (uint16_t) (GPIO_BIT_N6);
dkato 0:702bf7b2b7d8 374
dkato 0:702bf7b2b7d8 375 /* SSITxD5(P2_7, Alternative Mode 4,Output) */
dkato 0:702bf7b2b7d8 376 GPIO.PIBC2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 377 GPIO.PBDC2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 378 GPIO.PM2 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 379 GPIO.PMC2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 380 GPIO.PIPC2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 381
dkato 0:702bf7b2b7d8 382 GPIO.PBDC2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 383 GPIO.PFC2 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 384 GPIO.PFCE2 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 385 GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 386
dkato 0:702bf7b2b7d8 387 GPIO.PMC2 |= (uint16_t) (GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 388 GPIO.PM2 &= (uint16_t)~(GPIO_BIT_N7);
dkato 0:702bf7b2b7d8 389
dkato 0:702bf7b2b7d8 390 /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
dkato 0:702bf7b2b7d8 391 GPIO.PIBC3 &= (uint16_t)~(GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 392 GPIO.PBDC3 &= (uint16_t)~(GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 393 GPIO.PM3 |= (uint16_t) (GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 394 GPIO.PMC3 &= (uint16_t)~(GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 395 GPIO.PIPC3 &= (uint16_t)~(GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 396
dkato 0:702bf7b2b7d8 397 GPIO.PBDC3 &= (uint16_t)~(GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 398 GPIO.PFC3 |= (uint16_t) (GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 399 GPIO.PFCE3 &= (uint16_t)~(GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 400 GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 401
dkato 0:702bf7b2b7d8 402 GPIO.PIPC3 |= (uint16_t) (GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 403 GPIO.PMC3 |= (uint16_t) (GPIO_BIT_N1);
dkato 0:702bf7b2b7d8 404 break;
dkato 0:702bf7b2b7d8 405
dkato 0:702bf7b2b7d8 406 default:
dkato 0:702bf7b2b7d8 407 ercd = EINVAL;
dkato 0:702bf7b2b7d8 408 break;
dkato 0:702bf7b2b7d8 409 }
dkato 0:702bf7b2b7d8 410 /* <- IPA R2.4.2 */
dkato 0:702bf7b2b7d8 411
dkato 0:702bf7b2b7d8 412 if (0 == was_masked)
dkato 0:702bf7b2b7d8 413 {
dkato 0:702bf7b2b7d8 414 __enable_irq();
dkato 0:702bf7b2b7d8 415 }
dkato 0:702bf7b2b7d8 416
dkato 0:702bf7b2b7d8 417 return ercd;
dkato 0:702bf7b2b7d8 418 #endif
dkato 0:702bf7b2b7d8 419 }
dkato 0:702bf7b2b7d8 420
dkato 0:702bf7b2b7d8 421 /******************************************************************************
dkato 0:702bf7b2b7d8 422 * Function Name: R_SSIF_Userdef_SetClockDiv
dkato 0:702bf7b2b7d8 423 * @brief This function make a value of divieded audio clock.
dkato 0:702bf7b2b7d8 424 *
dkato 0:702bf7b2b7d8 425 * Description:<br>
dkato 0:702bf7b2b7d8 426 *
dkato 0:702bf7b2b7d8 427 * @param[in] p_ch_cfg :pointer of channel configuration parameter.
dkato 0:702bf7b2b7d8 428 * @param[in,out] p_clk_div :pointer of SSICR register CKDV value
dkato 0:702bf7b2b7d8 429 * @retval ESUCCESS :Success.
dkato 0:702bf7b2b7d8 430 * @retval error code :Failure.
dkato 0:702bf7b2b7d8 431 ******************************************************************************/
dkato 0:702bf7b2b7d8 432 int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div)
dkato 0:702bf7b2b7d8 433 {
dkato 0:702bf7b2b7d8 434 uint32_t input_clk;
dkato 0:702bf7b2b7d8 435 uint32_t dot_clk;
dkato 0:702bf7b2b7d8 436 uint32_t n_syswd_per_smp;
dkato 0:702bf7b2b7d8 437 uint32_t syswd_len;
dkato 0:702bf7b2b7d8 438 uint32_t smp_freq;
dkato 0:702bf7b2b7d8 439 uint32_t result;
dkato 0:702bf7b2b7d8 440 uint32_t division;
dkato 0:702bf7b2b7d8 441 int_t ret = ESUCCESS;
dkato 0:702bf7b2b7d8 442
dkato 0:702bf7b2b7d8 443 if ((NULL == p_ch_cfg) || (NULL == p_clk_div))
dkato 0:702bf7b2b7d8 444 {
dkato 0:702bf7b2b7d8 445 ret = EFAULT;
dkato 0:702bf7b2b7d8 446 }
dkato 0:702bf7b2b7d8 447 else
dkato 0:702bf7b2b7d8 448 {
dkato 0:702bf7b2b7d8 449 if (SSIF_CFG_CKS_AUDIO_X1 == p_ch_cfg->clk_select)
dkato 0:702bf7b2b7d8 450 {
dkato 0:702bf7b2b7d8 451 input_clk = SSIF_AUDIO_X1;
dkato 0:702bf7b2b7d8 452 }
dkato 0:702bf7b2b7d8 453 else if (SSIF_CFG_CKS_AUDIO_CLK == p_ch_cfg->clk_select)
dkato 0:702bf7b2b7d8 454 {
dkato 0:702bf7b2b7d8 455 input_clk = SSIF_AUDIO_CLK;
dkato 0:702bf7b2b7d8 456 }
dkato 0:702bf7b2b7d8 457 else
dkato 0:702bf7b2b7d8 458 {
dkato 0:702bf7b2b7d8 459 input_clk = 0u;
dkato 0:702bf7b2b7d8 460 }
dkato 0:702bf7b2b7d8 461
dkato 0:702bf7b2b7d8 462 if (0u == input_clk)
dkato 0:702bf7b2b7d8 463 {
dkato 0:702bf7b2b7d8 464 ret = EINVAL;
dkato 0:702bf7b2b7d8 465 }
dkato 0:702bf7b2b7d8 466
dkato 0:702bf7b2b7d8 467 if (ESUCCESS == ret)
dkato 0:702bf7b2b7d8 468 {
dkato 0:702bf7b2b7d8 469 syswd_len = (uint32_t)R_SSIF_SWLtoLen(p_ch_cfg->system_word);
dkato 0:702bf7b2b7d8 470 smp_freq = p_ch_cfg->sample_freq;
dkato 0:702bf7b2b7d8 471
dkato 0:702bf7b2b7d8 472 if (SSIF_CFG_DISABLE_TDM == p_ch_cfg->tdm_mode)
dkato 0:702bf7b2b7d8 473 {
dkato 0:702bf7b2b7d8 474 /* I2S format has 2 system_words */
dkato 0:702bf7b2b7d8 475 n_syswd_per_smp = SSIF_I2S_LR_CH;
dkato 0:702bf7b2b7d8 476 }
dkato 0:702bf7b2b7d8 477 else
dkato 0:702bf7b2b7d8 478 {
dkato 0:702bf7b2b7d8 479 /* TDM frame has [(CHNL+1) * 2] system_words */
dkato 0:702bf7b2b7d8 480 n_syswd_per_smp = (((uint32_t)p_ch_cfg->multi_ch) + 1) * SSIF_I2S_LR_CH;
dkato 0:702bf7b2b7d8 481 }
dkato 0:702bf7b2b7d8 482
dkato 0:702bf7b2b7d8 483 dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
dkato 0:702bf7b2b7d8 484
dkato 0:702bf7b2b7d8 485 if (0u == dot_clk)
dkato 0:702bf7b2b7d8 486 {
dkato 0:702bf7b2b7d8 487 ret = EINVAL;
dkato 0:702bf7b2b7d8 488 }
dkato 0:702bf7b2b7d8 489 else
dkato 0:702bf7b2b7d8 490 {
dkato 0:702bf7b2b7d8 491 /* check if input audio clock can be divided by dotclock */
dkato 0:702bf7b2b7d8 492 result = input_clk % dot_clk;
dkato 0:702bf7b2b7d8 493
dkato 0:702bf7b2b7d8 494 if (0u != result)
dkato 0:702bf7b2b7d8 495 {
dkato 0:702bf7b2b7d8 496 /* cannot create dotclock from input audio clock */
dkato 0:702bf7b2b7d8 497 ret = EINVAL;
dkato 0:702bf7b2b7d8 498 }
dkato 0:702bf7b2b7d8 499 else
dkato 0:702bf7b2b7d8 500 {
dkato 0:702bf7b2b7d8 501 division = input_clk / dot_clk;
dkato 0:702bf7b2b7d8 502
dkato 0:702bf7b2b7d8 503 switch (division)
dkato 0:702bf7b2b7d8 504 {
dkato 0:702bf7b2b7d8 505 case SSIF_AUDIO_CLK_DIV_1:
dkato 0:702bf7b2b7d8 506 *p_clk_div = SSIF_CFG_CKDV_BITS_1;
dkato 0:702bf7b2b7d8 507 break;
dkato 0:702bf7b2b7d8 508 case SSIF_AUDIO_CLK_DIV_2:
dkato 0:702bf7b2b7d8 509 *p_clk_div = SSIF_CFG_CKDV_BITS_2;
dkato 0:702bf7b2b7d8 510 break;
dkato 0:702bf7b2b7d8 511 case SSIF_AUDIO_CLK_DIV_4:
dkato 0:702bf7b2b7d8 512 *p_clk_div = SSIF_CFG_CKDV_BITS_4;
dkato 0:702bf7b2b7d8 513 break;
dkato 0:702bf7b2b7d8 514 case SSIF_AUDIO_CLK_DIV_8:
dkato 0:702bf7b2b7d8 515 *p_clk_div = SSIF_CFG_CKDV_BITS_8;
dkato 0:702bf7b2b7d8 516 break;
dkato 0:702bf7b2b7d8 517 case SSIF_AUDIO_CLK_DIV_16:
dkato 0:702bf7b2b7d8 518 *p_clk_div = SSIF_CFG_CKDV_BITS_16;
dkato 0:702bf7b2b7d8 519 break;
dkato 0:702bf7b2b7d8 520 case SSIF_AUDIO_CLK_DIV_32:
dkato 0:702bf7b2b7d8 521 *p_clk_div = SSIF_CFG_CKDV_BITS_32;
dkato 0:702bf7b2b7d8 522 break;
dkato 0:702bf7b2b7d8 523 case SSIF_AUDIO_CLK_DIV_64:
dkato 0:702bf7b2b7d8 524 *p_clk_div = SSIF_CFG_CKDV_BITS_64;
dkato 0:702bf7b2b7d8 525 break;
dkato 0:702bf7b2b7d8 526 case SSIF_AUDIO_CLK_DIV_128:
dkato 0:702bf7b2b7d8 527 *p_clk_div = SSIF_CFG_CKDV_BITS_128;
dkato 0:702bf7b2b7d8 528 break;
dkato 0:702bf7b2b7d8 529 case SSIF_AUDIO_CLK_DIV_6:
dkato 0:702bf7b2b7d8 530 *p_clk_div = SSIF_CFG_CKDV_BITS_6;
dkato 0:702bf7b2b7d8 531 break;
dkato 0:702bf7b2b7d8 532 case SSIF_AUDIO_CLK_DIV_12:
dkato 0:702bf7b2b7d8 533 *p_clk_div = SSIF_CFG_CKDV_BITS_12;
dkato 0:702bf7b2b7d8 534 break;
dkato 0:702bf7b2b7d8 535 case SSIF_AUDIO_CLK_DIV_24:
dkato 0:702bf7b2b7d8 536 *p_clk_div = SSIF_CFG_CKDV_BITS_24;
dkato 0:702bf7b2b7d8 537 break;
dkato 0:702bf7b2b7d8 538 case SSIF_AUDIO_CLK_DIV_48:
dkato 0:702bf7b2b7d8 539 *p_clk_div = SSIF_CFG_CKDV_BITS_48;
dkato 0:702bf7b2b7d8 540 break;
dkato 0:702bf7b2b7d8 541 case SSIF_AUDIO_CLK_DIV_96:
dkato 0:702bf7b2b7d8 542 *p_clk_div = SSIF_CFG_CKDV_BITS_96;
dkato 0:702bf7b2b7d8 543 break;
dkato 0:702bf7b2b7d8 544 default:
dkato 0:702bf7b2b7d8 545 ret = EINVAL;
dkato 0:702bf7b2b7d8 546 break;
dkato 0:702bf7b2b7d8 547 }
dkato 0:702bf7b2b7d8 548 }
dkato 0:702bf7b2b7d8 549 }
dkato 0:702bf7b2b7d8 550 }
dkato 0:702bf7b2b7d8 551 }
dkato 0:702bf7b2b7d8 552
dkato 0:702bf7b2b7d8 553 return ret;
dkato 0:702bf7b2b7d8 554 }
dkato 0:702bf7b2b7d8 555