RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

Dependents:   GR-PEACH_Azure_Speech ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample ... more

Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Tue May 31 01:45:35 2016 +0000
Revision:
11:fb9eda52224e
Parent:
5:1390bfcb667c
"inline" of the ssif_init function is removed.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:702bf7b2b7d8 1 /*******************************************************************************
dkato 0:702bf7b2b7d8 2 * DISCLAIMER
dkato 0:702bf7b2b7d8 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:702bf7b2b7d8 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:702bf7b2b7d8 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:702bf7b2b7d8 6 * all applicable laws, including copyright laws.
dkato 0:702bf7b2b7d8 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:702bf7b2b7d8 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:702bf7b2b7d8 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:702bf7b2b7d8 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:702bf7b2b7d8 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:702bf7b2b7d8 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:702bf7b2b7d8 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:702bf7b2b7d8 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:702bf7b2b7d8 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:702bf7b2b7d8 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:702bf7b2b7d8 17 * and to discontinue the availability of this software. By using this software,
dkato 0:702bf7b2b7d8 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:702bf7b2b7d8 19 * following link:
dkato 0:702bf7b2b7d8 20 * http://www.renesas.com/disclaimer*
dkato 0:702bf7b2b7d8 21 * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
dkato 0:702bf7b2b7d8 22 *******************************************************************************/
dkato 0:702bf7b2b7d8 23
dkato 0:702bf7b2b7d8 24 /**************************************************************************//**
dkato 0:702bf7b2b7d8 25 * @file dma.h
dkato 5:1390bfcb667c 26 * $Rev: 1616 $
dkato 5:1390bfcb667c 27 * $Date:: 2015-04-21 19:00:08 +0900#$
dkato 0:702bf7b2b7d8 28 * @brief DMA Driver internal headers
dkato 0:702bf7b2b7d8 29 ******************************************************************************/
dkato 0:702bf7b2b7d8 30
dkato 0:702bf7b2b7d8 31 /*****************************************************************************
dkato 0:702bf7b2b7d8 32 * History : DD.MM.YYYY Version Description
dkato 0:702bf7b2b7d8 33 * : 15.01.2013 1.00 First Release
dkato 0:702bf7b2b7d8 34 ******************************************************************************/
dkato 0:702bf7b2b7d8 35
dkato 0:702bf7b2b7d8 36 #ifndef DMA_H
dkato 0:702bf7b2b7d8 37 #define DMA_H
dkato 0:702bf7b2b7d8 38
dkato 0:702bf7b2b7d8 39 /******************************************************************************
dkato 0:702bf7b2b7d8 40 Includes <System Includes>, "Project Includes"
dkato 0:702bf7b2b7d8 41 ******************************************************************************/
dkato 0:702bf7b2b7d8 42
dkato 0:702bf7b2b7d8 43 #include "dma_if.h"
dkato 0:702bf7b2b7d8 44 #include "Renesas_RZ_A1.h"
dkato 0:702bf7b2b7d8 45 #include "bsp_drv_cmn.h"
dkato 0:702bf7b2b7d8 46
dkato 0:702bf7b2b7d8 47 /******************************************************************************
dkato 0:702bf7b2b7d8 48 Macro definitions
dkato 0:702bf7b2b7d8 49 ******************************************************************************/
dkato 0:702bf7b2b7d8 50
dkato 0:702bf7b2b7d8 51 /* Number of channel configure table */
dkato 0:702bf7b2b7d8 52 #define DMA_CH_CONFIG_TABLE_NUM (95U)
dkato 0:702bf7b2b7d8 53
dkato 0:702bf7b2b7d8 54 /* Magic Number */
dkato 0:702bf7b2b7d8 55 #define SHIFT_DMARS_EVEN_CH (0U) /* Shift Value for DMARS Register access in Even ch */
dkato 0:702bf7b2b7d8 56 #define SHIFT_DMARS_ODD_CH (16U) /* Shift Value for DMARS Register access in Odd ch */
dkato 0:702bf7b2b7d8 57 #define MASK_DMARS_EVEN_CH (0xFFFF0000U) /* Mask value for DMARS Register in Even ch */
dkato 0:702bf7b2b7d8 58 #define MASK_DMARS_ODD_CH (0x0000FFFFU) /* Mask value for DMARS Register in Odd ch */
dkato 0:702bf7b2b7d8 59 #define HIGH_COMMON_REG_OFFSET (8) /* for Common Register Access in ch 0-8 */
dkato 0:702bf7b2b7d8 60 #define CHECK_ODD_EVEN_MASK (0x00000001U) /* for check value of odd or even */
dkato 0:702bf7b2b7d8 61 #define DMA_STOP_WAIT_MAX_CNT (10U) /* Loop count for DMA stop (usually, a count is set to 0 or 1) */
dkato 0:702bf7b2b7d8 62
dkato 0:702bf7b2b7d8 63 /* Register Set Value */
dkato 0:702bf7b2b7d8 64 /* Init Value */
dkato 0:702bf7b2b7d8 65 #define N0SA_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 66 #define N1SA_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 67 #define N0DA_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 68 #define N1DA_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 69 #define N0TB_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 70 #define N1TB_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 71 #define CHCTRL_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 72 #define CHCFG_INIT_VALUE (0x01000000U) /* interrupt disable */
dkato 0:702bf7b2b7d8 73 #define CHITVL_INIT_VALUE (0U) /* DMA interval = 0 */
dkato 0:702bf7b2b7d8 74 #define CHEXT_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 75 #define NXLA_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 76 #define DCTRL_INIT_VALUE (0x00000001U) /* interrupt output : pulse, round robin mode */
dkato 0:702bf7b2b7d8 77 #define DMARS_INIT_VALUE (0U) /* HW init value */
dkato 0:702bf7b2b7d8 78 /* Fixed Setting for CHCFG */
dkato 0:702bf7b2b7d8 79 #define CHCFG_FIXED_VALUE (0x00000020U) /* register mode, not buffer sweep, interrupt detect when high pulse */
dkato 0:702bf7b2b7d8 80
dkato 0:702bf7b2b7d8 81 /* Bit Value & Mask */
dkato 0:702bf7b2b7d8 82 /* CHSTAT */
dkato 0:702bf7b2b7d8 83 #define CHSTAT_MASK_SR (0x00000080U)
dkato 0:702bf7b2b7d8 84 #define CHSTAT_MASK_END (0x00000020U)
dkato 0:702bf7b2b7d8 85 #define CHSTAT_MASK_ER (0x00000010U)
dkato 0:702bf7b2b7d8 86 #define CHSTAT_MASK_TACT (0x00000004U)
dkato 0:702bf7b2b7d8 87 #define CHSTAT_MASK_EN (0x00000001U)
dkato 0:702bf7b2b7d8 88 /* CHCTRL */
dkato 0:702bf7b2b7d8 89 #define CHCTRL_SET_CLRTC (0x00000040U)
dkato 0:702bf7b2b7d8 90 #define CHCTRL_SET_CLREND (0x00000020U)
dkato 0:702bf7b2b7d8 91 #define CHCTRL_SET_SWRST (0x00000008U)
dkato 0:702bf7b2b7d8 92 #define CHCTRL_SET_CLREN (0x00000002U)
dkato 0:702bf7b2b7d8 93 #define CHCTRL_SET_SETEN (0x00000001U)
dkato 0:702bf7b2b7d8 94 /* CHCFG */
dkato 0:702bf7b2b7d8 95 #define CHCFG_SET_REN (0x40000000U)
dkato 0:702bf7b2b7d8 96 #define CHCFG_MASK_REN (0x40000000U)
dkato 0:702bf7b2b7d8 97 #define CHCFG_SET_RSW (0x20000000U)
dkato 0:702bf7b2b7d8 98 #define CHCFG_MASK_RSW (0x20000000U)
dkato 0:702bf7b2b7d8 99 #define CHCFG_SET_RSEL (0x10000000U)
dkato 0:702bf7b2b7d8 100 #define CHCFG_MASK_RSEL (0x10000000U)
dkato 0:702bf7b2b7d8 101 #define CHCFG_SET_DEM (0x01000000U)
dkato 0:702bf7b2b7d8 102 #define CHCFG_MASK_DEM (0x01000000U)
dkato 0:702bf7b2b7d8 103 #define CHCFG_MASK_DAD (0x00200000U)
dkato 0:702bf7b2b7d8 104 #define CHCFG_MASK_SAD (0x00100000U)
dkato 0:702bf7b2b7d8 105 #define CHCFG_MASK_DDS (0x000f0000U)
dkato 0:702bf7b2b7d8 106 #define CHCFG_MASK_SDS (0x0000f000U)
dkato 0:702bf7b2b7d8 107 #define CHCFG_SET_AM_LEVEL (0x00000100U)
dkato 0:702bf7b2b7d8 108 #define CHCFG_SET_AM_BUS_CYCLE (0x00000200U)
dkato 0:702bf7b2b7d8 109 #define CHCFG_MASK_AM (0x00000700U)
dkato 0:702bf7b2b7d8 110 #define CHCFG_SET_LVL_EDGE (0x00000000U)
dkato 0:702bf7b2b7d8 111 #define CHCFG_SET_LVL_LEVEL (0x00000040U)
dkato 0:702bf7b2b7d8 112 #define CHCFG_MASK_LVL (0x00000040U)
dkato 0:702bf7b2b7d8 113 #define CHCFG_SET_REQD_SRC (0x00000000U)
dkato 0:702bf7b2b7d8 114 #define CHCFG_SET_REQD_DST (0x00000008U)
dkato 0:702bf7b2b7d8 115 #define CHCFG_MASK_REQD (0x00000008U)
dkato 0:702bf7b2b7d8 116 #define CHCFG_SHIFT_DAD (21U)
dkato 0:702bf7b2b7d8 117 #define CHCFG_SHIFT_SAD (20U)
dkato 0:702bf7b2b7d8 118 #define CHCFG_SHIFT_DDS (16U)
dkato 0:702bf7b2b7d8 119 #define CHCFG_SHIFT_SDS (12U)
dkato 0:702bf7b2b7d8 120 /* CHEXT */
dkato 0:702bf7b2b7d8 121 #define CHEXT_SET_DCA_NORMAL (0x00003000U)
dkato 0:702bf7b2b7d8 122 #define CHEXT_SET_DCA_STRONG (0x00000000U)
dkato 0:702bf7b2b7d8 123 #define CHEXT_SET_DPR_NON_SECURE (0x00000200U)
dkato 0:702bf7b2b7d8 124 #define CHEXT_SET_SCA_NORMAL (0x00000030U)
dkato 0:702bf7b2b7d8 125 #define CHEXT_SET_SCA_STRONG (0x00000000U)
dkato 0:702bf7b2b7d8 126 #define CHEXT_SET_SPR_NON_SECURE (0x00000002U)
dkato 0:702bf7b2b7d8 127
dkato 0:702bf7b2b7d8 128
dkato 0:702bf7b2b7d8 129 /* REQD value in CHCFG is undecided on config table */
dkato 0:702bf7b2b7d8 130 /* used case of a resource is the same and two or more direction value exists. */
dkato 0:702bf7b2b7d8 131 #define CHCFG_REQD_UNDEFINED DMA_REQ_MAX
dkato 0:702bf7b2b7d8 132
dkato 0:702bf7b2b7d8 133 /* Address of area which is the target of setting change */
dkato 0:702bf7b2b7d8 134 #define DMA_EXTERNAL_BUS_START (0x00000000U)
dkato 0:702bf7b2b7d8 135 #define DMA_EXTERNAL_BUS_END (0x1FFFFFFFU)
dkato 0:702bf7b2b7d8 136 #define DMA_EXTERNAL_BUS_MIRROR_START (0x40000000U)
dkato 0:702bf7b2b7d8 137 #define DMA_EXTERNAL_BUS_MIRROR_END (0x5FFFFFFFU)
dkato 0:702bf7b2b7d8 138
dkato 0:702bf7b2b7d8 139 /*************************************************************************
dkato 0:702bf7b2b7d8 140 Enumerated Types
dkato 0:702bf7b2b7d8 141 *************************************************************************/
dkato 0:702bf7b2b7d8 142
dkato 0:702bf7b2b7d8 143 /* DRV Status */
dkato 0:702bf7b2b7d8 144 typedef enum
dkato 0:702bf7b2b7d8 145 {
dkato 0:702bf7b2b7d8 146 DMA_DRV_UNINIT = 0, /* Uninit */
dkato 0:702bf7b2b7d8 147 DMA_DRV_INIT = 1 /* Init */
dkato 0:702bf7b2b7d8 148 } dma_stat_drv_t;
dkato 0:702bf7b2b7d8 149
dkato 0:702bf7b2b7d8 150 /* Channel Status */
dkato 0:702bf7b2b7d8 151 typedef enum
dkato 0:702bf7b2b7d8 152 {
dkato 0:702bf7b2b7d8 153 DMA_CH_UNINIT = 0, /* Uninit */
dkato 0:702bf7b2b7d8 154 DMA_CH_INIT = 1, /* Init */
dkato 0:702bf7b2b7d8 155 DMA_CH_OPEN = 2, /* Open */
dkato 0:702bf7b2b7d8 156 DMA_CH_TRANSFER = 4 /* Transfer */
dkato 0:702bf7b2b7d8 157 } dma_stat_ch_t;
dkato 0:702bf7b2b7d8 158
dkato 0:702bf7b2b7d8 159 /*************************************************************************
dkato 0:702bf7b2b7d8 160 Structures
dkato 0:702bf7b2b7d8 161 *************************************************************************/
dkato 0:702bf7b2b7d8 162
dkato 0:702bf7b2b7d8 163 /* DMA Register (Common) */
dkato 0:702bf7b2b7d8 164 typedef struct
dkato 0:702bf7b2b7d8 165 {
dkato 0:702bf7b2b7d8 166 volatile uint32_t dctrl;
dkato 0:702bf7b2b7d8 167 volatile uint32_t dstat_en;
dkato 0:702bf7b2b7d8 168 volatile uint32_t dstat_er;
dkato 0:702bf7b2b7d8 169 volatile uint32_t dstat_end;
dkato 0:702bf7b2b7d8 170 volatile uint32_t dstat_tc;
dkato 0:702bf7b2b7d8 171 volatile uint32_t dstat_sus;
dkato 0:702bf7b2b7d8 172 } dma_reg_common_t;
dkato 0:702bf7b2b7d8 173
dkato 0:702bf7b2b7d8 174 /* DMA Register (every Channel) */
dkato 0:702bf7b2b7d8 175 typedef struct
dkato 0:702bf7b2b7d8 176 {
dkato 0:702bf7b2b7d8 177 volatile uint32_t n0sa;
dkato 0:702bf7b2b7d8 178 volatile uint32_t n0da;
dkato 0:702bf7b2b7d8 179 volatile uint32_t n0tb;
dkato 0:702bf7b2b7d8 180 volatile uint32_t n1sa;
dkato 0:702bf7b2b7d8 181 volatile uint32_t n1da;
dkato 0:702bf7b2b7d8 182 volatile uint32_t n1tb;
dkato 0:702bf7b2b7d8 183 volatile uint32_t crsa;
dkato 0:702bf7b2b7d8 184 volatile uint32_t crda;
dkato 0:702bf7b2b7d8 185 volatile uint32_t crtb;
dkato 0:702bf7b2b7d8 186 volatile uint32_t chstat;
dkato 0:702bf7b2b7d8 187 volatile uint32_t chctrl;
dkato 0:702bf7b2b7d8 188 volatile uint32_t chcfg;
dkato 0:702bf7b2b7d8 189 volatile uint32_t chitvl;
dkato 0:702bf7b2b7d8 190 volatile uint32_t chext;
dkato 0:702bf7b2b7d8 191 volatile uint32_t nxla;
dkato 0:702bf7b2b7d8 192 volatile uint32_t crla;
dkato 0:702bf7b2b7d8 193 } dma_reg_ch_t;
dkato 0:702bf7b2b7d8 194
dkato 0:702bf7b2b7d8 195 /* Information of Channel */
dkato 0:702bf7b2b7d8 196 typedef struct
dkato 0:702bf7b2b7d8 197 {
dkato 0:702bf7b2b7d8 198 int_t ch; /* Channel Number */
dkato 0:702bf7b2b7d8 199 dma_stat_ch_t ch_stat; /* Channel Status */
dkato 0:702bf7b2b7d8 200 dma_res_select_t resource; /* DMA Transfer Resource */
dkato 0:702bf7b2b7d8 201 dma_req_dir_t direction; /* DMA Transfer Direction */
dkato 0:702bf7b2b7d8 202 dma_unit_size_t src_width; /* DMA Transfer Unit Size (Source) */
dkato 0:702bf7b2b7d8 203 dma_addr_cnt_t src_cnt; /* DMA Address Count (Source) */
dkato 0:702bf7b2b7d8 204 dma_unit_size_t dst_width; /* DMA Transfer Unit Size (Destination) */
dkato 0:702bf7b2b7d8 205 dma_addr_cnt_t dst_cnt; /* DMA Address Count (Destination) */
dkato 0:702bf7b2b7d8 206 void *src_addr0; /* Sorce Address (Next Register Set 0)*/
dkato 0:702bf7b2b7d8 207 void *dst_addr0; /* Destination Address (Next Register Set 0)*/
dkato 0:702bf7b2b7d8 208 uint32_t count0; /* DMA Transfer Size (Next Register Set 0)*/
dkato 0:702bf7b2b7d8 209 void *src_addr1; /* Sorce Address (Next Register Set 1)*/
dkato 0:702bf7b2b7d8 210 void *dst_addr1; /* Destination Address (Next Register Set 1)*/
dkato 0:702bf7b2b7d8 211 uint32_t count1; /* DMA Transfer Size (Next Register Set 1)*/
dkato 0:702bf7b2b7d8 212 IRQn_Type end_irq_num; /* DMA end interrupt number */
dkato 0:702bf7b2b7d8 213 AIOCB *p_end_aio; /* set callback function (DMA end interrupt) */
dkato 0:702bf7b2b7d8 214 bool_t next_dma_flag; /* Setting Flag of Continous DMA */
dkato 0:702bf7b2b7d8 215 uint32_t shift_dmars; /* set SHIFT_DMARS_ODD_CH or SHIFT_DMARS_EVEN_CH */
dkato 0:702bf7b2b7d8 216 uint32_t mask_dmars; /* set MASK_DMA_ODD_CH or MASK_DMARS_EVEN_CH */
dkato 0:702bf7b2b7d8 217 bool_t setup_flag; /* incdicate called DMA_Setup() flag */
dkato 0:702bf7b2b7d8 218 volatile struct st_dmac_n *p_dma_ch_reg; /* DMA Register for every channel */
dkato 0:702bf7b2b7d8 219 volatile struct st_dmaccommon_n *p_dma_common_reg; /* DMA Register for common */
dkato 0:702bf7b2b7d8 220 volatile uint32_t *p_dma_dmars_reg; /* DMARS Regsiter */
dkato 0:702bf7b2b7d8 221 } dma_info_ch_t;
dkato 0:702bf7b2b7d8 222
dkato 0:702bf7b2b7d8 223 /* Information of Driver */
dkato 0:702bf7b2b7d8 224 typedef struct
dkato 0:702bf7b2b7d8 225 {
dkato 0:702bf7b2b7d8 226 dma_stat_drv_t drv_stat; /* DRV Status */
dkato 0:702bf7b2b7d8 227 AIOCB *p_err_aio; /* set callback function (DMA error interrupt) */
dkato 0:702bf7b2b7d8 228 IRQn_Type err_irq_num; /* DMA error interrupt number */
dkato 0:702bf7b2b7d8 229 dma_info_ch_t info_ch[DMA_CH_NUM]; /* Enable Channel */
dkato 0:702bf7b2b7d8 230 } dma_info_drv_t;
dkato 0:702bf7b2b7d8 231
dkato 0:702bf7b2b7d8 232 /* DMA Channel Configure Table */
dkato 0:702bf7b2b7d8 233 typedef struct
dkato 0:702bf7b2b7d8 234 {
dkato 0:702bf7b2b7d8 235 dma_res_select_t dmars; /* Set Value for DMARS Register */
dkato 0:702bf7b2b7d8 236 uint32_t tm; /* Set Value for TM Bit (CHCFG Register) */
dkato 0:702bf7b2b7d8 237 uint32_t lvl; /* Set Value for LVL Bit (CHCFG Register) */
dkato 0:702bf7b2b7d8 238 uint32_t reqd; /* Set Value for REQD (CHCFG Register) */
dkato 0:702bf7b2b7d8 239 } dma_ch_cfg_t;
dkato 0:702bf7b2b7d8 240
dkato 0:702bf7b2b7d8 241 /***********************************************************************************
dkato 0:702bf7b2b7d8 242 Function Prototypes
dkato 0:702bf7b2b7d8 243 ***********************************************************************************/
dkato 0:702bf7b2b7d8 244
dkato 0:702bf7b2b7d8 245 dma_info_drv_t *DMA_GetDrvInstance(void);
dkato 0:702bf7b2b7d8 246 dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel);
dkato 5:1390bfcb667c 247 int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param);
dkato 0:702bf7b2b7d8 248 int_t DMA_UnInitialize(void);
dkato 0:702bf7b2b7d8 249 int_t DMA_GetFreeChannel(void);
dkato 0:702bf7b2b7d8 250 int_t DMA_GetFixedChannel(const int_t channel);
dkato 0:702bf7b2b7d8 251 void DMA_CloseChannel(const int_t channel);
dkato 0:702bf7b2b7d8 252 void DMA_SetParam(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
dkato 0:702bf7b2b7d8 253 const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd);
dkato 0:702bf7b2b7d8 254 void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data);
dkato 0:702bf7b2b7d8 255 void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
dkato 0:702bf7b2b7d8 256 const uint32_t next_register_set);
dkato 0:702bf7b2b7d8 257 void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data);
dkato 0:702bf7b2b7d8 258 void DMA_Start(const int_t channel, const bool_t restart_flag);
dkato 0:702bf7b2b7d8 259 void DMA_Stop(const int_t channel, uint32_t * const p_remain);
dkato 0:702bf7b2b7d8 260 void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno);
dkato 0:702bf7b2b7d8 261
dkato 0:702bf7b2b7d8 262 #endif /* DMA_H */