RZ/A1H CMSIS-RTOS RTX BSP for GR-PEACH.

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Fork of R_BSP by Daiki Kato

SSIF

The SSIF driver implements transmission and reception functionality which uses the SSIF in the RZ/A Series.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Ssif.h"
00003 #include "sine_data_tbl.h"
00004 
00005 //I2S send only, The upper limit of write buffer is 8.
00006 R_BSP_Ssif ssif(P4_4, P4_5, P4_7, P4_6, 0x80, 8, 0);
00007 
00008 static void callback_ssif_write_end(void * p_data, int32_t result, void * p_app_data) {
00009     if (result < 0) {
00010         printf("ssif write callback error %d\n", result);
00011     }
00012 }
00013 
00014 int main() {
00015     rbsp_data_conf_t   ssif_write_end_conf = {&callback_ssif_write_end, NULL};
00016     ssif_channel_cfg_t ssif_cfg;
00017     int32_t            result;
00018 
00019     //I2S Master, 44.1kHz, 16bit, 2ch
00020     ssif_cfg.enabled                = true;
00021     ssif_cfg.int_level              = 0x78;
00022     ssif_cfg.slave_mode             = false;
00023     ssif_cfg.sample_freq            = 44100u;
00024     ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
00025     ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
00026     ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
00027     ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
00028     ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
00029     ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
00030     ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
00031     ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
00032     ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
00033     ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
00034     ssif_cfg.noise_cancel           = SSIF_CFG_DISABLE_NOISE_CANCEL;
00035     ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
00036     ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
00037     ssif_cfg.romdec_direct.p_cbfunc = NULL;
00038     result = ssif.ConfigChannel(&ssif_cfg);
00039     if (result < 0) {
00040         printf("ssif config error %d\n", result);
00041     }
00042 
00043     while (1) {
00044         //The upper limit of write buffer is 8.
00045         result = ssif.write((void *)sin_data_44100Hz_16bit_2ch, 
00046                             sizeof(sin_data_44100Hz_16bit_2ch), &ssif_write_end_conf);
00047         if (result < 0) {
00048             printf("ssif write api error %d\n", result);
00049         }
00050     }
00051 }

API

Import library

Public Member Functions

R_BSP_Ssif (PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor.
virtual ~R_BSP_Ssif ()
Destructor.
int32_t GetSsifChNo (void)
Get a value of SSIF channel number.
bool ConfigChannel (const ssif_channel_cfg_t *const p_ch_cfg)
Save configuration to the SSIF driver.
bool GetStatus (uint32_t *const p_status)
Get a value of SSISR register.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Interface

See the Pinout page for more details


SCUX

The SCUX module consists of a sampling rate converter, a digital volume unit, and a mixer.
The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate converter. The SCUX driver uses the DMA transfer mode to input and output audio data.

Hello World!

Import program

00001 #include "mbed.h"
00002 #include "R_BSP_Scux.h"
00003 #include "USBHostMSD.h"
00004 
00005 R_BSP_Scux scux(SCUX_CH_0);
00006 
00007 #define WRITE_SAMPLE_NUM (128)
00008 #define READ_SAMPLE_NUM  (2048)
00009 
00010 const short sin_data[WRITE_SAMPLE_NUM] = {
00011  0x0000,0x0000,0x0C8C,0x0C8C,0x18F9,0x18F9,0x2528,0x2528
00012 ,0x30FB,0x30FB,0x3C56,0x3C56,0x471C,0x471C,0x5133,0x5133
00013 ,0x5A82,0x5A82,0x62F1,0x62F1,0x6A6D,0x6A6D,0x70E2,0x70E2
00014 ,0x7641,0x7641,0x7A7C,0x7A7C,0x7D89,0x7D89,0x7F61,0x7F61
00015 ,0x7FFF,0x7FFF,0x7F61,0x7F61,0x7D89,0x7D89,0x7A7C,0x7A7C
00016 ,0x7641,0x7641,0x70E2,0x70E2,0x6A6D,0x6A6D,0x62F1,0x62F1
00017 ,0x5A82,0x5A82,0x5133,0x5133,0x471C,0x471C,0x3C56,0x3C56
00018 ,0x30FB,0x30FB,0x2528,0x2528,0x18F9,0x18F9,0x0C8C,0x0C8C
00019 ,0x0000,0x0000,0xF374,0xF374,0xE707,0xE707,0xDAD8,0xDAD8
00020 ,0xCF05,0xCF05,0xC3AA,0xC3AA,0xB8E4,0xB8E4,0xAECD,0xAECD
00021 ,0xA57E,0xA57E,0x9D0F,0x9D0F,0x9593,0x9593,0x8F1E,0x8F1E
00022 ,0x89BF,0x89BF,0x8584,0x8584,0x8277,0x8277,0x809F,0x809F
00023 ,0x8001,0x8001,0x809F,0x809F,0x8277,0x8277,0x8584,0x8584
00024 ,0x89BF,0x89BF,0x8F1E,0x8F1E,0x9593,0x9593,0x9D0F,0x9D0F
00025 ,0xA57E,0xA57E,0xAECD,0xAECD,0xB8E4,0xB8E4,0xC3AA,0xC3AA
00026 ,0xCF05,0xCF05,0xDAD8,0xDAD8,0xE707,0xE707,0xF374,0xF374
00027 };
00028 
00029 #if defined(__ICCARM__)
00030 #pragma data_alignment=4
00031 short write_buff[WRITE_SAMPLE_NUM]@ ".mirrorram";
00032 #pragma data_alignment=4
00033 short read_buff[READ_SAMPLE_NUM]@ ".mirrorram";
00034 #else
00035 short write_buff[WRITE_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00036 short read_buff[READ_SAMPLE_NUM] __attribute((section("NC_BSS"),aligned(4)));
00037 #endif
00038 
00039 void scux_setup(void);
00040 void write_task(void const*);
00041 void file_output_to_usb(void);
00042 
00043 int main(void) {
00044     // set up SRC parameters.
00045     scux_setup();
00046 
00047     printf("Sampling rate conversion Start.\n");
00048     // start accepting transmit/receive requests.
00049     scux.TransStart();
00050 
00051     // create a new thread to write to SCUX.
00052     Thread writeTask(write_task, NULL, osPriorityNormal, 1024 * 4);
00053 
00054     // receive request to the SCUX driver.
00055     scux.read(read_buff, sizeof(read_buff));
00056     printf("Sampling rate conversion End.\n");
00057 
00058     // output binary file to USB port 0.
00059     file_output_to_usb();
00060 }
00061 
00062 void scux_setup(void) {
00063     scux_src_usr_cfg_t src_cfg;
00064 
00065     src_cfg.src_enable           = true;
00066     src_cfg.word_len             = SCUX_DATA_LEN_16;
00067     src_cfg.mode_sync            = true;
00068     src_cfg.input_rate           = SAMPLING_RATE_48000HZ;
00069     src_cfg.output_rate          = SAMPLING_RATE_96000HZ;
00070     src_cfg.select_in_data_ch[0] = SELECT_IN_DATA_CH_0;
00071     src_cfg.select_in_data_ch[1] = SELECT_IN_DATA_CH_1;
00072 
00073     scux.SetSrcCfg(&src_cfg);
00074 }
00075 
00076 void scux_flush_callback(int scux_ch) {
00077     // do nothing
00078 }
00079 
00080 void write_task(void const*) {
00081     memcpy(write_buff, sin_data, sizeof(write_buff));
00082     // send request to the SCUX driver.
00083     scux.write(write_buff, sizeof(write_buff));
00084 
00085     // stop the acceptance of transmit/receive requests.
00086     scux.FlushStop(&scux_flush_callback);
00087 }
00088 
00089 void file_output_to_usb(void) {
00090     FILE * fp = NULL;
00091     int i;
00092 
00093     USBHostMSD msd("usb");
00094 
00095     // try to connect a MSD device
00096     for(i = 0; i < 10; i++) {
00097         if (msd.connect()) {
00098             break;
00099         }
00100         wait(0.5);
00101     }
00102 
00103     if (msd.connected()) {
00104         fp = fopen("/usb/scux_input.dat", "rb");
00105         if (fp == NULL) {
00106             fp = fopen("/usb/scux_input.dat", "wb");
00107             if (fp != NULL) {
00108                 fwrite(write_buff, sizeof(short), WRITE_SAMPLE_NUM, fp);
00109                 fclose(fp);
00110                 printf("Output binary file(Input data) to USB.\n");
00111             } else {
00112                 printf("Failed to output binary file(Input data).\n");
00113             }
00114         } else {
00115             printf("Binary file(Input data) exists.\n");
00116             fclose(fp);
00117         }
00118 
00119         fp = fopen("/usb/scux_output.dat", "rb");
00120         if (fp == NULL) {
00121             fp = fopen("/usb/scux_output.dat", "wb");
00122             if (fp != NULL) {
00123                 fwrite(read_buff, sizeof(short), READ_SAMPLE_NUM, fp);
00124                 fclose(fp);
00125                 printf("Output binary file(Output data) to USB.\n");
00126             } else {
00127                 printf("Failed to output binary file(Output data).\n");
00128             }
00129         } else {
00130             printf("Binary file(Output data) exists.\n");
00131             fclose(fp);
00132         }
00133     } else {
00134         printf("Failed to connect to the USB device.\n");
00135     }
00136 } 

API

Import library

Public Member Functions

R_BSP_Scux ( scux_ch_num_t channel, uint8_t int_level=0x80, int32_t max_write_num=16, int32_t max_read_num=16)
Constructor: Initializes and opens the channel designated by the SCUX driver.
virtual ~R_BSP_Scux (void)
Destructor: Closes the channel designated by the SCUX driver and exits.
bool TransStart (void)
Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
bool FlushStop (void(*const callback)(int32_t))
Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer, then stops the HW operation.
bool ClearStop (void)
Discards all data in the SCUX that is requested for transfer before stopping the hardware operation and stops accepting write/read requests.
bool SetSrcCfg (const scux_src_usr_cfg_t *const p_src_param)
Sets up SRC parameters.
bool GetWriteStat (uint32_t *const p_write_stat)
Obtains the state information of the write request.
bool GetReadStat (uint32_t *const p_read_stat)
Obtains the state information of the read request.
int32_t write (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Write count bytes to the file associated.
int32_t read (void *const p_data, uint32_t data_size, const rbsp_data_conf_t *const p_data_conf=NULL)
Read count bytes to the file associated.

Protected Member Functions

void write_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Write init.
void read_init (void *handle, void *p_func_a, int32_t max_buff_num=16)
Read init.

Write request state transition diagram

/media/uploads/dkato/scux_write_state_transition.png

Read request state transition diagram

/media/uploads/dkato/scux_read_state_transition.png

Committer:
dkato
Date:
Tue May 31 01:45:35 2016 +0000
Revision:
11:fb9eda52224e
Parent:
7:30ebba78fff0
"inline" of the ssif_init function is removed.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 6:aa1fc6a5cc2a 1 /*******************************************************************************
dkato 6:aa1fc6a5cc2a 2 * DISCLAIMER
dkato 6:aa1fc6a5cc2a 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 6:aa1fc6a5cc2a 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 6:aa1fc6a5cc2a 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 6:aa1fc6a5cc2a 6 * all applicable laws, including copyright laws.
dkato 6:aa1fc6a5cc2a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 6:aa1fc6a5cc2a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 6:aa1fc6a5cc2a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 6:aa1fc6a5cc2a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 6:aa1fc6a5cc2a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 6:aa1fc6a5cc2a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 6:aa1fc6a5cc2a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 6:aa1fc6a5cc2a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 6:aa1fc6a5cc2a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 6:aa1fc6a5cc2a 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 6:aa1fc6a5cc2a 17 * and to discontinue the availability of this software. By using this software,
dkato 6:aa1fc6a5cc2a 18 * you agree to the additional terms and conditions found by accessing the
dkato 6:aa1fc6a5cc2a 19 * following link:
dkato 6:aa1fc6a5cc2a 20 * http://www.renesas.com/disclaimer
dkato 6:aa1fc6a5cc2a 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
dkato 6:aa1fc6a5cc2a 22 *******************************************************************************/
dkato 6:aa1fc6a5cc2a 23 /**************************************************************************//**
dkato 6:aa1fc6a5cc2a 24 * @file scux_if.h
dkato 6:aa1fc6a5cc2a 25 * $Rev: 1032 $
dkato 6:aa1fc6a5cc2a 26 * $Date:: 2014-08-06 09:04:50 +0900#$
dkato 6:aa1fc6a5cc2a 27 * @brief SCUX Driver IOIF API header
dkato 6:aa1fc6a5cc2a 28 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 29
dkato 6:aa1fc6a5cc2a 30 #ifndef SCUX_IF_H
dkato 6:aa1fc6a5cc2a 31 #define SCUX_IF_H
dkato 6:aa1fc6a5cc2a 32
dkato 6:aa1fc6a5cc2a 33 /******************************************************************************
dkato 6:aa1fc6a5cc2a 34 Includes <System Includes> , "Project Includes"
dkato 6:aa1fc6a5cc2a 35 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 36
dkato 6:aa1fc6a5cc2a 37 #include "cmsis_os.h"
dkato 6:aa1fc6a5cc2a 38 #include "r_errno.h"
dkato 6:aa1fc6a5cc2a 39 #include "r_typedefs.h"
dkato 6:aa1fc6a5cc2a 40 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 41 #include "ioif_aio.h"
dkato 6:aa1fc6a5cc2a 42 #include "misratypes.h"
dkato 7:30ebba78fff0 43 #include "R_BSP_mbed_fns.h"
dkato 6:aa1fc6a5cc2a 44 #include "R_BSP_ScuxDef.h"
dkato 6:aa1fc6a5cc2a 45 #else /* not mbed */
dkato 6:aa1fc6a5cc2a 46 #include "ioif_public.h"
dkato 6:aa1fc6a5cc2a 47 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 48
dkato 6:aa1fc6a5cc2a 49 #ifdef __cplusplus
dkato 6:aa1fc6a5cc2a 50 extern "C"
dkato 6:aa1fc6a5cc2a 51 {
dkato 6:aa1fc6a5cc2a 52 #endif /* __cplusplus */
dkato 6:aa1fc6a5cc2a 53
dkato 6:aa1fc6a5cc2a 54 /*************************************************************************
dkato 6:aa1fc6a5cc2a 55 Enumerated Types
dkato 6:aa1fc6a5cc2a 56 *************************************************************************/
dkato 6:aa1fc6a5cc2a 57
dkato 6:aa1fc6a5cc2a 58 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 59 #else /* not mbed */
dkato 6:aa1fc6a5cc2a 60 /* Number of SCUX channel */
dkato 6:aa1fc6a5cc2a 61 typedef enum
dkato 6:aa1fc6a5cc2a 62 {
dkato 6:aa1fc6a5cc2a 63 SCUX_CH_0 = 0,
dkato 6:aa1fc6a5cc2a 64 SCUX_CH_1 = 1,
dkato 6:aa1fc6a5cc2a 65 SCUX_CH_2 = 2,
dkato 6:aa1fc6a5cc2a 66 SCUX_CH_3 = 3,
dkato 6:aa1fc6a5cc2a 67 SCUX_CH_NUM = 4 /* Number of SCUX channel */
dkato 6:aa1fc6a5cc2a 68 } scux_ch_num_t;
dkato 6:aa1fc6a5cc2a 69 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 70
dkato 6:aa1fc6a5cc2a 71 /* SCUX route setting */
dkato 6:aa1fc6a5cc2a 72 typedef enum
dkato 6:aa1fc6a5cc2a 73 {
dkato 6:aa1fc6a5cc2a 74 /* mem to mem */
dkato 6:aa1fc6a5cc2a 75 SCUX_ROUTE_SRC_MEM_MIN = 0x1000,
dkato 6:aa1fc6a5cc2a 76 SCUX_ROUTE_SRC0_MEM = 0x1001,
dkato 6:aa1fc6a5cc2a 77 SCUX_ROUTE_SRC1_MEM = 0x1002,
dkato 6:aa1fc6a5cc2a 78 SCUX_ROUTE_SRC2_MEM = 0x1003,
dkato 6:aa1fc6a5cc2a 79 SCUX_ROUTE_SRC3_MEM = 0x1004,
dkato 6:aa1fc6a5cc2a 80 SCUX_ROUTE_SRC_MEM_MAX = 0x1005,
dkato 6:aa1fc6a5cc2a 81 /* mem to SSIF */
dkato 6:aa1fc6a5cc2a 82 SCUX_ROUTE_SRC_SSIF_MIN = 0x2000,
dkato 6:aa1fc6a5cc2a 83 SCUX_ROUTE_SRC0_SSIF0 = 0x2001,
dkato 6:aa1fc6a5cc2a 84 SCUX_ROUTE_SRC0_SSIF012 = 0x2002,
dkato 6:aa1fc6a5cc2a 85 SCUX_ROUTE_SRC0_SSIF3 = 0x2003,
dkato 6:aa1fc6a5cc2a 86 SCUX_ROUTE_SRC0_SSIF345 = 0x2004,
dkato 6:aa1fc6a5cc2a 87 SCUX_ROUTE_SRC1_SSIF0 = 0x2005,
dkato 6:aa1fc6a5cc2a 88 SCUX_ROUTE_SRC1_SSIF012 = 0x2006,
dkato 6:aa1fc6a5cc2a 89 SCUX_ROUTE_SRC1_SSIF3 = 0x2007,
dkato 6:aa1fc6a5cc2a 90 SCUX_ROUTE_SRC1_SSIF345 = 0x2008,
dkato 6:aa1fc6a5cc2a 91 SCUX_ROUTE_SRC2_SSIF1 = 0x2009,
dkato 6:aa1fc6a5cc2a 92 SCUX_ROUTE_SRC2_SSIF4 = 0x200A,
dkato 6:aa1fc6a5cc2a 93 SCUX_ROUTE_SRC3_SSIF2 = 0x200B,
dkato 6:aa1fc6a5cc2a 94 SCUX_ROUTE_SRC3_SSIF5 = 0x200C,
dkato 6:aa1fc6a5cc2a 95 SCUX_ROUTE_SRC_SSIF_MAX = 0x200D,
dkato 6:aa1fc6a5cc2a 96 /* mem to NIX to SSIF */
dkato 6:aa1fc6a5cc2a 97 SCUX_ROUTE_SRC_MIX_SSIF_MIN = 0x3000,
dkato 6:aa1fc6a5cc2a 98 SCUX_ROUTE_SRC0_MIX_SSIF0 = 0x3001,
dkato 6:aa1fc6a5cc2a 99 SCUX_ROUTE_SRC0_MIX_SSIF012 = 0x3002,
dkato 6:aa1fc6a5cc2a 100 SCUX_ROUTE_SRC0_MIX_SSIF3 = 0x3003,
dkato 6:aa1fc6a5cc2a 101 SCUX_ROUTE_SRC0_MIX_SSIF345 = 0x3004,
dkato 6:aa1fc6a5cc2a 102 SCUX_ROUTE_SRC1_MIX_SSIF0 = 0x3005,
dkato 6:aa1fc6a5cc2a 103 SCUX_ROUTE_SRC1_MIX_SSIF012 = 0x3006,
dkato 6:aa1fc6a5cc2a 104 SCUX_ROUTE_SRC1_MIX_SSIF3 = 0x3007,
dkato 6:aa1fc6a5cc2a 105 SCUX_ROUTE_SRC1_MIX_SSIF345 = 0x3008,
dkato 6:aa1fc6a5cc2a 106 SCUX_ROUTE_SRC2_MIX_SSIF0 = 0x3009,
dkato 6:aa1fc6a5cc2a 107 SCUX_ROUTE_SRC2_MIX_SSIF012 = 0x300A,
dkato 6:aa1fc6a5cc2a 108 SCUX_ROUTE_SRC2_MIX_SSIF3 = 0x300B,
dkato 6:aa1fc6a5cc2a 109 SCUX_ROUTE_SRC2_MIX_SSIF345 = 0x300C,
dkato 6:aa1fc6a5cc2a 110 SCUX_ROUTE_SRC3_MIX_SSIF0 = 0x300D,
dkato 6:aa1fc6a5cc2a 111 SCUX_ROUTE_SRC3_MIX_SSIF012 = 0x300E,
dkato 6:aa1fc6a5cc2a 112 SCUX_ROUTE_SRC3_MIX_SSIF3 = 0x300F,
dkato 6:aa1fc6a5cc2a 113 SCUX_ROUTE_SRC3_MIX_SSIF345 = 0x3010,
dkato 6:aa1fc6a5cc2a 114 SCUX_ROUTE_SRC_MIX_SSIF_MAX = 0x3011
dkato 6:aa1fc6a5cc2a 115 } scux_route_t;
dkato 6:aa1fc6a5cc2a 116
dkato 6:aa1fc6a5cc2a 117 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 118 #else /* not mbed */
dkato 6:aa1fc6a5cc2a 119 /* used audio channel number setting */
dkato 6:aa1fc6a5cc2a 120 typedef enum
dkato 6:aa1fc6a5cc2a 121 {
dkato 6:aa1fc6a5cc2a 122 SCUX_USE_CH_1 = 1, /* used audio channel number is 1 */
dkato 6:aa1fc6a5cc2a 123 SCUX_USE_CH_2 = 2, /* used audio channel number is 2 */
dkato 6:aa1fc6a5cc2a 124 SCUX_USE_CH_4 = 4, /* used audio channel number is 4 */
dkato 6:aa1fc6a5cc2a 125 SCUX_USE_CH_6 = 6, /* used audio channel number is 6 */
dkato 6:aa1fc6a5cc2a 126 SCUX_USE_CH_8 = 8 /* used audio channel number is 8 */
dkato 6:aa1fc6a5cc2a 127 } scux_use_channel_t;
dkato 6:aa1fc6a5cc2a 128 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 129
dkato 6:aa1fc6a5cc2a 130 /* select audio channel number setting */
dkato 6:aa1fc6a5cc2a 131 typedef enum
dkato 6:aa1fc6a5cc2a 132 {
dkato 6:aa1fc6a5cc2a 133 SCUX_AUDIO_CH_MIN = -1,
dkato 6:aa1fc6a5cc2a 134 SCUX_AUDIO_CH_0 = 0, /* select audio channel number is 0 */
dkato 6:aa1fc6a5cc2a 135 SCUX_AUDIO_CH_1 = 1, /* select audio channel number is 1 */
dkato 6:aa1fc6a5cc2a 136 SCUX_AUDIO_CH_2 = 2, /* select audio channel number is 2 */
dkato 6:aa1fc6a5cc2a 137 SCUX_AUDIO_CH_3 = 3, /* select audio channel number is 3 */
dkato 6:aa1fc6a5cc2a 138 SCUX_AUDIO_CH_4 = 4, /* select audio channel number is 4 */
dkato 6:aa1fc6a5cc2a 139 SCUX_AUDIO_CH_5 = 5, /* select audio channel number is 5 */
dkato 6:aa1fc6a5cc2a 140 SCUX_AUDIO_CH_6 = 6, /* select audio channel number is 6 */
dkato 6:aa1fc6a5cc2a 141 SCUX_AUDIO_CH_7 = 7, /* select audio channel number is 7 */
dkato 6:aa1fc6a5cc2a 142 SCUX_AUDIO_CH_MAX = 8
dkato 6:aa1fc6a5cc2a 143 } scux_audio_channel_t;
dkato 6:aa1fc6a5cc2a 144
dkato 6:aa1fc6a5cc2a 145 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 146 #else /* not mbed */
dkato 6:aa1fc6a5cc2a 147 /* SCUX data word length */
dkato 6:aa1fc6a5cc2a 148 typedef enum
dkato 6:aa1fc6a5cc2a 149 {
dkato 6:aa1fc6a5cc2a 150 SCUX_DATA_LEN_MIN =(-1),
dkato 6:aa1fc6a5cc2a 151 SCUX_DATA_LEN_24 = 0, /* data word length is 24bit */
dkato 6:aa1fc6a5cc2a 152 SCUX_DATA_LEN_16 = 1, /* data word length is 16bit */
dkato 6:aa1fc6a5cc2a 153 SCUX_DATA_LEN_16_TO_24 = 2, /* data word length is 24bit */
dkato 6:aa1fc6a5cc2a 154 SCUX_DATA_LEN_MAX = 3
dkato 6:aa1fc6a5cc2a 155 } scux_data_word_len_t;
dkato 6:aa1fc6a5cc2a 156 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 157
dkato 6:aa1fc6a5cc2a 158 /* SSIF PIN mode setting */
dkato 6:aa1fc6a5cc2a 159 typedef enum
dkato 6:aa1fc6a5cc2a 160 {
dkato 6:aa1fc6a5cc2a 161 SCUX_PIN_MODE_MIN =(-1),
dkato 6:aa1fc6a5cc2a 162 SCUX_PIN_MODE_INDEPEND = 0, /* PIN mode is independent */
dkato 6:aa1fc6a5cc2a 163 SCUX_PIN_MODE_SLAVE_SLAVE = 1, /* PIN mode is slave-slave */
dkato 6:aa1fc6a5cc2a 164 SCUX_PIN_MODE_MASTER_SLAVE = 2, /* PIN mode is master-slave */
dkato 6:aa1fc6a5cc2a 165 SCUX_PIN_MODE_MAX = 3
dkato 6:aa1fc6a5cc2a 166 } scux_pin_mode_t;
dkato 6:aa1fc6a5cc2a 167
dkato 6:aa1fc6a5cc2a 168 /* SCUX sampling rate */
dkato 6:aa1fc6a5cc2a 169 typedef enum
dkato 6:aa1fc6a5cc2a 170 {
dkato 6:aa1fc6a5cc2a 171 SCUX_SYNC_RATE_8 = 8000, /* 8KHz */
dkato 6:aa1fc6a5cc2a 172 SCUX_SYNC_RATE_11_025 = 11025, /* 11.025KHz */
dkato 6:aa1fc6a5cc2a 173 SCUX_SYNC_RATE_12 = 12000, /* 12KHz */
dkato 6:aa1fc6a5cc2a 174 SCUX_SYNC_RATE_16 = 16000, /* 16KHz */
dkato 6:aa1fc6a5cc2a 175 SCUX_SYNC_RATE_22_05 = 22050, /* 22.05KHz */
dkato 6:aa1fc6a5cc2a 176 SCUX_SYNC_RATE_24 = 24000, /* 24KHz */
dkato 6:aa1fc6a5cc2a 177 SCUX_SYNC_RATE_32 = 32000, /* 32KHz */
dkato 6:aa1fc6a5cc2a 178 SCUX_SYNC_RATE_44_1 = 44100, /* 44.1KHz */
dkato 6:aa1fc6a5cc2a 179 SCUX_SYNC_RATE_48 = 48000, /* 48KHz */
dkato 6:aa1fc6a5cc2a 180 SCUX_SYNC_RATE_64 = 64000, /* 64KHz */
dkato 6:aa1fc6a5cc2a 181 SCUX_SYNC_RATE_88_2 = 88200, /* 88.2KHz */
dkato 6:aa1fc6a5cc2a 182 SCUX_SYNC_RATE_96 = 96000 /* 96KHz */
dkato 6:aa1fc6a5cc2a 183 } scux_src_sync_rate_t;
dkato 6:aa1fc6a5cc2a 184
dkato 6:aa1fc6a5cc2a 185 /* SCUX clock source setting */
dkato 6:aa1fc6a5cc2a 186 typedef enum
dkato 6:aa1fc6a5cc2a 187 {
dkato 6:aa1fc6a5cc2a 188 SCUX_CLK_MIN =(-1),
dkato 6:aa1fc6a5cc2a 189 SCUX_CLK_AUDIO_CLK = 0, /* clock source is AUDIO_CLK */
dkato 6:aa1fc6a5cc2a 190 SCUX_CLK_AUDIO_X1 = 1, /* clock source is AUDIO_X1 */
dkato 6:aa1fc6a5cc2a 191 SCUX_CLK_MLB_CLK = 2, /* clock source is MLB_CLK */
dkato 6:aa1fc6a5cc2a 192 SCUX_CLK_USB_X1 = 3, /* clock source is USB_X1 */
dkato 6:aa1fc6a5cc2a 193 SCUX_CLK_CLKP1_2 = 4, /* clock source is surrounding clock */
dkato 6:aa1fc6a5cc2a 194 SCUX_CLK_MTU_TIOC3A = 5, /* clock source is TIOC3A */
dkato 6:aa1fc6a5cc2a 195 SCUX_CLK_MTU_TIOC4A = 6, /* clock source is TIOC4A */
dkato 6:aa1fc6a5cc2a 196 SCUX_CLK_SSIF0_WS = 8, /* clock source is SSIF0 WS */
dkato 6:aa1fc6a5cc2a 197 SCUX_CLK_SSIF1_WS = 9, /* clock source is SSIF1 WS */
dkato 6:aa1fc6a5cc2a 198 SCUX_CLK_SSIF2_WS = 10, /* clock source is SSIF2 WS */
dkato 6:aa1fc6a5cc2a 199 SCUX_CLK_SSIF3_WS = 11, /* clock source is SSIF3 WS */
dkato 6:aa1fc6a5cc2a 200 SCUX_CLK_SSIF4_WS = 12, /* clock source is SSIF4 WS */
dkato 6:aa1fc6a5cc2a 201 SCUX_CLK_SSIF5_WS = 13, /* clock source is SSIF5 WS */
dkato 6:aa1fc6a5cc2a 202 SCUX_CLK_MAX = 14
dkato 6:aa1fc6a5cc2a 203 } scux_src_clk_source_t;
dkato 6:aa1fc6a5cc2a 204
dkato 6:aa1fc6a5cc2a 205 /* SCUX delay mode setting */
dkato 6:aa1fc6a5cc2a 206 typedef enum
dkato 6:aa1fc6a5cc2a 207 {
dkato 6:aa1fc6a5cc2a 208 SCUX_DELAY_MIN =(-1),
dkato 6:aa1fc6a5cc2a 209 SCUX_DELAY_NORMAL = 0, /* Delay mode is normal */
dkato 6:aa1fc6a5cc2a 210 SCUX_DELAY_LOW_DELAY1 = 1, /* Delay mode is Low Delay1 */
dkato 6:aa1fc6a5cc2a 211 SCUX_DELAY_LOW_DELAY2 = 2, /* Delay mode is Low Delay2 */
dkato 6:aa1fc6a5cc2a 212 SCUX_DELAY_MAX = 3
dkato 6:aa1fc6a5cc2a 213 } scux_src_delay_mode_t;
dkato 6:aa1fc6a5cc2a 214
dkato 6:aa1fc6a5cc2a 215 /* DVU ramp time setting */
dkato 6:aa1fc6a5cc2a 216 typedef enum
dkato 6:aa1fc6a5cc2a 217 {
dkato 6:aa1fc6a5cc2a 218 SCUX_DVU_TIME_MIN =(-1),
dkato 6:aa1fc6a5cc2a 219 SCUX_DVU_TIME_128DB_1STEP = 0, /* volume change 128DB among 1 step */
dkato 6:aa1fc6a5cc2a 220 SCUX_DVU_TIME_64DB_1STEP = 1, /* volume change 64DB among 1 step */
dkato 6:aa1fc6a5cc2a 221 SCUX_DVU_TIME_32DB_1STEP = 2, /* volume change 32DB among 1 step */
dkato 6:aa1fc6a5cc2a 222 SCUX_DVU_TIME_16DB_1STEP = 3, /* volume change 16DB among 1 step */
dkato 6:aa1fc6a5cc2a 223 SCUX_DVU_TIME_8DB_1STEP = 4, /* volume change 8DB among 1 step */
dkato 6:aa1fc6a5cc2a 224 SCUX_DVU_TIME_4DB_1STEP = 5, /* volume change 4DB among 1 step */
dkato 6:aa1fc6a5cc2a 225 SCUX_DVU_TIME_2DB_1STEP = 6, /* volume change 2DB among 1 step */
dkato 6:aa1fc6a5cc2a 226 SCUX_DVU_TIME_1DB_1STEP = 7, /* volume change 1DB among 1 step */
dkato 6:aa1fc6a5cc2a 227 SCUX_DVU_TIME_0_5DB_1STEP = 8, /* volume change 0.5DB among 1 step */
dkato 6:aa1fc6a5cc2a 228 SCUX_DVU_TIME_0_25DB_1STEP = 9, /* volume change 0.25DB among 1 step */
dkato 6:aa1fc6a5cc2a 229 SCUX_DVU_TIME_0_125DB_1STEP = 10, /* volume change 0.125DB among 1 step */
dkato 6:aa1fc6a5cc2a 230 SCUX_DVU_TIME_0_125DB_2STEP = 11, /* volume change 0.125DB among 2 step */
dkato 6:aa1fc6a5cc2a 231 SCUX_DVU_TIME_0_125DB_4STEP = 12, /* volume change 0.125DB among 4 step */
dkato 6:aa1fc6a5cc2a 232 SCUX_DVU_TIME_0_125DB_8STEP = 13, /* volume change 0.125DB among 8 step */
dkato 6:aa1fc6a5cc2a 233 SCUX_DVU_TIME_0_125DB_16STEP = 14, /* volume change 0.125DB among 16 step */
dkato 6:aa1fc6a5cc2a 234 SCUX_DVU_TIME_0_125DB_32STEP = 15, /* volume change 0.125DB among 32 step */
dkato 6:aa1fc6a5cc2a 235 SCUX_DVU_TIME_0_125DB_64STEP = 16, /* volume change 0.125DB among 64 step */
dkato 6:aa1fc6a5cc2a 236 SCUX_DVU_TIME_0_125DB_128STEP = 17, /* volume change 0.125DB among 128 step */
dkato 6:aa1fc6a5cc2a 237 SCUX_DVU_TIME_0_125DB_256STEP = 18, /* volume change 0.125DB among 256 step */
dkato 6:aa1fc6a5cc2a 238 SCUX_DVU_TIME_0_125DB_512STEP = 19, /* volume change 0.125DB among 512 step */
dkato 6:aa1fc6a5cc2a 239 SCUX_DVU_TIME_0_125DB_1024STEP = 20, /* volume change 0.125DB among 1024 step */
dkato 6:aa1fc6a5cc2a 240 SCUX_DVU_TIME_0_125DB_2048STEP = 21, /* volume change 0.125DB among 2048 step */
dkato 6:aa1fc6a5cc2a 241 SCUX_DVU_TIME_0_125DB_4096STEP = 22, /* volume change 0.125DB among 4096 step */
dkato 6:aa1fc6a5cc2a 242 SCUX_DVU_TIME_0_125DB_8192STEP = 23, /* volume change 0.125DB among 8192 step */
dkato 6:aa1fc6a5cc2a 243 SCUX_DVU_TIME_MAX = 24
dkato 6:aa1fc6a5cc2a 244 } scux_dvu_ramp_time_t;
dkato 6:aa1fc6a5cc2a 245
dkato 6:aa1fc6a5cc2a 246 /* MIX ramp time setting */
dkato 6:aa1fc6a5cc2a 247 typedef enum
dkato 6:aa1fc6a5cc2a 248 {
dkato 6:aa1fc6a5cc2a 249 SCUX_MIX_TIME_MIN =(-1),
dkato 6:aa1fc6a5cc2a 250 SCUX_MIX_TIME_128DB_1STEP = 0, /* volume change 128DB among 1 step */
dkato 6:aa1fc6a5cc2a 251 SCUX_MIX_TIME_64DB_1STEP = 1, /* volume change 64DB among 1 step */
dkato 6:aa1fc6a5cc2a 252 SCUX_MIX_TIME_32DB_1STEP = 2, /* volume change 32DB among 1 step */
dkato 6:aa1fc6a5cc2a 253 SCUX_MIX_TIME_16DB_1STEP = 3, /* volume change 16DB among 1 step */
dkato 6:aa1fc6a5cc2a 254 SCUX_MIX_TIME_8DB_1STEP = 4, /* volume change 8DB among 1 step */
dkato 6:aa1fc6a5cc2a 255 SCUX_MIX_TIME_4DB_1STEP = 5, /* volume change 4DB among 1 step */
dkato 6:aa1fc6a5cc2a 256 SCUX_MIX_TIME_2DB_1STEP = 6, /* volume change 2DB among 1 step */
dkato 6:aa1fc6a5cc2a 257 SCUX_MIX_TIME_1DB_1STEP = 7, /* volume change 1DB among 1 step */
dkato 6:aa1fc6a5cc2a 258 SCUX_MIX_TIME_0_5DB_1STEP = 8, /* volume change 0.5DB among 1 step */
dkato 6:aa1fc6a5cc2a 259 SCUX_MIX_TIME_0_25DB_1STEP = 9, /* volume change 0.25DB among 1 step */
dkato 6:aa1fc6a5cc2a 260 SCUX_MIX_TIME_0_125DB_1STEP = 10, /* volume change 0.125DB among 1 step */
dkato 6:aa1fc6a5cc2a 261 SCUX_MIX_TIME_MAX = 11
dkato 6:aa1fc6a5cc2a 262 } scux_mix_ramp_time_t;
dkato 6:aa1fc6a5cc2a 263
dkato 6:aa1fc6a5cc2a 264 /* SSIF channels */
dkato 6:aa1fc6a5cc2a 265 typedef enum
dkato 6:aa1fc6a5cc2a 266 {
dkato 6:aa1fc6a5cc2a 267 SCUX_SSIF_CH_0 = 0, /* volume change 128DB among 1 step */
dkato 6:aa1fc6a5cc2a 268 SCUX_SSIF_CH_1 = 1, /* volume change 64DB among 1 step */
dkato 6:aa1fc6a5cc2a 269 SCUX_SSIF_CH_2 = 2, /* volume change 32DB among 1 step */
dkato 6:aa1fc6a5cc2a 270 SCUX_SSIF_CH_3 = 3, /* volume change 16DB among 1 step */
dkato 6:aa1fc6a5cc2a 271 SCUX_SSIF_CH_4 = 4, /* volume change 8DB among 1 step */
dkato 6:aa1fc6a5cc2a 272 SCUX_SSIF_CH_5 = 5, /* volume change 4DB among 1 step */
dkato 6:aa1fc6a5cc2a 273 SCUX_SSIF_CH_NUM = 6
dkato 6:aa1fc6a5cc2a 274 } scux_ssif_ch_num_t;
dkato 6:aa1fc6a5cc2a 275
dkato 6:aa1fc6a5cc2a 276 /* SSIF channels */
dkato 6:aa1fc6a5cc2a 277 typedef enum
dkato 6:aa1fc6a5cc2a 278 {
dkato 6:aa1fc6a5cc2a 279 SCUX_SSIF_SYSTEM_LEN_MIN = 0,
dkato 6:aa1fc6a5cc2a 280 SCUX_SSIF_SYSTEM_LEN_16 = 1, /* SSIF system word length is 16bit */
dkato 6:aa1fc6a5cc2a 281 SCUX_SSIF_SYSTEM_LEN_24 = 2, /* SSIF system word length is 24bit */
dkato 6:aa1fc6a5cc2a 282 SCUX_SSIF_SYSTEM_LEN_32 = 3, /* SSIF system word length is 32bit */
dkato 6:aa1fc6a5cc2a 283 SCUX_SSIF_SYSTEM_LEN_48 = 4, /* SSIF system word length is 48bit */
dkato 6:aa1fc6a5cc2a 284 SCUX_SSIF_SYSTEM_LEN_64 = 5, /* SSIF system word length is 64bit */
dkato 6:aa1fc6a5cc2a 285 SCUX_SSIF_SYSTEM_LEN_128 = 6, /* SSIF system word length is 128bit */
dkato 6:aa1fc6a5cc2a 286 SCUX_SSIF_SYSTEM_LEN_256 = 7, /* SSIF system word length is 256bit */
dkato 6:aa1fc6a5cc2a 287 SCUX_SSIF_SYSTEM_LEN_MAX = 8
dkato 6:aa1fc6a5cc2a 288 } scux_ssif_system_len_t;
dkato 6:aa1fc6a5cc2a 289
dkato 6:aa1fc6a5cc2a 290 /******************************************************************************
dkato 6:aa1fc6a5cc2a 291 Macro definitions
dkato 6:aa1fc6a5cc2a 292 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 293
dkato 6:aa1fc6a5cc2a 294 /* SCUX IOCTL function code */
dkato 6:aa1fc6a5cc2a 295 #define SCUX_IOCTL_MIN (-1)
dkato 6:aa1fc6a5cc2a 296 #define SCUX_IOCTL_SET_START 0 /* start transfer */
dkato 6:aa1fc6a5cc2a 297 #define SCUX_IOCTL_SET_FLUSH_STOP 1 /* set flush stop function */
dkato 6:aa1fc6a5cc2a 298 #define SCUX_IOCTL_SET_CLEAR_STOP 2 /* set clear stop function */
dkato 6:aa1fc6a5cc2a 299 #define SCUX_IOCTL_SET_ROUTE 3 /* set route parameter */
dkato 6:aa1fc6a5cc2a 300 #define SCUX_IOCTL_SET_PIN_CLK 4 /* set pin clock parameter */
dkato 6:aa1fc6a5cc2a 301 #define SCUX_IOCTL_SET_PIN_MODE 5 /* set pin mode parameter */
dkato 6:aa1fc6a5cc2a 302 #define SCUX_IOCTL_SET_SRC_CFG 6 /* set SRC parameter */
dkato 6:aa1fc6a5cc2a 303 #define SCUX_IOCTL_SET_DVU_CFG 7 /* set DVU parameter */
dkato 6:aa1fc6a5cc2a 304 #define SCUX_IOCTL_SET_DVU_DIGI_VOL 8 /* set dgital volume parameter */
dkato 6:aa1fc6a5cc2a 305 #define SCUX_IOCTL_SET_DVU_RAMP_VOL 9 /* set ramp volume parameter */
dkato 6:aa1fc6a5cc2a 306 #define SCUX_IOCTL_SET_ZEROCROSS_MUTE 10 /* set zerocross mute paramter */
dkato 6:aa1fc6a5cc2a 307 #define SCUX_IOCTL_SET_STOP_MUTE 11 /* set mute stop */
dkato 6:aa1fc6a5cc2a 308 #define SCUX_IOCTL_SET_MIX_CFG 12 /* set MIX parameter */
dkato 6:aa1fc6a5cc2a 309 #define SCUX_IOCTL_SET_MIX_VOL 13 /* set MIX volume parameter */
dkato 6:aa1fc6a5cc2a 310 #define SCUX_IOCTL_SET_SSIF_CFG 14 /* set SSIF parameter */
dkato 6:aa1fc6a5cc2a 311 #define SCUX_IOCTL_GET_WRITE_STAT 15 /* get write status */
dkato 6:aa1fc6a5cc2a 312 #define SCUX_IOCTL_GET_READ_STAT 16 /* get read status */
dkato 6:aa1fc6a5cc2a 313 #define SCUX_IOCTL_GET_DVU_STAT 17 /* get DVU status */
dkato 6:aa1fc6a5cc2a 314 #define SCUX_IOCTL_GET_MUTE_STAT 18 /* get MUTE status */
dkato 6:aa1fc6a5cc2a 315 #define SCUX_IOCTL_GET_MIX_STAT 19 /* get MIX status */
dkato 6:aa1fc6a5cc2a 316 #define SCUX_IOCTL_MAX 20
dkato 6:aa1fc6a5cc2a 317
dkato 6:aa1fc6a5cc2a 318 #if(1) /* mbed */
dkato 6:aa1fc6a5cc2a 319 #else /* not mbed */
dkato 6:aa1fc6a5cc2a 320 /* SCUX status */
dkato 6:aa1fc6a5cc2a 321 #define SCUX_STAT_STOP 0 /* request regstration isn't start */
dkato 6:aa1fc6a5cc2a 322 #define SCUX_STAT_IDLE 1 /* request isn't receied */
dkato 6:aa1fc6a5cc2a 323 #define SCUX_STAT_TRANS 2 /* under data transfer execution */
dkato 6:aa1fc6a5cc2a 324 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 325
dkato 6:aa1fc6a5cc2a 326 /* DVU status */
dkato 6:aa1fc6a5cc2a 327 #define SCUX_DVU_STAT_MUTE 0 /* DVU volume is mute */
dkato 6:aa1fc6a5cc2a 328 #define SCUX_DVU_STAT_RAMP_DOWN 1 /* DVU volume is ramp down */
dkato 6:aa1fc6a5cc2a 329 #define SCUX_DVU_STAT_RAMP_UP 2 /* DVU volume is ramp up */
dkato 6:aa1fc6a5cc2a 330 #define SCUX_DVU_STAT_RAMP_FIXED 3 /* DVU volume change is stop */
dkato 6:aa1fc6a5cc2a 331 #define SCUX_DVU_STAT_ORIGINAL_SIZE 4 /* DVU volume is original size */
dkato 6:aa1fc6a5cc2a 332
dkato 6:aa1fc6a5cc2a 333 /* MIX status */
dkato 6:aa1fc6a5cc2a 334 #define SCUX_MIX_STAT_RAMP_FIXED 0 /* MIX volume change is stop */
dkato 6:aa1fc6a5cc2a 335 #define SCUX_MIX_STAT_RAMP_DOWN 1 /* MIX volume is ramp down */
dkato 6:aa1fc6a5cc2a 336 #define SCUX_MIX_STAT_RAMP_UP 2 /* MIX volume is ramp up */
dkato 6:aa1fc6a5cc2a 337
dkato 6:aa1fc6a5cc2a 338 /*************************************************************************
dkato 6:aa1fc6a5cc2a 339 Structures
dkato 6:aa1fc6a5cc2a 340 *************************************************************************/
dkato 6:aa1fc6a5cc2a 341
dkato 6:aa1fc6a5cc2a 342 /* SSIF channel synchronous setting */
dkato 6:aa1fc6a5cc2a 343 typedef struct
dkato 6:aa1fc6a5cc2a 344 {
dkato 6:aa1fc6a5cc2a 345 scux_ssif_ch_num_t ssif_ch_num; /* ssif channel number */
dkato 6:aa1fc6a5cc2a 346 scux_pin_mode_t pin_mode; /* SSIF sync setting */
dkato 6:aa1fc6a5cc2a 347 } scux_ssif_pin_mode_t;
dkato 6:aa1fc6a5cc2a 348
dkato 6:aa1fc6a5cc2a 349 /* SSIF AUDIO_CLK source parameters */
dkato 6:aa1fc6a5cc2a 350 typedef struct
dkato 6:aa1fc6a5cc2a 351 {
dkato 6:aa1fc6a5cc2a 352 scux_ssif_ch_num_t ssif_ch_num; /* ssif channel number */
dkato 6:aa1fc6a5cc2a 353 scux_src_clk_source_t pin_clk; /* AUDIO_CLK source */
dkato 6:aa1fc6a5cc2a 354 } scux_ssif_pin_clk_t;
dkato 6:aa1fc6a5cc2a 355
dkato 6:aa1fc6a5cc2a 356 /* SSIF parameters */
dkato 6:aa1fc6a5cc2a 357 typedef struct
dkato 6:aa1fc6a5cc2a 358 {
dkato 6:aa1fc6a5cc2a 359 scux_ssif_ch_num_t ssif_ch_num; /* ssif channel number */
dkato 6:aa1fc6a5cc2a 360 bool_t mode_master; /* master mode / slave mode select */
dkato 6:aa1fc6a5cc2a 361 bool_t select_audio_clk; /* AUDIO_X1 / AUDIO_CLK select */
dkato 6:aa1fc6a5cc2a 362 scux_ssif_system_len_t system_word; /* system word length */
dkato 6:aa1fc6a5cc2a 363 bool_t sck_polarity_rise; /* SCK polarity type select */
dkato 6:aa1fc6a5cc2a 364 bool_t ws_polarity_high; /* WS polarity type select */
dkato 6:aa1fc6a5cc2a 365 bool_t padding_high; /* padding type select */
dkato 6:aa1fc6a5cc2a 366 bool_t serial_data_align; /* serial data alingment type select */
dkato 6:aa1fc6a5cc2a 367 bool_t ws_delay; /* WS delay type select */
dkato 6:aa1fc6a5cc2a 368 bool_t use_noise_cancel; /* noise cancel ON / OFF select */
dkato 6:aa1fc6a5cc2a 369 bool_t use_tdm; /* TDM mode ON / OFF select */
dkato 6:aa1fc6a5cc2a 370 } scux_ssif_cfg_t;
dkato 6:aa1fc6a5cc2a 371
dkato 6:aa1fc6a5cc2a 372 /* MIX parameters */
dkato 6:aa1fc6a5cc2a 373 typedef struct
dkato 6:aa1fc6a5cc2a 374 {
dkato 6:aa1fc6a5cc2a 375 bool_t mixmode_ramp; /* ramp mode / step mpde select */
dkato 6:aa1fc6a5cc2a 376 scux_mix_ramp_time_t up_period; /* ramp up period */
dkato 6:aa1fc6a5cc2a 377 scux_mix_ramp_time_t down_period; /* ramp down period */
dkato 6:aa1fc6a5cc2a 378 uint32_t mix_vol[SCUX_CH_NUM]; /* MIX volume value */
dkato 6:aa1fc6a5cc2a 379 scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
dkato 6:aa1fc6a5cc2a 380 } scux_mix_cfg_t;
dkato 6:aa1fc6a5cc2a 381
dkato 6:aa1fc6a5cc2a 382 /* zerocross mute parameters */
dkato 6:aa1fc6a5cc2a 383 typedef struct
dkato 6:aa1fc6a5cc2a 384 {
dkato 6:aa1fc6a5cc2a 385 bool_t zc_mute_enable[SCUX_AUDIO_CH_MAX]; /* zerocross mute enable setting */
dkato 6:aa1fc6a5cc2a 386 void (*pcallback[SCUX_AUDIO_CH_MAX])(void); /* callback pointer for zerocross */
dkato 6:aa1fc6a5cc2a 387 } scux_zc_mute_t;
dkato 6:aa1fc6a5cc2a 388
dkato 6:aa1fc6a5cc2a 389 /* ramp volume parameters */
dkato 6:aa1fc6a5cc2a 390 typedef struct
dkato 6:aa1fc6a5cc2a 391 {
dkato 6:aa1fc6a5cc2a 392 bool_t ramp_vol_enable[SCUX_AUDIO_CH_MAX]; /* ramp volume enable setting */
dkato 6:aa1fc6a5cc2a 393 scux_dvu_ramp_time_t up_period; /* ramp up period */
dkato 6:aa1fc6a5cc2a 394 scux_dvu_ramp_time_t down_period; /* ramp down period */
dkato 6:aa1fc6a5cc2a 395 uint32_t ramp_vol; /* ramp volume value */
dkato 6:aa1fc6a5cc2a 396 uint32_t ramp_wait_time; /* wait time for volume change */
dkato 6:aa1fc6a5cc2a 397 } scux_dvu_ramp_vol_t;
dkato 6:aa1fc6a5cc2a 398
dkato 6:aa1fc6a5cc2a 399 /* digital volume parameters */
dkato 6:aa1fc6a5cc2a 400 typedef struct
dkato 6:aa1fc6a5cc2a 401 {
dkato 6:aa1fc6a5cc2a 402 bool_t digi_vol_enable; /* digital volume enable setting */
dkato 6:aa1fc6a5cc2a 403 uint32_t digi_vol[SCUX_AUDIO_CH_MAX]; /* digital volume value */
dkato 6:aa1fc6a5cc2a 404 } scux_dvu_digi_vol_t;
dkato 6:aa1fc6a5cc2a 405
dkato 6:aa1fc6a5cc2a 406 /* DVU parameters */
dkato 6:aa1fc6a5cc2a 407 typedef struct
dkato 6:aa1fc6a5cc2a 408 {
dkato 6:aa1fc6a5cc2a 409 bool_t dvu_enable; /* DVU enable setting */
dkato 6:aa1fc6a5cc2a 410 scux_dvu_digi_vol_t dvu_digi_vol; /* digital volume setting */
dkato 6:aa1fc6a5cc2a 411 scux_dvu_ramp_vol_t dvu_ramp_vol; /* ramp volume setting */
dkato 6:aa1fc6a5cc2a 412 scux_zc_mute_t dvu_zc_mute; /* zerocross mute setting */
dkato 6:aa1fc6a5cc2a 413 } scux_dvu_cfg_t;
dkato 6:aa1fc6a5cc2a 414
dkato 6:aa1fc6a5cc2a 415 /* SRC parameters */
dkato 6:aa1fc6a5cc2a 416 typedef struct
dkato 6:aa1fc6a5cc2a 417 {
dkato 6:aa1fc6a5cc2a 418 bool_t src_enable; /* SRC enable setting */
dkato 6:aa1fc6a5cc2a 419 scux_use_channel_t use_ch; /* used data channel setting */
dkato 6:aa1fc6a5cc2a 420 scux_data_word_len_t word_len; /* used word length setting */
dkato 6:aa1fc6a5cc2a 421 bool_t mode_sync; /* sync mode/async mode select */
dkato 6:aa1fc6a5cc2a 422 scux_src_sync_rate_t input_rate_sync; /* input rate on sync mode */
dkato 6:aa1fc6a5cc2a 423 scux_src_clk_source_t input_clk_async; /* input clock source on async mode */
dkato 6:aa1fc6a5cc2a 424 uint32_t input_div_async; /* input divide rate on async mode */
dkato 6:aa1fc6a5cc2a 425 scux_src_sync_rate_t output_rate_sync; /* output rate on sync mode */
dkato 6:aa1fc6a5cc2a 426 scux_src_clk_source_t output_clk_async; /* output clock source on async mode */
dkato 6:aa1fc6a5cc2a 427 uint32_t output_div_async; /* output divide rate on async mode */
dkato 6:aa1fc6a5cc2a 428 uint32_t input_ws; /* input WS frequency */
dkato 6:aa1fc6a5cc2a 429 uint32_t output_ws; /* output WS frequency */
dkato 6:aa1fc6a5cc2a 430 uint32_t freq_tioc3a; /* frequency of TIOC3A */
dkato 6:aa1fc6a5cc2a 431 uint32_t freq_tioc4a; /* frequency of TIOC4A */
dkato 6:aa1fc6a5cc2a 432 scux_src_delay_mode_t delay_mode; /* delay mode setting */
dkato 6:aa1fc6a5cc2a 433 uint32_t wait_sample; /* wait time setting */
dkato 6:aa1fc6a5cc2a 434 uint8_t min_rate_percentage; /* minimum rate setting */
dkato 6:aa1fc6a5cc2a 435 scux_audio_channel_t select_in_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
dkato 6:aa1fc6a5cc2a 436 } scux_src_cfg_t;
dkato 6:aa1fc6a5cc2a 437
dkato 6:aa1fc6a5cc2a 438 /* SCUX setup parameter */
dkato 6:aa1fc6a5cc2a 439 typedef struct
dkato 6:aa1fc6a5cc2a 440 {
dkato 6:aa1fc6a5cc2a 441 bool_t enabled; /* channel used flag */
dkato 6:aa1fc6a5cc2a 442 uint8_t int_level; /* interrupt priority */
dkato 6:aa1fc6a5cc2a 443 scux_route_t route; /* reoute setting */
dkato 6:aa1fc6a5cc2a 444 scux_src_cfg_t src_cfg; /* SRC parameters */
dkato 6:aa1fc6a5cc2a 445 } scux_channel_cfg_t;
dkato 6:aa1fc6a5cc2a 446
dkato 6:aa1fc6a5cc2a 447 /******************************************************************************
dkato 6:aa1fc6a5cc2a 448 Functions Prototypes
dkato 6:aa1fc6a5cc2a 449 ******************************************************************************/
dkato 6:aa1fc6a5cc2a 450
dkato 6:aa1fc6a5cc2a 451 #if(1) /* mbed */
dkato 7:30ebba78fff0 452 RBSP_MBED_FNS* R_SCUX_MakeCbTbl_mbed(void);
dkato 6:aa1fc6a5cc2a 453 #else /* not mbed */
dkato 6:aa1fc6a5cc2a 454 IOIF_DRV_API* R_SCUX_MakeCbTbl(void);
dkato 6:aa1fc6a5cc2a 455 #endif /* end mbed */
dkato 6:aa1fc6a5cc2a 456
dkato 6:aa1fc6a5cc2a 457 extern uint16_t R_SCUX_GetVersion(void);
dkato 6:aa1fc6a5cc2a 458
dkato 6:aa1fc6a5cc2a 459 #ifdef __cplusplus
dkato 6:aa1fc6a5cc2a 460 }
dkato 6:aa1fc6a5cc2a 461 #endif /* __cplusplus */
dkato 6:aa1fc6a5cc2a 462
dkato 6:aa1fc6a5cc2a 463 #endif /* SCUX_IF_H */