cpg_iobitmask.h

00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
00006 * all applicable laws, including copyright laws.
00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /*******************************************************************************
00024 * File Name   : cpg_iobitmask.h
00025 * $Rev: 809 $
00026 * $Date:: 2014-04-09 15:06:36 +0900#$
00027 * Description : CPG register define header
00028 *******************************************************************************/
00029 #ifndef CPG_IOBITMASK_H
00030 #define CPG_IOBITMASK_H
00031 
00032 
00033 /* ==== Mask values for IO registers ==== */
00034 #define CPG_FRQCR_IFC                   (0x0300u)
00035 #define CPG_FRQCR_CKOEN                 (0x3000u)
00036 #define CPG_FRQCR_CKOEN2                (0x4000u)
00037 
00038 #define CPG_FRQCR2_GFC                  (0x0003u)
00039 
00040 #define CPG_CPUSTS_ISBUSY               (0x10u)
00041 
00042 #define CPG_STBCR1_DEEP                 (0x40u)
00043 #define CPG_STBCR1_STBY                 (0x80u)
00044 
00045 #define CPG_STBCR2_MSTP20               (0x01u)
00046 #define CPG_STBCR2_HIZ                  (0x80u)
00047 
00048 #define CPG_STBREQ1_STBRQ10             (0x01u)
00049 #define CPG_STBREQ1_STBRQ12             (0x04u)
00050 #define CPG_STBREQ1_STBRQ13             (0x08u)
00051 #define CPG_STBREQ1_STBRQ15             (0x20u)
00052 
00053 #define CPG_STBREQ2_STBRQ20             (0x01u)
00054 #define CPG_STBREQ2_STBRQ21             (0x02u)
00055 #define CPG_STBREQ2_STBRQ22             (0x04u)
00056 #define CPG_STBREQ2_STBRQ23             (0x08u)
00057 #define CPG_STBREQ2_STBRQ24             (0x10u)
00058 #define CPG_STBREQ2_STBRQ25             (0x20u)
00059 #define CPG_STBREQ2_STBRQ26             (0x40u)
00060 #define CPG_STBREQ2_STBRQ27             (0x80u)
00061 
00062 #define CPG_STBACK1_STBAK10             (0x01u)
00063 #define CPG_STBACK1_STBAK12             (0x04u)
00064 #define CPG_STBACK1_STBAK13             (0x08u)
00065 #define CPG_STBACK1_STBAK15             (0x20u)
00066 
00067 #define CPG_STBACK2_STBAK20             (0x01u)
00068 #define CPG_STBACK2_STBAK21             (0x02u)
00069 #define CPG_STBACK2_STBAK22             (0x04u)
00070 #define CPG_STBACK2_STBAK23             (0x08u)
00071 #define CPG_STBACK2_STBAK24             (0x10u)
00072 #define CPG_STBACK2_STBAK25             (0x20u)
00073 #define CPG_STBACK2_STBAK26             (0x40u)
00074 #define CPG_STBACK2_STBAK27             (0x80u)
00075 
00076 #define CPG_SYSCR1_VRAME0               (0x01u)
00077 #define CPG_SYSCR1_VRAME1               (0x02u)
00078 #define CPG_SYSCR1_VRAME2               (0x04u)
00079 #define CPG_SYSCR1_VRAME3               (0x08u)
00080 #define CPG_SYSCR1_VRAME4               (0x10u)
00081 
00082 #define CPG_SYSCR2_VRAMWE0              (0x01u)
00083 #define CPG_SYSCR2_VRAMWE1              (0x02u)
00084 #define CPG_SYSCR2_VRAMWE2              (0x04u)
00085 #define CPG_SYSCR2_VRAMWE3              (0x08u)
00086 #define CPG_SYSCR2_VRAMWE4              (0x10u)
00087 
00088 #define CPG_SYSCR3_RRAMWE0              (0x01u)
00089 #define CPG_SYSCR3_RRAMWE1              (0x02u)
00090 #define CPG_SYSCR3_RRAMWE2              (0x04u)
00091 #define CPG_SYSCR3_RRAMWE3              (0x08u)
00092 
00093 #define CPG_STBCR3_MSTP30               (0x01u)
00094 #define CPG_STBCR3_MSTP31               (0x02u)
00095 #define CPG_STBCR3_MSTP32               (0x04u)
00096 #define CPG_STBCR3_MSTP33               (0x08u)
00097 #define CPG_STBCR3_MSTP34               (0x10u)
00098 #define CPG_STBCR3_MSTP35               (0x20u)
00099 #define CPG_STBCR3_MSTP36               (0x40u)
00100 #define CPG_STBCR3_MSTP37               (0x80u)
00101 
00102 #define CPG_STBCR4_MSTP40               (0x01u)
00103 #define CPG_STBCR4_MSTP41               (0x02u)
00104 #define CPG_STBCR4_MSTP42               (0x04u)
00105 #define CPG_STBCR4_MSTP43               (0x08u)
00106 #define CPG_STBCR4_MSTP44               (0x10u)
00107 #define CPG_STBCR4_MSTP45               (0x20u)
00108 #define CPG_STBCR4_MSTP46               (0x40u)
00109 #define CPG_STBCR4_MSTP47               (0x80u)
00110 
00111 #define CPG_STBCR5_MSTP50               (0x01u)
00112 #define CPG_STBCR5_MSTP51               (0x02u)
00113 #define CPG_STBCR5_MSTP52               (0x04u)
00114 #define CPG_STBCR5_MSTP53               (0x08u)
00115 #define CPG_STBCR5_MSTP54               (0x10u)
00116 #define CPG_STBCR5_MSTP55               (0x20u)
00117 #define CPG_STBCR5_MSTP56               (0x40u)
00118 #define CPG_STBCR5_MSTP57               (0x80u)
00119 
00120 #define CPG_STBCR6_MSTP60               (0x01u)
00121 #define CPG_STBCR6_MSTP61               (0x02u)
00122 #define CPG_STBCR6_MSTP62               (0x04u)
00123 #define CPG_STBCR6_MSTP63               (0x08u)
00124 #define CPG_STBCR6_MSTP64               (0x10u)
00125 #define CPG_STBCR6_MSTP65               (0x20u)
00126 #define CPG_STBCR6_MSTP66               (0x40u)
00127 #define CPG_STBCR6_MSTP67               (0x80u)
00128 
00129 #define CPG_STBCR7_MSTP70               (0x01u)
00130 #define CPG_STBCR7_MSTP71               (0x02u)
00131 #define CPG_STBCR7_MSTP73               (0x08u)
00132 #define CPG_STBCR7_MSTP74               (0x10u)
00133 #define CPG_STBCR7_MSTP76               (0x40u)
00134 #define CPG_STBCR7_MSTP77               (0x80u)
00135 
00136 #define CPG_STBCR8_MSTP81               (0x02u)
00137 #define CPG_STBCR8_MSTP82               (0x04u)
00138 #define CPG_STBCR8_MSTP83               (0x08u)
00139 #define CPG_STBCR8_MSTP84               (0x10u)
00140 #define CPG_STBCR8_MSTP85               (0x20u)
00141 #define CPG_STBCR8_MSTP86               (0x40u)
00142 #define CPG_STBCR8_MSTP87               (0x80u)
00143 
00144 #define CPG_STBCR9_MSTP90               (0x01u)
00145 #define CPG_STBCR9_MSTP91               (0x02u)
00146 #define CPG_STBCR9_MSTP92               (0x04u)
00147 #define CPG_STBCR9_MSTP93               (0x08u)
00148 #define CPG_STBCR9_MSTP94               (0x10u)
00149 #define CPG_STBCR9_MSTP95               (0x20u)
00150 #define CPG_STBCR9_MSTP96               (0x40u)
00151 #define CPG_STBCR9_MSTP97               (0x80u)
00152 
00153 #define CPG_STBCR10_MSTP100             (0x01u)
00154 #define CPG_STBCR10_MSTP101             (0x02u)
00155 #define CPG_STBCR10_MSTP102             (0x04u)
00156 #define CPG_STBCR10_MSTP103             (0x08u)
00157 #define CPG_STBCR10_MSTP104             (0x10u)
00158 #define CPG_STBCR10_MSTP105             (0x20u)
00159 #define CPG_STBCR10_MSTP106             (0x40u)
00160 #define CPG_STBCR10_MSTP107             (0x80u)
00161 
00162 #define CPG_STBCR11_MSTP110             (0x01u)
00163 #define CPG_STBCR11_MSTP111             (0x02u)
00164 #define CPG_STBCR11_MSTP112             (0x04u)
00165 #define CPG_STBCR11_MSTP113             (0x08u)
00166 #define CPG_STBCR11_MSTP114             (0x10u)
00167 #define CPG_STBCR11_MSTP115             (0x20u)
00168 
00169 #define CPG_STBCR12_MSTP120             (0x01u)
00170 #define CPG_STBCR12_MSTP121             (0x02u)
00171 #define CPG_STBCR12_MSTP122             (0x04u)
00172 #define CPG_STBCR12_MSTP123             (0x08u)
00173 
00174 #define CPG_STBCR13_MSTP131             (0x02u)
00175 #define CPG_STBCR13_MSTP132             (0x04u)
00176 
00177 #define CPG_SWRSTCR1_SRST11             (0x02u)
00178 #define CPG_SWRSTCR1_SRST12             (0x04u)
00179 #define CPG_SWRSTCR1_SRST13             (0x08u)
00180 #define CPG_SWRSTCR1_SRST14             (0x10u)
00181 #define CPG_SWRSTCR1_SRST15             (0x20u)
00182 #define CPG_SWRSTCR1_SRST16             (0x40u)
00183 #define CPG_SWRSTCR1_AXTALE             (0x80u)
00184 
00185 #define CPG_SWRSTCR2_SRST21             (0x02u)
00186 
00187 #define CPG_SWRSTCR3_SRST32             (0x04u)
00188 
00189 #define CPG_RRAMKP_RRAMKP0              (0x01u)
00190 #define CPG_RRAMKP_RRAMKP1              (0x02u)
00191 #define CPG_RRAMKP_RRAMKP2              (0x04u)
00192 #define CPG_RRAMKP_RRAMKP3              (0x08u)
00193 
00194 #define CPG_DSCTR_RAMBOOT               (0x40u)
00195 #define CPG_DSCTR_EBUSKEEPE             (0x80u)
00196 
00197 #define CPG_DSSSR_P8_2                  (0x0001u)
00198 #define CPG_DSSSR_P9_1                  (0x0002u)
00199 #define CPG_DSSSR_P2_15                 (0x0004u)
00200 #define CPG_DSSSR_P7_8                  (0x0008u)
00201 #define CPG_DSSSR_P5_9                  (0x0010u)
00202 #define CPG_DSSSR_P6_4                  (0x0020u)
00203 #define CPG_DSSSR_RTCAR                 (0x0040u)
00204 #define CPG_DSSSR_NMI                   (0x0100u)
00205 #define CPG_DSSSR_P3_3                  (0x0200u)
00206 #define CPG_DSSSR_P8_7                  (0x0400u)
00207 #define CPG_DSSSR_P2_12                 (0x0800u)
00208 #define CPG_DSSSR_P3_1                  (0x1000u)
00209 #define CPG_DSSSR_P3_9                  (0x2000u)
00210 #define CPG_DSSSR_P6_2                  (0x4000u)
00211 
00212 #define CPG_DSESR_P8_2E                 (0x0001u)
00213 #define CPG_DSESR_P9_1E                 (0x0002u)
00214 #define CPG_DSESR_P2_15E                (0x0004u)
00215 #define CPG_DSESR_P7_8E                 (0x0008u)
00216 #define CPG_DSESR_P5_9E                 (0x0010u)
00217 #define CPG_DSESR_P6_4E                 (0x0020u)
00218 #define CPG_DSESR_NMIE                  (0x0100u)
00219 #define CPG_DSESR_P3_3E                 (0x0200u)
00220 #define CPG_DSESR_P8_7E                 (0x0400u)
00221 #define CPG_DSESR_P2_12E                (0x0800u)
00222 #define CPG_DSESR_P3_1E                 (0x1000u)
00223 #define CPG_DSESR_P3_9E                 (0x2000u)
00224 #define CPG_DSESR_P6_2E                 (0x4000u)
00225 
00226 #define CPG_DSFR_P8_2F                  (0x0001u)
00227 #define CPG_DSFR_P9_1F                  (0x0002u)
00228 #define CPG_DSFR_P2_15F                 (0x0004u)
00229 #define CPG_DSFR_P7_8F                  (0x0008u)
00230 #define CPG_DSFR_P5_9F                  (0x0010u)
00231 #define CPG_DSFR_P6_4F                  (0x0020u)
00232 #define CPG_DSFR_RTCARF                 (0x0040u)
00233 #define CPG_DSFR_NMIF                   (0x0100u)
00234 #define CPG_DSFR_P3_3F                  (0x0200u)
00235 #define CPG_DSFR_P8_7F                  (0x0400u)
00236 #define CPG_DSFR_P2_12F                 (0x0800u)
00237 #define CPG_DSFR_P3_1F                  (0x1000u)
00238 #define CPG_DSFR_P3_9F                  (0x2000u)
00239 #define CPG_DSFR_P6_2F                  (0x4000u)
00240 #define CPG_DSFR_IOKEEP                 (0x8000u)
00241 
00242 #define CPG_XTALCTR_GAIN0               (0x01u)
00243 #define CPG_XTALCTR_GAIN1               (0x02u)
00244 
00245 
00246 /* ==== Shift values for IO registers ==== */
00247 #define CPG_FRQCR_IFC_SHIFT             (8u)
00248 #define CPG_FRQCR_CKOEN_SHIFT           (12u)
00249 #define CPG_FRQCR_CKOEN2_SHIFT          (14u)
00250 
00251 #define CPG_FRQCR2_GFC_SHIFT            (0u)
00252 
00253 #define CPG_CPUSTS_ISBUSY_SHIFT         (4u)
00254 
00255 #define CPG_STBCR1_DEEP_SHIFT           (6u)
00256 #define CPG_STBCR1_STBY_SHIFT           (7u)
00257 
00258 #define CPG_STBCR2_MSTP20_SHIFT         (0u)
00259 #define CPG_STBCR2_HIZ_SHIFT            (7u)
00260 
00261 #define CPG_STBREQ1_STBRQ10_SHIFT       (0u)
00262 #define CPG_STBREQ1_STBRQ12_SHIFT       (2u)
00263 #define CPG_STBREQ1_STBRQ13_SHIFT       (3u)
00264 #define CPG_STBREQ1_STBRQ15_SHIFT       (5u)
00265 
00266 #define CPG_STBREQ2_STBRQ20_SHIFT       (0u)
00267 #define CPG_STBREQ2_STBRQ21_SHIFT       (1u)
00268 #define CPG_STBREQ2_STBRQ22_SHIFT       (2u)
00269 #define CPG_STBREQ2_STBRQ23_SHIFT       (3u)
00270 #define CPG_STBREQ2_STBRQ24_SHIFT       (4u)
00271 #define CPG_STBREQ2_STBRQ25_SHIFT       (5u)
00272 #define CPG_STBREQ2_STBRQ26_SHIFT       (6u)
00273 #define CPG_STBREQ2_STBRQ27_SHIFT       (7u)
00274 
00275 #define CPG_STBACK1_STBAK10_SHIFT       (0u)
00276 #define CPG_STBACK1_STBAK12_SHIFT       (2u)
00277 #define CPG_STBACK1_STBAK13_SHIFT       (3u)
00278 #define CPG_STBACK1_STBAK15_SHIFT       (5u)
00279 
00280 #define CPG_STBACK2_STBAK20_SHIFT       (0u)
00281 #define CPG_STBACK2_STBAK21_SHIFT       (1u)
00282 #define CPG_STBACK2_STBAK22_SHIFT       (2u)
00283 #define CPG_STBACK2_STBAK23_SHIFT       (3u)
00284 #define CPG_STBACK2_STBAK24_SHIFT       (4u)
00285 #define CPG_STBACK2_STBAK25_SHIFT       (5u)
00286 #define CPG_STBACK2_STBAK26_SHIFT       (6u)
00287 #define CPG_STBACK2_STBAK27_SHIFT       (7u)
00288 
00289 #define CPG_SYSCR1_VRAME0_SHIFT         (0u)
00290 #define CPG_SYSCR1_VRAME1_SHIFT         (1u)
00291 #define CPG_SYSCR1_VRAME2_SHIFT         (2u)
00292 #define CPG_SYSCR1_VRAME3_SHIFT         (3u)
00293 #define CPG_SYSCR1_VRAME4_SHIFT         (4u)
00294 
00295 #define CPG_SYSCR2_VRAMWE0_SHIFT        (0u)
00296 #define CPG_SYSCR2_VRAMWE1_SHIFT        (1u)
00297 #define CPG_SYSCR2_VRAMWE2_SHIFT        (2u)
00298 #define CPG_SYSCR2_VRAMWE3_SHIFT        (3u)
00299 #define CPG_SYSCR2_VRAMWE4_SHIFT        (4u)
00300 
00301 #define CPG_SYSCR3_RRAMWE0_SHIFT        (0u)
00302 #define CPG_SYSCR3_RRAMWE1_SHIFT        (1u)
00303 #define CPG_SYSCR3_RRAMWE2_SHIFT        (2u)
00304 #define CPG_SYSCR3_RRAMWE3_SHIFT        (3u)
00305 
00306 #define CPG_STBCR3_MSTP30_SHIFT         (0u)
00307 #define CPG_STBCR3_MSTP31_SHIFT         (1u)
00308 #define CPG_STBCR3_MSTP32_SHIFT         (2u)
00309 #define CPG_STBCR3_MSTP33_SHIFT         (3u)
00310 #define CPG_STBCR3_MSTP34_SHIFT         (4u)
00311 #define CPG_STBCR3_MSTP35_SHIFT         (5u)
00312 #define CPG_STBCR3_MSTP36_SHIFT         (6u)
00313 #define CPG_STBCR3_MSTP37_SHIFT         (7u)
00314 
00315 #define CPG_STBCR4_MSTP40_SHIFT         (0u)
00316 #define CPG_STBCR4_MSTP41_SHIFT         (1u)
00317 #define CPG_STBCR4_MSTP42_SHIFT         (2u)
00318 #define CPG_STBCR4_MSTP43_SHIFT         (3u)
00319 #define CPG_STBCR4_MSTP44_SHIFT         (4u)
00320 #define CPG_STBCR4_MSTP45_SHIFT         (5u)
00321 #define CPG_STBCR4_MSTP46_SHIFT         (6u)
00322 #define CPG_STBCR4_MSTP47_SHIFT         (7u)
00323 
00324 #define CPG_STBCR5_MSTP50_SHIFT         (0u)
00325 #define CPG_STBCR5_MSTP51_SHIFT         (1u)
00326 #define CPG_STBCR5_MSTP52_SHIFT         (2u)
00327 #define CPG_STBCR5_MSTP53_SHIFT         (3u)
00328 #define CPG_STBCR5_MSTP54_SHIFT         (4u)
00329 #define CPG_STBCR5_MSTP55_SHIFT         (5u)
00330 #define CPG_STBCR5_MSTP56_SHIFT         (6u)
00331 #define CPG_STBCR5_MSTP57_SHIFT         (7u)
00332 
00333 #define CPG_STBCR6_MSTP60_SHIFT         (0u)
00334 #define CPG_STBCR6_MSTP61_SHIFT         (1u)
00335 #define CPG_STBCR6_MSTP62_SHIFT         (2u)
00336 #define CPG_STBCR6_MSTP63_SHIFT         (3u)
00337 #define CPG_STBCR6_MSTP64_SHIFT         (4u)
00338 #define CPG_STBCR6_MSTP65_SHIFT         (5u)
00339 #define CPG_STBCR6_MSTP66_SHIFT         (6u)
00340 #define CPG_STBCR6_MSTP67_SHIFT         (7u)
00341 
00342 #define CPG_STBCR7_MSTP70_SHIFT         (0u)
00343 #define CPG_STBCR7_MSTP71_SHIFT         (1u)
00344 #define CPG_STBCR7_MSTP73_SHIFT         (3u)
00345 #define CPG_STBCR7_MSTP74_SHIFT         (4u)
00346 #define CPG_STBCR7_MSTP76_SHIFT         (6u)
00347 #define CPG_STBCR7_MSTP77_SHIFT         (7u)
00348 
00349 #define CPG_STBCR8_MSTP81_SHIFT         (1u)
00350 #define CPG_STBCR8_MSTP82_SHIFT         (2u)
00351 #define CPG_STBCR8_MSTP83_SHIFT         (3u)
00352 #define CPG_STBCR8_MSTP84_SHIFT         (4u)
00353 #define CPG_STBCR8_MSTP85_SHIFT         (5u)
00354 #define CPG_STBCR8_MSTP86_SHIFT         (6u)
00355 #define CPG_STBCR8_MSTP87_SHIFT         (7u)
00356 
00357 #define CPG_STBCR9_MSTP90_SHIFT         (0u)
00358 #define CPG_STBCR9_MSTP91_SHIFT         (1u)
00359 #define CPG_STBCR9_MSTP92_SHIFT         (2u)
00360 #define CPG_STBCR9_MSTP93_SHIFT         (3u)
00361 #define CPG_STBCR9_MSTP94_SHIFT         (4u)
00362 #define CPG_STBCR9_MSTP95_SHIFT         (5u)
00363 #define CPG_STBCR9_MSTP96_SHIFT         (6u)
00364 #define CPG_STBCR9_MSTP97_SHIFT         (7u)
00365 
00366 #define CPG_STBCR10_MSTP100_SHIFT       (0u)
00367 #define CPG_STBCR10_MSTP101_SHIFT       (1u)
00368 #define CPG_STBCR10_MSTP102_SHIFT       (2u)
00369 #define CPG_STBCR10_MSTP103_SHIFT       (3u)
00370 #define CPG_STBCR10_MSTP104_SHIFT       (4u)
00371 #define CPG_STBCR10_MSTP105_SHIFT       (5u)
00372 #define CPG_STBCR10_MSTP106_SHIFT       (6u)
00373 #define CPG_STBCR10_MSTP107_SHIFT       (7u)
00374 
00375 #define CPG_STBCR11_MSTP110_SHIFT       (0u)
00376 #define CPG_STBCR11_MSTP111_SHIFT       (1u)
00377 #define CPG_STBCR11_MSTP112_SHIFT       (2u)
00378 #define CPG_STBCR11_MSTP113_SHIFT       (3u)
00379 #define CPG_STBCR11_MSTP114_SHIFT       (4u)
00380 #define CPG_STBCR11_MSTP115_SHIFT       (5u)
00381 
00382 #define CPG_STBCR12_MSTP120_SHIFT       (0u)
00383 #define CPG_STBCR12_MSTP121_SHIFT       (1u)
00384 #define CPG_STBCR12_MSTP122_SHIFT       (2u)
00385 #define CPG_STBCR12_MSTP123_SHIFT       (3u)
00386 
00387 #define CPG_STBCR13_MSTP131_SHIFT       (1u)
00388 #define CPG_STBCR13_MSTP132_SHIFT       (2u)
00389 
00390 #define CPG_SWRSTCR1_SRST11_SHIFT       (1u)
00391 #define CPG_SWRSTCR1_SRST12_SHIFT       (2u)
00392 #define CPG_SWRSTCR1_SRST13_SHIFT       (3u)
00393 #define CPG_SWRSTCR1_SRST14_SHIFT       (4u)
00394 #define CPG_SWRSTCR1_SRST15_SHIFT       (5u)
00395 #define CPG_SWRSTCR1_SRST16_SHIFT       (6u)
00396 #define CPG_SWRSTCR1_AXTALE_SHIFT       (7u)
00397 
00398 #define CPG_SWRSTCR2_SRST21_SHIFT       (1u)
00399 
00400 #define CPG_SWRSTCR3_SRST32_SHIFT       (2u)
00401 
00402 #define CPG_RRAMKP_RRAMKP0_SHIFT        (0u)
00403 #define CPG_RRAMKP_RRAMKP1_SHIFT        (1u)
00404 #define CPG_RRAMKP_RRAMKP2_SHIFT        (2u)
00405 #define CPG_RRAMKP_RRAMKP3_SHIFT        (3u)
00406 
00407 #define CPG_DSCTR_RAMBOOT_SHIFT         (6u)
00408 #define CPG_DSCTR_EBUSKEEPE_SHIFT       (7u)
00409 
00410 #define CPG_DSSSR_P8_2_SHIFT            (0u)
00411 #define CPG_DSSSR_P9_1_SHIFT            (1u)
00412 #define CPG_DSSSR_P2_15_SHIFT           (2u)
00413 #define CPG_DSSSR_P7_8_SHIFT            (3u)
00414 #define CPG_DSSSR_P5_9_SHIFT            (4u)
00415 #define CPG_DSSSR_P6_4_SHIFT            (5u)
00416 #define CPG_DSSSR_RTCAR_SHIFT           (6u)
00417 #define CPG_DSSSR_NMI_SHIFT             (8u)
00418 #define CPG_DSSSR_P3_3_SHIFT            (9u)
00419 #define CPG_DSSSR_P8_7_SHIFT            (10u)
00420 #define CPG_DSSSR_P2_12_SHIFT           (11u)
00421 #define CPG_DSSSR_P3_1_SHIFT            (12u)
00422 #define CPG_DSSSR_P3_9_SHIFT            (13u)
00423 #define CPG_DSSSR_P6_2_SHIFT            (14u)
00424 
00425 #define CPG_DSESR_P8_2E_SHIFT           (0u)
00426 #define CPG_DSESR_P9_1E_SHIFT           (1u)
00427 #define CPG_DSESR_P2_15E_SHIFT          (2u)
00428 #define CPG_DSESR_P7_8E_SHIFT           (3u)
00429 #define CPG_DSESR_P5_9E_SHIFT           (4u)
00430 #define CPG_DSESR_P6_4E_SHIFT           (5u)
00431 #define CPG_DSESR_NMIE_SHIFT            (8u)
00432 #define CPG_DSESR_P3_3E_SHIFT           (9u)
00433 #define CPG_DSESR_P8_7E_SHIFT           (10u)
00434 #define CPG_DSESR_P2_12E_SHIFT          (11u)
00435 #define CPG_DSESR_P3_1E_SHIFT           (12u)
00436 #define CPG_DSESR_P3_9E_SHIFT           (13u)
00437 #define CPG_DSESR_P6_2E_SHIFT           (14u)
00438 
00439 #define CPG_DSFR_P8_2F_SHIFT            (0u)
00440 #define CPG_DSFR_P9_1F_SHIFT            (1u)
00441 #define CPG_DSFR_P2_15F_SHIFT           (2u)
00442 #define CPG_DSFR_P7_8F_SHIFT            (3u)
00443 #define CPG_DSFR_P5_9F_SHIFT            (4u)
00444 #define CPG_DSFR_P6_4F_SHIFT            (5u)
00445 #define CPG_DSFR_RTCARF_SHIFT           (6u)
00446 #define CPG_DSFR_NMIF_SHIFT             (8u)
00447 #define CPG_DSFR_P3_3F_SHIFT            (9u)
00448 #define CPG_DSFR_P8_7F_SHIFT            (10u)
00449 #define CPG_DSFR_P2_12F_SHIFT           (11u)
00450 #define CPG_DSFR_P3_1F_SHIFT            (12u)
00451 #define CPG_DSFR_P3_9F_SHIFT            (13u)
00452 #define CPG_DSFR_P6_2F_SHIFT            (14u)
00453 #define CPG_DSFR_IOKEEP_SHIFT           (15u)
00454 
00455 #define CPG_XTALCTR_GAIN0_SHIFT         (0u)
00456 #define CPG_XTALCTR_GAIN1_SHIFT         (1u)
00457 
00458 
00459 #endif /* CPG_IOBITMASK_H */
00460 
00461 /* End of File */