clib_registers.h

00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
00006 * all applicable laws, including copyright laws.
00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
00022 *******************************************************************************/
00023 /**
00024 * @file  clib_registers.h
00025 * @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
00026 * $Rev: 30 $
00027 * $Date:: 2014-02-13 21:21:47 +0900#$
00028 * - Description: Common code for drivers and more.
00029 */
00030 
00031 #ifndef  CLIB_REGISTERS_H
00032 #define  CLIB_REGISTERS_H
00033 
00034 /******************************************************************************
00035 Includes   <System Includes> , "Project Includes"
00036 ******************************************************************************/
00037 #include  "r_typedefs.h"
00038 #include  "r_ospl.h"
00039 
00040 
00041 #ifdef __cplusplus
00042 extern "C" {
00043 #endif /* __cplusplus */
00044 
00045 
00046 /******************************************************************************
00047 Typedef definitions
00048 ******************************************************************************/
00049 
00050 /******************************************************************************
00051 Macro definitions
00052 ******************************************************************************/
00053 
00054 /******************************************************************************
00055 Variable Externs
00056 ******************************************************************************/
00057 
00058 /******************************************************************************
00059 Functions Prototypes
00060 ******************************************************************************/
00061 
00062 /******************************************************************************
00063 Inline Functions
00064 ******************************************************************************/
00065 
00066 
00067 /**
00068 * @brief   CPG unit of RZ/A1H.
00069 *
00070 * @par Parameters
00071 *    None
00072 * @return  Pointer to CPG structure.
00073 */
00074 INLINE struct st_cpg  *R_Get_CPG_Base(void) {
00075     /* ->QAC 0306 */
00076 #if IODEFINE_H_VERSION >= 100
00077     return  &CPG;
00078 #else
00079     return  (struct st_cpg *) &CPG;
00080 #endif
00081     /* <-QAC 0306 */
00082 }
00083 
00084 
00085 /***********************************************************************
00086 * Group: Register_Access
00087 ************************************************************************/
00088 
00089 /**
00090 * @brief   Set a value to register bit field.
00091 *
00092 * @param   in_out_Register Address of register or variable
00093 * @param   RegisterName Name of register
00094 * @param   BitName Name of bit
00095 * @param   Value Writing value
00096 * @return  None.
00097 *
00098 * @par Description
00099 *    Bit width is got from "RegisterName".
00100 */
00101 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00102 #define  R_DRV_SET_REGISTER_BIT_FIELD( \
00103         in_out_Register, RegisterName, BitName, Value ) \
00104     R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
00105         in_out_Register, RegisterName, BitName, Value, \
00106         DRV__BIT_WIDTH__##RegisterName )
00107 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00108 
00109 
00110 /**
00111 * @brief   Set a value to register bit field with width parameter.
00112 *
00113 * @param   in_out_Register Address of register or variable
00114 * @param   RegisterName Name of register
00115 * @param   BitName Name of bit
00116 * @param   Value Writing value
00117 * @param   BitWidth BitWidth
00118 * @return  None.
00119 */
00120 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00121 /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
00122 /* ->SEC M5.1.3 */
00123 #define  R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
00124         in_out_Register, RegisterName, BitName, Value, BitWidth ) \
00125     R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
00126         in_out_Register, RegisterName##__##BitName, Value, BitWidth )
00127 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
00128 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00129 
00130 /* Sub macro */
00131 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00132 /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
00133 /* ->SEC M5.1.3 */
00134 #define  R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
00135         in_out_Register, RegisterBitName, Value, BitWidth ) \
00136     R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
00137         in_out_Register, RegisterBitName, Value, BitWidth )
00138 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
00139 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00140 
00141 /* Sub macro */
00142 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00143 #define  R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
00144         in_out_Register, RegisterBitName, Value, BitWidth ) \
00145     R_OSPL_SET_TO_##BitWidth##_BIT_REGISTER( \
00146         (volatile uint##BitWidth##_t*)(in_out_Register), \
00147         DRV__MASK##BitWidth##__##RegisterBitName, \
00148         DRV__SHIFT__##RegisterBitName, \
00149         (uint##BitWidth##_t)(Value) )
00150 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00151 
00152 
00153 /**
00154 * @brief   Get a value from register bit field.
00155 *
00156 * @param   RegisterValue Value of register or variable
00157 * @param   RegisterName Name of register
00158 * @param   BitName Name of bit
00159 * @return  Value of shifted bit field.
00160 *
00161 * @par Description
00162 *    Bit width is got from "RegisterName".
00163 */
00164 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00165 #define  R_DRV_GET_REGISTER_BIT_FIELD( \
00166         RegisterValue, RegisterName, BitName ) \
00167     R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
00168         RegisterValue, RegisterName, BitName, \
00169         DRV__BIT_WIDTH__##RegisterName )
00170 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00171 
00172 
00173 /**
00174 * @brief   Get a value from register bit field with width parameter.
00175 *
00176 * @param   RegisterValue Value of register or variable
00177 * @param   RegisterName Name of register
00178 * @param   BitName Name of bit
00179 * @param   BitWidth BitWidth
00180 * @return  Value of shifted bit field.
00181 */
00182 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00183 /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
00184 /* ->SEC M5.1.3 */
00185 #define  R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
00186         RegisterValue, RegisterName, BitName, BitWidth ) \
00187     R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
00188         RegisterValue, RegisterName##__##BitName, BitWidth )
00189 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
00190 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00191 
00192 /* Sub macro */
00193 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00194 /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
00195 /* ->SEC M5.1.3 */
00196 #define  R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
00197         RegisterValue, RegisterBitName, BitWidth ) \
00198     R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
00199         RegisterValue, RegisterBitName, BitWidth )
00200 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
00201 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00202 
00203 /* Sub macro */
00204 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00205 #define  R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
00206         RegisterValue, RegisterBitName, BitWidth ) \
00207     R_OSPL_GET_FROM_##BitWidth##_BIT_REGISTER( \
00208         (volatile const uint##BitWidth##_t*) &(RegisterValue), \
00209         DRV__MASK##BitWidth##__##RegisterBitName, \
00210         DRV__SHIFT__##RegisterBitName )
00211 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00212 
00213 
00214 /**
00215 * @brief   Returns whether specified value is overflowed from the bit field.
00216 *
00217 * @param   RegisterName Name of register
00218 * @param   BitName Name of bit
00219 * @param   Value Checking value
00220 * @return  Whether specified value is overflowed.
00221 */
00222 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00223 #define  R_DRV_IS_OVERFLOW_BIT_FIELD( \
00224         RegisterName, BitName, Value ) \
00225     R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
00226         RegisterName, BitName, Value, DRV__BIT_WIDTH__##RegisterName )
00227 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00228 
00229 
00230 /**
00231 * @brief   Returns whether specified value is overflowed from the bit field.
00232 *
00233 * @param   RegisterName Name of register
00234 * @param   BitName Name of bit
00235 * @param   Value Checking value
00236 * @param   BitWidth BitWidth
00237 * @return  Whether specified value is overflowed.
00238 */
00239 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00240 /* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
00241 /* ->SEC M5.1.3 */
00242 #define  R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
00243         RegisterName, BitName, Value, BitWidth ) \
00244     R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
00245         RegisterName##__##BitName, Value, BitWidth )
00246 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
00247 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00248 
00249 /* Sub macro */
00250 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00251 /* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
00252 /* ->SEC M5.1.3 */
00253 #define  R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
00254         RegisterBitName, Value, BitWidth ) \
00255     R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
00256         RegisterBitName, Value, BitWidth )
00257 /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
00258 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00259 
00260 /* Sub macro */
00261 /* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
00262 #define  R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
00263         RegisterBitName, Value, BitWidth ) \
00264     R_DRV_IsOverflowBitField##BitWidth##_Sub( \
00265         DRV__MASK##BitWidth##__##RegisterBitName, \
00266         DRV__SHIFT__##RegisterBitName, \
00267         Value )
00268 /* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
00269 
00270 
00271 /* Sub function */
00272 /* : R_DRV_IsOverflowBitField32_Sub */
00273 /* : R_DRV_IsOverflowBitField16_Sub */
00274 /* : R_DRV_IsOverflowBitField8_Sub */
00275 INLINE bool_t  R_DRV_IsOverflowBitField32_Sub( uint32_t const  Mask,
00276         int_fast32_t const  Shift,  uint32_t const  Value )
00277 {
00278     return  ( ( (uint32_t)(Value) &
00279                 ~( (uint32_t)(Mask) >> (Shift) ) )
00280               != 0u );
00281 }
00282 
00283 INLINE bool_t  R_DRV_IsOverflowBitField16_Sub( uint16_t const  Mask,
00284         int_fast32_t const  Shift,  uint16_t const  Value )
00285 {
00286     return  ( ( (uint_fast16_t)(Value) &
00287                 ~( (uint_fast16_t)(Mask) >> (Shift) ) )
00288               != 0u );
00289 }
00290 
00291 INLINE bool_t  R_DRV_IsOverflowBitField8_Sub( uint8_t const  Mask,
00292         int_fast32_t const  Shift, uint8_t const  Value )
00293 {
00294     return  ( ( (uint_fast8_t)(Value) &
00295                 ~( (uint_fast8_t)(Mask) >> (Shift) ) )
00296               != 0u );
00297 }
00298 
00299 
00300 /**
00301 * @def  CPG
00302 * @brief  CPG
00303 */
00304 /* 0xFCFE0438 */
00305 
00306 #define  DRV__BIT_WIDTH__STBCR9  8
00307 
00308 enum { /*uint8_t */       DRV__MASK8__STBCR9__MSTP91 = 0x02 };  /* VDC5-0, LVDS */
00309 enum { /*uint8_t */       DRV__MASK8__STBCR9__MSTP90 = 0x01 };  /* VDC5-1 */
00310 
00311 enum { /* int_fast32_t */  DRV__SHIFT__STBCR9__MSTP91 =  1 };
00312 enum { /* int_fast32_t */  DRV__SHIFT__STBCR9__MSTP90 =  0 };
00313 
00314 #ifdef __cplusplus
00315 }  /* extern "C" */
00316 #endif /* __cplusplus */
00317 
00318 #endif  /* CLIB_REGISTERS_H */
00319 
00320 
00321