Graphics framework for GR-PEACH. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Dependents:   ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample GR-PEACH_LCD_4_3inch_Save_to_USB ... more

License

When you use this library, we judge you have agreed to the following contents.

https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Note

If you import the GraphicsFramework library, please import GR-PEACH_video library and R_BSP library together.



JPEG Converter

The JPEG Converter driver implements encode and decode functionality which uses the JCU of the RZ/A Series.

Hello World!

Import programJCU_HelloWorld

Hello World for JCU(JPEG Codec Unit). JCU is JPEG codec unit of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

API

Import library

Data Structures

struct bitmap_buff_info_t
Bitmap data setting struct. More...
struct encode_options_t
Encode option setting. More...

Public Types

enum jpeg_conv_error_t {
JPEG_CONV_OK = 0, JPEG_CONV_JCU_ERR = -1, JPEG_CONV_FORMA_ERR = -2, JPEG_CONV_PARAM_ERR = -3,
JPEG_CONV_BUSY = -4, JPEG_CONV_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT = 1, WR_RD_WRSWA_16BIT = 2, WR_RD_WRSWA_16_8BIT = 3,
WR_RD_WRSWA_32BIT = 4, WR_RD_WRSWA_32_8BIT = 5, WR_RD_WRSWA_32_16BIT = 6, WR_RD_WRSWA_32_16_8BIT = 7
}

Write/Read image pixcel frame buffer swap setting.

More...
enum wr_rd_format_t { WR_RD_YCbCr422 = 0x00, WR_RD_ARGB8888 = 0x01, WR_RD_RGB565 = 0x02 }

Write/Read image pixcel format selects.

More...
enum sub_sampling_t { SUB_SAMPLING_1_1 = 0x00, SUB_SAMPLING_1_2 = 0x01, SUB_SAMPLING_1_4 = 0x02, SUB_SAMPLING_1_8 = 0x03 }

Thinning output image selects.

More...
enum cbcr_offset_t { CBCR_OFFSET_0 = 0x00, CBCR_OFFSET_128 = 0x01 }

Cb/Cr range selects for decode.

More...

Public Member Functions

JPEG_Converter ()
Constructor method of JPEG converter(encode/decode)
virtual ~JPEG_Converter ()
Destructor method of JPEG converter(encode/decode)
JPEG_Converter::jpeg_conv_error_t decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff)
Decode JPEG to rinear data.
JPEG_Converter::jpeg_conv_error_t decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff, decode_options_t *pOptions)
JPEG data decode to bitmap.
JPEG_Converter::jpeg_conv_error_t encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize)
Encode rinear data to JPEG.
JPEG_Converter::jpeg_conv_error_t encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize, encode_options_t *pOptions)
Bitmap data encode to JPEG.
JPEG_Converter::jpeg_conv_error_t SetQuality (const uint8_t qual)
Set encode quality.

Correspondence file

A correspondence file of JPEG Converter is as the following table.

JPEGCorrespondence
Width>0(greater than 0)
Height>0(greater than 0)
Color formatYCbCr444, YCbCr422, YCbCr420, YCbCr411
BitmapCorrespondence
Width>0(greater than 0)
Height>0(greater than 0)
Color formatYCbCr422

Notice

You run JPEG converter once destruction each time.

You set whether these JPEG files aren't input, or it check error setting decode(set in "flag" = true). The JPEG file which becomes correspondence outside will be the following condition.

  • File besides the above-mentioned correspondence file.
  • As information in the JPEG file, WIDTH or HEIGHT is larger than output buffer setting.

Buffer area is used encode/decode, set 8 bytes align and non-cash memory area. The output buffer when decoding, is made beyond the size decided in the size of the JPEG file, the format, setting of thinning out. You make output buffer for decode/encode to enough big size in order to stock this result. JPEG Converter, if you do not particularly perform specified, does not check size against the output data at the time of encoding and decoding. You set the output buffer so that there is no effect of corruption by the output data.

Color format

Color format in case to be converted from Bitmap to JPEG is either ARGB8888 or RGB555, YCbCr422. Color format of the If you want to convert from JPEG file to Bitmap file is YCbCr422. You correct "alpha(member of decode_options_t)" of setting and "output_cb_cr_offset(member of decode_options_t)" according to color format when decoding.

  • example
    decode to ARGB8888(WR_RD_ARGB8888 set in format member of bitmap_buff_info_t)
    alpha = 0x01-0xFF
    output_cb_cr_offset = CBCR_OFFSET_0

    decode to YCbCr422(WR_RD_YCbCr422 set in format member of bitmap_buff_info_t)
    alpha = 0
    output_cb_cr_offset = CBCR_OFFSET_0 or CBCR_OFFSET_128

    decode to RGB565(WR_RD_RGB565 set in format member of bitmap_buff_info_t)
    alpha = 0
    output_cb_cr_offset = CBCR_OFFSET_0

Decode/encode settings are optional

If omitted encode/decode settings, it will work with the following settings.
[Decode option setting (member of decode_options_t)]

  • Vertical sub sampling is thinning output image to 1/1.
  • Horizontal sub sampling is thinning output image to 1/1.
  • Output data of Cb/Cr range is -128 to 127.
  • Output data of swap in 8-bit units: 2-1-4-3-6-5-8-7.
  • Alpha value of 0.
  • JPEG format correspondence outside error check.
  • It decode in a synchronous function.

[Encode option setting (member of encode_options_t)]

  • DRI value is 0.
  • Encoding JPEG file start width offset is 0.
  • Encoding JPEG file start height offset is 0.
  • Input data of Cb/Cr range of input data is -128 to 127.
  • Input data swap in 8-bit units: 2-1-4-3-6-5-8-7.
  • It don't check encode size.
  • Quantization Y use default table(Quality75).
  • Quantization C use default table(Quality75).
  • Huffman Y DC use default table.
  • Huffman C DC use default table.
  • Huffman Y AC use default table.
  • Huffman C AC use default table.
  • It encode in a synchronous function.

Synchronous/asynchronous switching

Decoding and encoding setting to operate asynchronously by setting a callback function(decode_options_t and encode_options_t).

Quality

Quality changes are possible. If you want to change the Quality, please specify the table made of Quality you want to change the address of the setting. If you do not want to change the Quality, it will operate at Quality75.

RGA

The RGA library implements fast drawing functionality which uses the RGA of the RZ/A Series.
Supporting compiler is ARMCC, GCC ARM and IAR.

Hello World!

Import programRGA_HelloWorld

Hello World for RGA(Renesas Graphics Architecture). RGA is the Graphics Library of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Committer:
1050186
Date:
Wed Jan 20 02:35:17 2016 +0000
Revision:
3:9f857750e4e9
Parent:
0:37e1e6a45ced
Child:
8:c4526298e222
Add RGA library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:37e1e6a45ced 1 /*******************************************************************************
dkato 0:37e1e6a45ced 2 * DISCLAIMER
dkato 0:37e1e6a45ced 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:37e1e6a45ced 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:37e1e6a45ced 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:37e1e6a45ced 6 * all applicable laws, including copyright laws.
dkato 0:37e1e6a45ced 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:37e1e6a45ced 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:37e1e6a45ced 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:37e1e6a45ced 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:37e1e6a45ced 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:37e1e6a45ced 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:37e1e6a45ced 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:37e1e6a45ced 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:37e1e6a45ced 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:37e1e6a45ced 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:37e1e6a45ced 17 * and to discontinue the availability of this software. By using this software,
dkato 0:37e1e6a45ced 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:37e1e6a45ced 19 * following link:
dkato 0:37e1e6a45ced 20 * http://www.renesas.com/disclaimer
dkato 0:37e1e6a45ced 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:37e1e6a45ced 22 *******************************************************************************/
dkato 0:37e1e6a45ced 23 /**
dkato 0:37e1e6a45ced 24 * @file r_ospl_memory.c
dkato 0:37e1e6a45ced 25 * @brief Memory map
dkato 0:37e1e6a45ced 26 *
dkato 0:37e1e6a45ced 27 * $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
dkato 0:37e1e6a45ced 28 * $Rev: $
dkato 0:37e1e6a45ced 29 * $Date:: $
dkato 0:37e1e6a45ced 30 */
dkato 0:37e1e6a45ced 31
dkato 0:37e1e6a45ced 32
dkato 0:37e1e6a45ced 33 /******************************************************************************
dkato 0:37e1e6a45ced 34 Includes <System Includes> , "Project Includes"
dkato 0:37e1e6a45ced 35 ******************************************************************************/
dkato 0:37e1e6a45ced 36 #include "r_ospl.h"
dkato 0:37e1e6a45ced 37 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 38 #include "r_ospl_test.h"
dkato 0:37e1e6a45ced 39 #endif
dkato 0:37e1e6a45ced 40 #include "r_ospl_private.h"
dkato 0:37e1e6a45ced 41
dkato 0:37e1e6a45ced 42 /******************************************************************************
dkato 0:37e1e6a45ced 43 Typedef definitions
dkato 0:37e1e6a45ced 44 ******************************************************************************/
dkato 0:37e1e6a45ced 45
dkato 0:37e1e6a45ced 46 /**
dkato 0:37e1e6a45ced 47 * @struct gs_address_table_line_t
dkato 0:37e1e6a45ced 48 * @brief gs_address_table_line_t
dkato 0:37e1e6a45ced 49 */
dkato 0:37e1e6a45ced 50 typedef struct st_gs_address_table_line_t gs_address_table_line_t;
dkato 0:37e1e6a45ced 51 struct st_gs_address_table_line_t {
dkato 0:37e1e6a45ced 52
dkato 0:37e1e6a45ced 53 /** Address */
dkato 0:37e1e6a45ced 54 uintptr_t Address;
dkato 0:37e1e6a45ced 55
dkato 0:37e1e6a45ced 56 /** Value */
dkato 0:37e1e6a45ced 57 int_fast32_t Value;
dkato 0:37e1e6a45ced 58 };
dkato 0:37e1e6a45ced 59
dkato 0:37e1e6a45ced 60
dkato 0:37e1e6a45ced 61 /**
dkato 0:37e1e6a45ced 62 * @struct gs_address_table_line_c_t
dkato 0:37e1e6a45ced 63 * @brief gs_address_table_line_c_t
dkato 0:37e1e6a45ced 64 */
dkato 0:37e1e6a45ced 65 typedef struct st_gs_address_table_line_c_t gs_address_table_line_c_t;
dkato 0:37e1e6a45ced 66 struct st_gs_address_table_line_c_t {
dkato 0:37e1e6a45ced 67
dkato 0:37e1e6a45ced 68 /** Address */
dkato 0:37e1e6a45ced 69 uintptr_t Address;
dkato 0:37e1e6a45ced 70
dkato 0:37e1e6a45ced 71 /** Value */
dkato 0:37e1e6a45ced 72 r_ospl_axi_cache_attribute_t Value;
dkato 0:37e1e6a45ced 73 };
dkato 0:37e1e6a45ced 74
dkato 0:37e1e6a45ced 75
dkato 0:37e1e6a45ced 76 /******************************************************************************
dkato 0:37e1e6a45ced 77 Macro definitions
dkato 0:37e1e6a45ced 78 ******************************************************************************/
dkato 0:37e1e6a45ced 79
dkato 0:37e1e6a45ced 80 /* ->MISRA 17.4 : These are addresses */
dkato 0:37e1e6a45ced 81
dkato 0:37e1e6a45ced 82 #define GS_MIRROR_SIZE 0x40000000u
dkato 0:37e1e6a45ced 83 #define GS_CACHED_START 0x00000000u
dkato 0:37e1e6a45ced 84 #define GS_CACHED_END ( GS_CACHED_START + GS_MIRROR_SIZE )
dkato 0:37e1e6a45ced 85 #define GS_UNCACHED_START 0x40000000u
dkato 0:37e1e6a45ced 86 #define GS_UNCACHED_END ( GS_UNCACHED_START + GS_MIRROR_SIZE )
dkato 0:37e1e6a45ced 87
dkato 0:37e1e6a45ced 88 #define GS_IO_START 0x60A00000u
dkato 0:37e1e6a45ced 89
dkato 0:37e1e6a45ced 90 /* From "scatter.scat" file */
dkato 0:37e1e6a45ced 91 #if defined( RZ_A1L )
dkato 0:37e1e6a45ced 92 #define LRAM_SIZE 0x00300000u
dkato 0:37e1e6a45ced 93 #else /* RZ/A1H */
dkato 0:37e1e6a45ced 94 #define LRAM_SIZE 0x00A00000u
dkato 0:37e1e6a45ced 95 #endif
dkato 0:37e1e6a45ced 96 #define LRAM_START 0x20000000u
dkato 0:37e1e6a45ced 97 #define LRAM_END ( LRAM_START + LRAM_SIZE )
dkato 0:37e1e6a45ced 98 #define UNUSED_UNCACHED_LRAM_START 0x60000000u
dkato 0:37e1e6a45ced 99 #define UNCACHED_LRAM_END ( UNUSED_UNCACHED_LRAM_START + LRAM_SIZE )
dkato 0:37e1e6a45ced 100
dkato 0:37e1e6a45ced 101 /* <-MISRA 17.4 */
dkato 0:37e1e6a45ced 102
dkato 0:37e1e6a45ced 103 #define GS_EXTERNAL_START_0x00000000 0x00000000u
dkato 0:37e1e6a45ced 104 #define GS_EXTERNAL_SDRAM_START_0x08000000 0x08000000u
dkato 0:37e1e6a45ced 105 #define GS_INTERNAL_RAM_START_0x20000000 0x20000000u
dkato 0:37e1e6a45ced 106 #define GS_INTERNAL_REGISTERS_START_0x80000000 0x80000000u
dkato 0:37e1e6a45ced 107
dkato 0:37e1e6a45ced 108 #if defined( RZ_A1L_EV_BOARD )
dkato 0:37e1e6a45ced 109 #define GS_SDRAM_SIZE 0x04000000u
dkato 0:37e1e6a45ced 110 #else
dkato 0:37e1e6a45ced 111 #define GS_SDRAM_SIZE 0x08000000u
dkato 0:37e1e6a45ced 112 #endif
dkato 0:37e1e6a45ced 113
dkato 0:37e1e6a45ced 114
dkato 0:37e1e6a45ced 115 /******************************************************************************
dkato 0:37e1e6a45ced 116 Imported global variables and functions (from other files)
dkato 0:37e1e6a45ced 117 ******************************************************************************/
dkato 0:37e1e6a45ced 118
dkato 0:37e1e6a45ced 119 /******************************************************************************
dkato 0:37e1e6a45ced 120 Exported global variables and functions (to be accessed by other files)
dkato 0:37e1e6a45ced 121 ******************************************************************************/
dkato 0:37e1e6a45ced 122
dkato 0:37e1e6a45ced 123 /******************************************************************************
dkato 0:37e1e6a45ced 124 Private global variables and functions
dkato 0:37e1e6a45ced 125 ******************************************************************************/
dkato 0:37e1e6a45ced 126 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 127 static r_ospl_axi_envronment_t gs_Environment;
dkato 0:37e1e6a45ced 128 #endif
dkato 0:37e1e6a45ced 129
dkato 0:37e1e6a45ced 130
dkato 0:37e1e6a45ced 131 /******************************************************************************
dkato 0:37e1e6a45ced 132 * Implement: R_OSPL_ToPhysicalAddress
dkato 0:37e1e6a45ced 133 ******************************************************************************/
dkato 0:37e1e6a45ced 134 errnum_t R_OSPL_ToPhysicalAddress( const volatile void *in_Address, uintptr_t *out_PhysicalAddress )
dkato 0:37e1e6a45ced 135 {
dkato 0:37e1e6a45ced 136 errnum_t e;
dkato 0:37e1e6a45ced 137 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
dkato 0:37e1e6a45ced 138 uintptr_t const address = (uintptr_t) in_Address;
dkato 0:37e1e6a45ced 139 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
dkato 0:37e1e6a45ced 140
dkato 0:37e1e6a45ced 141 IF_DQ( out_PhysicalAddress == NULL ) {
dkato 0:37e1e6a45ced 142 e=E_OTHERS;
dkato 0:37e1e6a45ced 143 goto fin;
dkato 0:37e1e6a45ced 144 }
dkato 0:37e1e6a45ced 145
dkato 0:37e1e6a45ced 146 *out_PhysicalAddress = address;
dkato 0:37e1e6a45ced 147
dkato 0:37e1e6a45ced 148 e=0;
dkato 0:37e1e6a45ced 149 fin:
dkato 0:37e1e6a45ced 150 return e;
dkato 0:37e1e6a45ced 151 }
dkato 0:37e1e6a45ced 152
dkato 0:37e1e6a45ced 153
dkato 0:37e1e6a45ced 154 /******************************************************************************
dkato 0:37e1e6a45ced 155 * Implement: R_OSPL_ToCachedAddress
dkato 0:37e1e6a45ced 156 ******************************************************************************/
dkato 0:37e1e6a45ced 157 errnum_t R_OSPL_ToCachedAddress( const volatile void *in_Address, void *out_CachedAddress )
dkato 0:37e1e6a45ced 158 {
dkato 0:37e1e6a45ced 159 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
dkato 0:37e1e6a45ced 160 /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base */
dkato 0:37e1e6a45ced 161 errnum_t e;
dkato 0:37e1e6a45ced 162 #if IS_MBED_USED
dkato 0:37e1e6a45ced 163 uintptr_t address = (uintptr_t) in_Address;
dkato 0:37e1e6a45ced 164 const uintptr_t uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
dkato 0:37e1e6a45ced 165 #else
dkato 0:37e1e6a45ced 166 uintptr_t const address = (uintptr_t) in_Address;
dkato 0:37e1e6a45ced 167 #endif
dkato 0:37e1e6a45ced 168
dkato 0:37e1e6a45ced 169 IF_DQ( out_CachedAddress == NULL ) {
dkato 0:37e1e6a45ced 170 e=E_OTHERS;
dkato 0:37e1e6a45ced 171 goto fin;
dkato 0:37e1e6a45ced 172 }
dkato 0:37e1e6a45ced 173
dkato 0:37e1e6a45ced 174 #if IS_MBED_USED
dkato 0:37e1e6a45ced 175 IF ( address < LRAM_START ) {
dkato 0:37e1e6a45ced 176 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 177 }
dkato 0:37e1e6a45ced 178 else if ( address < LRAM_END ) {
dkato 0:37e1e6a45ced 179 e = 0;
1050186 3:9f857750e4e9 180 } else IF ( address < UNUSED_UNCACHED_LRAM_START ) {
dkato 0:37e1e6a45ced 181 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 182 }
dkato 0:37e1e6a45ced 183 else if ( address < UNCACHED_LRAM_END ) {
dkato 0:37e1e6a45ced 184 address -= uncached_from_cached;
dkato 0:37e1e6a45ced 185 e = 0;
dkato 0:37e1e6a45ced 186 } else {
dkato 0:37e1e6a45ced 187 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 188 }
dkato 0:37e1e6a45ced 189 #else
dkato 0:37e1e6a45ced 190 IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base) &&
dkato 0:37e1e6a45ced 191 (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
dkato 0:37e1e6a45ced 192 /* "BEGIN_OF_NOCACHE_RAM_BARRIER" is defined in "scatter.sct" file. */
dkato 0:37e1e6a45ced 193 /* Image$$ execution region symbols */
dkato 0:37e1e6a45ced 194 /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0377d/CHDFHJDJ.html */
dkato 0:37e1e6a45ced 195
dkato 0:37e1e6a45ced 196 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 197 }
dkato 0:37e1e6a45ced 198 else IF ( address >= UNUSED_UNCACHED_LRAM_START ) {
dkato 0:37e1e6a45ced 199 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 200 }
dkato 0:37e1e6a45ced 201 else {
dkato 0:37e1e6a45ced 202 e = 0;
dkato 0:37e1e6a45ced 203 }
dkato 0:37e1e6a45ced 204 #endif
dkato 0:37e1e6a45ced 205
dkato 0:37e1e6a45ced 206 *(void **) out_CachedAddress = (void *) address;
dkato 0:37e1e6a45ced 207
dkato 0:37e1e6a45ced 208 fin:
dkato 0:37e1e6a45ced 209 return e;
dkato 0:37e1e6a45ced 210 /* <-QAC 0289 *//* <-QAC 1002 */
dkato 0:37e1e6a45ced 211 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
dkato 0:37e1e6a45ced 212 }
dkato 0:37e1e6a45ced 213
dkato 0:37e1e6a45ced 214
dkato 0:37e1e6a45ced 215 /******************************************************************************
dkato 0:37e1e6a45ced 216 * Implement: R_OSPL_ToUncachedAddress
dkato 0:37e1e6a45ced 217 ******************************************************************************/
dkato 0:37e1e6a45ced 218 errnum_t R_OSPL_ToUncachedAddress( const volatile void *in_Address, void *out_UncachedAddress )
dkato 0:37e1e6a45ced 219 {
dkato 0:37e1e6a45ced 220 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
dkato 0:37e1e6a45ced 221 /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base */
dkato 0:37e1e6a45ced 222 errnum_t e;
dkato 0:37e1e6a45ced 223 #if IS_MBED_USED
dkato 0:37e1e6a45ced 224 uintptr_t address = (uintptr_t) in_Address;
1050186 3:9f857750e4e9 225 uintptr_t nc_base = UNUSED_UNCACHED_LRAM_START;
dkato 0:37e1e6a45ced 226 const uintptr_t uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
dkato 0:37e1e6a45ced 227 #else
dkato 0:37e1e6a45ced 228 uintptr_t const address = (uintptr_t) in_Address;
dkato 0:37e1e6a45ced 229 #endif
dkato 0:37e1e6a45ced 230
dkato 0:37e1e6a45ced 231 IF_DQ( out_UncachedAddress == NULL ) {
dkato 0:37e1e6a45ced 232 e=E_OTHERS;
dkato 0:37e1e6a45ced 233 goto fin;
dkato 0:37e1e6a45ced 234 }
dkato 0:37e1e6a45ced 235
dkato 0:37e1e6a45ced 236 #if IS_MBED_USED
dkato 0:37e1e6a45ced 237 IF ( address < nc_base - uncached_from_cached ) {
dkato 0:37e1e6a45ced 238 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 239 }
dkato 0:37e1e6a45ced 240 else if ( address < LRAM_END ) {
dkato 0:37e1e6a45ced 241 address += uncached_from_cached;
dkato 0:37e1e6a45ced 242 e = 0;
dkato 0:37e1e6a45ced 243 } else IF ( address < nc_base ) {
dkato 0:37e1e6a45ced 244 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 245 }
dkato 0:37e1e6a45ced 246 else if ( address < UNCACHED_LRAM_END ) {
dkato 0:37e1e6a45ced 247 e = 0;
dkato 0:37e1e6a45ced 248 } else {
dkato 0:37e1e6a45ced 249 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 250 }
dkato 0:37e1e6a45ced 251 #else
dkato 0:37e1e6a45ced 252 IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base) &&
dkato 0:37e1e6a45ced 253 (address < (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$ZI$$Limit) ) {
dkato 0:37e1e6a45ced 254 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 255 }
dkato 0:37e1e6a45ced 256 else if ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base) &&
dkato 0:37e1e6a45ced 257 (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
dkato 0:37e1e6a45ced 258 e = 0;
dkato 0:37e1e6a45ced 259 } else IF ( R_CUT_IF_ALWAYS_TRUE( (address >= GS_CACHED_START) &&) (address < GS_CACHED_END) ) {
dkato 0:37e1e6a45ced 260 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 261 }
dkato 0:37e1e6a45ced 262 else IF ( (address >= UNUSED_UNCACHED_LRAM_START) && (address < GS_IO_START) ) {
dkato 0:37e1e6a45ced 263 e = E_ACCESS_DENIED;
dkato 0:37e1e6a45ced 264 }
dkato 0:37e1e6a45ced 265 else {
dkato 0:37e1e6a45ced 266 e = 0;
dkato 0:37e1e6a45ced 267 }
dkato 0:37e1e6a45ced 268 #endif
dkato 0:37e1e6a45ced 269
dkato 0:37e1e6a45ced 270 *(void **) out_UncachedAddress = (void *) address;
dkato 0:37e1e6a45ced 271
dkato 0:37e1e6a45ced 272 fin:
dkato 0:37e1e6a45ced 273 return e;
dkato 0:37e1e6a45ced 274 /* <-QAC 0289 *//* <-QAC 1002 */
dkato 0:37e1e6a45ced 275 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
dkato 0:37e1e6a45ced 276 }
dkato 0:37e1e6a45ced 277
dkato 0:37e1e6a45ced 278
dkato 0:37e1e6a45ced 279 /******************************************************************************
dkato 0:37e1e6a45ced 280 * Implement: R_OSPL_MEMORY_GetLevelOfFlush
dkato 0:37e1e6a45ced 281 ******************************************************************************/
dkato 0:37e1e6a45ced 282 errnum_t R_OSPL_MEMORY_GetLevelOfFlush( const void *in_Address, int_fast32_t *out_Level )
dkato 0:37e1e6a45ced 283 {
dkato 0:37e1e6a45ced 284 uintptr_t address = (uintptr_t) in_Address;
dkato 0:37e1e6a45ced 285
dkato 0:37e1e6a45ced 286 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 287 if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
dkato 0:37e1e6a45ced 288 #endif
dkato 0:37e1e6a45ced 289 static const gs_address_table_line_t table[] = {
dkato 0:37e1e6a45ced 290 /* .Address .Value */
dkato 0:37e1e6a45ced 291 { GS_EXTERNAL_START_0x00000000, 0 },
dkato 0:37e1e6a45ced 292 { GS_EXTERNAL_SDRAM_START_0x08000000, 1 },
dkato 0:37e1e6a45ced 293 { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE, 0 },
dkato 0:37e1e6a45ced 294 { GS_INTERNAL_RAM_START_0x20000000, 1 },
dkato 0:37e1e6a45ced 295 { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE, 0 }
dkato 0:37e1e6a45ced 296 };
dkato 0:37e1e6a45ced 297
dkato 0:37e1e6a45ced 298
dkato 0:37e1e6a45ced 299 if ( address < table[1].Address ) {
dkato 0:37e1e6a45ced 300 *out_Level = table[0].Value;
dkato 0:37e1e6a45ced 301 } else if ( address < table[2].Address ) {
dkato 0:37e1e6a45ced 302 *out_Level = table[1].Value;
dkato 0:37e1e6a45ced 303 } else if ( address < table[3].Address ) {
dkato 0:37e1e6a45ced 304 *out_Level = table[2].Value;
dkato 0:37e1e6a45ced 305 } else if ( address < table[4].Address ) {
dkato 0:37e1e6a45ced 306 *out_Level = table[3].Value;
dkato 0:37e1e6a45ced 307 } else {
dkato 0:37e1e6a45ced 308 *out_Level = table[4].Value;
dkato 0:37e1e6a45ced 309 }
dkato 0:37e1e6a45ced 310 R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
dkato 0:37e1e6a45ced 311
dkato 0:37e1e6a45ced 312 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 313 } else {
dkato 0:37e1e6a45ced 314 static const gs_address_table_line_t table[] = {
dkato 0:37e1e6a45ced 315 /* .Address .Value */
dkato 0:37e1e6a45ced 316 { GS_EXTERNAL_START_0x00000000, 0 },
dkato 0:37e1e6a45ced 317 { GS_EXTERNAL_SDRAM_START_0x08000000, 2 },
dkato 0:37e1e6a45ced 318 { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE, 0 },
dkato 0:37e1e6a45ced 319 { GS_INTERNAL_RAM_START_0x20000000, 1 },
dkato 0:37e1e6a45ced 320 { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE, 0 },
dkato 0:37e1e6a45ced 321 /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000, 2 }, */
dkato 0:37e1e6a45ced 322 /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000 + GS_SDRAM_SIZE, 0 }, */
dkato 0:37e1e6a45ced 323 /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000, 0 }, */
dkato 0:37e1e6a45ced 324 /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000 + LRAM_SIZE, 0 } */
dkato 0:37e1e6a45ced 325 };
dkato 0:37e1e6a45ced 326
dkato 0:37e1e6a45ced 327
dkato 0:37e1e6a45ced 328 ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
dkato 0:37e1e6a45ced 329
dkato 0:37e1e6a45ced 330 if ( address < table[1].Address ) {
dkato 0:37e1e6a45ced 331 *out_Level = table[0].Value;
dkato 0:37e1e6a45ced 332 } else if ( address < table[2].Address ) {
dkato 0:37e1e6a45ced 333 *out_Level = table[1].Value;
dkato 0:37e1e6a45ced 334 } else if ( address < table[3].Address ) {
dkato 0:37e1e6a45ced 335 *out_Level = table[2].Value;
dkato 0:37e1e6a45ced 336 } else if ( address < table[4].Address ) {
dkato 0:37e1e6a45ced 337 *out_Level = table[3].Value;
dkato 0:37e1e6a45ced 338 } else {
dkato 0:37e1e6a45ced 339 *out_Level = table[4].Value;
dkato 0:37e1e6a45ced 340 }
dkato 0:37e1e6a45ced 341 R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
dkato 0:37e1e6a45ced 342 }
dkato 0:37e1e6a45ced 343 #endif
dkato 0:37e1e6a45ced 344 return 0;
dkato 0:37e1e6a45ced 345 }
dkato 0:37e1e6a45ced 346
dkato 0:37e1e6a45ced 347
dkato 0:37e1e6a45ced 348 /******************************************************************************
dkato 0:37e1e6a45ced 349 * Implement: R_OSPL_AXI_Get2ndCacheAttribute
dkato 0:37e1e6a45ced 350 ******************************************************************************/
dkato 0:37e1e6a45ced 351 errnum_t R_OSPL_AXI_Get2ndCacheAttribute( uintptr_t const in_PhysicalAddress,
dkato 0:37e1e6a45ced 352 r_ospl_axi_cache_attribute_t *const out_CacheAttribute )
dkato 0:37e1e6a45ced 353 {
dkato 0:37e1e6a45ced 354 uintptr_t address = in_PhysicalAddress;
dkato 0:37e1e6a45ced 355
dkato 0:37e1e6a45ced 356 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 357 if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
dkato 0:37e1e6a45ced 358 #endif
dkato 0:37e1e6a45ced 359 static const gs_address_table_line_c_t table[] = {
dkato 0:37e1e6a45ced 360 /* .Address .Value */
dkato 0:37e1e6a45ced 361 { GS_EXTERNAL_START_0x00000000, R_OSPL_AXI_WRITE_BACK_W },
dkato 0:37e1e6a45ced 362 /*{ GS_EXTERNAL_SDRAM_START_0x08000000, R_OSPL_AXI_WRITE_BACK_W },*/
dkato 0:37e1e6a45ced 363 { GS_INTERNAL_RAM_START_0x20000000, R_OSPL_AXI_CACHE_ZERO },
dkato 0:37e1e6a45ced 364 /*{ GS_INTERNAL_REGISTERS_START_0x80000000, R_OSPL_AXI_CACHE_ZERO }*/
dkato 0:37e1e6a45ced 365 /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
dkato 0:37e1e6a45ced 366 };
dkato 0:37e1e6a45ced 367
dkato 0:37e1e6a45ced 368
dkato 0:37e1e6a45ced 369 if ( address < table[1].Address ) {
dkato 0:37e1e6a45ced 370 *out_CacheAttribute = table[0].Value;
dkato 0:37e1e6a45ced 371 } else {
dkato 0:37e1e6a45ced 372 *out_CacheAttribute = table[1].Value;
dkato 0:37e1e6a45ced 373 }
dkato 0:37e1e6a45ced 374 R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
dkato 0:37e1e6a45ced 375
dkato 0:37e1e6a45ced 376 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 377 } else {
dkato 0:37e1e6a45ced 378 static const gs_address_table_line_c_t table[] = {
dkato 0:37e1e6a45ced 379 /* .Address .Value */
dkato 0:37e1e6a45ced 380 { GS_EXTERNAL_START_0x00000000, R_OSPL_AXI_STRONGLY },
dkato 0:37e1e6a45ced 381 /*{ GS_EXTERNAL_SDRAM_START_0x08000000, R_OSPL_AXI_STRONGLY },*/
dkato 0:37e1e6a45ced 382 { GS_INTERNAL_RAM_START_0x20000000, R_OSPL_AXI_CACHE_ZERO },
dkato 0:37e1e6a45ced 383 /*{ GS_EXTERNAL_MIRROR_START_0x40000000, R_OSPL_AXI_STRONGLY },*/
dkato 0:37e1e6a45ced 384 /*{ GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,R_OSPL_AXI_STRONGLY },*/
dkato 0:37e1e6a45ced 385 /*{ GS_INTERNAL_RAM_MIRROR_START_0x60000000, R_OSPL_AXI_CACHE_ZERO },*/
dkato 0:37e1e6a45ced 386 /*{ GS_INTERNAL_REGISTERS_START_0x80000000, R_OSPL_AXI_CACHE_ZERO }*/
dkato 0:37e1e6a45ced 387 /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
dkato 0:37e1e6a45ced 388 };
dkato 0:37e1e6a45ced 389
dkato 0:37e1e6a45ced 390
dkato 0:37e1e6a45ced 391 ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
dkato 0:37e1e6a45ced 392
dkato 0:37e1e6a45ced 393 if ( address < table[1].Address ) {
dkato 0:37e1e6a45ced 394 *out_CacheAttribute = table[0].Value;
dkato 0:37e1e6a45ced 395 } else {
dkato 0:37e1e6a45ced 396 *out_CacheAttribute = table[1].Value;
dkato 0:37e1e6a45ced 397 }
dkato 0:37e1e6a45ced 398 R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
dkato 0:37e1e6a45ced 399 }
dkato 0:37e1e6a45ced 400 #endif
dkato 0:37e1e6a45ced 401 return 0;
dkato 0:37e1e6a45ced 402 }
dkato 0:37e1e6a45ced 403
dkato 0:37e1e6a45ced 404
dkato 0:37e1e6a45ced 405 /***********************************************************************
dkato 0:37e1e6a45ced 406 * Implement: R_OSPL_AXI_GetProtection
dkato 0:37e1e6a45ced 407 ************************************************************************/
dkato 0:37e1e6a45ced 408 errnum_t R_OSPL_AXI_GetProtection( uintptr_t const in_PhysicalAddress,
dkato 0:37e1e6a45ced 409 r_ospl_axi_protection_t *const out_Protection )
dkato 0:37e1e6a45ced 410 {
dkato 0:37e1e6a45ced 411 *out_Protection = R_OSPL_AXI_NON_SECURE; /* Same as CPU(TTB) NS bit */
dkato 0:37e1e6a45ced 412
dkato 0:37e1e6a45ced 413 return 0;
dkato 0:37e1e6a45ced 414 }
dkato 0:37e1e6a45ced 415
dkato 0:37e1e6a45ced 416
dkato 0:37e1e6a45ced 417 /***********************************************************************
dkato 0:37e1e6a45ced 418 * Implement: R_OSPL_AXI_SetEnvironment
dkato 0:37e1e6a45ced 419 ************************************************************************/
dkato 0:37e1e6a45ced 420 #ifdef R_OSPL_TEST_CODE
dkato 0:37e1e6a45ced 421 errnum_t R_OSPL_AXI_SetEnvironment( r_ospl_axi_envronment_t in_Environment )
dkato 0:37e1e6a45ced 422 {
dkato 0:37e1e6a45ced 423 gs_Environment = in_Environment;
dkato 0:37e1e6a45ced 424 return 0;
dkato 0:37e1e6a45ced 425 }
dkato 0:37e1e6a45ced 426 #endif
dkato 0:37e1e6a45ced 427
dkato 0:37e1e6a45ced 428