Graphics framework for GR-PEACH. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Dependents:   ImageZoomInout_Sample ImageRotaion_Sample ImageScroll_Sample GR-PEACH_LCD_4_3inch_Save_to_USB ... more

License

When you use this library, we judge you have agreed to the following contents.

https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Note

If you import the GraphicsFramework library, please import GR-PEACH_video library and R_BSP library together.



JPEG Converter

The JPEG Converter driver implements encode and decode functionality which uses the JCU of the RZ/A Series.

Hello World!

Import programJCU_HelloWorld

Hello World for JCU(JPEG Codec Unit). JCU is JPEG codec unit of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

API

Import library

Data Structures

struct bitmap_buff_info_t
Bitmap data setting struct. More...
struct encode_options_t
Encode option setting. More...

Public Types

enum jpeg_conv_error_t {
JPEG_CONV_OK = 0, JPEG_CONV_JCU_ERR = -1, JPEG_CONV_FORMA_ERR = -2, JPEG_CONV_PARAM_ERR = -3,
JPEG_CONV_BUSY = -4, JPEG_CONV_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT = 1, WR_RD_WRSWA_16BIT = 2, WR_RD_WRSWA_16_8BIT = 3,
WR_RD_WRSWA_32BIT = 4, WR_RD_WRSWA_32_8BIT = 5, WR_RD_WRSWA_32_16BIT = 6, WR_RD_WRSWA_32_16_8BIT = 7
}

Write/Read image pixcel frame buffer swap setting.

More...
enum wr_rd_format_t { WR_RD_YCbCr422 = 0x00, WR_RD_ARGB8888 = 0x01, WR_RD_RGB565 = 0x02 }

Write/Read image pixcel format selects.

More...
enum sub_sampling_t { SUB_SAMPLING_1_1 = 0x00, SUB_SAMPLING_1_2 = 0x01, SUB_SAMPLING_1_4 = 0x02, SUB_SAMPLING_1_8 = 0x03 }

Thinning output image selects.

More...
enum cbcr_offset_t { CBCR_OFFSET_0 = 0x00, CBCR_OFFSET_128 = 0x01 }

Cb/Cr range selects for decode.

More...

Public Member Functions

JPEG_Converter ()
Constructor method of JPEG converter(encode/decode)
virtual ~JPEG_Converter ()
Destructor method of JPEG converter(encode/decode)
JPEG_Converter::jpeg_conv_error_t decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff)
Decode JPEG to rinear data.
JPEG_Converter::jpeg_conv_error_t decode (void *pJpegBuff, bitmap_buff_info_t *psOutputBuff, decode_options_t *pOptions)
JPEG data decode to bitmap.
JPEG_Converter::jpeg_conv_error_t encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize)
Encode rinear data to JPEG.
JPEG_Converter::jpeg_conv_error_t encode ( bitmap_buff_info_t *psInputBuff, void *pJpegBuff, size_t *pEncodeSize, encode_options_t *pOptions)
Bitmap data encode to JPEG.
JPEG_Converter::jpeg_conv_error_t SetQuality (const uint8_t qual)
Set encode quality.

Correspondence file

A correspondence file of JPEG Converter is as the following table.

JPEGCorrespondence
Width>0(greater than 0)
Height>0(greater than 0)
Color formatYCbCr444, YCbCr422, YCbCr420, YCbCr411
BitmapCorrespondence
Width>0(greater than 0)
Height>0(greater than 0)
Color formatYCbCr422

Notice

You run JPEG converter once destruction each time.

You set whether these JPEG files aren't input, or it check error setting decode(set in "flag" = true). The JPEG file which becomes correspondence outside will be the following condition.

  • File besides the above-mentioned correspondence file.
  • As information in the JPEG file, WIDTH or HEIGHT is larger than output buffer setting.

Buffer area is used encode/decode, set 8 bytes align and non-cash memory area. The output buffer when decoding, is made beyond the size decided in the size of the JPEG file, the format, setting of thinning out. You make output buffer for decode/encode to enough big size in order to stock this result. JPEG Converter, if you do not particularly perform specified, does not check size against the output data at the time of encoding and decoding. You set the output buffer so that there is no effect of corruption by the output data.

Color format

Color format in case to be converted from Bitmap to JPEG is either ARGB8888 or RGB555, YCbCr422. Color format of the If you want to convert from JPEG file to Bitmap file is YCbCr422. You correct "alpha(member of decode_options_t)" of setting and "output_cb_cr_offset(member of decode_options_t)" according to color format when decoding.

  • example
    decode to ARGB8888(WR_RD_ARGB8888 set in format member of bitmap_buff_info_t)
    alpha = 0x01-0xFF
    output_cb_cr_offset = CBCR_OFFSET_0

    decode to YCbCr422(WR_RD_YCbCr422 set in format member of bitmap_buff_info_t)
    alpha = 0
    output_cb_cr_offset = CBCR_OFFSET_0 or CBCR_OFFSET_128

    decode to RGB565(WR_RD_RGB565 set in format member of bitmap_buff_info_t)
    alpha = 0
    output_cb_cr_offset = CBCR_OFFSET_0

Decode/encode settings are optional

If omitted encode/decode settings, it will work with the following settings.
[Decode option setting (member of decode_options_t)]

  • Vertical sub sampling is thinning output image to 1/1.
  • Horizontal sub sampling is thinning output image to 1/1.
  • Output data of Cb/Cr range is -128 to 127.
  • Output data of swap in 8-bit units: 2-1-4-3-6-5-8-7.
  • Alpha value of 0.
  • JPEG format correspondence outside error check.
  • It decode in a synchronous function.

[Encode option setting (member of encode_options_t)]

  • DRI value is 0.
  • Encoding JPEG file start width offset is 0.
  • Encoding JPEG file start height offset is 0.
  • Input data of Cb/Cr range of input data is -128 to 127.
  • Input data swap in 8-bit units: 2-1-4-3-6-5-8-7.
  • It don't check encode size.
  • Quantization Y use default table(Quality75).
  • Quantization C use default table(Quality75).
  • Huffman Y DC use default table.
  • Huffman C DC use default table.
  • Huffman Y AC use default table.
  • Huffman C AC use default table.
  • It encode in a synchronous function.

Synchronous/asynchronous switching

Decoding and encoding setting to operate asynchronously by setting a callback function(decode_options_t and encode_options_t).

Quality

Quality changes are possible. If you want to change the Quality, please specify the table made of Quality you want to change the address of the setting. If you do not want to change the Quality, it will operate at Quality75.

RGA

The RGA library implements fast drawing functionality which uses the RGA of the RZ/A Series.
Supporting compiler is ARMCC, GCC ARM and IAR.

Hello World!

Import programRGA_HelloWorld

Hello World for RGA(Renesas Graphics Architecture). RGA is the Graphics Library of RZ/A1. When you use this program, we judge you have agreed to the following contents. https://developer.mbed.org/teams/Renesas/wiki/About-LICENSE

Committer:
dkato
Date:
Mon Apr 24 08:16:23 2017 +0000
Revision:
13:1ee2176ef13f
Parent:
3:9f857750e4e9
Add "SetQuality()" to JCU.
; Bug fixes.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
1050186 3:9f857750e4e9 1 /*******************************************************************************
1050186 3:9f857750e4e9 2 * DISCLAIMER
1050186 3:9f857750e4e9 3 * This software is supplied by Renesas Electronics Corporation and is only
1050186 3:9f857750e4e9 4 * intended for use with Renesas products. No other uses are authorized. This
1050186 3:9f857750e4e9 5 * software is owned by Renesas Electronics Corporation and is protected under
1050186 3:9f857750e4e9 6 * all applicable laws, including copyright laws.
1050186 3:9f857750e4e9 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
1050186 3:9f857750e4e9 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
1050186 3:9f857750e4e9 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
1050186 3:9f857750e4e9 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
1050186 3:9f857750e4e9 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
1050186 3:9f857750e4e9 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
1050186 3:9f857750e4e9 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
1050186 3:9f857750e4e9 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
1050186 3:9f857750e4e9 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
1050186 3:9f857750e4e9 16 * Renesas reserves the right, without notice, to make changes to this software
1050186 3:9f857750e4e9 17 * and to discontinue the availability of this software. By using this software,
1050186 3:9f857750e4e9 18 * you agree to the additional terms and conditions found by accessing the
1050186 3:9f857750e4e9 19 * following link:
1050186 3:9f857750e4e9 20 * http://www.renesas.com/disclaimer
1050186 3:9f857750e4e9 21 * Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
1050186 3:9f857750e4e9 22 *******************************************************************************/
1050186 3:9f857750e4e9 23 /**
1050186 3:9f857750e4e9 24 * @file video_input.c
1050186 3:9f857750e4e9 25 * @brief $Rev: 51 $
1050186 3:9f857750e4e9 26 * $Date:: 2014-03-14 18:42:33 +0900#$
1050186 3:9f857750e4e9 27 */
1050186 3:9f857750e4e9 28
1050186 3:9f857750e4e9 29
1050186 3:9f857750e4e9 30 /******************************************************************************
1050186 3:9f857750e4e9 31 Includes <System Includes> , "Project Includes"
1050186 3:9f857750e4e9 32 *******************************************************************************/
1050186 3:9f857750e4e9 33 #include "r_typedefs.h"
1050186 3:9f857750e4e9 34 #include "r_ospl.h"
1050186 3:9f857750e4e9 35 #include "video_input.h"
1050186 3:9f857750e4e9 36 #include "video_decoder.h"
1050186 3:9f857750e4e9 37 #include "window_surfaces_typedef.h" /* WINDOW_SURFACES_DEFAULT_CHANNEL */
1050186 3:9f857750e4e9 38 #ifndef R_OSPL_NDEBUG
1050186 3:9f857750e4e9 39 #include <stdio.h>
1050186 3:9f857750e4e9 40 #endif
1050186 3:9f857750e4e9 41
1050186 3:9f857750e4e9 42
1050186 3:9f857750e4e9 43 /******************************************************************************
1050186 3:9f857750e4e9 44 Typedef definitions
1050186 3:9f857750e4e9 45 ******************************************************************************/
1050186 3:9f857750e4e9 46
1050186 3:9f857750e4e9 47 /**
1050186 3:9f857750e4e9 48 * @typedef video_input_vdc5_layer_t
1050186 3:9f857750e4e9 49 * @brief video_input_vdc5_layer_t
1050186 3:9f857750e4e9 50 */
1050186 3:9f857750e4e9 51 typedef struct st_video_input_vdc5_layer_t video_input_vdc5_layer_t;
1050186 3:9f857750e4e9 52 struct st_video_input_vdc5_layer_t {
1050186 3:9f857750e4e9 53 bool_t is_data_control;
1050186 3:9f857750e4e9 54 vdc5_layer_id_t data_control_ID;
1050186 3:9f857750e4e9 55 };
1050186 3:9f857750e4e9 56
1050186 3:9f857750e4e9 57
1050186 3:9f857750e4e9 58 /**
1050186 3:9f857750e4e9 59 * @typedef vdc5_int_cb_t
1050186 3:9f857750e4e9 60 * @brief vdc5_int_cb_t
1050186 3:9f857750e4e9 61 */
1050186 3:9f857750e4e9 62 typedef void (* vdc5_int_cb_t )( const uint32_t );
1050186 3:9f857750e4e9 63
1050186 3:9f857750e4e9 64
1050186 3:9f857750e4e9 65 /******************************************************************************
1050186 3:9f857750e4e9 66 Macro definitions
1050186 3:9f857750e4e9 67 ******************************************************************************/
1050186 3:9f857750e4e9 68
1050186 3:9f857750e4e9 69 #define VSYNC_1_2_FH_TIMING (858u) /* Vsync signal 1/2fH phase timing */
1050186 3:9f857750e4e9 70 #define VSYNC_1_4_FH_TIMING (429u) /* Vsync signal 1/4fH phase timing */
1050186 3:9f857750e4e9 71
1050186 3:9f857750e4e9 72 #define IMGCAP_SIZE_NTSC_HS (122u * 2u)
1050186 3:9f857750e4e9 73 #define IMGCAP_SIZE_NTSC_HW (720u * 2u)
1050186 3:9f857750e4e9 74 #define IMGCAP_SIZE_NTSC_VS (16u)
1050186 3:9f857750e4e9 75 #define IMGCAP_SIZE_NTSC_VW (480u/2u)
1050186 3:9f857750e4e9 76
1050186 3:9f857750e4e9 77 #define IMGCAP_SIZE_PAL_HS (132u * 2u)
1050186 3:9f857750e4e9 78 #define IMGCAP_SIZE_PAL_HW (720u * 2u)
1050186 3:9f857750e4e9 79 #define IMGCAP_SIZE_PAL_VS (19u)
1050186 3:9f857750e4e9 80 #define IMGCAP_SIZE_PAL_VW (560u/2u)
1050186 3:9f857750e4e9 81
1050186 3:9f857750e4e9 82 #define VIDEO_FORMAT (VDC5_RES_MD_YCBCR422)
1050186 3:9f857750e4e9 83
1050186 3:9f857750e4e9 84
1050186 3:9f857750e4e9 85 /******************************************************************************
1050186 3:9f857750e4e9 86 Imported global variables and functions (from other files)
1050186 3:9f857750e4e9 87 ******************************************************************************/
1050186 3:9f857750e4e9 88
1050186 3:9f857750e4e9 89 /******************************************************************************
1050186 3:9f857750e4e9 90 Exported global variables and functions (to be accessed by other files)
1050186 3:9f857750e4e9 91 ******************************************************************************/
1050186 3:9f857750e4e9 92
1050186 3:9f857750e4e9 93 /******************************************************************************
1050186 3:9f857750e4e9 94 Private global variables and functions
1050186 3:9f857750e4e9 95 ******************************************************************************/
1050186 3:9f857750e4e9 96
1050186 3:9f857750e4e9 97 static void R_VIDEO_INPUT_OnVideoInVSync( vdc5_channel_t video_input_channel, vdc5_int_type_t int_type );
1050186 3:9f857750e4e9 98 static void R_VIDEO_INPUT_OnVideoInVSync_Ch0( vdc5_int_type_t int_type );
1050186 3:9f857750e4e9 99 static void R_VIDEO_INPUT_OnVideoInVSync_Ch1( vdc5_int_type_t int_type );
1050186 3:9f857750e4e9 100 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 101 static void InterruptCallbackVector_S0_VI_VSYNC0(void);
1050186 3:9f857750e4e9 102 static void InterruptCallbackVector_S0_VI_VSYNC1(void);
1050186 3:9f857750e4e9 103 static void InterruptCallbackVector_S1_VI_VSYNC0(void);
1050186 3:9f857750e4e9 104 static void InterruptCallbackVector_S1_VI_VSYNC1(void);
1050186 3:9f857750e4e9 105 vdc5_int_cb_t gs_VDC5_ISR_S0_VI_VSYNC0;
1050186 3:9f857750e4e9 106 vdc5_int_cb_t gs_VDC5_ISR_S0_VI_VSYNC1;
1050186 3:9f857750e4e9 107 vdc5_int_cb_t gs_VDC5_ISR_S1_VI_VSYNC0;
1050186 3:9f857750e4e9 108 vdc5_int_cb_t gs_VDC5_ISR_S1_VI_VSYNC1;
1050186 3:9f857750e4e9 109 #endif
1050186 3:9f857750e4e9 110
1050186 3:9f857750e4e9 111 static video_input_t *gs_InterruptToSelf[ 2 /* video_input_channel */ ][ 2 /* data_control_ID */ ];
1050186 3:9f857750e4e9 112
1050186 3:9f857750e4e9 113 static errnum_t R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
1050186 3:9f857750e4e9 114 vdc5_channel_t in_video_input_channel, vdc5_layer_id_t in_data_control_ID,
1050186 3:9f857750e4e9 115 video_input_t *in_self );
1050186 3:9f857750e4e9 116 static errnum_t R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
1050186 3:9f857750e4e9 117 vdc5_channel_t in_video_input_channel, vdc5_layer_id_t in_data_control_ID,
1050186 3:9f857750e4e9 118 video_input_t *in_self );
1050186 3:9f857750e4e9 119 static errnum_t R_VIDEO_INPUT_STATIC_GetSelfPointer(
1050186 3:9f857750e4e9 120 vdc5_channel_t in_video_input_channel, vdc5_layer_id_t in_data_control_ID,
1050186 3:9f857750e4e9 121 video_input_t *** out_self_pp );
1050186 3:9f857750e4e9 122 static errnum_t R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt(
1050186 3:9f857750e4e9 123 vdc5_channel_t in_video_input_channel, vdc5_int_type_t in_interrupt,
1050186 3:9f857750e4e9 124 video_input_t **out_self );
1050186 3:9f857750e4e9 125
1050186 3:9f857750e4e9 126
1050186 3:9f857750e4e9 127 /**
1050186 3:9f857750e4e9 128 * @brief Initializes by constant data.
1050186 3:9f857750e4e9 129 *
1050186 3:9f857750e4e9 130 * @param self video_input_t.
1050186 3:9f857750e4e9 131 * @return None.
1050186 3:9f857750e4e9 132 */
1050186 3:9f857750e4e9 133 void R_VIDEO_INPUT_InitConst( video_input_t *const self )
1050186 3:9f857750e4e9 134 {
1050186 3:9f857750e4e9 135 self->is_data_control = false;
1050186 3:9f857750e4e9 136 self->is_vsync_interrupt_registered[0] = false;
1050186 3:9f857750e4e9 137 self->is_vsync_interrupt_registered[1] = false;
1050186 3:9f857750e4e9 138 self->is_vsync_interrupt_registered[2] = false;
1050186 3:9f857750e4e9 139 }
1050186 3:9f857750e4e9 140
1050186 3:9f857750e4e9 141
1050186 3:9f857750e4e9 142 /***********************************************************************
1050186 3:9f857750e4e9 143 * Implement: R_VIDEO_INPUT_Initialize
1050186 3:9f857750e4e9 144 ************************************************************************/
1050186 3:9f857750e4e9 145 errnum_t R_VIDEO_INPUT_Initialize( video_input_t *const self,
1050186 3:9f857750e4e9 146 video_input_config_t *in_out_Config )
1050186 3:9f857750e4e9 147 {
1050186 3:9f857750e4e9 148 errnum_t e;
1050186 3:9f857750e4e9 149 vdc5_error_t e_vdc5;
1050186 3:9f857750e4e9 150 #ifdef IS_MBED_USED
1050186 3:9f857750e4e9 151 vdec_error_t e_vdec;
1050186 3:9f857750e4e9 152 #endif
1050186 3:9f857750e4e9 153 vdc5_write_t writing_config;
1050186 3:9f857750e4e9 154 frame_buffer_t *frame;
1050186 3:9f857750e4e9 155 uintptr_t frame_physical_address[ R_COUNT_OF( frame->buffer_address ) ];
1050186 3:9f857750e4e9 156
1050186 3:9f857750e4e9 157
1050186 3:9f857750e4e9 158 /* Initialize by constant */
1050186 3:9f857750e4e9 159 ASSERT_R( ! self->is_data_control, e=E_STATE; goto fin );
1050186 3:9f857750e4e9 160 ASSERT_R( ! self->is_vsync_interrupt_registered[0], e=E_STATE; goto fin );
1050186 3:9f857750e4e9 161 ASSERT_R( ! self->is_vsync_interrupt_registered[1], e=E_STATE; goto fin );
1050186 3:9f857750e4e9 162 ASSERT_R( ! self->is_vsync_interrupt_registered[2], e=E_STATE; goto fin );
1050186 3:9f857750e4e9 163 self->captured_count = 0;
1050186 3:9f857750e4e9 164
1050186 3:9f857750e4e9 165
1050186 3:9f857750e4e9 166 /* Check necessary flags */
1050186 3:9f857750e4e9 167 {
1050186 3:9f857750e4e9 168 enum { necessary_flags =
1050186 3:9f857750e4e9 169 VIDEO_INPUT_CONFIG_T_FRAME_BUFFER
1050186 3:9f857750e4e9 170 };
1050186 3:9f857750e4e9 171
1050186 3:9f857750e4e9 172 ASSERT_R( IS_ALL_BITS_SET( in_out_Config->flags, necessary_flags ),
1050186 3:9f857750e4e9 173 e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 174 }
1050186 3:9f857750e4e9 175
1050186 3:9f857750e4e9 176
1050186 3:9f857750e4e9 177 /* Set "frame" */
1050186 3:9f857750e4e9 178 {
1050186 3:9f857750e4e9 179 int_fast32_t i;
1050186 3:9f857750e4e9 180
1050186 3:9f857750e4e9 181 frame = in_out_Config->frame_buffer;
1050186 3:9f857750e4e9 182 ASSERT_R( frame->buffer_count == 2, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 183 self->frame_buffer = *frame;
1050186 3:9f857750e4e9 184
1050186 3:9f857750e4e9 185 for ( i = 0; i < frame->buffer_count; i += 1 ) {
1050186 3:9f857750e4e9 186 e= R_OSPL_ToPhysicalAddress( frame->buffer_address[ i ],
1050186 3:9f857750e4e9 187 &frame_physical_address[ i ] );
1050186 3:9f857750e4e9 188 IF(e!=0) {
1050186 3:9f857750e4e9 189 goto fin;
1050186 3:9f857750e4e9 190 }
1050186 3:9f857750e4e9 191 }
1050186 3:9f857750e4e9 192 }
1050186 3:9f857750e4e9 193
1050186 3:9f857750e4e9 194
1050186 3:9f857750e4e9 195 /* Set default "in_out_Config->video_input_channel_num" */
1050186 3:9f857750e4e9 196 if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM ) ) {
1050186 3:9f857750e4e9 197 in_out_Config->video_input_channel_num = WINDOW_SURFACES_DEFAULT_CHANNEL;
1050186 3:9f857750e4e9 198 }
1050186 3:9f857750e4e9 199
1050186 3:9f857750e4e9 200
1050186 3:9f857750e4e9 201 /* Set from "in_out_Config->video_input_channel_num" */
1050186 3:9f857750e4e9 202 switch ( in_out_Config->video_input_channel_num ) {
1050186 3:9f857750e4e9 203 case 0:
1050186 3:9f857750e4e9 204 self->video_input_channel = VDC5_CHANNEL_0;
1050186 3:9f857750e4e9 205 self->video_input_select = VDEC_ADC_VINSEL_VIN1;
1050186 3:9f857750e4e9 206 break;
1050186 3:9f857750e4e9 207 case 1:
1050186 3:9f857750e4e9 208 self->video_input_channel = VDC5_CHANNEL_1;
1050186 3:9f857750e4e9 209 self->video_input_select = VDEC_ADC_VINSEL_VIN1;
1050186 3:9f857750e4e9 210 break;
1050186 3:9f857750e4e9 211 case 2:
1050186 3:9f857750e4e9 212 self->video_input_channel = VDC5_CHANNEL_0;
1050186 3:9f857750e4e9 213 self->video_input_select = VDEC_ADC_VINSEL_VIN2;
1050186 3:9f857750e4e9 214 break;
1050186 3:9f857750e4e9 215 case 3:
1050186 3:9f857750e4e9 216 self->video_input_channel = VDC5_CHANNEL_1;
1050186 3:9f857750e4e9 217 self->video_input_select = VDEC_ADC_VINSEL_VIN2;
1050186 3:9f857750e4e9 218 break;
1050186 3:9f857750e4e9 219 default:
1050186 3:9f857750e4e9 220 ASSERT_R( false, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 221 }
1050186 3:9f857750e4e9 222
1050186 3:9f857750e4e9 223
1050186 3:9f857750e4e9 224 /* Set default "in_out_Config->display_channel_num" */
1050186 3:9f857750e4e9 225 if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM ) ) {
1050186 3:9f857750e4e9 226 if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM ) ) {
1050186 3:9f857750e4e9 227 in_out_Config->display_channel_num = VIDEO_INPUT_NOT_DISPLAY;
1050186 3:9f857750e4e9 228 } else {
1050186 3:9f857750e4e9 229 in_out_Config->display_channel_num = WINDOW_SURFACES_DEFAULT_CHANNEL;
1050186 3:9f857750e4e9 230 }
1050186 3:9f857750e4e9 231 }
1050186 3:9f857750e4e9 232
1050186 3:9f857750e4e9 233
1050186 3:9f857750e4e9 234 /* Set default "in_out_Config->display_layer_num" */
1050186 3:9f857750e4e9 235 if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM ) ) {
1050186 3:9f857750e4e9 236 if ( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY ) {
1050186 3:9f857750e4e9 237 in_out_Config->display_layer_num = VIDEO_INPUT_NOT_DISPLAY;
1050186 3:9f857750e4e9 238 } else {
1050186 3:9f857750e4e9 239 in_out_Config->display_layer_num = -1;
1050186 3:9f857750e4e9 240 }
1050186 3:9f857750e4e9 241 }
1050186 3:9f857750e4e9 242 ASSERT_D( in_out_Config->display_layer_num == VIDEO_INPUT_NOT_DISPLAY ||
1050186 3:9f857750e4e9 243 in_out_Config->display_layer_num <= -1, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 244 ASSERT_D(
1050186 3:9f857750e4e9 245 ( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY &&
1050186 3:9f857750e4e9 246 in_out_Config->display_layer_num == VIDEO_INPUT_NOT_DISPLAY ) ||
1050186 3:9f857750e4e9 247 ( in_out_Config->display_channel_num != VIDEO_INPUT_NOT_DISPLAY &&
1050186 3:9f857750e4e9 248 in_out_Config->display_layer_num != VIDEO_INPUT_NOT_DISPLAY ),
1050186 3:9f857750e4e9 249 e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 250
1050186 3:9f857750e4e9 251
1050186 3:9f857750e4e9 252 /* Set "self->data_control_ID" : No care of "display_layer_num" */
1050186 3:9f857750e4e9 253 if ( in_out_Config->display_channel_num == 0 ) {
1050186 3:9f857750e4e9 254 if ( self->video_input_channel == 0 ) {
1050186 3:9f857750e4e9 255 self->data_control_ID = VDC5_LAYER_ID_0_WR;
1050186 3:9f857750e4e9 256 } else {
1050186 3:9f857750e4e9 257 self->data_control_ID = VDC5_LAYER_ID_1_WR;
1050186 3:9f857750e4e9 258 }
1050186 3:9f857750e4e9 259 } else if ( in_out_Config->display_channel_num == 1 ) {
1050186 3:9f857750e4e9 260 if ( self->video_input_channel == 0 ) {
1050186 3:9f857750e4e9 261 self->data_control_ID = VDC5_LAYER_ID_1_WR;
1050186 3:9f857750e4e9 262 } else {
1050186 3:9f857750e4e9 263 self->data_control_ID = VDC5_LAYER_ID_0_WR;
1050186 3:9f857750e4e9 264 }
1050186 3:9f857750e4e9 265 } else {
1050186 3:9f857750e4e9 266 ASSERT_D( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY,
1050186 3:9f857750e4e9 267 e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 268
1050186 3:9f857750e4e9 269 self->data_control_ID = VDC5_LAYER_ID_0_WR;
1050186 3:9f857750e4e9 270 }
1050186 3:9f857750e4e9 271
1050186 3:9f857750e4e9 272
1050186 3:9f857750e4e9 273 /* Set "self->captured_async" */
1050186 3:9f857750e4e9 274 self->captured_async = NULL;
1050186 3:9f857750e4e9 275 if ( IS_BIT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC ) ) {
1050186 3:9f857750e4e9 276 self->captured_async = in_out_Config->captured_async;
1050186 3:9f857750e4e9 277 }
1050186 3:9f857750e4e9 278
1050186 3:9f857750e4e9 279
1050186 3:9f857750e4e9 280 /* From GRPDRV_Init() */
1050186 3:9f857750e4e9 281 {
1050186 3:9f857750e4e9 282 vdc5_input_t input;
1050186 3:9f857750e4e9 283
1050186 3:9f857750e4e9 284 /* Input parameter */
1050186 3:9f857750e4e9 285 input.inp_sel = VDC5_INPUT_SEL_VDEC; /* Input select */
1050186 3:9f857750e4e9 286 input.inp_fh50 = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
1050186 3:9f857750e4e9 287 input.inp_fh25 = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
1050186 3:9f857750e4e9 288 input.dly = NULL; /* Sync signal delay adjustment */
1050186 3:9f857750e4e9 289 input.ext_sig = NULL; /* External input signal */
1050186 3:9f857750e4e9 290 e_vdc5 = R_VDC5_VideoInput( self->video_input_channel, &input );
1050186 3:9f857750e4e9 291 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 292 e=E_OTHERS;
1050186 3:9f857750e4e9 293 goto fin;
1050186 3:9f857750e4e9 294 }
1050186 3:9f857750e4e9 295 }
1050186 3:9f857750e4e9 296
1050186 3:9f857750e4e9 297
1050186 3:9f857750e4e9 298 /* ... */
1050186 3:9f857750e4e9 299 {
1050186 3:9f857750e4e9 300 vdec_channel_t vdec_channel; /* video decoder channel */
1050186 3:9f857750e4e9 301 #ifdef IS_MBED_USED
1050186 3:9f857750e4e9 302 graphics_col_sys_t color_system = GRPH_COL_SYS_NTSC_358;
1050186 3:9f857750e4e9 303 #else
1050186 3:9f857750e4e9 304 graphics_col_sys_t color_system;
1050186 3:9f857750e4e9 305 #endif
1050186 3:9f857750e4e9 306 vdc5_scalingdown_rot_t *writing_scale = &writing_config.scalingdown_rot;
1050186 3:9f857750e4e9 307
1050186 3:9f857750e4e9 308
1050186 3:9f857750e4e9 309 /* From SetVideoDecoder() */
1050186 3:9f857750e4e9 310
1050186 3:9f857750e4e9 311 if ( self->video_input_channel == VDC5_CHANNEL_0 ) {
1050186 3:9f857750e4e9 312 vdec_channel = VDEC_CHANNEL_0;
1050186 3:9f857750e4e9 313 } else {
1050186 3:9f857750e4e9 314 ASSERT_R( self->video_input_channel == VDC5_CHANNEL_1, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 315 vdec_channel = VDEC_CHANNEL_1;
1050186 3:9f857750e4e9 316 }
1050186 3:9f857750e4e9 317 #ifdef IS_MBED_USED
1050186 3:9f857750e4e9 318 e_vdec = GRAPHICS_VideoDecoderInit( self->video_input_select, vdec_channel, color_system );
1050186 3:9f857750e4e9 319 IF ( e_vdec != VDEC_OK ) {
1050186 3:9f857750e4e9 320 e=E_OTHERS;
1050186 3:9f857750e4e9 321 goto fin;
1050186 3:9f857750e4e9 322 }
1050186 3:9f857750e4e9 323 #else
1050186 3:9f857750e4e9 324 color_system = GRAPHICS_VideoDecoderInit( self->video_input_select, vdec_channel );
1050186 3:9f857750e4e9 325 if ( color_system == GRPH_COL_SYS_UNKNOWN ) {
1050186 3:9f857750e4e9 326 color_system = GRPH_COL_SYS_NTSC_358;
1050186 3:9f857750e4e9 327 }
1050186 3:9f857750e4e9 328 #endif
1050186 3:9f857750e4e9 329
1050186 3:9f857750e4e9 330
1050186 3:9f857750e4e9 331 /* From GRPDRV_VideoCreateNonDispSurface() */
1050186 3:9f857750e4e9 332
1050186 3:9f857750e4e9 333 /* Image area to be captured */
1050186 3:9f857750e4e9 334 #if VIDEO_FORMAT_TYPE == VIDEO_FORMAT_TYPE_NTSC
1050186 3:9f857750e4e9 335 ASSERT_R( (color_system == GRPH_COL_SYS_NTSC_358) ||
1050186 3:9f857750e4e9 336 (color_system == GRPH_COL_SYS_NTSC_443),
1050186 3:9f857750e4e9 337 e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 338
1050186 3:9f857750e4e9 339 writing_scale->res.vs = (uint16_t)( IMGCAP_SIZE_NTSC_VS - 1 );
1050186 3:9f857750e4e9 340 writing_scale->res.vw = (uint16_t)IMGCAP_SIZE_NTSC_VW;
1050186 3:9f857750e4e9 341 writing_scale->res.hs = (uint16_t)IMGCAP_SIZE_NTSC_HS;
1050186 3:9f857750e4e9 342 writing_scale->res.hw = (uint16_t)IMGCAP_SIZE_NTSC_HW;
1050186 3:9f857750e4e9 343 /* v = vertical, h = horizontal, s = start, w = width */
1050186 3:9f857750e4e9 344 #elif VIDEO_FORMAT_TYPE == VIDEO_FORMAT_TYPE_PAL
1050186 3:9f857750e4e9 345 ASSERT_R( (color_system != GRPH_COL_SYS_NTSC_358) &&
1050186 3:9f857750e4e9 346 (color_system != GRPH_COL_SYS_NTSC_443),
1050186 3:9f857750e4e9 347 e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 348
1050186 3:9f857750e4e9 349 writing_scale->res.vs = (uint16_t)( IMGCAP_SIZE_PAL_VS - 1 );
1050186 3:9f857750e4e9 350 writing_scale->res.vw = (uint16_t)IMGCAP_SIZE_PAL_VW;
1050186 3:9f857750e4e9 351 writing_scale->res.hs = (uint16_t)IMGCAP_SIZE_PAL_HS;
1050186 3:9f857750e4e9 352 writing_scale->res.hw = (uint16_t)IMGCAP_SIZE_PAL_HW;
1050186 3:9f857750e4e9 353 #else
1050186 3:9f857750e4e9 354 #error
1050186 3:9f857750e4e9 355 #endif
1050186 3:9f857750e4e9 356
1050186 3:9f857750e4e9 357
1050186 3:9f857750e4e9 358 /* Write data parameter */
1050186 3:9f857750e4e9 359 writing_scale->res_pfil_sel = VDC5_ON;
1050186 3:9f857750e4e9 360 /* Prefilter mode select for brightness signals (on/off) */
1050186 3:9f857750e4e9 361
1050186 3:9f857750e4e9 362 writing_scale->res_out_vw = frame->height / 2;
1050186 3:9f857750e4e9 363 /* Number of valid lines in vertical direction */
1050186 3:9f857750e4e9 364 /* output by scaling-down control block */
1050186 3:9f857750e4e9 365
1050186 3:9f857750e4e9 366 writing_scale->res_out_hw = frame->width;
1050186 3:9f857750e4e9 367 /* Number of valid horizontal pixels */
1050186 3:9f857750e4e9 368 /* output by scaling-down control block */
1050186 3:9f857750e4e9 369
1050186 3:9f857750e4e9 370 writing_scale->adj_sel = VDC5_ON;
1050186 3:9f857750e4e9 371 /* Measures to decrease the influence */
1050186 3:9f857750e4e9 372 /* by lack of last-input line (on/off) */
1050186 3:9f857750e4e9 373
1050186 3:9f857750e4e9 374 writing_scale->res_ds_wr_md = VDC5_WR_MD_NORMAL;
1050186 3:9f857750e4e9 375 /* Frame buffer writing mode */
1050186 3:9f857750e4e9 376 }
1050186 3:9f857750e4e9 377
1050186 3:9f857750e4e9 378
1050186 3:9f857750e4e9 379 /* From GRPDRV_VideoCreateNonDispSurface() */
1050186 3:9f857750e4e9 380 {
1050186 3:9f857750e4e9 381 writing_config.res_wrswa = VDC5_WR_RD_WRSWA_16BIT;
1050186 3:9f857750e4e9 382 /* Frame buffer swap setting */
1050186 3:9f857750e4e9 383
1050186 3:9f857750e4e9 384 writing_config.res_md = VIDEO_FORMAT;
1050186 3:9f857750e4e9 385 /* Frame buffer video-signal writing format */
1050186 3:9f857750e4e9 386
1050186 3:9f857750e4e9 387 writing_config.res_bst_md = VDC5_BST_MD_32BYTE;
1050186 3:9f857750e4e9 388 /* Transfer burst length for frame buffer */
1050186 3:9f857750e4e9 389
1050186 3:9f857750e4e9 390 writing_config.res_inter = VDC5_RES_INTER_INTERLACE;
1050186 3:9f857750e4e9 391 /* Field operating mode select */
1050186 3:9f857750e4e9 392
1050186 3:9f857750e4e9 393 writing_config.res_fs_rate = VDC5_RES_FS_RATE_PER1;
1050186 3:9f857750e4e9 394 /* Writing rate */
1050186 3:9f857750e4e9 395
1050186 3:9f857750e4e9 396 writing_config.res_fld_sel = VDC5_RES_FLD_SEL_TOP;
1050186 3:9f857750e4e9 397 /* Write field select */
1050186 3:9f857750e4e9 398
1050186 3:9f857750e4e9 399 writing_config.res_dth_on = VDC5_ON;
1050186 3:9f857750e4e9 400 /* Dither correction on/off */
1050186 3:9f857750e4e9 401
1050186 3:9f857750e4e9 402 writing_config.base = (void *) frame_physical_address[0];
1050186 3:9f857750e4e9 403 /* Frame buffer base address */
1050186 3:9f857750e4e9 404
1050186 3:9f857750e4e9 405 writing_config.ln_off = frame->stride;
1050186 3:9f857750e4e9 406 /* Frame buffer line offset address [byte] */
1050186 3:9f857750e4e9 407
1050186 3:9f857750e4e9 408 writing_config.flm_num = (uint32_t)( frame->buffer_count - 1u );
1050186 3:9f857750e4e9 409 /* Number of frames of buffer (res_flm_num + 1) */
1050186 3:9f857750e4e9 410
1050186 3:9f857750e4e9 411 writing_config.flm_off = frame_physical_address[1] - frame_physical_address[0];
1050186 3:9f857750e4e9 412
1050186 3:9f857750e4e9 413 writing_config.btm_base = NULL;
1050186 3:9f857750e4e9 414 /* Frame buffer base address for bottom */
1050186 3:9f857750e4e9 415
1050186 3:9f857750e4e9 416
1050186 3:9f857750e4e9 417 e_vdc5 = R_VDC5_WriteDataControl( self->video_input_channel,
1050186 3:9f857750e4e9 418 self->data_control_ID, &writing_config );
1050186 3:9f857750e4e9 419 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 420 e=E_OTHERS;
1050186 3:9f857750e4e9 421 goto fin;
1050186 3:9f857750e4e9 422 }
1050186 3:9f857750e4e9 423
1050186 3:9f857750e4e9 424 self->is_data_control = true;
1050186 3:9f857750e4e9 425 }
1050186 3:9f857750e4e9 426
1050186 3:9f857750e4e9 427
1050186 3:9f857750e4e9 428 {
1050186 3:9f857750e4e9 429 vdc5_start_t start;
1050186 3:9f857750e4e9 430
1050186 3:9f857750e4e9 431 e_vdc5 = R_VDC5_StartProcess( self->video_input_channel, self->data_control_ID, &start );
1050186 3:9f857750e4e9 432 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 433 e = E_OTHERS;
1050186 3:9f857750e4e9 434 goto fin;
1050186 3:9f857750e4e9 435 }
1050186 3:9f857750e4e9 436
1050186 3:9f857750e4e9 437 /* This module does not call "R_VDC5_StartProcess" function for reading (showing). */
1050186 3:9f857750e4e9 438 }
1050186 3:9f857750e4e9 439
1050186 3:9f857750e4e9 440
1050186 3:9f857750e4e9 441 {
1050186 3:9f857750e4e9 442 vdc5_int_t *config = &self->interrupt_for_VDC5;
1050186 3:9f857750e4e9 443 bsp_int_err_t ret_b;
1050186 3:9f857750e4e9 444 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 445 vdc5_int_cb_t *p_VDC5_ISR;
1050186 3:9f857750e4e9 446 #endif
1050186 3:9f857750e4e9 447
1050186 3:9f857750e4e9 448 e= R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
1050186 3:9f857750e4e9 449 self->video_input_channel, self->data_control_ID, self );
1050186 3:9f857750e4e9 450 IF(e) {
1050186 3:9f857750e4e9 451 goto fin;
1050186 3:9f857750e4e9 452 }
1050186 3:9f857750e4e9 453
1050186 3:9f857750e4e9 454 self->is_vsync_interrupt_registered[2] = true;
1050186 3:9f857750e4e9 455
1050186 3:9f857750e4e9 456
1050186 3:9f857750e4e9 457 if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
1050186 3:9f857750e4e9 458 config->type = VDC5_INT_TYPE_S0_VI_VSYNC;
1050186 3:9f857750e4e9 459 } else {
1050186 3:9f857750e4e9 460 config->type = VDC5_INT_TYPE_S1_VI_VSYNC;
1050186 3:9f857750e4e9 461 }
1050186 3:9f857750e4e9 462 if ( self->video_input_channel == 0 ) {
1050186 3:9f857750e4e9 463 config->callback = R_VIDEO_INPUT_OnVideoInVSync_Ch0;
1050186 3:9f857750e4e9 464
1050186 3:9f857750e4e9 465 if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
1050186 3:9f857750e4e9 466 self->interrupt_ID = BSP_INT_SRC_S0_VI_VSYNC0;
1050186 3:9f857750e4e9 467
1050186 3:9f857750e4e9 468 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 469 p_VDC5_ISR = &gs_VDC5_ISR_S0_VI_VSYNC0;
1050186 3:9f857750e4e9 470 self->interrupt_vector = InterruptCallbackVector_S0_VI_VSYNC0;
1050186 3:9f857750e4e9 471 #endif
1050186 3:9f857750e4e9 472 } else {
1050186 3:9f857750e4e9 473 self->interrupt_ID = BSP_INT_SRC_S1_VI_VSYNC0;
1050186 3:9f857750e4e9 474
1050186 3:9f857750e4e9 475 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 476 p_VDC5_ISR = &gs_VDC5_ISR_S1_VI_VSYNC0;
1050186 3:9f857750e4e9 477 self->interrupt_vector = InterruptCallbackVector_S1_VI_VSYNC0;
1050186 3:9f857750e4e9 478 #endif
1050186 3:9f857750e4e9 479 }
1050186 3:9f857750e4e9 480 } else {
1050186 3:9f857750e4e9 481 config->callback = R_VIDEO_INPUT_OnVideoInVSync_Ch1;
1050186 3:9f857750e4e9 482
1050186 3:9f857750e4e9 483 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 484 if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
1050186 3:9f857750e4e9 485 self->interrupt_ID = BSP_INT_SRC_S0_VI_VSYNC1;
1050186 3:9f857750e4e9 486
1050186 3:9f857750e4e9 487 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 488 p_VDC5_ISR = &gs_VDC5_ISR_S0_VI_VSYNC1;
1050186 3:9f857750e4e9 489 self->interrupt_vector = InterruptCallbackVector_S0_VI_VSYNC1;
1050186 3:9f857750e4e9 490 #endif
1050186 3:9f857750e4e9 491 } else {
1050186 3:9f857750e4e9 492 self->interrupt_ID = BSP_INT_SRC_S1_VI_VSYNC1;
1050186 3:9f857750e4e9 493
1050186 3:9f857750e4e9 494 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 495 p_VDC5_ISR = &gs_VDC5_ISR_S1_VI_VSYNC1;
1050186 3:9f857750e4e9 496 self->interrupt_vector = InterruptCallbackVector_S1_VI_VSYNC1;
1050186 3:9f857750e4e9 497 #endif
1050186 3:9f857750e4e9 498 }
1050186 3:9f857750e4e9 499 #endif
1050186 3:9f857750e4e9 500 }
1050186 3:9f857750e4e9 501 config->line_num = 0;
1050186 3:9f857750e4e9 502
1050186 3:9f857750e4e9 503 e_vdc5 = R_VDC5_CallbackISR( self->video_input_channel, config );
1050186 3:9f857750e4e9 504 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 505 e=E_OTHERS;
1050186 3:9f857750e4e9 506 goto fin;
1050186 3:9f857750e4e9 507 }
1050186 3:9f857750e4e9 508
1050186 3:9f857750e4e9 509 self->is_vsync_interrupt_registered[1] = true;
1050186 3:9f857750e4e9 510
1050186 3:9f857750e4e9 511
1050186 3:9f857750e4e9 512 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_LESS
1050186 3:9f857750e4e9 513 {
1050186 3:9f857750e4e9 514 vdc5_int_cb_t a_VDC5_ISR;
1050186 3:9f857750e4e9 515
1050186 3:9f857750e4e9 516 a_VDC5_ISR = R_VDC5_GetISR( self->video_input_channel, config->type );
1050186 3:9f857750e4e9 517 ret_b = R_BSP_InterruptWrite( self->interrupt_ID, a_VDC5_ISR );
1050186 3:9f857750e4e9 518 IF ( ret_b != BSP_INT_SUCCESS ) {
1050186 3:9f857750e4e9 519 e=E_OTHERS;
1050186 3:9f857750e4e9 520 goto fin;
1050186 3:9f857750e4e9 521 }
1050186 3:9f857750e4e9 522 }
1050186 3:9f857750e4e9 523 #else
1050186 3:9f857750e4e9 524 *p_VDC5_ISR = R_VDC5_GetISR( self->video_input_channel, config->type );
1050186 3:9f857750e4e9 525 ret_b = R_BSP_InterruptWrite( self->interrupt_ID, self->interrupt_vector );
1050186 3:9f857750e4e9 526 IF ( ret_b != BSP_INT_SUCCESS ) {
1050186 3:9f857750e4e9 527 e=E_OTHERS;
1050186 3:9f857750e4e9 528 goto fin;
1050186 3:9f857750e4e9 529 }
1050186 3:9f857750e4e9 530 #endif
1050186 3:9f857750e4e9 531
1050186 3:9f857750e4e9 532 self->is_vsync_interrupt_registered[0] = true;
1050186 3:9f857750e4e9 533 }
1050186 3:9f857750e4e9 534
1050186 3:9f857750e4e9 535
1050186 3:9f857750e4e9 536 #ifndef R_OSPL_NDEBUG
1050186 3:9f857750e4e9 537 printf( "VideoInput %dx%dx%dx%d stride=%d \n address[0]=0x%08X address[1]=0x%08X\n",
1050186 3:9f857750e4e9 538 frame->buffer_count, frame->width, frame->height, frame->byte_per_pixel,
1050186 3:9f857750e4e9 539 frame->stride,
1050186 3:9f857750e4e9 540 (uintptr_t) frame->buffer_address[0],
1050186 3:9f857750e4e9 541 (uintptr_t) frame->buffer_address[1] );
1050186 3:9f857750e4e9 542 /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
1050186 3:9f857750e4e9 543 #endif
1050186 3:9f857750e4e9 544
1050186 3:9f857750e4e9 545
1050186 3:9f857750e4e9 546 e=0;
1050186 3:9f857750e4e9 547 fin:
1050186 3:9f857750e4e9 548 if ( e != 0 ) {
1050186 3:9f857750e4e9 549 e= R_VIDEO_INPUT_Finalize( self, e );
1050186 3:9f857750e4e9 550 }
1050186 3:9f857750e4e9 551 return e;
1050186 3:9f857750e4e9 552 }
1050186 3:9f857750e4e9 553
1050186 3:9f857750e4e9 554
1050186 3:9f857750e4e9 555 /***********************************************************************
1050186 3:9f857750e4e9 556 * Implement: R_VIDEO_INPUT_Finalize
1050186 3:9f857750e4e9 557 ************************************************************************/
1050186 3:9f857750e4e9 558 errnum_t R_VIDEO_INPUT_Finalize( video_input_t *const self, errnum_t e )
1050186 3:9f857750e4e9 559 {
1050186 3:9f857750e4e9 560 errnum_t ee;
1050186 3:9f857750e4e9 561 vdc5_error_t e_vdc5;
1050186 3:9f857750e4e9 562 bsp_int_err_t ret_b;
1050186 3:9f857750e4e9 563
1050186 3:9f857750e4e9 564 if ( self->is_vsync_interrupt_registered[0] ) {
1050186 3:9f857750e4e9 565 ret_b = R_BSP_InterruptWrite( self->interrupt_ID, FIT_NO_FUNC );
1050186 3:9f857750e4e9 566 IF ( ret_b != BSP_INT_SUCCESS ) {
1050186 3:9f857750e4e9 567 e= R_OSPL_MergeErrNum( e, E_OTHERS );
1050186 3:9f857750e4e9 568 }
1050186 3:9f857750e4e9 569
1050186 3:9f857750e4e9 570 self->is_vsync_interrupt_registered[0] = false;
1050186 3:9f857750e4e9 571 }
1050186 3:9f857750e4e9 572
1050186 3:9f857750e4e9 573
1050186 3:9f857750e4e9 574 if ( self->is_vsync_interrupt_registered[1] ) {
1050186 3:9f857750e4e9 575 vdc5_int_t *config = &self->interrupt_for_VDC5;
1050186 3:9f857750e4e9 576
1050186 3:9f857750e4e9 577 config->callback = NULL;
1050186 3:9f857750e4e9 578 config->line_num = 0;
1050186 3:9f857750e4e9 579
1050186 3:9f857750e4e9 580 e_vdc5 = R_VDC5_CallbackISR( self->video_input_channel, config );
1050186 3:9f857750e4e9 581 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 582 e= R_OSPL_MergeErrNum( e, E_OTHERS );
1050186 3:9f857750e4e9 583 }
1050186 3:9f857750e4e9 584
1050186 3:9f857750e4e9 585 config->type = VDC5_INT_TYPE_NUM; /* Not Used interrupt type */
1050186 3:9f857750e4e9 586
1050186 3:9f857750e4e9 587 self->is_vsync_interrupt_registered[1] = false;
1050186 3:9f857750e4e9 588 }
1050186 3:9f857750e4e9 589
1050186 3:9f857750e4e9 590
1050186 3:9f857750e4e9 591 if ( self->is_vsync_interrupt_registered[2] ) {
1050186 3:9f857750e4e9 592 ee= R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
1050186 3:9f857750e4e9 593 self->video_input_channel, self->data_control_ID, self );
1050186 3:9f857750e4e9 594 e= R_OSPL_MergeErrNum( e, ee );
1050186 3:9f857750e4e9 595
1050186 3:9f857750e4e9 596 self->is_vsync_interrupt_registered[2] = false;
1050186 3:9f857750e4e9 597 }
1050186 3:9f857750e4e9 598
1050186 3:9f857750e4e9 599
1050186 3:9f857750e4e9 600 if ( self->is_data_control ) {
1050186 3:9f857750e4e9 601 e_vdc5 = R_VDC5_StopProcess( self->video_input_channel,
1050186 3:9f857750e4e9 602 self->data_control_ID );
1050186 3:9f857750e4e9 603 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 604 e= R_OSPL_MergeErrNum( e, E_OTHERS );
1050186 3:9f857750e4e9 605 }
1050186 3:9f857750e4e9 606
1050186 3:9f857750e4e9 607 e_vdc5 = R_VDC5_ReleaseDataControl( self->video_input_channel,
1050186 3:9f857750e4e9 608 self->data_control_ID );
1050186 3:9f857750e4e9 609 IF ( e_vdc5 != VDC5_OK ) {
1050186 3:9f857750e4e9 610 e= R_OSPL_MergeErrNum( e, E_OTHERS );
1050186 3:9f857750e4e9 611 }
1050186 3:9f857750e4e9 612
1050186 3:9f857750e4e9 613 self->is_data_control = false;
1050186 3:9f857750e4e9 614 }
1050186 3:9f857750e4e9 615
1050186 3:9f857750e4e9 616 return e;
1050186 3:9f857750e4e9 617 }
1050186 3:9f857750e4e9 618
1050186 3:9f857750e4e9 619
1050186 3:9f857750e4e9 620 /**
1050186 3:9f857750e4e9 621 * @brief Video input V-Sync interrupt handler.
1050186 3:9f857750e4e9 622 *
1050186 3:9f857750e4e9 623 * @param channel_num channel_num.
1050186 3:9f857750e4e9 624 * @param int_type vdc5_int_type_t.
1050186 3:9f857750e4e9 625 * @return None.
1050186 3:9f857750e4e9 626 */
1050186 3:9f857750e4e9 627 static void R_VIDEO_INPUT_OnVideoInVSync( vdc5_channel_t video_input_channel, vdc5_int_type_t int_type )
1050186 3:9f857750e4e9 628 {
1050186 3:9f857750e4e9 629 errnum_t e;
1050186 3:9f857750e4e9 630 video_input_t *self = NULL;
1050186 3:9f857750e4e9 631 /* NULL is for avoiding warning C4017W of mbed cloud compiler */
1050186 3:9f857750e4e9 632
1050186 3:9f857750e4e9 633 e= R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt( video_input_channel, int_type, &self );
1050186 3:9f857750e4e9 634 IF(e) {
1050186 3:9f857750e4e9 635 R_NOOP();
1050186 3:9f857750e4e9 636 }
1050186 3:9f857750e4e9 637 else if (
1050186 3:9f857750e4e9 638 int_type == VDC5_INT_TYPE_S0_VI_VSYNC ||
1050186 3:9f857750e4e9 639 int_type == VDC5_INT_TYPE_S1_VI_VSYNC ||
1050186 3:9f857750e4e9 640 int_type == VDC5_INT_TYPE_S0_WLINE ||
1050186 3:9f857750e4e9 641 int_type == VDC5_INT_TYPE_S1_WLINE ) {
1050186 3:9f857750e4e9 642 if ( IS_BIT_SET( VDC51.SC0_SCL1_WR7, 0x00000001u ) ) {
1050186 3:9f857750e4e9 643 self->captured_buffer_index = 0;
1050186 3:9f857750e4e9 644 } else {
1050186 3:9f857750e4e9 645 self->captured_buffer_index = 1;
1050186 3:9f857750e4e9 646 }
1050186 3:9f857750e4e9 647
1050186 3:9f857750e4e9 648 self->captured_count += 1;
1050186 3:9f857750e4e9 649
1050186 3:9f857750e4e9 650 if ( self->captured_async != NULL ) {
1050186 3:9f857750e4e9 651 R_OSPL_EVENT_Set(
1050186 3:9f857750e4e9 652 self->captured_async->A_Thread,
1050186 3:9f857750e4e9 653 self->captured_async->A_EventValue );
1050186 3:9f857750e4e9 654 }
1050186 3:9f857750e4e9 655 }
1050186 3:9f857750e4e9 656
1050186 3:9f857750e4e9 657 R_DEBUG_BREAK_IF_ERROR();
1050186 3:9f857750e4e9 658 }
1050186 3:9f857750e4e9 659
1050186 3:9f857750e4e9 660
1050186 3:9f857750e4e9 661 /**
1050186 3:9f857750e4e9 662 * @brief R_VIDEO_INPUT_OnVideoInVSync_Ch0
1050186 3:9f857750e4e9 663 *
1050186 3:9f857750e4e9 664 * @par Parameters
1050186 3:9f857750e4e9 665 * None
1050186 3:9f857750e4e9 666 * @return None.
1050186 3:9f857750e4e9 667 */
1050186 3:9f857750e4e9 668 static void R_VIDEO_INPUT_OnVideoInVSync_Ch0( vdc5_int_type_t int_type )
1050186 3:9f857750e4e9 669 {
1050186 3:9f857750e4e9 670 R_VIDEO_INPUT_OnVideoInVSync( VDC5_CHANNEL_0, int_type );
1050186 3:9f857750e4e9 671 }
1050186 3:9f857750e4e9 672
1050186 3:9f857750e4e9 673
1050186 3:9f857750e4e9 674 /**
1050186 3:9f857750e4e9 675 * @brief R_VIDEO_INPUT_OnVideoInVSync_Ch1
1050186 3:9f857750e4e9 676 *
1050186 3:9f857750e4e9 677 * @par Parameters
1050186 3:9f857750e4e9 678 * None
1050186 3:9f857750e4e9 679 * @return None.
1050186 3:9f857750e4e9 680 */
1050186 3:9f857750e4e9 681 static void R_VIDEO_INPUT_OnVideoInVSync_Ch1( vdc5_int_type_t int_type )
1050186 3:9f857750e4e9 682 {
1050186 3:9f857750e4e9 683 R_VIDEO_INPUT_OnVideoInVSync( VDC5_CHANNEL_1, int_type );
1050186 3:9f857750e4e9 684 }
1050186 3:9f857750e4e9 685
1050186 3:9f857750e4e9 686
1050186 3:9f857750e4e9 687 /**
1050186 3:9f857750e4e9 688 * @brief InterruptCallbackVector_S0_VI_VSYNC0
1050186 3:9f857750e4e9 689 *
1050186 3:9f857750e4e9 690 * @par Parameters
1050186 3:9f857750e4e9 691 * None
1050186 3:9f857750e4e9 692 * @return None.
1050186 3:9f857750e4e9 693 */
1050186 3:9f857750e4e9 694 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 695 static void InterruptCallbackVector_S0_VI_VSYNC0(void)
1050186 3:9f857750e4e9 696 {
1050186 3:9f857750e4e9 697 gs_VDC5_ISR_S0_VI_VSYNC0(0);
1050186 3:9f857750e4e9 698 GIC_EndInterrupt( BSP_INT_SRC_S0_VI_VSYNC0 );
1050186 3:9f857750e4e9 699 }
1050186 3:9f857750e4e9 700 #endif
1050186 3:9f857750e4e9 701
1050186 3:9f857750e4e9 702
1050186 3:9f857750e4e9 703 /**
1050186 3:9f857750e4e9 704 * @brief InterruptCallbackVector_S0_VI_VSYNC1
1050186 3:9f857750e4e9 705 *
1050186 3:9f857750e4e9 706 * @par Parameters
1050186 3:9f857750e4e9 707 * None
1050186 3:9f857750e4e9 708 * @return None.
1050186 3:9f857750e4e9 709 */
1050186 3:9f857750e4e9 710 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 711 static void InterruptCallbackVector_S0_VI_VSYNC1(void)
1050186 3:9f857750e4e9 712 {
1050186 3:9f857750e4e9 713 gs_VDC5_ISR_S0_VI_VSYNC1(0);
1050186 3:9f857750e4e9 714 GIC_EndInterrupt( BSP_INT_SRC_S0_VI_VSYNC1 );
1050186 3:9f857750e4e9 715 }
1050186 3:9f857750e4e9 716 #endif
1050186 3:9f857750e4e9 717
1050186 3:9f857750e4e9 718
1050186 3:9f857750e4e9 719 /**
1050186 3:9f857750e4e9 720 * @brief InterruptCallbackVector_S1_VI_VSYNC0
1050186 3:9f857750e4e9 721 *
1050186 3:9f857750e4e9 722 * @par Parameters
1050186 3:9f857750e4e9 723 * None
1050186 3:9f857750e4e9 724 * @return None.
1050186 3:9f857750e4e9 725 */
1050186 3:9f857750e4e9 726 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 727 static void InterruptCallbackVector_S1_VI_VSYNC0(void)
1050186 3:9f857750e4e9 728 {
1050186 3:9f857750e4e9 729 gs_VDC5_ISR_S1_VI_VSYNC0(0);
1050186 3:9f857750e4e9 730 GIC_EndInterrupt( BSP_INT_SRC_S1_VI_VSYNC0 );
1050186 3:9f857750e4e9 731 }
1050186 3:9f857750e4e9 732 #endif
1050186 3:9f857750e4e9 733
1050186 3:9f857750e4e9 734
1050186 3:9f857750e4e9 735 /**
1050186 3:9f857750e4e9 736 * @brief InterruptCallbackVector_S1_VI_VSYNC1
1050186 3:9f857750e4e9 737 *
1050186 3:9f857750e4e9 738 * @par Parameters
1050186 3:9f857750e4e9 739 * None
1050186 3:9f857750e4e9 740 * @return None.
1050186 3:9f857750e4e9 741 */
1050186 3:9f857750e4e9 742 #if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
1050186 3:9f857750e4e9 743 static void InterruptCallbackVector_S1_VI_VSYNC1(void)
1050186 3:9f857750e4e9 744 {
1050186 3:9f857750e4e9 745 gs_VDC5_ISR_S1_VI_VSYNC1(0);
1050186 3:9f857750e4e9 746 GIC_EndInterrupt( BSP_INT_SRC_S1_VI_VSYNC1 );
1050186 3:9f857750e4e9 747 }
1050186 3:9f857750e4e9 748 #endif
1050186 3:9f857750e4e9 749
1050186 3:9f857750e4e9 750
1050186 3:9f857750e4e9 751 /**
1050186 3:9f857750e4e9 752 * @brief R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt
1050186 3:9f857750e4e9 753 *
1050186 3:9f857750e4e9 754 * @param in_video_input_channel vdc5_channel_t.
1050186 3:9f857750e4e9 755 * @param in_data_control_ID vdc5_layer_id_t.
1050186 3:9f857750e4e9 756 * @param in_self video_input_t*
1050186 3:9f857750e4e9 757 * @return Error Code. 0=No Error.
1050186 3:9f857750e4e9 758 */
1050186 3:9f857750e4e9 759 static errnum_t R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
1050186 3:9f857750e4e9 760 vdc5_channel_t in_video_input_channel, vdc5_layer_id_t in_data_control_ID,
1050186 3:9f857750e4e9 761 video_input_t *in_self )
1050186 3:9f857750e4e9 762 {
1050186 3:9f857750e4e9 763 errnum_t e;
1050186 3:9f857750e4e9 764 video_input_t **self_pp = NULL;
1050186 3:9f857750e4e9 765 /* NULL is for avoiding warning C4017W of mbed cloud compiler */
1050186 3:9f857750e4e9 766
1050186 3:9f857750e4e9 767 e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
1050186 3:9f857750e4e9 768 in_video_input_channel, in_data_control_ID,
1050186 3:9f857750e4e9 769 &self_pp );
1050186 3:9f857750e4e9 770 IF(e) {
1050186 3:9f857750e4e9 771 goto fin;
1050186 3:9f857750e4e9 772 }
1050186 3:9f857750e4e9 773
1050186 3:9f857750e4e9 774 ASSERT_R( *self_pp == NULL, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 775
1050186 3:9f857750e4e9 776 *self_pp = in_self;
1050186 3:9f857750e4e9 777
1050186 3:9f857750e4e9 778 e=0;
1050186 3:9f857750e4e9 779 fin:
1050186 3:9f857750e4e9 780 return e;
1050186 3:9f857750e4e9 781 }
1050186 3:9f857750e4e9 782
1050186 3:9f857750e4e9 783
1050186 3:9f857750e4e9 784 /**
1050186 3:9f857750e4e9 785 * @brief R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt
1050186 3:9f857750e4e9 786 *
1050186 3:9f857750e4e9 787 * @param in_video_input_channel vdc5_channel_t.
1050186 3:9f857750e4e9 788 * @param in_data_control_ID vdc5_layer_id_t.
1050186 3:9f857750e4e9 789 * @param in_self video_input_t*
1050186 3:9f857750e4e9 790 * @return Error Code. 0=No Error.
1050186 3:9f857750e4e9 791 */
1050186 3:9f857750e4e9 792 static errnum_t R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
1050186 3:9f857750e4e9 793 vdc5_channel_t in_video_input_channel, vdc5_layer_id_t in_data_control_ID,
1050186 3:9f857750e4e9 794 video_input_t *in_self )
1050186 3:9f857750e4e9 795 {
1050186 3:9f857750e4e9 796 errnum_t e;
1050186 3:9f857750e4e9 797 video_input_t **self_pp = NULL;
1050186 3:9f857750e4e9 798 /* NULL is for avoiding warning C4017W of mbed cloud compiler */
1050186 3:9f857750e4e9 799
1050186 3:9f857750e4e9 800 e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
1050186 3:9f857750e4e9 801 in_video_input_channel, in_data_control_ID,
1050186 3:9f857750e4e9 802 &self_pp );
1050186 3:9f857750e4e9 803 IF(e) {
1050186 3:9f857750e4e9 804 goto fin;
1050186 3:9f857750e4e9 805 }
1050186 3:9f857750e4e9 806
1050186 3:9f857750e4e9 807 ASSERT_R( *self_pp == in_self, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 808
1050186 3:9f857750e4e9 809 *self_pp = NULL;
1050186 3:9f857750e4e9 810
1050186 3:9f857750e4e9 811 e=0;
1050186 3:9f857750e4e9 812 fin:
1050186 3:9f857750e4e9 813 return e;
1050186 3:9f857750e4e9 814 }
1050186 3:9f857750e4e9 815
1050186 3:9f857750e4e9 816
1050186 3:9f857750e4e9 817 /**
1050186 3:9f857750e4e9 818 * @brief R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt
1050186 3:9f857750e4e9 819 *
1050186 3:9f857750e4e9 820 * @param in_interrupt vdc5_int_type_t.
1050186 3:9f857750e4e9 821 * @param in_self video_input_t*
1050186 3:9f857750e4e9 822 * @return Error Code. 0=No Error.
1050186 3:9f857750e4e9 823 */
1050186 3:9f857750e4e9 824 static errnum_t R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt(
1050186 3:9f857750e4e9 825 vdc5_channel_t in_video_input_channel, vdc5_int_type_t in_interrupt,
1050186 3:9f857750e4e9 826 video_input_t **out_self )
1050186 3:9f857750e4e9 827 {
1050186 3:9f857750e4e9 828 errnum_t e;
1050186 3:9f857750e4e9 829 vdc5_layer_id_t data_control_ID = VDC5_LAYER_ID_0_WR;
1050186 3:9f857750e4e9 830 /* VDC5_LAYER_ID_0_WR is for avoiding warning C4017W of mbed cloud compiler */
1050186 3:9f857750e4e9 831 video_input_t **self_pp = NULL;
1050186 3:9f857750e4e9 832 /* NULL is for avoiding warning C4017W of mbed cloud compiler */
1050186 3:9f857750e4e9 833
1050186 3:9f857750e4e9 834
1050186 3:9f857750e4e9 835 switch ( in_interrupt ) {
1050186 3:9f857750e4e9 836 case VDC5_INT_TYPE_S0_VI_VSYNC:
1050186 3:9f857750e4e9 837 data_control_ID = VDC5_LAYER_ID_0_WR;
1050186 3:9f857750e4e9 838 break;
1050186 3:9f857750e4e9 839
1050186 3:9f857750e4e9 840 case VDC5_INT_TYPE_S1_VI_VSYNC:
1050186 3:9f857750e4e9 841 data_control_ID = VDC5_LAYER_ID_1_WR;
1050186 3:9f857750e4e9 842 break;
1050186 3:9f857750e4e9 843
1050186 3:9f857750e4e9 844 default:
1050186 3:9f857750e4e9 845 ASSERT_R( false, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 846 }
1050186 3:9f857750e4e9 847
1050186 3:9f857750e4e9 848
1050186 3:9f857750e4e9 849 e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
1050186 3:9f857750e4e9 850 in_video_input_channel, data_control_ID, &self_pp );
1050186 3:9f857750e4e9 851 IF(e) {
1050186 3:9f857750e4e9 852 goto fin;
1050186 3:9f857750e4e9 853 }
1050186 3:9f857750e4e9 854
1050186 3:9f857750e4e9 855 *out_self = *self_pp;
1050186 3:9f857750e4e9 856
1050186 3:9f857750e4e9 857 e=0;
1050186 3:9f857750e4e9 858 fin:
1050186 3:9f857750e4e9 859 return e;
1050186 3:9f857750e4e9 860 }
1050186 3:9f857750e4e9 861
1050186 3:9f857750e4e9 862
1050186 3:9f857750e4e9 863 /**
1050186 3:9f857750e4e9 864 * @brief R_VIDEO_INPUT_STATIC_GetSelfPointer
1050186 3:9f857750e4e9 865 *
1050186 3:9f857750e4e9 866 * @param in_video_input_channel vdc5_channel_t.
1050186 3:9f857750e4e9 867 * @param in_data_control_ID vdc5_layer_id_t.
1050186 3:9f857750e4e9 868 * @param out_self_pp video_input_t*
1050186 3:9f857750e4e9 869 * @return Error Code. 0=No Error.
1050186 3:9f857750e4e9 870 */
1050186 3:9f857750e4e9 871 static errnum_t R_VIDEO_INPUT_STATIC_GetSelfPointer(
1050186 3:9f857750e4e9 872 vdc5_channel_t in_video_input_channel, vdc5_layer_id_t in_data_control_ID,
1050186 3:9f857750e4e9 873 video_input_t *** out_self_pp )
1050186 3:9f857750e4e9 874 {
1050186 3:9f857750e4e9 875 errnum_t e;
1050186 3:9f857750e4e9 876 int_fast32_t video_input_index;
1050186 3:9f857750e4e9 877 int_fast32_t data_control_index;
1050186 3:9f857750e4e9 878
1050186 3:9f857750e4e9 879
1050186 3:9f857750e4e9 880 if ( in_video_input_channel == VDC5_CHANNEL_0 ) {
1050186 3:9f857750e4e9 881 video_input_index = 0;
1050186 3:9f857750e4e9 882 } else {
1050186 3:9f857750e4e9 883 ASSERT_D( in_video_input_channel == VDC5_CHANNEL_1, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 884
1050186 3:9f857750e4e9 885 video_input_index = 1;
1050186 3:9f857750e4e9 886 }
1050186 3:9f857750e4e9 887
1050186 3:9f857750e4e9 888 if ( in_data_control_ID == VDC5_LAYER_ID_0_WR ) {
1050186 3:9f857750e4e9 889 data_control_index = 0;
1050186 3:9f857750e4e9 890 } else {
1050186 3:9f857750e4e9 891 ASSERT_D( in_data_control_ID == VDC5_LAYER_ID_1_WR, e=E_OTHERS; goto fin );
1050186 3:9f857750e4e9 892
1050186 3:9f857750e4e9 893 data_control_index = 1;
1050186 3:9f857750e4e9 894 }
1050186 3:9f857750e4e9 895
1050186 3:9f857750e4e9 896 *out_self_pp = &gs_InterruptToSelf[ video_input_index ][ data_control_index ];
1050186 3:9f857750e4e9 897
1050186 3:9f857750e4e9 898 e=0;
1050186 3:9f857750e4e9 899 #ifndef R_OSPL_NDEBUG
1050186 3:9f857750e4e9 900 fin:
1050186 3:9f857750e4e9 901 #endif
1050186 3:9f857750e4e9 902 return e;
1050186 3:9f857750e4e9 903 }
1050186 3:9f857750e4e9 904
1050186 3:9f857750e4e9 905