r_vdc5_register.h

00001 /*******************************************************************************
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00022 *******************************************************************************/
00023 /**************************************************************************//**
00024 * @file         r_vdc5_register.h
00025 * @version      1.00
00026 * $Rev: 199 $
00027 * $Date:: 2014-05-23 16:33:52 +0900#$
00028 * @brief        VDC5 driver register setup definitions
00029 ******************************************************************************/
00030 
00031 #ifndef R_VDC5_REGISTER_H
00032 #define R_VDC5_REGISTER_H
00033 
00034 /******************************************************************************
00035 Includes   <System Includes> , "Project Includes"
00036 ******************************************************************************/
00037 #include    "r_vdc5.h"
00038 #include    "r_vdc5_user.h"
00039 
00040 
00041 /******************************************************************************
00042 Macro definitions
00043 ******************************************************************************/
00044 #define     VDC5_GAM_LUT_REG_NUM    (16u)   /*!< The number of table setting register in gamma correction block */
00045 #define     VDC5_GAM_AREA_REG_NUM   (8u)    /*!< The number of area setting register in gamma correction block */
00046 
00047 
00048 /******************************************************************************
00049 Typedef definitions
00050 ******************************************************************************/
00051 /*! VDC5 input controller register address list */
00052 typedef struct {
00053     volatile uint32_t * inp_update;
00054     volatile uint32_t * inp_sel_cnt;
00055     volatile uint32_t * inp_ext_sync_cnt;
00056     volatile uint32_t * inp_vsync_ph_adj;
00057     volatile uint32_t * inp_dly_adj;
00058     volatile uint32_t * imgcnt_update;
00059     volatile uint32_t * imgcnt_nr_cnt0;
00060     volatile uint32_t * imgcnt_nr_cnt1;
00061 } vdc5_regaddr_input_ctrl_t ;
00062 
00063 /*! VDC5 scaler register address list */
00064 typedef struct {
00065     volatile uint32_t * scl0_update;
00066     volatile uint32_t * scl0_frc1;
00067     volatile uint32_t * scl0_frc2;
00068     volatile uint32_t * scl0_frc3;
00069     volatile uint32_t * scl0_frc4;
00070     volatile uint32_t * scl0_frc5;
00071     volatile uint32_t * scl0_frc6;
00072     volatile uint32_t * scl0_frc7;
00073     volatile uint32_t * scl0_frc9;
00074     volatile uint16_t * scl0_mon0;
00075     volatile uint16_t * scl0_int;
00076     volatile uint32_t * scl0_ds1;
00077     volatile uint32_t * scl0_ds2;
00078     volatile uint32_t * scl0_ds3;
00079     volatile uint32_t * scl0_ds4;
00080     volatile uint32_t * scl0_ds5;
00081     volatile uint32_t * scl0_ds6;
00082     volatile uint32_t * scl0_ds7;
00083     volatile uint32_t * scl0_us1;
00084     volatile uint32_t * scl0_us2;
00085     volatile uint32_t * scl0_us3;
00086     volatile uint32_t * scl0_us4;
00087     volatile uint32_t * scl0_us5;
00088     volatile uint32_t * scl0_us6;
00089     volatile uint32_t * scl0_us7;
00090     volatile uint32_t * scl0_us8;
00091     volatile uint32_t * scl0_ovr1;
00092     volatile uint32_t * scl1_update;
00093     volatile uint32_t * scl1_wr1;
00094     volatile uint32_t * scl1_wr2;
00095     volatile uint32_t * scl1_wr3;
00096     volatile uint32_t * scl1_wr4;
00097     volatile uint32_t * scl1_wr5;
00098     volatile uint32_t * scl1_wr6;
00099     volatile uint32_t * scl1_wr7;
00100     volatile uint32_t * scl1_wr8;
00101     volatile uint32_t * scl1_wr9;
00102     volatile uint32_t * scl1_wr10;
00103     volatile uint32_t * scl1_wr11;
00104     volatile uint32_t * scl1_mon1;
00105     volatile uint32_t * scl1_pbuf0;
00106     volatile uint32_t * scl1_pbuf1;
00107     volatile uint32_t * scl1_pbuf2;
00108     volatile uint32_t * scl1_pbuf3;
00109     volatile uint32_t * scl1_pbuf_fld;
00110     volatile uint32_t * scl1_pbuf_cnt;
00111 } vdc5_regaddr_scaler_t ;
00112 
00113 /*! VDC5 image quality improver register address list */
00114 typedef struct {
00115     volatile uint32_t * adj_update;
00116     volatile uint32_t * adj_bkstr_set;
00117     volatile uint32_t * adj_enh_tim1;
00118     volatile uint32_t * adj_enh_tim2;
00119     volatile uint32_t * adj_enh_tim3;
00120     volatile uint32_t * adj_enh_shp1;
00121     volatile uint32_t * adj_enh_shp2;
00122     volatile uint32_t * adj_enh_shp3;
00123     volatile uint32_t * adj_enh_shp4;
00124     volatile uint32_t * adj_enh_shp5;
00125     volatile uint32_t * adj_enh_shp6;
00126     volatile uint32_t * adj_enh_lti1;
00127     volatile uint32_t * adj_enh_lti2;
00128 } vdc5_regaddr_img_qlty_imp_t ;
00129 
00130 /*! VDC5 color matrix register address list */
00131 typedef struct {
00132     volatile uint32_t * mtx_update;
00133     volatile uint32_t * mtx_mode;
00134     volatile uint32_t * mtx_yg_adj0;
00135     volatile uint32_t * mtx_yg_adj1;
00136     volatile uint32_t * mtx_cbb_adj0;
00137     volatile uint32_t * mtx_cbb_adj1;
00138     volatile uint32_t * mtx_crr_adj0;
00139     volatile uint32_t * mtx_crr_adj1;
00140 } vdc5_regaddr_color_matrix_t ;
00141 
00142 /*! VDC5 image synthesizer register address list */
00143 typedef struct {
00144     volatile uint32_t * gr_update;
00145     volatile uint32_t * gr_flm_rd;
00146     volatile uint32_t * gr_flm1;
00147     volatile uint32_t * gr_flm2;
00148     volatile uint32_t * gr_flm3;
00149     volatile uint32_t * gr_flm4;
00150     volatile uint32_t * gr_flm5;
00151     volatile uint32_t * gr_flm6;
00152     volatile uint32_t * gr_ab1;
00153     volatile uint32_t * gr_ab2;
00154     volatile uint32_t * gr_ab3;
00155     volatile uint32_t * gr_ab4;
00156     volatile uint32_t * gr_ab5;
00157     volatile uint32_t * gr_ab6;
00158     volatile uint32_t * gr_ab7;
00159     volatile uint32_t * gr_ab8;
00160     volatile uint32_t * gr_ab9;
00161     volatile uint32_t * gr_ab10;
00162     volatile uint32_t * gr_ab11;
00163     volatile uint32_t * gr_base;
00164     volatile uint32_t * gr_clut;
00165     volatile uint32_t * gr_mon;
00166 } vdc5_regaddr_img_synthesizer_t ;
00167 
00168 /*! VDC5 gamma correction register address list */
00169 typedef struct {
00170     volatile uint32_t * gam_sw;
00171     volatile uint32_t * gam_g_update;
00172     volatile uint32_t * gam_g_lut[VDC5_GAM_LUT_REG_NUM];
00173     volatile uint32_t * gam_g_area[VDC5_GAM_AREA_REG_NUM];
00174     volatile uint32_t * gam_b_update;
00175     volatile uint32_t * gam_b_lut[VDC5_GAM_LUT_REG_NUM];
00176     volatile uint32_t * gam_b_area[VDC5_GAM_AREA_REG_NUM];
00177     volatile uint32_t * gam_r_update;
00178     volatile uint32_t * gam_r_lut[VDC5_GAM_LUT_REG_NUM];
00179     volatile uint32_t * gam_r_area[VDC5_GAM_AREA_REG_NUM];
00180 } vdc5_regaddr_gamma_t ;
00181 
00182 /*! VDC5 output controller register address list */
00183 typedef struct {
00184     volatile uint32_t * tcon_update;
00185     volatile uint32_t * tcon_tim;
00186     volatile uint32_t * tcon_tim_stva1;
00187     volatile uint32_t * tcon_tim_stva2;
00188     volatile uint32_t * tcon_tim_stvb1;
00189     volatile uint32_t * tcon_tim_stvb2;
00190     volatile uint32_t * tcon_tim_sth1;
00191     volatile uint32_t * tcon_tim_sth2;
00192     volatile uint32_t * tcon_tim_stb1;
00193     volatile uint32_t * tcon_tim_stb2;
00194     volatile uint32_t * tcon_tim_cpv1;
00195     volatile uint32_t * tcon_tim_cpv2;
00196     volatile uint32_t * tcon_tim_pola1;
00197     volatile uint32_t * tcon_tim_pola2;
00198     volatile uint32_t * tcon_tim_polb1;
00199     volatile uint32_t * tcon_tim_polb2;
00200     volatile uint32_t * tcon_tim_de;
00201     volatile uint32_t * out_update;
00202     volatile uint32_t * out_set;
00203     volatile uint32_t * out_bright1;
00204     volatile uint32_t * out_bright2;
00205     volatile uint32_t * out_contrast;
00206     volatile uint32_t * out_pdtha;
00207     volatile uint32_t * out_clk_phase;
00208 } vdc5_regaddr_output_ctrl_t ;
00209 
00210 /*! VDC5 system controller register address list */
00211 typedef struct {
00212     volatile uint32_t * syscnt_int1;
00213     volatile uint32_t * syscnt_int2;
00214     volatile uint32_t * syscnt_int3;
00215     volatile uint32_t * syscnt_int4;
00216     volatile uint32_t * syscnt_int5;
00217     volatile uint32_t * syscnt_int6;
00218     volatile uint16_t * syscnt_panel_clk;
00219     volatile uint16_t * syscnt_clut;
00220 } vdc5_regaddr_system_ctrl_t ;
00221 
00222 /*! LVDS register address list */
00223 typedef struct {
00224     volatile uint32_t * lvds_update;
00225     volatile uint32_t * lvdsfcl;
00226     volatile uint32_t * lclkselr;
00227     volatile uint32_t * lpllsetr;
00228     volatile uint32_t * lphyacc;
00229 } vdc5_regaddr_lvds_t ;
00230 
00231 
00232 /******************************************************************************
00233 Variable Externs
00234 ******************************************************************************/
00235 extern const vdc5_regaddr_input_ctrl_t       vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM ];
00236 extern const vdc5_regaddr_scaler_t           vdc5_regaddr_scaler[VDC5_CHANNEL_NUM ][VDC5_SC_TYPE_NUM ];
00237 extern const vdc5_regaddr_img_qlty_imp_t     vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM ][VDC5_IMG_IMPRV_NUM ];
00238 extern const vdc5_regaddr_color_matrix_t     vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM ][VDC5_COLORMTX_NUM];
00239 extern const vdc5_regaddr_img_synthesizer_t  vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM ][VDC5_GR_TYPE_NUM ];
00240 extern uint32_t                     * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM ][VDC5_GR_TYPE_NUM ];
00241 extern const vdc5_regaddr_output_ctrl_t      vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM ];
00242 extern const vdc5_regaddr_gamma_t            vdc5_regaddr_gamma[VDC5_CHANNEL_NUM ];
00243 extern const vdc5_regaddr_system_ctrl_t      vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM ];
00244 extern const vdc5_regaddr_lvds_t             vdc5_regaddr_lvds;
00245 
00246 
00247 /******************************************************************************
00248 Functions Prototypes
00249 ******************************************************************************/
00250 void VDC5_Initialize(const vdc5_channel_t  ch, const vdc5_init_t  * const param);
00251 void VDC5_Terminate(const vdc5_channel_t  ch);
00252 void VDC5_VideoInput(const vdc5_channel_t  ch, const vdc5_input_t  * const param);
00253 void VDC5_SyncControl(const vdc5_channel_t  ch, const vdc5_sync_ctrl_t  * const param);
00254 void VDC5_DisplayOutput(const vdc5_channel_t  ch, const vdc5_output_t  * const param);
00255 void VDC5_WriteDataControl(
00256     const vdc5_channel_t         ch,
00257     const vdc5_scaling_type_t    scaling_id,
00258     const vdc5_write_t   * const param);
00259 void VDC5_ChangeWriteProcess(
00260     const vdc5_channel_t             ch,
00261     const vdc5_scaling_type_t        scaling_id,
00262     const vdc5_write_chg_t   * const param);
00263 void VDC5_ReadDataControl(
00264     const vdc5_channel_t         ch,
00265     const vdc5_graphics_type_t   graphics_id,
00266     const vdc5_read_t    * const param);
00267 void VDC5_ChangeReadProcess(
00268     const vdc5_channel_t             ch,
00269     const vdc5_graphics_type_t       graphics_id,
00270     const vdc5_read_chg_t    * const param);
00271 void VDC5_StartProcess(const vdc5_channel_t  ch, const vdc5_layer_id_t  layer_id, const vdc5_start_t  * const param);
00272 void VDC5_StopProcess(const vdc5_channel_t  ch, const vdc5_layer_id_t  layer_id);
00273 void VDC5_ReleaseDataControl(const vdc5_channel_t  ch, const vdc5_layer_id_t  layer_id);
00274 void VDC5_VideoNoiseReduction(
00275     const vdc5_channel_t                     ch,
00276     const vdc5_onoff_t                       nr1d_on,
00277     const vdc5_noise_reduction_t     * const param);
00278 void VDC5_ImageColorMatrix(const vdc5_channel_t  ch, const vdc5_color_matrix_t  * const param);
00279 void VDC5_ImageEnhancement(
00280     const vdc5_channel_t                 ch,
00281     const vdc5_imgimprv_id_t             imgimprv_id,
00282     const vdc5_onoff_t                   shp_h_on,
00283     const vdc5_enhance_sharp_t   * const sharp_param,
00284     const vdc5_onoff_t                   lti_h_on,
00285     const vdc5_enhance_lti_t     * const lti_param,
00286     const vdc5_period_rect_t     * const enh_area);
00287 void VDC5_ImageBlackStretch(
00288     const vdc5_channel_t         ch,
00289     const vdc5_imgimprv_id_t     imgimprv_id,
00290     const vdc5_onoff_t           bkstr_on,
00291     const vdc5_black_t   * const param);
00292 void VDC5_AlphaBlending(
00293     const vdc5_channel_t                 ch,
00294     const vdc5_graphics_type_t           graphics_id,
00295     const vdc5_alpha_blending_t  * const param);
00296 void VDC5_AlphaBlendingRect(
00297     const vdc5_channel_t                         ch,
00298     const vdc5_graphics_type_t                   graphics_id,
00299     const vdc5_onoff_t                           gr_arc_on,
00300     const vdc5_alpha_blending_rect_t     * const param);
00301 void VDC5_Chromakey(
00302     const vdc5_channel_t             ch,
00303     const vdc5_graphics_type_t       graphics_id,
00304     const vdc5_onoff_t               gr_ck_on,
00305     const vdc5_chromakey_t   * const param);
00306 void VDC5_CLUT(const vdc5_channel_t  ch, const vdc5_graphics_type_t  graphics_id, const vdc5_clut_t  * const param);
00307 void VDC5_DisplayCalibration(const vdc5_channel_t  ch, const vdc5_disp_calibration_t  * const param);
00308 void VDC5_GammaCorrection(
00309     const vdc5_channel_t                     ch,
00310     const vdc5_onoff_t                       gam_on,
00311     const vdc5_gamma_correction_t    * const param);
00312 
00313 void VDC5_Int_Disable(const vdc5_channel_t  ch);
00314 void VDC5_Int_SetInterrupt(const vdc5_channel_t  ch, const vdc5_int_t  * const param);
00315 
00316 
00317 #endif  /* R_VDC5_REGISTER_H */
00318