Video library for GR-PEACH
Dependents: Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more
lcd_analog_rgb_ch1.h
00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file lcd_analog_rgb_ch1.h 00025 * @version 1.00 00026 * $Rev: 199 $ 00027 * $Date:: 2014-05-23 16:33:52 +0900#$ 00028 * @brief LCD panel for vdc5 channel 1 definition header 00029 ******************************************************************************/ 00030 00031 #ifndef LCD_ANALOG_RGB_CH1_H 00032 #define LCD_ANALOG_RGB_CH1_H 00033 00034 #ifndef LCD_PANEL_H 00035 #error Do not include this file directly! 00036 #else 00037 /****************************************************************************** 00038 Includes <System Includes> , "Project Includes" 00039 ******************************************************************************/ 00040 #include <stdlib.h> 00041 00042 #include "r_typedefs.h" 00043 00044 #include "r_vdc5.h" 00045 00046 #include "lcd_analog_rgb.h" 00047 00048 00049 /****************************************************************************** 00050 Macro definitions 00051 ******************************************************************************/ 00052 /* Option board (part number: RTK7721000B00000BR) 00053 ADV7123 (Video DAC), U10 00054 Analog RGB D-sub15 (RGB888), J16 */ 00055 #define LCD_CH1_S_HSYNC (0u) /* Hsync start position */ 00056 #define LCD_CH1_W_HSYNC (LCD_SVGA_H_SYNC_WIDTH) /* Hsync width */ 00057 #define LCD_CH1_POL_HSYNC (LCD_SVGA_H_POLARITY) /* Polarity of Hsync pulse */ 00058 /* LCD display area size, horizontal start position */ 00059 #define LCD_CH1_DISP_HS (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH) 00060 #define LCD_CH1_DISP_HW (LCD_SVGA_H_VISIBLE_AREA) /* LCD display area size, horizontal width */ 00061 00062 /* Vsync start position */ 00063 #define LCD_CH1_S_VSYNC (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH) 00064 #define LCD_CH1_W_VSYNC (LCD_SVGA_V_SYNC_WIDTH) /* Vsync width */ 00065 #define LCD_CH1_POL_VSYNC (LCD_SVGA_V_POLARITY) /* Polarity of Vsync pulse */ 00066 #define LCD_CH1_DISP_VS (LCD_SVGA_V_BACK_PORCH) /* LCD display area size, vertical start position */ 00067 #define LCD_CH1_DISP_VW (LCD_SVGA_V_VISIBLE_AREA) /* LCD display area size, height (vertical width) */ 00068 00069 #define LCD_CH1_SIG_FV (LCD_SVGA_V_TOTAL - 1u) /* Free-running Vsync period */ 00070 #define LCD_CH1_SIG_FH (LCD_SVGA_H_TOTAL - 1u) /* Hsync period */ 00071 /* Pixel data is latched in the rising edge of pixel clock on ADV7123. 00072 Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */ 00073 #define LCD_CH1_OUT_EDGE VDC5_EDGE_FALLING /* Output phase control of LCD_DATA[23:0] signal */ 00074 #define LCD_CH1_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB888 /* LCD output format select */ 00075 00076 #define LCD_CH1_PANEL_CLK VDC5_PANEL_ICKSEL_LVDS /* Panel clock select */ 00077 #define LCD_CH1_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_1 /* Panel clock frequency division ratio */ 00078 00079 #define LCD_CH1_TCON_HALF (LCD_CH1_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */ 00080 #define LCD_CH1_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */ 00081 00082 00083 /****************************************************************************** 00084 Typedef definitions 00085 ******************************************************************************/ 00086 00087 /****************************************************************************** 00088 Exported global functions (to be accessed by other files) 00089 ******************************************************************************/ 00090 void GRAPHICS_SetLcdPanel_Ch1(void); 00091 void GRAPHICS_SetLcdTconSettings_Ch1(const vdc5_lcd_tcon_timing_t * * const outctrl); 00092 00093 00094 #endif /* LCD_PANEL_H not defined */ 00095 #endif /* LCD_ANALOG_RGB_CH1_H */
Generated on Tue Jul 12 2022 15:08:46 by 1.7.2