Data Structures |
| struct | vdc5_period_rect_t |
| struct | vdc5_pd_disp_rect_t |
| struct | vdc5_lvds_t |
| struct | vdc5_init_t |
| struct | vdc5_sync_delay_t |
| struct | vdc5_ext_in_sig_t |
| struct | vdc5_input_t |
| struct | vdc5_vsync_cpmpe_t |
| struct | vdc5_sync_ctrl_t |
| struct | vdc5_lcd_tcon_timing_t |
| struct | vdc5_output_t |
| struct | vdc5_int_t |
| struct | vdc5_scalingdown_rot_t |
| struct | vdc5_write_t |
| struct | vdc5_write_chg_t |
| struct | vdc5_width_read_fb_t |
| struct | vdc5_read_t |
| struct | vdc5_read_chg_t |
| struct | vdc5_start_t |
| struct | vdc5_nr_param_t |
| struct | vdc5_noise_reduction_t |
| struct | vdc5_color_matrix_t |
| struct | vdc5_sharpness_ctrl_t |
| struct | vdc5_enhance_sharp_t |
| struct | vdc5_lti_ctrl_t |
| struct | vdc5_enhance_lti_t |
| struct | vdc5_black_t |
| struct | vdc5_alpha_argb1555_t |
| struct | vdc5_alpha_pixel_t |
| struct | vdc5_alpha_blending_t |
| struct | vdc5_alpha_rect_t |
| struct | vdc5_scl_und_sel_t |
| struct | vdc5_alpha_blending_rect_t |
| struct | vdc5_chromakey_t |
| struct | vdc5_clut_t |
| struct | vdc5_calibr_bright_t |
| struct | vdc5_calibr_contrast_t |
| struct | vdc5_calibr_dither_t |
| struct | vdc5_disp_calibration_t |
| struct | vdc5_gamma_correction_t |
Enumerations |
| enum | vdc5_error_t {
VDC5_OK = 0,
VDC5_ERR_PARAM_CHANNEL,
VDC5_ERR_PARAM_LAYER_ID,
VDC5_ERR_PARAM_NULL,
VDC5_ERR_PARAM_BIT_WIDTH,
VDC5_ERR_PARAM_UNDEFINED,
VDC5_ERR_PARAM_EXCEED_RANGE,
VDC5_ERR_PARAM_CONDITION,
VDC5_ERR_IF_CONDITION,
VDC5_ERR_RESOURCE_CLK,
VDC5_ERR_RESOURCE_VSYNC,
VDC5_ERR_RESOURCE_INPUT,
VDC5_ERR_RESOURCE_OUTPUT,
VDC5_ERR_RESOURCE_LVDS_CLK,
VDC5_ERR_RESOURCE_LAYER,
VDC5_ERR_NUM
} |
| enum | vdc5_channel_t { VDC5_CHANNEL_0 = 0,
VDC5_CHANNEL_1,
VDC5_CHANNEL_NUM
} |
| enum | vdc5_onoff_t { VDC5_OFF = 0,
VDC5_ON = 1
} |
| enum | vdc5_edge_t { VDC5_EDGE_RISING = 0,
VDC5_EDGE_FALLING = 1
} |
| enum | vdc5_sig_pol_t { VDC5_SIG_POL_NOT_INVERTED = 0,
VDC5_SIG_POL_INVERTED = 1
} |
| enum | vdc5_scaling_type_t { VDC5_SC_TYPE_SC0 = 0,
VDC5_SC_TYPE_SC1,
VDC5_SC_TYPE_OIR,
VDC5_SC_TYPE_NUM
} |
| enum | vdc5_graphics_type_t {
VDC5_GR_TYPE_GR0 = 0,
VDC5_GR_TYPE_GR1,
VDC5_GR_TYPE_GR2,
VDC5_GR_TYPE_GR3,
VDC5_GR_TYPE_VIN,
VDC5_GR_TYPE_OIR,
VDC5_GR_TYPE_NUM
} |
| enum | vdc5_layer_id_t {
VDC5_LAYER_ID_ALL = -1,
VDC5_LAYER_ID_0_WR = (VDC5_SC_TYPE_SC0 + 0),
VDC5_LAYER_ID_1_WR = (VDC5_SC_TYPE_SC1 + 0),
VDC5_LAYER_ID_OIR_WR = (VDC5_SC_TYPE_OIR + 0),
VDC5_LAYER_ID_0_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR0),
VDC5_LAYER_ID_1_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR1),
VDC5_LAYER_ID_2_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR2),
VDC5_LAYER_ID_3_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR3),
VDC5_LAYER_ID_VIN_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_VIN),
VDC5_LAYER_ID_OIR_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_OIR),
VDC5_LAYER_ID_NUM = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_NUM)
} |
| enum | vdc5_panel_clksel_t {
VDC5_PANEL_ICKSEL_IMG = 0,
VDC5_PANEL_ICKSEL_IMG_DV,
VDC5_PANEL_ICKSEL_EXT_0,
VDC5_PANEL_ICKSEL_EXT_1,
VDC5_PANEL_ICKSEL_PERI,
VDC5_PANEL_ICKSEL_LVDS,
VDC5_PANEL_ICKSEL_LVDS_DIV7,
VDC5_PANEL_ICKSEL_NUM
} |
| enum | vdc5_panel_clk_dcdr_t {
VDC5_PANEL_CLKDIV_1_1 = 0,
VDC5_PANEL_CLKDIV_1_2,
VDC5_PANEL_CLKDIV_1_3,
VDC5_PANEL_CLKDIV_1_4,
VDC5_PANEL_CLKDIV_1_5,
VDC5_PANEL_CLKDIV_1_6,
VDC5_PANEL_CLKDIV_1_7,
VDC5_PANEL_CLKDIV_1_8,
VDC5_PANEL_CLKDIV_1_9,
VDC5_PANEL_CLKDIV_1_12,
VDC5_PANEL_CLKDIV_1_16,
VDC5_PANEL_CLKDIV_1_24,
VDC5_PANEL_CLKDIV_1_32,
VDC5_PANEL_CLKDIV_NUM
} |
| enum | vdc5_lvds_in_clk_sel_t {
VDC5_LVDS_INCLK_SEL_IMG = 0,
VDC5_LVDS_INCLK_SEL_DV_0,
VDC5_LVDS_INCLK_SEL_DV_1,
VDC5_LVDS_INCLK_SEL_EXT_0,
VDC5_LVDS_INCLK_SEL_EXT_1,
VDC5_LVDS_INCLK_SEL_PERI
} |
| enum | vdc5_lvds_ndiv_t { VDC5_LVDS_NDIV_1 = 0,
VDC5_LVDS_NDIV_2,
VDC5_LVDS_NDIV_4
} |
| enum | vdc5_lvds_pll_nod_t { VDC5_LVDS_PLL_NOD_1 = 0,
VDC5_LVDS_PLL_NOD_2,
VDC5_LVDS_PLL_NOD_4,
VDC5_LVDS_PLL_NOD_8
} |
| enum | vdc5_input_sel_t { VDC5_INPUT_SEL_VDEC = 0,
VDC5_INPUT_SEL_EXT = 1
} |
| enum | vdc5_extin_format_t {
VDC5_EXTIN_FORMAT_RGB888 = 0,
VDC5_EXTIN_FORMAT_RGB666,
VDC5_EXTIN_FORMAT_RGB565,
VDC5_EXTIN_FORMAT_BT656,
VDC5_EXTIN_FORMAT_BT601,
VDC5_EXTIN_FORMAT_YCBCR422,
VDC5_EXTIN_FORMAT_YCBCR444
} |
| enum | vdc5_extin_ref_hsync_t { VDC5_EXTIN_REF_H_EAV = 0,
VDC5_EXTIN_REF_H_SAV = 1
} |
| enum | vdc5_extin_input_line_t { VDC5_EXTIN_LINE_525 = 0,
VDC5_EXTIN_LINE_625 = 1
} |
| enum | vdc5_extin_h_pos_t { VDC5_EXTIN_H_POS_CBYCRY = 0,
VDC5_EXTIN_H_POS_YCRYCB,
VDC5_EXTIN_H_POS_CRYCBY,
VDC5_EXTIN_H_POS_YCBYCR
} |
| enum | vdc5_res_vs_in_sel_t { VDC5_RES_VS_IN_SEL_SC0 = 0,
VDC5_RES_VS_IN_SEL_SC1 = 1
} |
| enum | vdc5_lcd_tcon_polmode_t { VDC5_LCD_TCON_POLMD_NORMAL = 0,
VDC5_LCD_TCON_POLMD_1X1REV,
VDC5_LCD_TCON_POLMD_1X2REV,
VDC5_LCD_TCON_POLMD_2X2REV
} |
| enum | vdc5_lcd_tcon_refsel_t { VDC5_LCD_TCON_REFSEL_HSYNC = 0,
VDC5_LCD_TCON_REFSEL_OFFSET_H = 1
} |
| enum | vdc5_lcd_tcon_pin_t {
VDC5_LCD_TCON_PIN_NON = -1,
VDC5_LCD_TCON_PIN_0,
VDC5_LCD_TCON_PIN_1,
VDC5_LCD_TCON_PIN_2,
VDC5_LCD_TCON_PIN_3,
VDC5_LCD_TCON_PIN_4,
VDC5_LCD_TCON_PIN_5,
VDC5_LCD_TCON_PIN_6
} |
| enum | vdc5_lcd_tcon_sigsel_t {
VDC5_LCD_TCONSIG_STVA_VS = 0,
VDC5_LCD_TCONSIG_STVB_VE,
VDC5_LCD_TCONSIG_STH_SP_HS,
VDC5_LCD_TCONSIG_STB_LP_HE,
VDC5_LCD_TCONSIG_CPV_GCK,
VDC5_LCD_TCONSIG_POLA,
VDC5_LCD_TCONSIG_POLB,
VDC5_LCD_TCONSIG_DE
} |
| enum | vdc5_lcd_outformat_t { VDC5_LCD_OUTFORMAT_RGB888 = 0,
VDC5_LCD_OUTFORMAT_RGB666,
VDC5_LCD_OUTFORMAT_RGB565,
VDC5_LCD_OUTFORMAT_SERIAL_RGB
} |
| enum | vdc5_lcd_clkfreqsel_t { VDC5_LCD_PARALLEL_CLKFRQ_1 = 0,
VDC5_LCD_SERIAL_CLKFRQ_3,
VDC5_LCD_SERIAL_CLKFRQ_4
} |
| enum | vdc5_lcd_scan_t { VDC5_LCD_SERIAL_SCAN_FORWARD = 0,
VDC5_LCD_SERIAL_SCAN_REVERSE = 1
} |
| enum | vdc5_lcd_clkphase_t { VDC5_LCD_SERIAL_CLKPHASE_0 = 0,
VDC5_LCD_SERIAL_CLKPHASE_1,
VDC5_LCD_SERIAL_CLKPHASE_2,
VDC5_LCD_SERIAL_CLKPHASE_3
} |
| enum | vdc5_int_type_t {
VDC5_INT_TYPE_S0_VI_VSYNC = 0,
VDC5_INT_TYPE_S0_LO_VSYNC,
VDC5_INT_TYPE_S0_VSYNCERR,
VDC5_INT_TYPE_VLINE,
VDC5_INT_TYPE_S0_VFIELD,
VDC5_INT_TYPE_IV1_VBUFERR,
VDC5_INT_TYPE_IV3_VBUFERR,
VDC5_INT_TYPE_IV5_VBUFERR,
VDC5_INT_TYPE_IV6_VBUFERR,
VDC5_INT_TYPE_S0_WLINE,
VDC5_INT_TYPE_S1_VI_VSYNC,
VDC5_INT_TYPE_S1_LO_VSYNC,
VDC5_INT_TYPE_S1_VSYNCERR,
VDC5_INT_TYPE_S1_VFIELD,
VDC5_INT_TYPE_IV2_VBUFERR,
VDC5_INT_TYPE_IV4_VBUFERR,
VDC5_INT_TYPE_S1_WLINE,
VDC5_INT_TYPE_OIR_VI_VSYNC,
VDC5_INT_TYPE_OIR_LO_VSYNC,
VDC5_INT_TYPE_OIR_VLINE,
VDC5_INT_TYPE_OIR_VFIELD,
VDC5_INT_TYPE_IV7_VBUFERR,
VDC5_INT_TYPE_IV8_VBUFERR,
VDC5_INT_TYPE_NUM
} |
| enum | vdc5_wr_md_t {
VDC5_WR_MD_NORMAL = 0,
VDC5_WR_MD_MIRROR,
VDC5_WR_MD_ROT_90DEG,
VDC5_WR_MD_ROT_180DEG,
VDC5_WR_MD_ROT_270DEG
} |
| enum | vdc5_wr_rd_swa_t {
VDC5_WR_RD_WRSWA_NON = 0,
VDC5_WR_RD_WRSWA_8BIT,
VDC5_WR_RD_WRSWA_16BIT,
VDC5_WR_RD_WRSWA_16_8BIT,
VDC5_WR_RD_WRSWA_32BIT,
VDC5_WR_RD_WRSWA_32_8BIT,
VDC5_WR_RD_WRSWA_32_16BIT,
VDC5_WR_RD_WRSWA_32_16_8BIT
} |
| enum | vdc5_res_md_t { VDC5_RES_MD_YCBCR422 = 0,
VDC5_RES_MD_RGB565,
VDC5_RES_MD_RGB888,
VDC5_RES_MD_YCBCR444
} |
| enum | vdc5_bst_md_t { VDC5_BST_MD_32BYTE = 0,
VDC5_BST_MD_128BYTE
} |
| enum | vdc5_res_inter_t { VDC5_RES_INTER_PROGRESSIVE = 0,
VDC5_RES_INTER_INTERLACE = 1
} |
| enum | vdc5_res_fs_rate_t |
| enum | vdc5_res_fld_sel_t { VDC5_RES_FLD_SEL_TOP = 0,
VDC5_RES_FLD_SEL_BOTTOM = 1
} |
| enum | vdc5_gr_ln_off_dir_t { VDC5_GR_LN_OFF_DIR_INC = 0,
VDC5_GR_LN_OFF_DIR_DEC
} |
| enum | vdc5_gr_flm_sel_t { VDC5_GR_FLM_SEL_SCALE_DOWN = 0,
VDC5_GR_FLM_SEL_FLM_NUM,
VDC5_GR_FLM_SEL_DISTORTION,
VDC5_GR_FLM_SEL_POINTER_BUFF
} |
| enum | vdc5_gr_format_t {
VDC5_GR_FORMAT_RGB565 = 0,
VDC5_GR_FORMAT_RGB888,
VDC5_GR_FORMAT_ARGB1555,
VDC5_GR_FORMAT_ARGB4444,
VDC5_GR_FORMAT_ARGB8888,
VDC5_GR_FORMAT_CLUT8,
VDC5_GR_FORMAT_CLUT4,
VDC5_GR_FORMAT_CLUT1,
VDC5_GR_FORMAT_YCBCR422,
VDC5_GR_FORMAT_YCBCR444,
VDC5_GR_FORMAT_RGBA5551,
VDC5_GR_FORMAT_RGBA8888,
VDC5_GR_FORMAT_NUM
} |
| enum | vdc5_gr_ycc_swap_t |
| enum | vdc5_gr_disp_sel_t {
VDC5_DISPSEL_IGNORED = -1,
VDC5_DISPSEL_BACK = 0,
VDC5_DISPSEL_LOWER = 1,
VDC5_DISPSEL_CURRENT = 2,
VDC5_DISPSEL_BLEND = 3,
VDC5_DISPSEL_NUM = 4
} |
| enum | vdc5_nr_tap_t { VDC5_NR_TAPSEL_1 = 0,
VDC5_NR_TAPSEL_2,
VDC5_NR_TAPSEL_3,
VDC5_NR_TAPSEL_4
} |
| enum | vdc5_nr_gain_t { VDC5_NR_GAIN_1_2 = 0,
VDC5_NR_GAIN_1_4,
VDC5_NR_GAIN_1_8,
VDC5_NR_GAIN_1_16
} |
| enum | vdc5_colormtx_module_t { VDC5_COLORMTX_IMGCNT = 0,
VDC5_COLORMTX_ADJ_0,
VDC5_COLORMTX_ADJ_1
} |
| enum | vdc5_colormtx_mode_t {
VDC5_COLORMTX_GBR_GBR = 0,
VDC5_COLORMTX_GBR_YCBCR,
VDC5_COLORMTX_YCBCR_GBR,
VDC5_COLORMTX_YCBCR_YCBCR,
VDC5_COLORMTX_MODE_NUM
} |
| enum | vdc5_colormtx_offset_t { VDC5_COLORMTX_OFFST_YG = 0,
VDC5_COLORMTX_OFFST_B,
VDC5_COLORMTX_OFFST_R,
VDC5_COLORMTX_OFFST_NUM
} |
| enum | vdc5_colormtx_gain_t {
VDC5_COLORMTX_GAIN_GG = 0,
VDC5_COLORMTX_GAIN_GB,
VDC5_COLORMTX_GAIN_GR,
VDC5_COLORMTX_GAIN_BG,
VDC5_COLORMTX_GAIN_BB,
VDC5_COLORMTX_GAIN_BR,
VDC5_COLORMTX_GAIN_RG,
VDC5_COLORMTX_GAIN_RB,
VDC5_COLORMTX_GAIN_RR,
VDC5_COLORMTX_GAIN_NUM
} |
| enum | vdc5_imgimprv_id_t { VDC5_IMG_IMPRV_0 = 0,
VDC5_IMG_IMPRV_1,
VDC5_IMG_IMPRV_NUM
} |
| enum | vdc5_img_enh_sh_t { VDC5_IMGENH_SHARP_H1 = 0,
VDC5_IMGENH_SHARP_H2,
VDC5_IMGENH_SHARP_H3,
VDC5_IMGENH_SHARP_NUM
} |
| enum | vdc5_img_enh_lti_t { VDC5_IMGENH_LTI1 = 0,
VDC5_IMGENH_LTI2,
VDC5_IMGENH_LTI_NUM
} |
| enum | vdc5_lti_mdfil_sel_t { VDC5_LTI_MDFIL_SEL_ADJ2 = 0,
VDC5_LTI_MDFIL_SEL_ADJ1
} |
| enum | vdc5_calibr_route_t { VDC5_CALIBR_ROUTE_BCG = 0,
VDC5_CALIBR_ROUTE_GBC
} |
| enum | vdc5_panel_dither_md_t { VDC5_PDTH_MD_TRU = 0,
VDC5_PDTH_MD_RDOF,
VDC5_PDTH_MD_2X2,
VDC5_PDTH_MD_RAND
} |
Functions |
| vdc5_error_t | R_VDC5_Initialize (const vdc5_channel_t ch, const vdc5_init_t *const param, void(*const init_func)(uint32_t), const uint32_t user_num) |
| | VDC5 driver initialization.
|
| vdc5_error_t | R_VDC5_Terminate (const vdc5_channel_t ch, void(*const quit_func)(uint32_t), const uint32_t user_num) |
| | VDC5 driver termination.
|
| vdc5_error_t | R_VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t *const param) |
| | Video input setup.
|
| vdc5_error_t | R_VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t *const param) |
| | Sync control setup.
|
| vdc5_error_t | R_VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t *const param) |
| | Display output setup.
|
| vdc5_error_t | R_VDC5_CallbackISR (const vdc5_channel_t ch, const vdc5_int_t *const param) |
| | Interrupt callback setup.
|
| vdc5_error_t | R_VDC5_WriteDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_write_t *const param) |
| | Data write control processing.
|
| vdc5_error_t | R_VDC5_ChangeWriteProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_write_chg_t *const param) |
| | Data write change processing.
|
| vdc5_error_t | R_VDC5_ReadDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_read_t *const param) |
| | Data read control processing.
|
| vdc5_error_t | R_VDC5_ChangeReadProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_read_chg_t *const param) |
| | Data read change processing.
|
| vdc5_error_t | R_VDC5_StartProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t *const param) |
| | Data write/read start processing.
|
| vdc5_error_t | R_VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id) |
| | Data write/read stop processing.
|
| vdc5_error_t | R_VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id) |
| | Data write/read control release processing.
|
| vdc5_error_t | R_VDC5_VideoNoiseReduction (const vdc5_channel_t ch, const vdc5_onoff_t nr1d_on, const vdc5_noise_reduction_t *const param) |
| | Noise reduction setup.
|
| vdc5_error_t | R_VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t *const param) |
| | Color matrix setup.
|
| vdc5_error_t | R_VDC5_ImageEnhancement (const vdc5_channel_t ch, const vdc5_imgimprv_id_t imgimprv_id, const vdc5_onoff_t shp_h_on, const vdc5_enhance_sharp_t *const sharp_param, const vdc5_onoff_t lti_h_on, const vdc5_enhance_lti_t *const lti_param, const vdc5_period_rect_t *const enh_area) |
| | Image enhancement processing.
|
| vdc5_error_t | R_VDC5_ImageBlackStretch (const vdc5_channel_t ch, const vdc5_imgimprv_id_t imgimprv_id, const vdc5_onoff_t bkstr_on, const vdc5_black_t *const param) |
| | Black stretch setup.
|
| vdc5_error_t | R_VDC5_AlphaBlending (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_alpha_blending_t *const param) |
| | Alpha blending setup.
|
| vdc5_error_t | R_VDC5_AlphaBlendingRect (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_onoff_t gr_arc_on, const vdc5_alpha_blending_rect_t *const param) |
| | Rectangle alpha blending setup.
|
| vdc5_error_t | R_VDC5_Chromakey (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_onoff_t gr_ck_on, const vdc5_chromakey_t *const param) |
| | Chroma-key setup.
|
| vdc5_error_t | R_VDC5_CLUT (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t *const param) |
| | CLUT setup.
|
| vdc5_error_t | R_VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t *const param) |
| | Display calibration processing.
|
| vdc5_error_t | R_VDC5_GammaCorrection (const vdc5_channel_t ch, const vdc5_onoff_t gam_on, const vdc5_gamma_correction_t *const param) |
| | Gamma correction setup.
|
Renesas
1.7.2