Renesas / GR-PEACH_video

Video library for GR-PEACH

Dependents:   Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more

Video ｌibrary for GR-PEACH.

Hello World!

Import programGR-PEACH_Camera_in

Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.

Last commit 28 Dec 2018 by Renesas

API

Import library
GR-PEACH_video - DisplayBase Class Reference

Data Structures

struct lcd_config_t
LCD configuration. More...
struct rect_t
The relative position within the graphics display area. More...
struct video_ext_in_config_t
Digital Video Input configuration. More...

Public Types

enum video_input_channel_t { VIDEO_INPUT_CHANNEL_0 = 0, VIDEO_INPUT_CHANNEL_1 }

Video input channel select.

More...
enum graphics_layer_t { GRAPHICS_LAYER_0 = 0, GRAPHICS_LAYER_1 , GRAPHICS_LAYER_2 , GRAPHICS_LAYER_3 }

Graphics layer select.

More...
enum graphics_error_t {
GRAPHICS_OK = 0, GRAPHICS_VDC5_ERR = -1, GRAPHICS_FORMA_ERR = -2, GRAPHICS_LAYER_ERR = -3,
GRAPHICS_CHANNLE_ERR = -4, GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, GRAPHICS_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum graphics_format_t { GRAPHICS_FORMAT_YCBCR422 = 0, GRAPHICS_FORMAT_RGB565 , GRAPHICS_FORMAT_RGB888 , GRAPHICS_FORMAT_ARGB8888 }

Graphics layer read format selects.

More...
enum video_format_t { VIDEO_FORMAT_YCBCR422 = 0, VIDEO_FORMAT_RGB565 , VIDEO_FORMAT_RGB888 }

Video writing format selects.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT , WR_RD_WRSWA_16BIT , WR_RD_WRSWA_16_8BIT ,
WR_RD_WRSWA_32BIT , WR_RD_WRSWA_32_8BIT , WR_RD_WRSWA_32_16BIT , WR_RD_WRSWA_32_16_8BIT
}

Frame buffer swap setting.

More...
enum lcd_tcon_pin_t { LCD_TCON_PIN_NON = -1, LCD_TCON_PIN_0 , LCD_TCON_PIN_1 , LCD_TCON_PIN_2 }

LCD tcon output pin selects.

More...
enum lcd_outformat_t { LCD_OUTFORMAT_RGB888 = 0, LCD_OUTFORMAT_RGB666 , LCD_OUTFORMAT_RGB565 }

LCD output format selects.

More...
enum edge_t { EDGE_RISING = 0, EDGE_FALLING = 1 }

Edge of a signal.

More...
enum lcd_type_t { LCD_TYPE_LVDS = 0, LCD_TYPE_PARALLEL_RGB }

LCD type.

More...
enum sig_pol_t { SIG_POL_NOT_INVERTED = 0, SIG_POL_INVERTED }

Polarity of a signal.

More...
enum int_type_t {
INT_TYPE_S0_VI_VSYNC = 0, INT_TYPE_S0_LO_VSYNC , INT_TYPE_S0_VSYNCERR , INT_TYPE_VLINE ,
INT_TYPE_S0_VFIELD , INT_TYPE_IV1_VBUFERR , INT_TYPE_IV3_VBUFERR , INT_TYPE_IV5_VBUFERR ,
INT_TYPE_IV6_VBUFERR , INT_TYPE_S0_WLINE , INT_TYPE_S1_VI_VSYNC , INT_TYPE_S1_LO_VSYNC ,
INT_TYPE_S1_VSYNCERR , INT_TYPE_S1_VFIELD , INT_TYPE_IV2_VBUFERR , INT_TYPE_IV4_VBUFERR ,
INT_TYPE_S1_WLINE , INT_TYPE_OIR_VI_VSYNC , INT_TYPE_OIR_LO_VSYNC , INT_TYPE_OIR_VLINE ,
INT_TYPE_OIR_VFIELD , INT_TYPE_IV7_VBUFERR , INT_TYPE_IV8_VBUFERR , INT_TYPE_NUM
}

Interrupt type.

More...
enum graphics_video_col_sys_t {
COL_SYS_NTSC_358 = 0, COL_SYS_NTSC_443 = 1, COL_SYS_PAL_443 = 2, COL_SYS_PAL_M = 3,
COL_SYS_PAL_N = 4, COL_SYS_SECAM = 5, COL_SYS_NTSC_443_60 = 6, COL_SYS_PAL_60 = 7
}

Video color system.

More...
enum video_input_sel_t { INPUT_SEL_VDEC = 0, INPUT_SEL_EXT = 1 }

External Input select.

More...
enum video_extin_format_t {
VIDEO_EXTIN_FORMAT_RGB888 = 0, VIDEO_EXTIN_FORMAT_RGB666 , VIDEO_EXTIN_FORMAT_RGB565 , VIDEO_EXTIN_FORMAT_BT656 ,
VIDEO_EXTIN_FORMAT_BT601 , VIDEO_EXTIN_FORMAT_YCBCR422 , VIDEO_EXTIN_FORMAT_YCBCR444
}

External input format select.

More...
enum onoff_t { OFF = 0, ON = 1 }

On/off.

More...
enum extin_input_line_t { EXTIN_LINE_525 = 0, EXTIN_LINE_625 = 1 }

Number of lines for BT.656 external input.

More...
enum extin_h_pos_t { EXTIN_H_POS_CBYCRY = 0, EXTIN_H_POS_YCRYCB , EXTIN_H_POS_CRYCBY , EXTIN_H_POS_YCBYCR }

Y/Cb/Y/Cr data string start timing.

More...

Public Member Functions

DisplayBase (void)
Constructor method of display base object.
graphics_error_t Graphics_init ( lcd_config_t *lcd_config)
Graphics initialization processing
If not using display, set NULL in parameter.
graphics_error_t Graphics_Video_init ( video_input_sel_t video_input_sel, video_ext_in_config_t *video_ext_in_config)
Graphics Video initialization processing
If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
graphics_error_t Graphics_Lcd_Port_Init (PinName *pin, unsigned int pin_count)
LCD output port initialization processing.
graphics_error_t Graphics_Lvds_Port_Init (PinName *pin, unsigned int pin_count)
LVDS output port initialization processing.
graphics_error_t Graphics_Dvinput_Port_Init (PinName *pin, unsigned int pin_count)
Digital video input port initialization processing.
graphics_error_t Graphics_Irq_Handler_Set ( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void(*callback)( int_type_t ))
Interrupt callback setup This function performs the following processing:

  • Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.

graphics_error_t Graphics_Start ( graphics_layer_t layer_id)
Start the graphics surface read process.
graphics_error_t Graphics_Stop ( graphics_layer_t layer_id)
Stop the graphics surface read process.
graphics_error_t Video_Start ( video_input_channel_t video_input_channel)
Start the video surface write process.
graphics_error_t Video_Stop ( video_input_channel_t video_input_channel)
Stop the video surface write process.
graphics_error_t Graphics_Read_Setting ( graphics_layer_t layer_id, void *framebuff, unsigned int fb_stride, graphics_format_t gr_format, wr_rd_swa_t wr_rd_swa, rect_t *gr_rect)
Graphics surface read process setting.
graphics_error_t Graphics_Read_Change ( graphics_layer_t layer_id, void *framebuff)
Graphics surface read buffer change process.
graphics_error_t Video_Write_Setting ( video_input_channel_t video_input_channel, graphics_video_col_sys_t col_sys, void *framebuff, unsigned int fb_stride, video_format_t video_format, wr_rd_swa_t wr_rd_swa, unsigned short video_write_buff_vw, unsigned short video_write_buff_hw)
Video surface write process setting.
graphics_error_t Video_Write_Change ( video_input_channel_t video_input_channel, void *framebuff, uint32_t fb_stride)
Video surface write buffer change process.

Interface

See the Pinout page for more details

drivers/vdc5/src/r_vdc5_interrupt.c@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdc5_interrupt.c
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDC5 driver interrupt related processing
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 /******************************************************************************
dkato 0:853f5b7408a7 32 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 33 ******************************************************************************/
dkato 0:853f5b7408a7 34 #include "r_vdc5.h"
dkato 0:853f5b7408a7 35 #include "r_vdc5_user.h"
dkato 0:853f5b7408a7 36 #include "r_vdc5_register.h"
dkato 0:853f5b7408a7 37
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39 /******************************************************************************
dkato 0:853f5b7408a7 40 Macro definitions
dkato 0:853f5b7408a7 41 ******************************************************************************/
dkato 0:853f5b7408a7 42 #define UNUSED_PARAM(param) (void)(param)
dkato 0:853f5b7408a7 43
dkato 0:853f5b7408a7 44 #define VDC5_INT_BIT_S0_VI_VSYNC ((uint32_t)0x00000001u)
dkato 0:853f5b7408a7 45 #define VDC5_INT_BIT_S0_LO_VSYNC ((uint32_t)0x00000010u)
dkato 0:853f5b7408a7 46 #define VDC5_INT_BIT_S0_VSYNCERR ((uint32_t)0x00000100u)
dkato 0:853f5b7408a7 47 #define VDC5_INT_BIT_VLINE ((uint32_t)0x00001000u)
dkato 0:853f5b7408a7 48 #define VDC5_INT_BIT_S0_VFIELD ((uint32_t)0x00010000u)
dkato 0:853f5b7408a7 49 #define VDC5_INT_BIT_IV1_VBUFERR ((uint32_t)0x00100000u)
dkato 0:853f5b7408a7 50 #define VDC5_INT_BIT_IV3_VBUFERR ((uint32_t)0x01000000u)
dkato 0:853f5b7408a7 51 #define VDC5_INT_BIT_IV5_VBUFERR ((uint32_t)0x10000000u)
dkato 0:853f5b7408a7 52 #define VDC5_INT_BIT_IV6_VBUFERR ((uint32_t)0x00000001u)
dkato 0:853f5b7408a7 53 #define VDC5_INT_BIT_S0_WLINE ((uint32_t)0x00000010u)
dkato 0:853f5b7408a7 54 #define VDC5_INT_BIT_S1_VI_VSYNC ((uint32_t)0x00000100u)
dkato 0:853f5b7408a7 55 #define VDC5_INT_BIT_S1_LO_VSYNC ((uint32_t)0x00001000u)
dkato 0:853f5b7408a7 56 #define VDC5_INT_BIT_S1_VSYNCERR ((uint32_t)0x00010000u)
dkato 0:853f5b7408a7 57 #define VDC5_INT_BIT_S1_VFIELD ((uint32_t)0x00100000u)
dkato 0:853f5b7408a7 58 #define VDC5_INT_BIT_IV2_VBUFERR ((uint32_t)0x01000000u)
dkato 0:853f5b7408a7 59 #define VDC5_INT_BIT_IV4_VBUFERR ((uint32_t)0x10000000u)
dkato 0:853f5b7408a7 60 #define VDC5_INT_BIT_S1_WLINE ((uint32_t)0x00000001u)
dkato 0:853f5b7408a7 61 #define VDC5_INT_BIT_OIR_VI_VSYNC ((uint32_t)0x00000010u)
dkato 0:853f5b7408a7 62 #define VDC5_INT_BIT_OIR_LO_VSYNC ((uint32_t)0x00000100u)
dkato 0:853f5b7408a7 63 #define VDC5_INT_BIT_OIR_VLINE ((uint32_t)0x00001000u)
dkato 0:853f5b7408a7 64 #define VDC5_INT_BIT_OIR_VFIELD ((uint32_t)0x00010000u)
dkato 0:853f5b7408a7 65 #define VDC5_INT_BIT_IV7_VBUFERR ((uint32_t)0x00100000u)
dkato 0:853f5b7408a7 66 #define VDC5_INT_BIT_IV8_VBUFERR ((uint32_t)0x01000000u)
dkato 0:853f5b7408a7 67
dkato 0:853f5b7408a7 68 #define VDC5_GR_UPDATE_P_VEN_BIT ((uint32_t)0x00000010u)
dkato 0:853f5b7408a7 69 #define VDC5_SCL0_UPDATE_VEN_A_BIT ((uint32_t)0x00000001u)
dkato 0:853f5b7408a7 70
dkato 0:853f5b7408a7 71 /* Valid bit range */
dkato 0:853f5b7408a7 72 #define VDC5_INT_RANGE_0X000007FF (0x000007FFu)
dkato 0:853f5b7408a7 73
dkato 0:853f5b7408a7 74 /******************************************************************************
dkato 0:853f5b7408a7 75 Typedef definitions
dkato 0:853f5b7408a7 76 ******************************************************************************/
dkato 0:853f5b7408a7 77
dkato 0:853f5b7408a7 78 /******************************************************************************
dkato 0:853f5b7408a7 79 Private global variables and functions
dkato 0:853f5b7408a7 80 ******************************************************************************/
dkato 0:853f5b7408a7 81 static void VDC5_Ch0_s0_vi_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 82 static void VDC5_Ch0_s0_lo_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 83 static void VDC5_Ch0_s0_vsyncerr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 84 static void VDC5_Ch0_vline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 85 static void VDC5_Ch0_s0_vfield_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 86 static void VDC5_Ch0_iv1_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 87 static void VDC5_Ch0_iv3_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 88 static void VDC5_Ch0_iv5_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 89 static void VDC5_Ch0_iv6_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 90 static void VDC5_Ch0_s0_wline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 91 static void VDC5_Ch0_s1_vi_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 92 static void VDC5_Ch0_s1_lo_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 93 static void VDC5_Ch0_s1_vsyncerr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 94 static void VDC5_Ch0_s1_vfield_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 95 static void VDC5_Ch0_iv2_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 96 static void VDC5_Ch0_iv4_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 97 static void VDC5_Ch0_s1_wline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 98 static void VDC5_Ch0_oir_vi_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 99 static void VDC5_Ch0_oir_lo_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 100 static void VDC5_Ch0_oir_vline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 101 static void VDC5_Ch0_oir_vfield_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 102 static void VDC5_Ch0_iv7_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 103 static void VDC5_Ch0_iv8_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 104
dkato 0:853f5b7408a7 105 static void VDC5_Ch1_s0_vi_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 106 static void VDC5_Ch1_s0_lo_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 107 static void VDC5_Ch1_s0_vsyncerr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 108 static void VDC5_Ch1_vline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 109 static void VDC5_Ch1_s0_vfield_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 110 static void VDC5_Ch1_iv1_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 111 static void VDC5_Ch1_iv3_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 112 static void VDC5_Ch1_iv5_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 113 static void VDC5_Ch1_iv6_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 114 static void VDC5_Ch1_s0_wline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 115 static void VDC5_Ch1_s1_vi_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 116 static void VDC5_Ch1_s1_lo_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 117 static void VDC5_Ch1_s1_vsyncerr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 118 static void VDC5_Ch1_s1_vfield_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 119 static void VDC5_Ch1_iv2_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 120 static void VDC5_Ch1_iv4_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 121 static void VDC5_Ch1_s1_wline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 122 static void VDC5_Ch1_oir_vi_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 123 static void VDC5_Ch1_oir_lo_vsync_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 124 static void VDC5_Ch1_oir_vline_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 125 static void VDC5_Ch1_oir_vfield_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 126 static void VDC5_Ch1_iv7_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 127 static void VDC5_Ch1_iv8_vbuferr_ISR(const uint32_t int_sense);
dkato 0:853f5b7408a7 128
dkato 0:853f5b7408a7 129 /*! List of the callback function pointers */
dkato 0:853f5b7408a7 130 static void (*vdc5_int_callback[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(vdc5_int_type_t int_type);
dkato 0:853f5b7408a7 131
dkato 0:853f5b7408a7 132
dkato 0:853f5b7408a7 133 /**************************************************************************//**
dkato 0:853f5b7408a7 134 * @brief Interrupt service routine acquisition processing
dkato 0:853f5b7408a7 135 *
dkato 0:853f5b7408a7 136 * Description:<br>
dkato 0:853f5b7408a7 137 * This function returns the function pointer to the specified interrupt service routine.
dkato 0:853f5b7408a7 138 * @param[in] ch : Channel
dkato 0:853f5b7408a7 139 * @param[in] type : VDC5 interrupt type
dkato 0:853f5b7408a7 140 * @retval VDC5 Interrupt service routine
dkato 0:853f5b7408a7 141 *****************************************************************************/
dkato 0:853f5b7408a7 142 void (*R_VDC5_GetISR (const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense)
dkato 0:853f5b7408a7 143 {
dkato 0:853f5b7408a7 144 static void (* const isr_table[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(const uint32_t int_sense) = {
dkato 0:853f5b7408a7 145 {
dkato 0:853f5b7408a7 146 &VDC5_Ch0_s0_vi_vsync_ISR,
dkato 0:853f5b7408a7 147 &VDC5_Ch0_s0_lo_vsync_ISR,
dkato 0:853f5b7408a7 148 &VDC5_Ch0_s0_vsyncerr_ISR,
dkato 0:853f5b7408a7 149 &VDC5_Ch0_vline_ISR,
dkato 0:853f5b7408a7 150 &VDC5_Ch0_s0_vfield_ISR,
dkato 0:853f5b7408a7 151 &VDC5_Ch0_iv1_vbuferr_ISR,
dkato 0:853f5b7408a7 152 &VDC5_Ch0_iv3_vbuferr_ISR,
dkato 0:853f5b7408a7 153 &VDC5_Ch0_iv5_vbuferr_ISR,
dkato 0:853f5b7408a7 154 &VDC5_Ch0_iv6_vbuferr_ISR,
dkato 0:853f5b7408a7 155 &VDC5_Ch0_s0_wline_ISR,
dkato 0:853f5b7408a7 156 &VDC5_Ch0_s1_vi_vsync_ISR,
dkato 0:853f5b7408a7 157 &VDC5_Ch0_s1_lo_vsync_ISR,
dkato 0:853f5b7408a7 158 &VDC5_Ch0_s1_vsyncerr_ISR,
dkato 0:853f5b7408a7 159 &VDC5_Ch0_s1_vfield_ISR,
dkato 0:853f5b7408a7 160 &VDC5_Ch0_iv2_vbuferr_ISR,
dkato 0:853f5b7408a7 161 &VDC5_Ch0_iv4_vbuferr_ISR,
dkato 0:853f5b7408a7 162 &VDC5_Ch0_s1_wline_ISR,
dkato 0:853f5b7408a7 163 &VDC5_Ch0_oir_vi_vsync_ISR,
dkato 0:853f5b7408a7 164 &VDC5_Ch0_oir_lo_vsync_ISR,
dkato 0:853f5b7408a7 165 &VDC5_Ch0_oir_vline_ISR,
dkato 0:853f5b7408a7 166 &VDC5_Ch0_oir_vfield_ISR,
dkato 0:853f5b7408a7 167 &VDC5_Ch0_iv7_vbuferr_ISR,
dkato 0:853f5b7408a7 168 &VDC5_Ch0_iv8_vbuferr_ISR
dkato 0:853f5b7408a7 169 },
dkato 0:853f5b7408a7 170 {
dkato 0:853f5b7408a7 171 &VDC5_Ch1_s0_vi_vsync_ISR,
dkato 0:853f5b7408a7 172 &VDC5_Ch1_s0_lo_vsync_ISR,
dkato 0:853f5b7408a7 173 &VDC5_Ch1_s0_vsyncerr_ISR,
dkato 0:853f5b7408a7 174 &VDC5_Ch1_vline_ISR,
dkato 0:853f5b7408a7 175 &VDC5_Ch1_s0_vfield_ISR,
dkato 0:853f5b7408a7 176 &VDC5_Ch1_iv1_vbuferr_ISR,
dkato 0:853f5b7408a7 177 &VDC5_Ch1_iv3_vbuferr_ISR,
dkato 0:853f5b7408a7 178 &VDC5_Ch1_iv5_vbuferr_ISR,
dkato 0:853f5b7408a7 179 &VDC5_Ch1_iv6_vbuferr_ISR,
dkato 0:853f5b7408a7 180 &VDC5_Ch1_s0_wline_ISR,
dkato 0:853f5b7408a7 181 &VDC5_Ch1_s1_vi_vsync_ISR,
dkato 0:853f5b7408a7 182 &VDC5_Ch1_s1_lo_vsync_ISR,
dkato 0:853f5b7408a7 183 &VDC5_Ch1_s1_vsyncerr_ISR,
dkato 0:853f5b7408a7 184 &VDC5_Ch1_s1_vfield_ISR,
dkato 0:853f5b7408a7 185 &VDC5_Ch1_iv2_vbuferr_ISR,
dkato 0:853f5b7408a7 186 &VDC5_Ch1_iv4_vbuferr_ISR,
dkato 0:853f5b7408a7 187 &VDC5_Ch1_s1_wline_ISR,
dkato 0:853f5b7408a7 188 &VDC5_Ch1_oir_vi_vsync_ISR,
dkato 0:853f5b7408a7 189 &VDC5_Ch1_oir_lo_vsync_ISR,
dkato 0:853f5b7408a7 190 &VDC5_Ch1_oir_vline_ISR,
dkato 0:853f5b7408a7 191 &VDC5_Ch1_oir_vfield_ISR,
dkato 0:853f5b7408a7 192 &VDC5_Ch1_iv7_vbuferr_ISR,
dkato 0:853f5b7408a7 193 &VDC5_Ch1_iv8_vbuferr_ISR
dkato 0:853f5b7408a7 194 }
dkato 0:853f5b7408a7 195 };
dkato 0:853f5b7408a7 196 void (* isr_function)(const uint32_t int_sense);
dkato 0:853f5b7408a7 197
dkato 0:853f5b7408a7 198 isr_function = isr_table[ch][type];
dkato 0:853f5b7408a7 199
dkato 0:853f5b7408a7 200 #ifdef R_VDC5_CHECK_PARAMETERS
dkato 0:853f5b7408a7 201 /* Channel and interrupt type */
dkato 0:853f5b7408a7 202 if ((ch >= VDC5_CHANNEL_NUM) || (type >= VDC5_INT_TYPE_NUM)) {
dkato 0:853f5b7408a7 203 isr_function = 0;
dkato 0:853f5b7408a7 204 }
dkato 0:853f5b7408a7 205 #endif /* R_VDC5_CHECK_PARAMETERS */
dkato 0:853f5b7408a7 206
dkato 0:853f5b7408a7 207 return isr_function;
dkato 0:853f5b7408a7 208 } /* End of function R_VDC5_GetISR() */
dkato 0:853f5b7408a7 209
dkato 0:853f5b7408a7 210 /**************************************************************************//**
dkato 0:853f5b7408a7 211 * @brief Disables all VDC5 interrupts
dkato 0:853f5b7408a7 212 * @param[in] ch : Channel
dkato 0:853f5b7408a7 213 * @retval None
dkato 0:853f5b7408a7 214 *****************************************************************************/
dkato 0:853f5b7408a7 215 void VDC5_Int_Disable (const vdc5_channel_t ch)
dkato 0:853f5b7408a7 216 {
dkato 0:853f5b7408a7 217 const vdc5_regaddr_system_ctrl_t * system_ctrl;
dkato 0:853f5b7408a7 218 int32_t int_type;
dkato 0:853f5b7408a7 219
dkato 0:853f5b7408a7 220 system_ctrl = &vdc5_regaddr_system_ctrl[ch];
dkato 0:853f5b7408a7 221
dkato 0:853f5b7408a7 222 for (int_type = 0; int_type < VDC5_INT_TYPE_NUM; int_type++) {
dkato 0:853f5b7408a7 223 vdc5_int_callback[ch][int_type] = 0;
dkato 0:853f5b7408a7 224 }
dkato 0:853f5b7408a7 225 /* Interrupt output off */
dkato 0:853f5b7408a7 226 *(system_ctrl->syscnt_int4) = 0u;
dkato 0:853f5b7408a7 227 *(system_ctrl->syscnt_int5) = 0u;
dkato 0:853f5b7408a7 228 *(system_ctrl->syscnt_int6) = 0u;
dkato 0:853f5b7408a7 229
dkato 0:853f5b7408a7 230 } /* End of function VDC5_Int_Disable() */
dkato 0:853f5b7408a7 231
dkato 0:853f5b7408a7 232 /**************************************************************************//**
dkato 0:853f5b7408a7 233 * @brief Enables/disables the specified VDC5 interrupt
dkato 0:853f5b7408a7 234 * @param[in] ch : Channel
dkato 0:853f5b7408a7 235 * @param[in] param : Interrupt callback setup parameter
dkato 0:853f5b7408a7 236 * @retval None
dkato 0:853f5b7408a7 237 *****************************************************************************/
dkato 0:853f5b7408a7 238 void VDC5_Int_SetInterrupt (const vdc5_channel_t ch, const vdc5_int_t * const param)
dkato 0:853f5b7408a7 239 {
dkato 0:853f5b7408a7 240 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 241 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 242 volatile uint32_t * linenum_reg;
dkato 0:853f5b7408a7 243 volatile uint16_t * linenum16_reg;
dkato 0:853f5b7408a7 244 volatile uint32_t * linenum_update_reg;
dkato 0:853f5b7408a7 245 uint32_t mask_bit;
dkato 0:853f5b7408a7 246 uint32_t reg_data;
dkato 0:853f5b7408a7 247 static const uint32_t interrupt_bit_table[VDC5_INT_TYPE_NUM] = {
dkato 0:853f5b7408a7 248 VDC5_INT_BIT_S0_VI_VSYNC,
dkato 0:853f5b7408a7 249 VDC5_INT_BIT_S0_LO_VSYNC,
dkato 0:853f5b7408a7 250 VDC5_INT_BIT_S0_VSYNCERR,
dkato 0:853f5b7408a7 251 VDC5_INT_BIT_VLINE,
dkato 0:853f5b7408a7 252 VDC5_INT_BIT_S0_VFIELD,
dkato 0:853f5b7408a7 253 VDC5_INT_BIT_IV1_VBUFERR,
dkato 0:853f5b7408a7 254 VDC5_INT_BIT_IV3_VBUFERR,
dkato 0:853f5b7408a7 255 VDC5_INT_BIT_IV5_VBUFERR,
dkato 0:853f5b7408a7 256 VDC5_INT_BIT_IV6_VBUFERR,
dkato 0:853f5b7408a7 257 VDC5_INT_BIT_S0_WLINE,
dkato 0:853f5b7408a7 258 VDC5_INT_BIT_S1_VI_VSYNC,
dkato 0:853f5b7408a7 259 VDC5_INT_BIT_S1_LO_VSYNC,
dkato 0:853f5b7408a7 260 VDC5_INT_BIT_S1_VSYNCERR,
dkato 0:853f5b7408a7 261 VDC5_INT_BIT_S1_VFIELD,
dkato 0:853f5b7408a7 262 VDC5_INT_BIT_IV2_VBUFERR,
dkato 0:853f5b7408a7 263 VDC5_INT_BIT_IV4_VBUFERR,
dkato 0:853f5b7408a7 264 VDC5_INT_BIT_S1_WLINE,
dkato 0:853f5b7408a7 265 VDC5_INT_BIT_OIR_VI_VSYNC,
dkato 0:853f5b7408a7 266 VDC5_INT_BIT_OIR_LO_VSYNC,
dkato 0:853f5b7408a7 267 VDC5_INT_BIT_OIR_VLINE,
dkato 0:853f5b7408a7 268 VDC5_INT_BIT_OIR_VFIELD,
dkato 0:853f5b7408a7 269 VDC5_INT_BIT_IV7_VBUFERR,
dkato 0:853f5b7408a7 270 VDC5_INT_BIT_IV8_VBUFERR
dkato 0:853f5b7408a7 271 };
dkato 0:853f5b7408a7 272
dkato 0:853f5b7408a7 273 if (param->type < VDC5_INT_TYPE_IV6_VBUFERR) {
dkato 0:853f5b7408a7 274 /* INT0: VDC5_INT_TYPE_S0_VI_VSYNC ~ INT7: VDC5_INT_TYPE_IV5_VBUFERR */
dkato 0:853f5b7408a7 275 int_clhd_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int1;
dkato 0:853f5b7408a7 276 int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int4;
dkato 0:853f5b7408a7 277 } else if (param->type < VDC5_INT_TYPE_S1_WLINE) {
dkato 0:853f5b7408a7 278 /* INT8: VDC5_INT_TYPE_IV6_VBUFERR ~ INT15: VDC5_INT_TYPE_IV4_VBUFERR */
dkato 0:853f5b7408a7 279 int_clhd_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int2;
dkato 0:853f5b7408a7 280 int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int5;
dkato 0:853f5b7408a7 281 } else {
dkato 0:853f5b7408a7 282 /* INT16: VDC5_INT_TYPE_S1_WLINE ~ INT22: VDC5_INT_TYPE_IV8_VBUFERR */
dkato 0:853f5b7408a7 283 int_clhd_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int3;
dkato 0:853f5b7408a7 284 int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int6;
dkato 0:853f5b7408a7 285 }
dkato 0:853f5b7408a7 286 mask_bit = interrupt_bit_table[param->type];
dkato 0:853f5b7408a7 287
dkato 0:853f5b7408a7 288 /* Interrupt callback function pointer */
dkato 0:853f5b7408a7 289 vdc5_int_callback[ch][param->type] = param->callback;
dkato 0:853f5b7408a7 290
dkato 0:853f5b7408a7 291 if (param->callback != 0) {
dkato 0:853f5b7408a7 292 /* ON */
dkato 0:853f5b7408a7 293 if ((*int_onoff_reg & mask_bit) == 0u) {
dkato 0:853f5b7408a7 294 /* OFF to ON */
dkato 0:853f5b7408a7 295 *int_onoff_reg |= mask_bit;
dkato 0:853f5b7408a7 296 reg_data = *int_onoff_reg;
dkato 0:853f5b7408a7 297 *int_clhd_reg = reg_data;
dkato 0:853f5b7408a7 298 }
dkato 0:853f5b7408a7 299
dkato 0:853f5b7408a7 300 if (param->type == VDC5_INT_TYPE_VLINE) {
dkato 0:853f5b7408a7 301 /* Specified line signal for panel output in graphics 3 */
dkato 0:853f5b7408a7 302 linenum_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_clut;
dkato 0:853f5b7408a7 303 linenum_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
dkato 0:853f5b7408a7 304 *linenum_reg &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
dkato 0:853f5b7408a7 305 *linenum_reg |= (uint32_t)param->line_num;
dkato 0:853f5b7408a7 306 *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
dkato 0:853f5b7408a7 307 } else if (param->type == VDC5_INT_TYPE_S0_WLINE) {
dkato 0:853f5b7408a7 308 /* Write specification line signal input to scaling-down control block in scaler 0 */
dkato 0:853f5b7408a7 309 linenum16_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_int;
dkato 0:853f5b7408a7 310 linenum_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
dkato 0:853f5b7408a7 311 *linenum16_reg = param->line_num;
dkato 0:853f5b7408a7 312 *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
dkato 0:853f5b7408a7 313 } else if (param->type == VDC5_INT_TYPE_S1_WLINE) {
dkato 0:853f5b7408a7 314 /* Write specification line signal input to scaling-down control block in scaler 1 */
dkato 0:853f5b7408a7 315 linenum16_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_int;
dkato 0:853f5b7408a7 316 linenum_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
dkato 0:853f5b7408a7 317 *linenum16_reg = param->line_num;
dkato 0:853f5b7408a7 318 *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
dkato 0:853f5b7408a7 319 } else if (param->type == VDC5_INT_TYPE_OIR_VLINE) {
dkato 0:853f5b7408a7 320 /* Specified line signal for panel output in output image generator */
dkato 0:853f5b7408a7 321 linenum_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_clut;
dkato 0:853f5b7408a7 322 linenum_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
dkato 0:853f5b7408a7 323 *linenum_reg &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
dkato 0:853f5b7408a7 324 *linenum_reg |= (uint32_t)param->line_num;
dkato 0:853f5b7408a7 325 *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
dkato 0:853f5b7408a7 326 } else {
dkato 0:853f5b7408a7 327 /* Do nothing */
dkato 0:853f5b7408a7 328 }
dkato 0:853f5b7408a7 329 } else {
dkato 0:853f5b7408a7 330 /* OFF */
dkato 0:853f5b7408a7 331 *int_onoff_reg &= (uint32_t)~mask_bit;
dkato 0:853f5b7408a7 332 reg_data = *int_onoff_reg;
dkato 0:853f5b7408a7 333 *int_clhd_reg = reg_data;
dkato 0:853f5b7408a7 334 }
dkato 0:853f5b7408a7 335
dkato 0:853f5b7408a7 336 } /* End of function VDC5_Int_Disable() */
dkato 0:853f5b7408a7 337
dkato 0:853f5b7408a7 338 /**************************************************************************//**
dkato 0:853f5b7408a7 339 * @brief VDC5 S0_VI_VSYNC interrupt service routine
dkato 0:853f5b7408a7 340 * @param[in] int_sense
dkato 0:853f5b7408a7 341 * @retval None
dkato 0:853f5b7408a7 342 *****************************************************************************/
dkato 0:853f5b7408a7 343 static void VDC5_Ch0_s0_vi_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 344 {
dkato 0:853f5b7408a7 345 uint32_t IntState;
dkato 0:853f5b7408a7 346 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 347 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 348
dkato 0:853f5b7408a7 349 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 350
dkato 0:853f5b7408a7 351 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 352 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 353 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 354
dkato 0:853f5b7408a7 355 if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 356 /* Clear */
dkato 0:853f5b7408a7 357 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
dkato 0:853f5b7408a7 358
dkato 0:853f5b7408a7 359 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
dkato 0:853f5b7408a7 360 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
dkato 0:853f5b7408a7 361 }
dkato 0:853f5b7408a7 362 /* Set */
dkato 0:853f5b7408a7 363 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 364 }
dkato 0:853f5b7408a7 365 } /* End of function VDC5_Ch0_s0_vi_vsync_ISR() */
dkato 0:853f5b7408a7 366
dkato 0:853f5b7408a7 367 /**************************************************************************//**
dkato 0:853f5b7408a7 368 * @brief VDC5 S0_LO_VSYNC interrupt service routine
dkato 0:853f5b7408a7 369 * @param[in] int_sense
dkato 0:853f5b7408a7 370 * @retval None
dkato 0:853f5b7408a7 371 *****************************************************************************/
dkato 0:853f5b7408a7 372 static void VDC5_Ch0_s0_lo_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 373 {
dkato 0:853f5b7408a7 374 uint32_t IntState;
dkato 0:853f5b7408a7 375 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 376 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 377
dkato 0:853f5b7408a7 378 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 379
dkato 0:853f5b7408a7 380 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 381 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 382 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 383
dkato 0:853f5b7408a7 384 if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 385 /* Clear */
dkato 0:853f5b7408a7 386 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
dkato 0:853f5b7408a7 387
dkato 0:853f5b7408a7 388 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
dkato 0:853f5b7408a7 389 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
dkato 0:853f5b7408a7 390 }
dkato 0:853f5b7408a7 391 /* Set */
dkato 0:853f5b7408a7 392 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 393 }
dkato 0:853f5b7408a7 394 } /* End of function VDC5_Ch0_s0_lo_vsync_ISR() */
dkato 0:853f5b7408a7 395
dkato 0:853f5b7408a7 396 /**************************************************************************//**
dkato 0:853f5b7408a7 397 * @brief VDC5 S0_VSYNCERR interrupt service routine
dkato 0:853f5b7408a7 398 * @param[in] int_sense
dkato 0:853f5b7408a7 399 * @retval None
dkato 0:853f5b7408a7 400 *****************************************************************************/
dkato 0:853f5b7408a7 401 static void VDC5_Ch0_s0_vsyncerr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 402 {
dkato 0:853f5b7408a7 403 uint32_t IntState;
dkato 0:853f5b7408a7 404 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 405 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 406
dkato 0:853f5b7408a7 407 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 408
dkato 0:853f5b7408a7 409 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 410 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 411 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 412
dkato 0:853f5b7408a7 413 if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
dkato 0:853f5b7408a7 414 /* Clear */
dkato 0:853f5b7408a7 415 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
dkato 0:853f5b7408a7 416
dkato 0:853f5b7408a7 417 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
dkato 0:853f5b7408a7 418 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
dkato 0:853f5b7408a7 419 }
dkato 0:853f5b7408a7 420 /* Set */
dkato 0:853f5b7408a7 421 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 422 }
dkato 0:853f5b7408a7 423 } /* End of function VDC5_Ch0_s0_vsyncerr_ISR() */
dkato 0:853f5b7408a7 424
dkato 0:853f5b7408a7 425 /**************************************************************************//**
dkato 0:853f5b7408a7 426 * @brief VDC5 VLINE interrupt service routine
dkato 0:853f5b7408a7 427 * @param[in] int_sense
dkato 0:853f5b7408a7 428 * @retval None
dkato 0:853f5b7408a7 429 *****************************************************************************/
dkato 0:853f5b7408a7 430 static void VDC5_Ch0_vline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 431 {
dkato 0:853f5b7408a7 432 uint32_t IntState;
dkato 0:853f5b7408a7 433 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 434 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 435
dkato 0:853f5b7408a7 436 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 437
dkato 0:853f5b7408a7 438 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 439 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 440 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 441
dkato 0:853f5b7408a7 442 if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
dkato 0:853f5b7408a7 443 /* Clear */
dkato 0:853f5b7408a7 444 *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
dkato 0:853f5b7408a7 445
dkato 0:853f5b7408a7 446 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE] != 0) {
dkato 0:853f5b7408a7 447 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
dkato 0:853f5b7408a7 448 }
dkato 0:853f5b7408a7 449 /* Set */
dkato 0:853f5b7408a7 450 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 451 }
dkato 0:853f5b7408a7 452 } /* End of function VDC5_Ch0_vline_ISR() */
dkato 0:853f5b7408a7 453
dkato 0:853f5b7408a7 454 /**************************************************************************//**
dkato 0:853f5b7408a7 455 * @brief VDC5 S0_VFIELD interrupt service routine
dkato 0:853f5b7408a7 456 * @param[in] int_sense
dkato 0:853f5b7408a7 457 * @retval None
dkato 0:853f5b7408a7 458 *****************************************************************************/
dkato 0:853f5b7408a7 459 static void VDC5_Ch0_s0_vfield_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 460 {
dkato 0:853f5b7408a7 461 uint32_t IntState;
dkato 0:853f5b7408a7 462 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 463 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 464
dkato 0:853f5b7408a7 465 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 466
dkato 0:853f5b7408a7 467 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 468 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 469 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 470
dkato 0:853f5b7408a7 471 if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
dkato 0:853f5b7408a7 472 /* Clear */
dkato 0:853f5b7408a7 473 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
dkato 0:853f5b7408a7 474
dkato 0:853f5b7408a7 475 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD] != 0) {
dkato 0:853f5b7408a7 476 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
dkato 0:853f5b7408a7 477 }
dkato 0:853f5b7408a7 478 /* Set */
dkato 0:853f5b7408a7 479 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 480 }
dkato 0:853f5b7408a7 481 } /* End of function VDC5_Ch0_s0_vfield_ISR() */
dkato 0:853f5b7408a7 482
dkato 0:853f5b7408a7 483 /**************************************************************************//**
dkato 0:853f5b7408a7 484 * @brief VDC5 IV1_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 485 * @param[in] int_sense
dkato 0:853f5b7408a7 486 * @retval None
dkato 0:853f5b7408a7 487 *****************************************************************************/
dkato 0:853f5b7408a7 488 static void VDC5_Ch0_iv1_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 489 {
dkato 0:853f5b7408a7 490 uint32_t IntState;
dkato 0:853f5b7408a7 491 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 492 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 493
dkato 0:853f5b7408a7 494 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 495
dkato 0:853f5b7408a7 496 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 497 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 498 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 499
dkato 0:853f5b7408a7 500 if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 501 /* Clear */
dkato 0:853f5b7408a7 502 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
dkato 0:853f5b7408a7 503
dkato 0:853f5b7408a7 504 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
dkato 0:853f5b7408a7 505 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
dkato 0:853f5b7408a7 506 }
dkato 0:853f5b7408a7 507 /* Set */
dkato 0:853f5b7408a7 508 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 509 }
dkato 0:853f5b7408a7 510 } /* End of function VDC5_Ch0_iv1_vbuferr_ISR() */
dkato 0:853f5b7408a7 511
dkato 0:853f5b7408a7 512 /**************************************************************************//**
dkato 0:853f5b7408a7 513 * @brief VDC5 IV3_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 514 * @param[in] int_sense
dkato 0:853f5b7408a7 515 * @retval None
dkato 0:853f5b7408a7 516 *****************************************************************************/
dkato 0:853f5b7408a7 517 static void VDC5_Ch0_iv3_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 518 {
dkato 0:853f5b7408a7 519 uint32_t IntState;
dkato 0:853f5b7408a7 520 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 521 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 522
dkato 0:853f5b7408a7 523 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 524
dkato 0:853f5b7408a7 525 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 526 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 527 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 528
dkato 0:853f5b7408a7 529 if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 530 /* Clear */
dkato 0:853f5b7408a7 531 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
dkato 0:853f5b7408a7 532
dkato 0:853f5b7408a7 533 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
dkato 0:853f5b7408a7 534 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
dkato 0:853f5b7408a7 535 }
dkato 0:853f5b7408a7 536 /* Set */
dkato 0:853f5b7408a7 537 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 538 }
dkato 0:853f5b7408a7 539 } /* End of function VDC5_Ch0_iv3_vbuferr_ISR() */
dkato 0:853f5b7408a7 540
dkato 0:853f5b7408a7 541 /**************************************************************************//**
dkato 0:853f5b7408a7 542 * @brief VDC5 IV5_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 543 * @param[in] int_sense
dkato 0:853f5b7408a7 544 * @retval None
dkato 0:853f5b7408a7 545 *****************************************************************************/
dkato 0:853f5b7408a7 546 static void VDC5_Ch0_iv5_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 547 {
dkato 0:853f5b7408a7 548 uint32_t IntState;
dkato 0:853f5b7408a7 549 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 550 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 551
dkato 0:853f5b7408a7 552 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 553
dkato 0:853f5b7408a7 554 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
dkato 0:853f5b7408a7 555 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
dkato 0:853f5b7408a7 556 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 557
dkato 0:853f5b7408a7 558 if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 559 /* Clear */
dkato 0:853f5b7408a7 560 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
dkato 0:853f5b7408a7 561
dkato 0:853f5b7408a7 562 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
dkato 0:853f5b7408a7 563 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
dkato 0:853f5b7408a7 564 }
dkato 0:853f5b7408a7 565 /* Set */
dkato 0:853f5b7408a7 566 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 567 }
dkato 0:853f5b7408a7 568 } /* End of function VDC5_Ch0_iv5_vbuferr_ISR() */
dkato 0:853f5b7408a7 569
dkato 0:853f5b7408a7 570 /**************************************************************************//**
dkato 0:853f5b7408a7 571 * @brief VDC5 IV6_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 572 * @param[in] int_sense
dkato 0:853f5b7408a7 573 * @retval None
dkato 0:853f5b7408a7 574 *****************************************************************************/
dkato 0:853f5b7408a7 575 static void VDC5_Ch0_iv6_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 576 {
dkato 0:853f5b7408a7 577 uint32_t IntState;
dkato 0:853f5b7408a7 578 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 579 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 580
dkato 0:853f5b7408a7 581 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 582
dkato 0:853f5b7408a7 583 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 584 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 585 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 586
dkato 0:853f5b7408a7 587 if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 588 /* Clear */
dkato 0:853f5b7408a7 589 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
dkato 0:853f5b7408a7 590
dkato 0:853f5b7408a7 591 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
dkato 0:853f5b7408a7 592 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
dkato 0:853f5b7408a7 593 }
dkato 0:853f5b7408a7 594 /* Set */
dkato 0:853f5b7408a7 595 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 596 }
dkato 0:853f5b7408a7 597 } /* End of function VDC5_Ch0_iv6_vbuferr_ISR() */
dkato 0:853f5b7408a7 598
dkato 0:853f5b7408a7 599 /**************************************************************************//**
dkato 0:853f5b7408a7 600 * @brief VDC5 S0_WLINE interrupt service routine
dkato 0:853f5b7408a7 601 * @param[in] int_sense
dkato 0:853f5b7408a7 602 * @retval None
dkato 0:853f5b7408a7 603 *****************************************************************************/
dkato 0:853f5b7408a7 604 static void VDC5_Ch0_s0_wline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 605 {
dkato 0:853f5b7408a7 606 uint32_t IntState;
dkato 0:853f5b7408a7 607 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 608 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 609
dkato 0:853f5b7408a7 610 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 611
dkato 0:853f5b7408a7 612 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 613 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 614 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 615
dkato 0:853f5b7408a7 616 if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
dkato 0:853f5b7408a7 617 /* Clear */
dkato 0:853f5b7408a7 618 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
dkato 0:853f5b7408a7 619
dkato 0:853f5b7408a7 620 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE] != 0) {
dkato 0:853f5b7408a7 621 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
dkato 0:853f5b7408a7 622 }
dkato 0:853f5b7408a7 623 /* Set */
dkato 0:853f5b7408a7 624 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 625 }
dkato 0:853f5b7408a7 626 } /* End of function VDC5_Ch0_s0_wline_ISR() */
dkato 0:853f5b7408a7 627
dkato 0:853f5b7408a7 628 /**************************************************************************//**
dkato 0:853f5b7408a7 629 * @brief VDC5 S1_VI_VSYNC interrupt service routine
dkato 0:853f5b7408a7 630 * @param[in] int_sense
dkato 0:853f5b7408a7 631 * @retval None
dkato 0:853f5b7408a7 632 *****************************************************************************/
dkato 0:853f5b7408a7 633 static void VDC5_Ch0_s1_vi_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 634 {
dkato 0:853f5b7408a7 635 uint32_t IntState;
dkato 0:853f5b7408a7 636 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 637 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 638
dkato 0:853f5b7408a7 639 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 640
dkato 0:853f5b7408a7 641 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 642 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 643 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 644
dkato 0:853f5b7408a7 645 if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 646 /* Clear */
dkato 0:853f5b7408a7 647 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
dkato 0:853f5b7408a7 648
dkato 0:853f5b7408a7 649 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
dkato 0:853f5b7408a7 650 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
dkato 0:853f5b7408a7 651 }
dkato 0:853f5b7408a7 652 /* Set */
dkato 0:853f5b7408a7 653 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 654 }
dkato 0:853f5b7408a7 655 } /* End of function VDC5_Ch0_s1_vi_vsync_ISR() */
dkato 0:853f5b7408a7 656
dkato 0:853f5b7408a7 657 /**************************************************************************//**
dkato 0:853f5b7408a7 658 * @brief VDC5 S1_LO_VSYNC interrupt service routine
dkato 0:853f5b7408a7 659 * @param[in] int_sense
dkato 0:853f5b7408a7 660 * @retval None
dkato 0:853f5b7408a7 661 *****************************************************************************/
dkato 0:853f5b7408a7 662 static void VDC5_Ch0_s1_lo_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 663 {
dkato 0:853f5b7408a7 664 uint32_t IntState;
dkato 0:853f5b7408a7 665 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 666 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 667
dkato 0:853f5b7408a7 668 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 669
dkato 0:853f5b7408a7 670 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 671 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 672 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 673
dkato 0:853f5b7408a7 674 if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 675 /* Clear */
dkato 0:853f5b7408a7 676 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
dkato 0:853f5b7408a7 677
dkato 0:853f5b7408a7 678 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
dkato 0:853f5b7408a7 679 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
dkato 0:853f5b7408a7 680 }
dkato 0:853f5b7408a7 681 /* Set */
dkato 0:853f5b7408a7 682 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 683 }
dkato 0:853f5b7408a7 684 } /* End of function VDC5_Ch0_s1_lo_vsync_ISR() */
dkato 0:853f5b7408a7 685
dkato 0:853f5b7408a7 686 /**************************************************************************//**
dkato 0:853f5b7408a7 687 * @brief VDC5 S1_VSYNCERR interrupt service routine
dkato 0:853f5b7408a7 688 * @param[in] int_sense
dkato 0:853f5b7408a7 689 * @retval None
dkato 0:853f5b7408a7 690 *****************************************************************************/
dkato 0:853f5b7408a7 691 static void VDC5_Ch0_s1_vsyncerr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 692 {
dkato 0:853f5b7408a7 693 uint32_t IntState;
dkato 0:853f5b7408a7 694 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 695 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 696
dkato 0:853f5b7408a7 697 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 698
dkato 0:853f5b7408a7 699 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 700 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 701 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 702
dkato 0:853f5b7408a7 703 if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
dkato 0:853f5b7408a7 704 /* Clear */
dkato 0:853f5b7408a7 705 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
dkato 0:853f5b7408a7 706
dkato 0:853f5b7408a7 707 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
dkato 0:853f5b7408a7 708 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
dkato 0:853f5b7408a7 709 }
dkato 0:853f5b7408a7 710 /* Set */
dkato 0:853f5b7408a7 711 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 712 }
dkato 0:853f5b7408a7 713 } /* End of function VDC5_Ch0_s1_vsyncerr_ISR() */
dkato 0:853f5b7408a7 714
dkato 0:853f5b7408a7 715 /**************************************************************************//**
dkato 0:853f5b7408a7 716 * @brief VDC5 S1_VFIELD interrupt service routine
dkato 0:853f5b7408a7 717 * @param[in] int_sense
dkato 0:853f5b7408a7 718 * @retval None
dkato 0:853f5b7408a7 719 *****************************************************************************/
dkato 0:853f5b7408a7 720 static void VDC5_Ch0_s1_vfield_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 721 {
dkato 0:853f5b7408a7 722 uint32_t IntState;
dkato 0:853f5b7408a7 723 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 724 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 725
dkato 0:853f5b7408a7 726 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 727
dkato 0:853f5b7408a7 728 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 729 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 730 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 731
dkato 0:853f5b7408a7 732 if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
dkato 0:853f5b7408a7 733 /* Clear */
dkato 0:853f5b7408a7 734 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
dkato 0:853f5b7408a7 735
dkato 0:853f5b7408a7 736 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD] != 0) {
dkato 0:853f5b7408a7 737 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
dkato 0:853f5b7408a7 738 }
dkato 0:853f5b7408a7 739 /* Set */
dkato 0:853f5b7408a7 740 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 741 }
dkato 0:853f5b7408a7 742 } /* End of function VDC5_Ch0_s1_vfield_ISR() */
dkato 0:853f5b7408a7 743
dkato 0:853f5b7408a7 744 /**************************************************************************//**
dkato 0:853f5b7408a7 745 * @brief VDC5 IV2_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 746 * @param[in] int_sense
dkato 0:853f5b7408a7 747 * @retval None
dkato 0:853f5b7408a7 748 *****************************************************************************/
dkato 0:853f5b7408a7 749 static void VDC5_Ch0_iv2_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 750 {
dkato 0:853f5b7408a7 751 uint32_t IntState;
dkato 0:853f5b7408a7 752 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 753 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 754
dkato 0:853f5b7408a7 755 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 756
dkato 0:853f5b7408a7 757 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 758 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 759 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 760
dkato 0:853f5b7408a7 761 if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 762 /* Clear */
dkato 0:853f5b7408a7 763 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
dkato 0:853f5b7408a7 764
dkato 0:853f5b7408a7 765 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
dkato 0:853f5b7408a7 766 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
dkato 0:853f5b7408a7 767 }
dkato 0:853f5b7408a7 768 /* Set */
dkato 0:853f5b7408a7 769 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 770 }
dkato 0:853f5b7408a7 771 } /* End of function VDC5_Ch0_iv2_vbuferr_ISR() */
dkato 0:853f5b7408a7 772
dkato 0:853f5b7408a7 773 /**************************************************************************//**
dkato 0:853f5b7408a7 774 * @brief VDC5 IV4_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 775 * @param[in] int_sense
dkato 0:853f5b7408a7 776 * @retval None
dkato 0:853f5b7408a7 777 *****************************************************************************/
dkato 0:853f5b7408a7 778 static void VDC5_Ch0_iv4_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 779 {
dkato 0:853f5b7408a7 780 uint32_t IntState;
dkato 0:853f5b7408a7 781 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 782 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 783
dkato 0:853f5b7408a7 784 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 785
dkato 0:853f5b7408a7 786 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
dkato 0:853f5b7408a7 787 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
dkato 0:853f5b7408a7 788 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 789
dkato 0:853f5b7408a7 790 if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 791 /* Clear */
dkato 0:853f5b7408a7 792 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
dkato 0:853f5b7408a7 793
dkato 0:853f5b7408a7 794 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
dkato 0:853f5b7408a7 795 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
dkato 0:853f5b7408a7 796 }
dkato 0:853f5b7408a7 797 /* Set */
dkato 0:853f5b7408a7 798 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 799 }
dkato 0:853f5b7408a7 800 } /* End of function VDC5_Ch0_iv4_vbuferr_ISR() */
dkato 0:853f5b7408a7 801
dkato 0:853f5b7408a7 802 /**************************************************************************//**
dkato 0:853f5b7408a7 803 * @brief VDC5 S1_WLINE interrupt service routine
dkato 0:853f5b7408a7 804 * @param[in] int_sense
dkato 0:853f5b7408a7 805 * @retval None
dkato 0:853f5b7408a7 806 *****************************************************************************/
dkato 0:853f5b7408a7 807 static void VDC5_Ch0_s1_wline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 808 {
dkato 0:853f5b7408a7 809 uint32_t IntState;
dkato 0:853f5b7408a7 810 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 811 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 812
dkato 0:853f5b7408a7 813 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 814
dkato 0:853f5b7408a7 815 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 816 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 817 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 818
dkato 0:853f5b7408a7 819 if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
dkato 0:853f5b7408a7 820 /* Clear */
dkato 0:853f5b7408a7 821 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
dkato 0:853f5b7408a7 822
dkato 0:853f5b7408a7 823 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE] != 0) {
dkato 0:853f5b7408a7 824 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
dkato 0:853f5b7408a7 825 }
dkato 0:853f5b7408a7 826 /* Set */
dkato 0:853f5b7408a7 827 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 828 }
dkato 0:853f5b7408a7 829 } /* End of function VDC5_Ch0_s1_wline_ISR() */
dkato 0:853f5b7408a7 830
dkato 0:853f5b7408a7 831 /**************************************************************************//**
dkato 0:853f5b7408a7 832 * @brief VDC5 OIR_VI_VSYNC interrupt service routine
dkato 0:853f5b7408a7 833 * @param[in] int_sense
dkato 0:853f5b7408a7 834 * @retval None
dkato 0:853f5b7408a7 835 *****************************************************************************/
dkato 0:853f5b7408a7 836 static void VDC5_Ch0_oir_vi_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 837 {
dkato 0:853f5b7408a7 838 uint32_t IntState;
dkato 0:853f5b7408a7 839 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 840 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 841
dkato 0:853f5b7408a7 842 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 843
dkato 0:853f5b7408a7 844 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 845 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 846 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 847
dkato 0:853f5b7408a7 848 if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 849 /* Clear */
dkato 0:853f5b7408a7 850 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
dkato 0:853f5b7408a7 851
dkato 0:853f5b7408a7 852 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
dkato 0:853f5b7408a7 853 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
dkato 0:853f5b7408a7 854 }
dkato 0:853f5b7408a7 855 /* Set */
dkato 0:853f5b7408a7 856 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 857 }
dkato 0:853f5b7408a7 858 } /* End of function VDC5_Ch0_oir_vi_vsync_ISR() */
dkato 0:853f5b7408a7 859
dkato 0:853f5b7408a7 860 /**************************************************************************//**
dkato 0:853f5b7408a7 861 * @brief VDC5 OIR_LO_VSYNC interrupt service routine
dkato 0:853f5b7408a7 862 * @param[in] int_sense
dkato 0:853f5b7408a7 863 * @retval None
dkato 0:853f5b7408a7 864 *****************************************************************************/
dkato 0:853f5b7408a7 865 static void VDC5_Ch0_oir_lo_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 866 {
dkato 0:853f5b7408a7 867 uint32_t IntState;
dkato 0:853f5b7408a7 868 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 869 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 870
dkato 0:853f5b7408a7 871 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 872
dkato 0:853f5b7408a7 873 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 874 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 875 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 876
dkato 0:853f5b7408a7 877 if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 878 /* Clear */
dkato 0:853f5b7408a7 879 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
dkato 0:853f5b7408a7 880
dkato 0:853f5b7408a7 881 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
dkato 0:853f5b7408a7 882 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
dkato 0:853f5b7408a7 883 }
dkato 0:853f5b7408a7 884 /* Set */
dkato 0:853f5b7408a7 885 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 886 }
dkato 0:853f5b7408a7 887 } /* End of function VDC5_Ch0_oir_lo_vsync_ISR() */
dkato 0:853f5b7408a7 888
dkato 0:853f5b7408a7 889 /**************************************************************************//**
dkato 0:853f5b7408a7 890 * @brief VDC5 OIR_VLINE interrupt service routine
dkato 0:853f5b7408a7 891 * @param[in] int_sense
dkato 0:853f5b7408a7 892 * @retval None
dkato 0:853f5b7408a7 893 *****************************************************************************/
dkato 0:853f5b7408a7 894 static void VDC5_Ch0_oir_vline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 895 {
dkato 0:853f5b7408a7 896 uint32_t IntState;
dkato 0:853f5b7408a7 897 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 898 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 899
dkato 0:853f5b7408a7 900 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 901
dkato 0:853f5b7408a7 902 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 903 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 904 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 905
dkato 0:853f5b7408a7 906 if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
dkato 0:853f5b7408a7 907 /* Clear */
dkato 0:853f5b7408a7 908 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
dkato 0:853f5b7408a7 909
dkato 0:853f5b7408a7 910 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE] != 0) {
dkato 0:853f5b7408a7 911 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
dkato 0:853f5b7408a7 912 }
dkato 0:853f5b7408a7 913 /* Set */
dkato 0:853f5b7408a7 914 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 915 }
dkato 0:853f5b7408a7 916 } /* End of function VDC5_Ch0_oir_vline_ISR() */
dkato 0:853f5b7408a7 917
dkato 0:853f5b7408a7 918 /**************************************************************************//**
dkato 0:853f5b7408a7 919 * @brief VDC5 OIR_VFIELD interrupt service routine
dkato 0:853f5b7408a7 920 * @param[in] int_sense
dkato 0:853f5b7408a7 921 * @retval None
dkato 0:853f5b7408a7 922 *****************************************************************************/
dkato 0:853f5b7408a7 923 static void VDC5_Ch0_oir_vfield_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 924 {
dkato 0:853f5b7408a7 925 uint32_t IntState;
dkato 0:853f5b7408a7 926 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 927 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 928
dkato 0:853f5b7408a7 929 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 930
dkato 0:853f5b7408a7 931 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 932 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 933 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 934
dkato 0:853f5b7408a7 935 if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
dkato 0:853f5b7408a7 936 /* Clear */
dkato 0:853f5b7408a7 937 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
dkato 0:853f5b7408a7 938
dkato 0:853f5b7408a7 939 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
dkato 0:853f5b7408a7 940 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
dkato 0:853f5b7408a7 941 }
dkato 0:853f5b7408a7 942 /* Set */
dkato 0:853f5b7408a7 943 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 944 }
dkato 0:853f5b7408a7 945 } /* End of function VDC5_Ch0_oir_vfield_ISR() */
dkato 0:853f5b7408a7 946
dkato 0:853f5b7408a7 947 /**************************************************************************//**
dkato 0:853f5b7408a7 948 * @brief VDC5 IV7_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 949 * @param[in] int_sense
dkato 0:853f5b7408a7 950 * @retval None
dkato 0:853f5b7408a7 951 *****************************************************************************/
dkato 0:853f5b7408a7 952 static void VDC5_Ch0_iv7_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 953 {
dkato 0:853f5b7408a7 954 uint32_t IntState;
dkato 0:853f5b7408a7 955 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 956 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 957
dkato 0:853f5b7408a7 958 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 959
dkato 0:853f5b7408a7 960 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 961 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 962 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 963
dkato 0:853f5b7408a7 964 if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 965 /* Clear */
dkato 0:853f5b7408a7 966 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
dkato 0:853f5b7408a7 967
dkato 0:853f5b7408a7 968 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
dkato 0:853f5b7408a7 969 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
dkato 0:853f5b7408a7 970 }
dkato 0:853f5b7408a7 971 /* Set */
dkato 0:853f5b7408a7 972 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 973 }
dkato 0:853f5b7408a7 974 } /* End of function VDC5_Ch0_iv7_vbuferr_ISR() */
dkato 0:853f5b7408a7 975
dkato 0:853f5b7408a7 976 /**************************************************************************//**
dkato 0:853f5b7408a7 977 * @brief VDC5 IV8_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 978 * @param[in] int_sense
dkato 0:853f5b7408a7 979 * @retval None
dkato 0:853f5b7408a7 980 *****************************************************************************/
dkato 0:853f5b7408a7 981 static void VDC5_Ch0_iv8_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 982 {
dkato 0:853f5b7408a7 983 uint32_t IntState;
dkato 0:853f5b7408a7 984 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 985 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 986
dkato 0:853f5b7408a7 987 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 988
dkato 0:853f5b7408a7 989 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
dkato 0:853f5b7408a7 990 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
dkato 0:853f5b7408a7 991 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 992
dkato 0:853f5b7408a7 993 if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 994 /* Clear */
dkato 0:853f5b7408a7 995 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
dkato 0:853f5b7408a7 996
dkato 0:853f5b7408a7 997 if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
dkato 0:853f5b7408a7 998 vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
dkato 0:853f5b7408a7 999 }
dkato 0:853f5b7408a7 1000 /* Set */
dkato 0:853f5b7408a7 1001 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1002 }
dkato 0:853f5b7408a7 1003 } /* End of function VDC5_Ch0_iv8_vbuferr_ISR() */
dkato 0:853f5b7408a7 1004
dkato 0:853f5b7408a7 1005 /**************************************************************************//**
dkato 0:853f5b7408a7 1006 * @brief VDC5 S0_VI_VSYNC interrupt service routine
dkato 0:853f5b7408a7 1007 * @param[in] int_sense
dkato 0:853f5b7408a7 1008 * @retval None
dkato 0:853f5b7408a7 1009 *****************************************************************************/
dkato 0:853f5b7408a7 1010 static void VDC5_Ch1_s0_vi_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1011 {
dkato 0:853f5b7408a7 1012 uint32_t IntState;
dkato 0:853f5b7408a7 1013 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1014 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1015
dkato 0:853f5b7408a7 1016 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1017
dkato 0:853f5b7408a7 1018 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1019 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1020 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1021
dkato 0:853f5b7408a7 1022 if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 1023 /* Clear */
dkato 0:853f5b7408a7 1024 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
dkato 0:853f5b7408a7 1025
dkato 0:853f5b7408a7 1026 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
dkato 0:853f5b7408a7 1027 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
dkato 0:853f5b7408a7 1028 }
dkato 0:853f5b7408a7 1029 /* Set */
dkato 0:853f5b7408a7 1030 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1031 }
dkato 0:853f5b7408a7 1032 } /* End of function VDC5_Ch1_s0_vi_vsync_ISR() */
dkato 0:853f5b7408a7 1033
dkato 0:853f5b7408a7 1034 /**************************************************************************//**
dkato 0:853f5b7408a7 1035 * @brief VDC5 S0_LO_VSYNC interrupt service routine
dkato 0:853f5b7408a7 1036 * @param[in] int_sense
dkato 0:853f5b7408a7 1037 * @retval None
dkato 0:853f5b7408a7 1038 *****************************************************************************/
dkato 0:853f5b7408a7 1039 static void VDC5_Ch1_s0_lo_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1040 {
dkato 0:853f5b7408a7 1041 uint32_t IntState;
dkato 0:853f5b7408a7 1042 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1043 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1044
dkato 0:853f5b7408a7 1045 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1046
dkato 0:853f5b7408a7 1047 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1048 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1049 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1050
dkato 0:853f5b7408a7 1051 if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 1052 /* Clear */
dkato 0:853f5b7408a7 1053 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
dkato 0:853f5b7408a7 1054
dkato 0:853f5b7408a7 1055 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
dkato 0:853f5b7408a7 1056 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
dkato 0:853f5b7408a7 1057 }
dkato 0:853f5b7408a7 1058 /* Set */
dkato 0:853f5b7408a7 1059 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1060 }
dkato 0:853f5b7408a7 1061 } /* End of function VDC5_Ch1_s0_lo_vsync_ISR() */
dkato 0:853f5b7408a7 1062
dkato 0:853f5b7408a7 1063 /**************************************************************************//**
dkato 0:853f5b7408a7 1064 * @brief VDC5 S0_VSYNCERR interrupt service routine
dkato 0:853f5b7408a7 1065 * @param[in] int_sense
dkato 0:853f5b7408a7 1066 * @retval None
dkato 0:853f5b7408a7 1067 *****************************************************************************/
dkato 0:853f5b7408a7 1068 static void VDC5_Ch1_s0_vsyncerr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1069 {
dkato 0:853f5b7408a7 1070 uint32_t IntState;
dkato 0:853f5b7408a7 1071 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1072 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1073
dkato 0:853f5b7408a7 1074 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1075
dkato 0:853f5b7408a7 1076 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1077 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1078 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1079
dkato 0:853f5b7408a7 1080 if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
dkato 0:853f5b7408a7 1081 /* Clear */
dkato 0:853f5b7408a7 1082 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
dkato 0:853f5b7408a7 1083
dkato 0:853f5b7408a7 1084 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
dkato 0:853f5b7408a7 1085 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
dkato 0:853f5b7408a7 1086 }
dkato 0:853f5b7408a7 1087 /* Set */
dkato 0:853f5b7408a7 1088 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1089 }
dkato 0:853f5b7408a7 1090 } /* End of function VDC5_Ch1_s0_vsyncerr_ISR() */
dkato 0:853f5b7408a7 1091
dkato 0:853f5b7408a7 1092 /**************************************************************************//**
dkato 0:853f5b7408a7 1093 * @brief VDC5 VLINE interrupt service routine
dkato 0:853f5b7408a7 1094 * @param[in] int_sense
dkato 0:853f5b7408a7 1095 * @retval None
dkato 0:853f5b7408a7 1096 *****************************************************************************/
dkato 0:853f5b7408a7 1097 static void VDC5_Ch1_vline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1098 {
dkato 0:853f5b7408a7 1099 uint32_t IntState;
dkato 0:853f5b7408a7 1100 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1101 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1102
dkato 0:853f5b7408a7 1103 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1104
dkato 0:853f5b7408a7 1105 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1106 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1107 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1108
dkato 0:853f5b7408a7 1109 if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
dkato 0:853f5b7408a7 1110 /* Clear */
dkato 0:853f5b7408a7 1111 *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
dkato 0:853f5b7408a7 1112
dkato 0:853f5b7408a7 1113 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE] != 0) {
dkato 0:853f5b7408a7 1114 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
dkato 0:853f5b7408a7 1115 }
dkato 0:853f5b7408a7 1116 /* Set */
dkato 0:853f5b7408a7 1117 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1118 }
dkato 0:853f5b7408a7 1119 } /* End of function VDC5_Ch1_vline_ISR() */
dkato 0:853f5b7408a7 1120
dkato 0:853f5b7408a7 1121 /**************************************************************************//**
dkato 0:853f5b7408a7 1122 * @brief VDC5 S0_VFIELD interrupt service routine
dkato 0:853f5b7408a7 1123 * @param[in] int_sense
dkato 0:853f5b7408a7 1124 * @retval None
dkato 0:853f5b7408a7 1125 *****************************************************************************/
dkato 0:853f5b7408a7 1126 static void VDC5_Ch1_s0_vfield_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1127 {
dkato 0:853f5b7408a7 1128 uint32_t IntState;
dkato 0:853f5b7408a7 1129 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1130 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1131
dkato 0:853f5b7408a7 1132 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1133
dkato 0:853f5b7408a7 1134 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1135 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1136 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1137
dkato 0:853f5b7408a7 1138 if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
dkato 0:853f5b7408a7 1139 /* Clear */
dkato 0:853f5b7408a7 1140 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
dkato 0:853f5b7408a7 1141
dkato 0:853f5b7408a7 1142 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD] != 0) {
dkato 0:853f5b7408a7 1143 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
dkato 0:853f5b7408a7 1144 }
dkato 0:853f5b7408a7 1145 /* Set */
dkato 0:853f5b7408a7 1146 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1147 }
dkato 0:853f5b7408a7 1148 } /* End of function VDC5_Ch1_s0_vfield_ISR() */
dkato 0:853f5b7408a7 1149
dkato 0:853f5b7408a7 1150 /**************************************************************************//**
dkato 0:853f5b7408a7 1151 * @brief VDC5 IV1_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1152 * @param[in] int_sense
dkato 0:853f5b7408a7 1153 * @retval None
dkato 0:853f5b7408a7 1154 *****************************************************************************/
dkato 0:853f5b7408a7 1155 static void VDC5_Ch1_iv1_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1156 {
dkato 0:853f5b7408a7 1157 uint32_t IntState;
dkato 0:853f5b7408a7 1158 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1159 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1160
dkato 0:853f5b7408a7 1161 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1162
dkato 0:853f5b7408a7 1163 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1164 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1165 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1166
dkato 0:853f5b7408a7 1167 if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1168 /* Clear */
dkato 0:853f5b7408a7 1169 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
dkato 0:853f5b7408a7 1170
dkato 0:853f5b7408a7 1171 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1172 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
dkato 0:853f5b7408a7 1173 }
dkato 0:853f5b7408a7 1174 /* Set */
dkato 0:853f5b7408a7 1175 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1176 }
dkato 0:853f5b7408a7 1177 } /* End of function VDC5_Ch1_iv1_vbuferr_ISR() */
dkato 0:853f5b7408a7 1178
dkato 0:853f5b7408a7 1179 /**************************************************************************//**
dkato 0:853f5b7408a7 1180 * @brief VDC5 IV3_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1181 * @param[in] int_sense
dkato 0:853f5b7408a7 1182 * @retval None
dkato 0:853f5b7408a7 1183 *****************************************************************************/
dkato 0:853f5b7408a7 1184 static void VDC5_Ch1_iv3_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1185 {
dkato 0:853f5b7408a7 1186 uint32_t IntState;
dkato 0:853f5b7408a7 1187 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1188 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1189
dkato 0:853f5b7408a7 1190 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1191
dkato 0:853f5b7408a7 1192 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1193 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1194 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1195
dkato 0:853f5b7408a7 1196 if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1197 /* Clear */
dkato 0:853f5b7408a7 1198 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
dkato 0:853f5b7408a7 1199
dkato 0:853f5b7408a7 1200 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1201 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
dkato 0:853f5b7408a7 1202 }
dkato 0:853f5b7408a7 1203 /* Set */
dkato 0:853f5b7408a7 1204 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1205 }
dkato 0:853f5b7408a7 1206 } /* End of function VDC5_Ch1_iv3_vbuferr_ISR() */
dkato 0:853f5b7408a7 1207
dkato 0:853f5b7408a7 1208 /**************************************************************************//**
dkato 0:853f5b7408a7 1209 * @brief VDC5 IV5_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1210 * @param[in] int_sense
dkato 0:853f5b7408a7 1211 * @retval None
dkato 0:853f5b7408a7 1212 *****************************************************************************/
dkato 0:853f5b7408a7 1213 static void VDC5_Ch1_iv5_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1214 {
dkato 0:853f5b7408a7 1215 uint32_t IntState;
dkato 0:853f5b7408a7 1216 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1217 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1218
dkato 0:853f5b7408a7 1219 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1220
dkato 0:853f5b7408a7 1221 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
dkato 0:853f5b7408a7 1222 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
dkato 0:853f5b7408a7 1223 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1224
dkato 0:853f5b7408a7 1225 if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1226 /* Clear */
dkato 0:853f5b7408a7 1227 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
dkato 0:853f5b7408a7 1228
dkato 0:853f5b7408a7 1229 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1230 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
dkato 0:853f5b7408a7 1231 }
dkato 0:853f5b7408a7 1232 /* Set */
dkato 0:853f5b7408a7 1233 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1234 }
dkato 0:853f5b7408a7 1235 } /* End of function VDC5_Ch1_iv5_vbuferr_ISR() */
dkato 0:853f5b7408a7 1236
dkato 0:853f5b7408a7 1237 /**************************************************************************//**
dkato 0:853f5b7408a7 1238 * @brief VDC5 IV6_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1239 * @param[in] int_sense
dkato 0:853f5b7408a7 1240 * @retval None
dkato 0:853f5b7408a7 1241 *****************************************************************************/
dkato 0:853f5b7408a7 1242 static void VDC5_Ch1_iv6_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1243 {
dkato 0:853f5b7408a7 1244 uint32_t IntState;
dkato 0:853f5b7408a7 1245 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1246 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1247
dkato 0:853f5b7408a7 1248 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1249
dkato 0:853f5b7408a7 1250 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1251 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1252 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1253
dkato 0:853f5b7408a7 1254 if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1255 /* Clear */
dkato 0:853f5b7408a7 1256 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
dkato 0:853f5b7408a7 1257
dkato 0:853f5b7408a7 1258 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1259 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
dkato 0:853f5b7408a7 1260 }
dkato 0:853f5b7408a7 1261 /* Set */
dkato 0:853f5b7408a7 1262 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1263 }
dkato 0:853f5b7408a7 1264 } /* End of function VDC5_Ch1_iv6_vbuferr_ISR() */
dkato 0:853f5b7408a7 1265
dkato 0:853f5b7408a7 1266 /**************************************************************************//**
dkato 0:853f5b7408a7 1267 * @brief VDC5 S0_WLINE interrupt service routine
dkato 0:853f5b7408a7 1268 * @param[in] int_sense
dkato 0:853f5b7408a7 1269 * @retval None
dkato 0:853f5b7408a7 1270 *****************************************************************************/
dkato 0:853f5b7408a7 1271 static void VDC5_Ch1_s0_wline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1272 {
dkato 0:853f5b7408a7 1273 uint32_t IntState;
dkato 0:853f5b7408a7 1274 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1275 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1276
dkato 0:853f5b7408a7 1277 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1278
dkato 0:853f5b7408a7 1279 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1280 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1281 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1282
dkato 0:853f5b7408a7 1283 if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
dkato 0:853f5b7408a7 1284 /* Clear */
dkato 0:853f5b7408a7 1285 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
dkato 0:853f5b7408a7 1286
dkato 0:853f5b7408a7 1287 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE] != 0) {
dkato 0:853f5b7408a7 1288 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
dkato 0:853f5b7408a7 1289 }
dkato 0:853f5b7408a7 1290 /* Set */
dkato 0:853f5b7408a7 1291 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1292 }
dkato 0:853f5b7408a7 1293 } /* End of function VDC5_Ch1_s0_wline_ISR() */
dkato 0:853f5b7408a7 1294
dkato 0:853f5b7408a7 1295 /**************************************************************************//**
dkato 0:853f5b7408a7 1296 * @brief VDC5 S1_VI_VSYNC interrupt service routine
dkato 0:853f5b7408a7 1297 * @param[in] int_sense
dkato 0:853f5b7408a7 1298 * @retval None
dkato 0:853f5b7408a7 1299 *****************************************************************************/
dkato 0:853f5b7408a7 1300 static void VDC5_Ch1_s1_vi_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1301 {
dkato 0:853f5b7408a7 1302 uint32_t IntState;
dkato 0:853f5b7408a7 1303 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1304 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1305
dkato 0:853f5b7408a7 1306 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1307
dkato 0:853f5b7408a7 1308 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1309 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1310 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1311
dkato 0:853f5b7408a7 1312 if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 1313 /* Clear */
dkato 0:853f5b7408a7 1314 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
dkato 0:853f5b7408a7 1315
dkato 0:853f5b7408a7 1316 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
dkato 0:853f5b7408a7 1317 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
dkato 0:853f5b7408a7 1318 }
dkato 0:853f5b7408a7 1319 /* Set */
dkato 0:853f5b7408a7 1320 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1321 }
dkato 0:853f5b7408a7 1322 } /* End of function VDC5_Ch1_s1_vi_vsync_ISR() */
dkato 0:853f5b7408a7 1323
dkato 0:853f5b7408a7 1324 /**************************************************************************//**
dkato 0:853f5b7408a7 1325 * @brief VDC5 S1_LO_VSYNC interrupt service routine
dkato 0:853f5b7408a7 1326 * @param[in] int_sense
dkato 0:853f5b7408a7 1327 * @retval None
dkato 0:853f5b7408a7 1328 *****************************************************************************/
dkato 0:853f5b7408a7 1329 static void VDC5_Ch1_s1_lo_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1330 {
dkato 0:853f5b7408a7 1331 uint32_t IntState;
dkato 0:853f5b7408a7 1332 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1333 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1334
dkato 0:853f5b7408a7 1335 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1336
dkato 0:853f5b7408a7 1337 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1338 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1339 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1340
dkato 0:853f5b7408a7 1341 if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 1342 /* Clear */
dkato 0:853f5b7408a7 1343 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
dkato 0:853f5b7408a7 1344
dkato 0:853f5b7408a7 1345 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
dkato 0:853f5b7408a7 1346 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
dkato 0:853f5b7408a7 1347 }
dkato 0:853f5b7408a7 1348 /* Set */
dkato 0:853f5b7408a7 1349 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1350 }
dkato 0:853f5b7408a7 1351 } /* End of function VDC5_Ch1_s1_lo_vsync_ISR() */
dkato 0:853f5b7408a7 1352
dkato 0:853f5b7408a7 1353 /**************************************************************************//**
dkato 0:853f5b7408a7 1354 * @brief VDC5 S1_VSYNCERR interrupt service routine
dkato 0:853f5b7408a7 1355 * @param[in] int_sense
dkato 0:853f5b7408a7 1356 * @retval None
dkato 0:853f5b7408a7 1357 *****************************************************************************/
dkato 0:853f5b7408a7 1358 static void VDC5_Ch1_s1_vsyncerr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1359 {
dkato 0:853f5b7408a7 1360 uint32_t IntState;
dkato 0:853f5b7408a7 1361 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1362 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1363
dkato 0:853f5b7408a7 1364 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1365
dkato 0:853f5b7408a7 1366 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1367 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1368 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1369
dkato 0:853f5b7408a7 1370 if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
dkato 0:853f5b7408a7 1371 /* Clear */
dkato 0:853f5b7408a7 1372 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
dkato 0:853f5b7408a7 1373
dkato 0:853f5b7408a7 1374 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
dkato 0:853f5b7408a7 1375 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
dkato 0:853f5b7408a7 1376 }
dkato 0:853f5b7408a7 1377 /* Set */
dkato 0:853f5b7408a7 1378 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1379 }
dkato 0:853f5b7408a7 1380 } /* End of function VDC5_Ch1_s1_vsyncerr_ISR() */
dkato 0:853f5b7408a7 1381
dkato 0:853f5b7408a7 1382 /**************************************************************************//**
dkato 0:853f5b7408a7 1383 * @brief VDC5 S1_VFIELD interrupt service routine
dkato 0:853f5b7408a7 1384 * @param[in] int_sense
dkato 0:853f5b7408a7 1385 * @retval None
dkato 0:853f5b7408a7 1386 *****************************************************************************/
dkato 0:853f5b7408a7 1387 static void VDC5_Ch1_s1_vfield_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1388 {
dkato 0:853f5b7408a7 1389 uint32_t IntState;
dkato 0:853f5b7408a7 1390 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1391 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1392
dkato 0:853f5b7408a7 1393 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1394
dkato 0:853f5b7408a7 1395 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1396 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1397 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1398
dkato 0:853f5b7408a7 1399 if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
dkato 0:853f5b7408a7 1400 /* Clear */
dkato 0:853f5b7408a7 1401 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
dkato 0:853f5b7408a7 1402
dkato 0:853f5b7408a7 1403 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD] != 0) {
dkato 0:853f5b7408a7 1404 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
dkato 0:853f5b7408a7 1405 }
dkato 0:853f5b7408a7 1406 /* Set */
dkato 0:853f5b7408a7 1407 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1408 }
dkato 0:853f5b7408a7 1409 } /* End of function VDC5_Ch1_s1_vfield_ISR() */
dkato 0:853f5b7408a7 1410
dkato 0:853f5b7408a7 1411 /**************************************************************************//**
dkato 0:853f5b7408a7 1412 * @brief VDC5 IV2_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1413 * @param[in] int_sense
dkato 0:853f5b7408a7 1414 * @retval None
dkato 0:853f5b7408a7 1415 *****************************************************************************/
dkato 0:853f5b7408a7 1416 static void VDC5_Ch1_iv2_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1417 {
dkato 0:853f5b7408a7 1418 uint32_t IntState;
dkato 0:853f5b7408a7 1419 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1420 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1421
dkato 0:853f5b7408a7 1422 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1423
dkato 0:853f5b7408a7 1424 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1425 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1426 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1427
dkato 0:853f5b7408a7 1428 if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1429 /* Clear */
dkato 0:853f5b7408a7 1430 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
dkato 0:853f5b7408a7 1431
dkato 0:853f5b7408a7 1432 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1433 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
dkato 0:853f5b7408a7 1434 }
dkato 0:853f5b7408a7 1435 /* Set */
dkato 0:853f5b7408a7 1436 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1437 }
dkato 0:853f5b7408a7 1438 } /* End of function VDC5_Ch1_iv2_vbuferr_ISR() */
dkato 0:853f5b7408a7 1439
dkato 0:853f5b7408a7 1440 /**************************************************************************//**
dkato 0:853f5b7408a7 1441 * @brief VDC5 IV4_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1442 * @param[in] int_sense
dkato 0:853f5b7408a7 1443 * @retval None
dkato 0:853f5b7408a7 1444 *****************************************************************************/
dkato 0:853f5b7408a7 1445 static void VDC5_Ch1_iv4_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1446 {
dkato 0:853f5b7408a7 1447 uint32_t IntState;
dkato 0:853f5b7408a7 1448 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1449 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1450
dkato 0:853f5b7408a7 1451 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1452
dkato 0:853f5b7408a7 1453 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
dkato 0:853f5b7408a7 1454 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
dkato 0:853f5b7408a7 1455 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1456
dkato 0:853f5b7408a7 1457 if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1458 /* Clear */
dkato 0:853f5b7408a7 1459 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
dkato 0:853f5b7408a7 1460
dkato 0:853f5b7408a7 1461 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1462 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
dkato 0:853f5b7408a7 1463 }
dkato 0:853f5b7408a7 1464 /* Set */
dkato 0:853f5b7408a7 1465 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1466 }
dkato 0:853f5b7408a7 1467 } /* End of function VDC5_Ch1_iv4_vbuferr_ISR() */
dkato 0:853f5b7408a7 1468
dkato 0:853f5b7408a7 1469 /**************************************************************************//**
dkato 0:853f5b7408a7 1470 * @brief VDC5 S1_WLINE interrupt service routine
dkato 0:853f5b7408a7 1471 * @param[in] int_sense
dkato 0:853f5b7408a7 1472 * @retval None
dkato 0:853f5b7408a7 1473 *****************************************************************************/
dkato 0:853f5b7408a7 1474 static void VDC5_Ch1_s1_wline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1475 {
dkato 0:853f5b7408a7 1476 uint32_t IntState;
dkato 0:853f5b7408a7 1477 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1478 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1479
dkato 0:853f5b7408a7 1480 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1481
dkato 0:853f5b7408a7 1482 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1483 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1484 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1485
dkato 0:853f5b7408a7 1486 if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
dkato 0:853f5b7408a7 1487 /* Clear */
dkato 0:853f5b7408a7 1488 *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
dkato 0:853f5b7408a7 1489
dkato 0:853f5b7408a7 1490 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE] != 0) {
dkato 0:853f5b7408a7 1491 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
dkato 0:853f5b7408a7 1492 }
dkato 0:853f5b7408a7 1493 /* Set */
dkato 0:853f5b7408a7 1494 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1495 }
dkato 0:853f5b7408a7 1496 } /* End of function VDC5_Ch1_s1_wline_ISR() */
dkato 0:853f5b7408a7 1497
dkato 0:853f5b7408a7 1498 /**************************************************************************//**
dkato 0:853f5b7408a7 1499 * @brief VDC5 OIR_VI_VSYNC interrupt service routine
dkato 0:853f5b7408a7 1500 * @param[in] int_sense
dkato 0:853f5b7408a7 1501 * @retval None
dkato 0:853f5b7408a7 1502 *****************************************************************************/
dkato 0:853f5b7408a7 1503 static void VDC5_Ch1_oir_vi_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1504 {
dkato 0:853f5b7408a7 1505 uint32_t IntState;
dkato 0:853f5b7408a7 1506 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1507 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1508
dkato 0:853f5b7408a7 1509 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1510
dkato 0:853f5b7408a7 1511 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1512 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1513 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1514
dkato 0:853f5b7408a7 1515 if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 1516 /* Clear */
dkato 0:853f5b7408a7 1517 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
dkato 0:853f5b7408a7 1518
dkato 0:853f5b7408a7 1519 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
dkato 0:853f5b7408a7 1520 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
dkato 0:853f5b7408a7 1521 }
dkato 0:853f5b7408a7 1522 /* Set */
dkato 0:853f5b7408a7 1523 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1524 }
dkato 0:853f5b7408a7 1525 } /* End of function VDC5_Ch1_oir_vi_vsync_ISR() */
dkato 0:853f5b7408a7 1526
dkato 0:853f5b7408a7 1527 /**************************************************************************//**
dkato 0:853f5b7408a7 1528 * @brief VDC5 OIR_LO_VSYNC interrupt service routine
dkato 0:853f5b7408a7 1529 * @param[in] int_sense
dkato 0:853f5b7408a7 1530 * @retval None
dkato 0:853f5b7408a7 1531 *****************************************************************************/
dkato 0:853f5b7408a7 1532 static void VDC5_Ch1_oir_lo_vsync_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1533 {
dkato 0:853f5b7408a7 1534 uint32_t IntState;
dkato 0:853f5b7408a7 1535 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1536 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1537
dkato 0:853f5b7408a7 1538 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1539
dkato 0:853f5b7408a7 1540 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1541 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1542 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1543
dkato 0:853f5b7408a7 1544 if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
dkato 0:853f5b7408a7 1545 /* Clear */
dkato 0:853f5b7408a7 1546 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
dkato 0:853f5b7408a7 1547
dkato 0:853f5b7408a7 1548 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
dkato 0:853f5b7408a7 1549 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
dkato 0:853f5b7408a7 1550 }
dkato 0:853f5b7408a7 1551 /* Set */
dkato 0:853f5b7408a7 1552 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1553 }
dkato 0:853f5b7408a7 1554 } /* End of function VDC5_Ch1_oir_lo_vsync_ISR() */
dkato 0:853f5b7408a7 1555
dkato 0:853f5b7408a7 1556 /**************************************************************************//**
dkato 0:853f5b7408a7 1557 * @brief VDC5 OIR_VLINE interrupt service routine
dkato 0:853f5b7408a7 1558 * @param[in] int_sense
dkato 0:853f5b7408a7 1559 * @retval None
dkato 0:853f5b7408a7 1560 *****************************************************************************/
dkato 0:853f5b7408a7 1561 static void VDC5_Ch1_oir_vline_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1562 {
dkato 0:853f5b7408a7 1563 uint32_t IntState;
dkato 0:853f5b7408a7 1564 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1565 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1566
dkato 0:853f5b7408a7 1567 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1568
dkato 0:853f5b7408a7 1569 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1570 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1571 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1572
dkato 0:853f5b7408a7 1573 if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
dkato 0:853f5b7408a7 1574 /* Clear */
dkato 0:853f5b7408a7 1575 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
dkato 0:853f5b7408a7 1576
dkato 0:853f5b7408a7 1577 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE] != 0) {
dkato 0:853f5b7408a7 1578 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
dkato 0:853f5b7408a7 1579 }
dkato 0:853f5b7408a7 1580 /* Set */
dkato 0:853f5b7408a7 1581 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1582 }
dkato 0:853f5b7408a7 1583 } /* End of function VDC5_Ch1_oir_vline_ISR() */
dkato 0:853f5b7408a7 1584
dkato 0:853f5b7408a7 1585 /**************************************************************************//**
dkato 0:853f5b7408a7 1586 * @brief VDC5 OIR_VFIELD interrupt service routine
dkato 0:853f5b7408a7 1587 * @param[in] int_sense
dkato 0:853f5b7408a7 1588 * @retval None
dkato 0:853f5b7408a7 1589 *****************************************************************************/
dkato 0:853f5b7408a7 1590 static void VDC5_Ch1_oir_vfield_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1591 {
dkato 0:853f5b7408a7 1592 uint32_t IntState;
dkato 0:853f5b7408a7 1593 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1594 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1595
dkato 0:853f5b7408a7 1596 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1597
dkato 0:853f5b7408a7 1598 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1599 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1600 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1601
dkato 0:853f5b7408a7 1602 if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
dkato 0:853f5b7408a7 1603 /* Clear */
dkato 0:853f5b7408a7 1604 *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
dkato 0:853f5b7408a7 1605
dkato 0:853f5b7408a7 1606 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
dkato 0:853f5b7408a7 1607 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
dkato 0:853f5b7408a7 1608 }
dkato 0:853f5b7408a7 1609 /* Set */
dkato 0:853f5b7408a7 1610 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1611 }
dkato 0:853f5b7408a7 1612 } /* End of function VDC5_Ch1_oir_vfield_ISR() */
dkato 0:853f5b7408a7 1613
dkato 0:853f5b7408a7 1614 /**************************************************************************//**
dkato 0:853f5b7408a7 1615 * @brief VDC5 IV7_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1616 * @param[in] int_sense
dkato 0:853f5b7408a7 1617 * @retval None
dkato 0:853f5b7408a7 1618 *****************************************************************************/
dkato 0:853f5b7408a7 1619 static void VDC5_Ch1_iv7_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1620 {
dkato 0:853f5b7408a7 1621 uint32_t IntState;
dkato 0:853f5b7408a7 1622 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1623 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1624
dkato 0:853f5b7408a7 1625 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1626
dkato 0:853f5b7408a7 1627 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1628 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1629 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1630
dkato 0:853f5b7408a7 1631 if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1632 /* Clear */
dkato 0:853f5b7408a7 1633 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
dkato 0:853f5b7408a7 1634
dkato 0:853f5b7408a7 1635 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1636 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
dkato 0:853f5b7408a7 1637 }
dkato 0:853f5b7408a7 1638 /* Set */
dkato 0:853f5b7408a7 1639 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1640 }
dkato 0:853f5b7408a7 1641 } /* End of function VDC5_Ch1_iv7_vbuferr_ISR() */
dkato 0:853f5b7408a7 1642
dkato 0:853f5b7408a7 1643 /**************************************************************************//**
dkato 0:853f5b7408a7 1644 * @brief VDC5 IV8_VBUFERR interrupt service routine
dkato 0:853f5b7408a7 1645 * @param[in] int_sense
dkato 0:853f5b7408a7 1646 * @retval None
dkato 0:853f5b7408a7 1647 *****************************************************************************/
dkato 0:853f5b7408a7 1648 static void VDC5_Ch1_iv8_vbuferr_ISR (const uint32_t int_sense)
dkato 0:853f5b7408a7 1649 {
dkato 0:853f5b7408a7 1650 uint32_t IntState;
dkato 0:853f5b7408a7 1651 volatile uint32_t * int_clhd_reg;
dkato 0:853f5b7408a7 1652 volatile uint32_t * int_onoff_reg;
dkato 0:853f5b7408a7 1653
dkato 0:853f5b7408a7 1654 UNUSED_PARAM(int_sense);
dkato 0:853f5b7408a7 1655
dkato 0:853f5b7408a7 1656 int_clhd_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
dkato 0:853f5b7408a7 1657 int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
dkato 0:853f5b7408a7 1658 IntState = *int_onoff_reg;
dkato 0:853f5b7408a7 1659
dkato 0:853f5b7408a7 1660 if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
dkato 0:853f5b7408a7 1661 /* Clear */
dkato 0:853f5b7408a7 1662 *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
dkato 0:853f5b7408a7 1663
dkato 0:853f5b7408a7 1664 if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
dkato 0:853f5b7408a7 1665 vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
dkato 0:853f5b7408a7 1666 }
dkato 0:853f5b7408a7 1667 /* Set */
dkato 0:853f5b7408a7 1668 *int_clhd_reg = IntState;
dkato 0:853f5b7408a7 1669 }
dkato 0:853f5b7408a7 1670 } /* End of function VDC5_Ch1_iv8_vbuferr_ISR() */
dkato 0:853f5b7408a7 1671