Renesas / GR-PEACH_video

Video library for GR-PEACH

Dependents:   Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more

Video ｌibrary for GR-PEACH.

Hello World!

Import programGR-PEACH_Camera_in

Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.

Last commit 28 Dec 2018 by Renesas

API

Import library
GR-PEACH_video - DisplayBase Class Reference

Data Structures

struct lcd_config_t
LCD configuration. More...
struct rect_t
The relative position within the graphics display area. More...
struct video_ext_in_config_t
Digital Video Input configuration. More...

Public Types

enum video_input_channel_t { VIDEO_INPUT_CHANNEL_0 = 0, VIDEO_INPUT_CHANNEL_1 }

Video input channel select.

More...
enum graphics_layer_t { GRAPHICS_LAYER_0 = 0, GRAPHICS_LAYER_1 , GRAPHICS_LAYER_2 , GRAPHICS_LAYER_3 }

Graphics layer select.

More...
enum graphics_error_t {
GRAPHICS_OK = 0, GRAPHICS_VDC5_ERR = -1, GRAPHICS_FORMA_ERR = -2, GRAPHICS_LAYER_ERR = -3,
GRAPHICS_CHANNLE_ERR = -4, GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, GRAPHICS_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum graphics_format_t { GRAPHICS_FORMAT_YCBCR422 = 0, GRAPHICS_FORMAT_RGB565 , GRAPHICS_FORMAT_RGB888 , GRAPHICS_FORMAT_ARGB8888 }

Graphics layer read format selects.

More...
enum video_format_t { VIDEO_FORMAT_YCBCR422 = 0, VIDEO_FORMAT_RGB565 , VIDEO_FORMAT_RGB888 }

Video writing format selects.

More...
enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT , WR_RD_WRSWA_16BIT , WR_RD_WRSWA_16_8BIT ,
WR_RD_WRSWA_32BIT , WR_RD_WRSWA_32_8BIT , WR_RD_WRSWA_32_16BIT , WR_RD_WRSWA_32_16_8BIT
}

Frame buffer swap setting.

More...
enum lcd_tcon_pin_t { LCD_TCON_PIN_NON = -1, LCD_TCON_PIN_0 , LCD_TCON_PIN_1 , LCD_TCON_PIN_2 }

LCD tcon output pin selects.

More...
enum lcd_outformat_t { LCD_OUTFORMAT_RGB888 = 0, LCD_OUTFORMAT_RGB666 , LCD_OUTFORMAT_RGB565 }

LCD output format selects.

More...
enum edge_t { EDGE_RISING = 0, EDGE_FALLING = 1 }

Edge of a signal.

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enum lcd_type_t { LCD_TYPE_LVDS = 0, LCD_TYPE_PARALLEL_RGB }

LCD type.

More...
enum sig_pol_t { SIG_POL_NOT_INVERTED = 0, SIG_POL_INVERTED }

Polarity of a signal.

More...
enum int_type_t {
INT_TYPE_S0_VI_VSYNC = 0, INT_TYPE_S0_LO_VSYNC , INT_TYPE_S0_VSYNCERR , INT_TYPE_VLINE ,
INT_TYPE_S0_VFIELD , INT_TYPE_IV1_VBUFERR , INT_TYPE_IV3_VBUFERR , INT_TYPE_IV5_VBUFERR ,
INT_TYPE_IV6_VBUFERR , INT_TYPE_S0_WLINE , INT_TYPE_S1_VI_VSYNC , INT_TYPE_S1_LO_VSYNC ,
INT_TYPE_S1_VSYNCERR , INT_TYPE_S1_VFIELD , INT_TYPE_IV2_VBUFERR , INT_TYPE_IV4_VBUFERR ,
INT_TYPE_S1_WLINE , INT_TYPE_OIR_VI_VSYNC , INT_TYPE_OIR_LO_VSYNC , INT_TYPE_OIR_VLINE ,
INT_TYPE_OIR_VFIELD , INT_TYPE_IV7_VBUFERR , INT_TYPE_IV8_VBUFERR , INT_TYPE_NUM
}

Interrupt type.

More...
enum graphics_video_col_sys_t {
COL_SYS_NTSC_358 = 0, COL_SYS_NTSC_443 = 1, COL_SYS_PAL_443 = 2, COL_SYS_PAL_M = 3,
COL_SYS_PAL_N = 4, COL_SYS_SECAM = 5, COL_SYS_NTSC_443_60 = 6, COL_SYS_PAL_60 = 7
}

Video color system.

More...
enum video_input_sel_t { INPUT_SEL_VDEC = 0, INPUT_SEL_EXT = 1 }

External Input select.

More...
enum video_extin_format_t {
VIDEO_EXTIN_FORMAT_RGB888 = 0, VIDEO_EXTIN_FORMAT_RGB666 , VIDEO_EXTIN_FORMAT_RGB565 , VIDEO_EXTIN_FORMAT_BT656 ,
VIDEO_EXTIN_FORMAT_BT601 , VIDEO_EXTIN_FORMAT_YCBCR422 , VIDEO_EXTIN_FORMAT_YCBCR444
}

External input format select.

More...
enum onoff_t { OFF = 0, ON = 1 }

On/off.

More...
enum extin_input_line_t { EXTIN_LINE_525 = 0, EXTIN_LINE_625 = 1 }

Number of lines for BT.656 external input.

More...
enum extin_h_pos_t { EXTIN_H_POS_CBYCRY = 0, EXTIN_H_POS_YCRYCB , EXTIN_H_POS_CRYCBY , EXTIN_H_POS_YCBYCR }

Y/Cb/Y/Cr data string start timing.

More...

Public Member Functions

DisplayBase (void)
Constructor method of display base object.
graphics_error_t Graphics_init ( lcd_config_t *lcd_config)
Graphics initialization processing
If not using display, set NULL in parameter.
graphics_error_t Graphics_Video_init ( video_input_sel_t video_input_sel, video_ext_in_config_t *video_ext_in_config)
Graphics Video initialization processing
If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
graphics_error_t Graphics_Lcd_Port_Init (PinName *pin, unsigned int pin_count)
LCD output port initialization processing.
graphics_error_t Graphics_Lvds_Port_Init (PinName *pin, unsigned int pin_count)
LVDS output port initialization processing.
graphics_error_t Graphics_Dvinput_Port_Init (PinName *pin, unsigned int pin_count)
Digital video input port initialization processing.
graphics_error_t Graphics_Irq_Handler_Set ( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void(*callback)( int_type_t ))
Interrupt callback setup This function performs the following processing:

  • Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.

graphics_error_t Graphics_Start ( graphics_layer_t layer_id)
Start the graphics surface read process.
graphics_error_t Graphics_Stop ( graphics_layer_t layer_id)
Stop the graphics surface read process.
graphics_error_t Video_Start ( video_input_channel_t video_input_channel)
Start the video surface write process.
graphics_error_t Video_Stop ( video_input_channel_t video_input_channel)
Stop the video surface write process.
graphics_error_t Graphics_Read_Setting ( graphics_layer_t layer_id, void *framebuff, unsigned int fb_stride, graphics_format_t gr_format, wr_rd_swa_t wr_rd_swa, rect_t *gr_rect)
Graphics surface read process setting.
graphics_error_t Graphics_Read_Change ( graphics_layer_t layer_id, void *framebuff)
Graphics surface read buffer change process.
graphics_error_t Video_Write_Setting ( video_input_channel_t video_input_channel, graphics_video_col_sys_t col_sys, void *framebuff, unsigned int fb_stride, video_format_t video_format, wr_rd_swa_t wr_rd_swa, unsigned short video_write_buff_vw, unsigned short video_write_buff_hw)
Video surface write process setting.
graphics_error_t Video_Write_Change ( video_input_channel_t video_input_channel, void *framebuff, uint32_t fb_stride)
Video surface write buffer change process.

Interface

See the Pinout page for more details

common/lcd_panel/lcd_analog_rgb_ch1.c@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file lcd_analog_rgb_ch1.c
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief LCD panel for vdc5 channel 1 function
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 /******************************************************************************
dkato 0:853f5b7408a7 32 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 33 ******************************************************************************/
dkato 0:853f5b7408a7 34 #include <string.h>
dkato 0:853f5b7408a7 35
dkato 0:853f5b7408a7 36 #include "r_typedefs.h"
dkato 0:853f5b7408a7 37
dkato 0:853f5b7408a7 38 #include "r_vdc5.h"
dkato 0:853f5b7408a7 39
dkato 0:853f5b7408a7 40 #include "iodefine.h"
dkato 0:853f5b7408a7 41 #include "lcd_panel.h"
dkato 0:853f5b7408a7 42
dkato 0:853f5b7408a7 43 #if (LCD_VDC5_CH1_PANEL==1)
dkato 0:853f5b7408a7 44
dkato 0:853f5b7408a7 45 /******************************************************************************
dkato 0:853f5b7408a7 46 Macro definitions
dkato 0:853f5b7408a7 47 ******************************************************************************/
dkato 0:853f5b7408a7 48 /* Port 4 */
dkato 0:853f5b7408a7 49 #define LCD_PORT4_2ND (0x5400u)
dkato 0:853f5b7408a7 50 /* Port 9 */
dkato 0:853f5b7408a7 51 #define LCD_PORT9_1ST (0x00FCu)
dkato 0:853f5b7408a7 52 /* Port 5 */
dkato 0:853f5b7408a7 53 #define LCD_PORT5_7TH (0x0600u)
dkato 0:853f5b7408a7 54 #define LCD_PORT5_2ND (0x00FFu)
dkato 0:853f5b7408a7 55 /* Port 2 */
dkato 0:853f5b7408a7 56 #define LCD_PORT2_7TH (0xF000u)
dkato 0:853f5b7408a7 57 #define LCD_PORT2_6TH (0x0F00u)
dkato 0:853f5b7408a7 58
dkato 0:853f5b7408a7 59 #define FH_1_2_CYCLE (2u)
dkato 0:853f5b7408a7 60
dkato 0:853f5b7408a7 61 /******************************************************************************
dkato 0:853f5b7408a7 62 Typedef definitions
dkato 0:853f5b7408a7 63 ******************************************************************************/
dkato 0:853f5b7408a7 64
dkato 0:853f5b7408a7 65 /******************************************************************************
dkato 0:853f5b7408a7 66 Imported global variables and functions (from other files)
dkato 0:853f5b7408a7 67 ******************************************************************************/
dkato 0:853f5b7408a7 68
dkato 0:853f5b7408a7 69 /******************************************************************************
dkato 0:853f5b7408a7 70 Exported global variables (to be accessed by other files)
dkato 0:853f5b7408a7 71 ******************************************************************************/
dkato 0:853f5b7408a7 72
dkato 0:853f5b7408a7 73 /******************************************************************************
dkato 0:853f5b7408a7 74 Private global variables and functions
dkato 0:853f5b7408a7 75 ******************************************************************************/
dkato 0:853f5b7408a7 76
dkato 0:853f5b7408a7 77 /**************************************************************************//**
dkato 0:853f5b7408a7 78 * @brief LCD panel I/O port setup (VDC5 channel 1)
dkato 0:853f5b7408a7 79 * @param[in] void
dkato 0:853f5b7408a7 80 * @retval None
dkato 0:853f5b7408a7 81 ******************************************************************************/
dkato 0:853f5b7408a7 82 void GRAPHICS_SetLcdPanel_Ch1 (void)
dkato 0:853f5b7408a7 83 {
dkato 0:853f5b7408a7 84 volatile uint32_t dummy_read;
dkato 0:853f5b7408a7 85 uint32_t reg_data;
dkato 0:853f5b7408a7 86
dkato 0:853f5b7408a7 87 /* Analog RGB D-sub15 (RGB888)
dkato 0:853f5b7408a7 88 VSYNC : LCD1_TCON1 ... P4_14, 2nd alternative function
dkato 0:853f5b7408a7 89 : LCD1_CLK ... P4_12, 2nd alternative function
dkato 0:853f5b7408a7 90 HSYNC : LCD1_TCON5 ... P4_10, 2nd alternative function
dkato 0:853f5b7408a7 91 LCD1_DATA
dkato 0:853f5b7408a7 92 R[7:0] : LCD1_DATA[23:18] ... P9_7 ~ P9_2, 1st alternative function
dkato 0:853f5b7408a7 93 : [17:16] ... P5_10 ~ P5_9, 7th alternative function
dkato 0:853f5b7408a7 94 G[7:0] : LCD1_DATA[15:12] ... P2_15 ~ P2_12, 7th alternative function
dkato 0:853f5b7408a7 95 : [11:8] ... P2_11 ~ P2_8, 6th alternative function
dkato 0:853f5b7408a7 96 B[7:0] : LCD1_DATA[7:0] ... P5_7 ~ P5_0, 2nd alternative function
dkato 0:853f5b7408a7 97 */
dkato 0:853f5b7408a7 98 /* Port 4 */
dkato 0:853f5b7408a7 99 reg_data = (uint32_t)GPIO.PMC4 & (uint32_t)~LCD_PORT4_2ND;
dkato 0:853f5b7408a7 100 GPIO.PMC4 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 101 reg_data = (uint32_t)GPIO.PMC4;
dkato 0:853f5b7408a7 102 dummy_read = reg_data;
dkato 0:853f5b7408a7 103 /* PFCAE4, PFCE4, PFC4 ... 2nd alternative function
dkato 0:853f5b7408a7 104 PIPC4, PMC4
dkato 0:853f5b7408a7 105 b14 : P4_14
dkato 0:853f5b7408a7 106 b12 : P4_12
dkato 0:853f5b7408a7 107 b10 : P4_10 */
dkato 0:853f5b7408a7 108 reg_data = (uint32_t)GPIO.PFCAE4 & (uint32_t)~LCD_PORT4_2ND;
dkato 0:853f5b7408a7 109 GPIO.PFCAE4 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 110 reg_data = (uint32_t)GPIO.PFCE4 & (uint32_t)~LCD_PORT4_2ND;
dkato 0:853f5b7408a7 111 GPIO.PFCE4 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 112 reg_data = (uint32_t)GPIO.PFC4 | (uint32_t)LCD_PORT4_2ND;
dkato 0:853f5b7408a7 113 GPIO.PFC4 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 114 reg_data = (uint32_t)GPIO.PIPC4 | (uint32_t)LCD_PORT4_2ND;
dkato 0:853f5b7408a7 115 GPIO.PIPC4 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 116 reg_data = (uint32_t)GPIO.PMC4 | (uint32_t)LCD_PORT4_2ND;
dkato 0:853f5b7408a7 117 GPIO.PMC4 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 118
dkato 0:853f5b7408a7 119 /* Port 9 */
dkato 0:853f5b7408a7 120 reg_data = (uint32_t)GPIO.PMC9 & (uint32_t)~LCD_PORT9_1ST;
dkato 0:853f5b7408a7 121 GPIO.PMC9 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 122 reg_data = (uint32_t)GPIO.PMC9;
dkato 0:853f5b7408a7 123 dummy_read = reg_data;
dkato 0:853f5b7408a7 124 /* PFCAE9, PFCE9, PFC9 ... 1st alternative function
dkato 0:853f5b7408a7 125 PIPC9, PMC9
dkato 0:853f5b7408a7 126 b7:b2 : P9_7 ~ P9_2 */
dkato 0:853f5b7408a7 127 reg_data = (uint32_t)GPIO.PFCAE9 & (uint32_t)~LCD_PORT9_1ST;
dkato 0:853f5b7408a7 128 GPIO.PFCAE9 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 129 reg_data = (uint32_t)GPIO.PFCE9 & (uint32_t)~LCD_PORT9_1ST;
dkato 0:853f5b7408a7 130 GPIO.PFCE9 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 131 reg_data = (uint32_t)GPIO.PFC9 & (uint32_t)~LCD_PORT9_1ST;
dkato 0:853f5b7408a7 132 GPIO.PFC9 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 133 reg_data = (uint32_t)GPIO.PIPC9 | (uint32_t)LCD_PORT9_1ST;
dkato 0:853f5b7408a7 134 GPIO.PIPC9 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 135 reg_data = (uint32_t)GPIO.PMC9 | (uint32_t)LCD_PORT9_1ST;
dkato 0:853f5b7408a7 136 GPIO.PMC9 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 137
dkato 0:853f5b7408a7 138 /* Port 5 */
dkato 0:853f5b7408a7 139 reg_data = (uint32_t)GPIO.PMC5 & (uint32_t)~(LCD_PORT5_7TH|LCD_PORT5_2ND);
dkato 0:853f5b7408a7 140 GPIO.PMC5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 141 reg_data = (uint32_t)GPIO.PMC5;
dkato 0:853f5b7408a7 142 dummy_read = reg_data;
dkato 0:853f5b7408a7 143 /* PFCAE5, PFCE5, PFC5 ... 7th alternative function
dkato 0:853f5b7408a7 144 b10:b9 : P5_10 ~ P5_9 */
dkato 0:853f5b7408a7 145 reg_data = (uint32_t)GPIO.PFCAE5 | (uint32_t)LCD_PORT5_7TH;
dkato 0:853f5b7408a7 146 GPIO.PFCAE5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 147 reg_data = (uint32_t)GPIO.PFCE5 | (uint32_t)LCD_PORT5_7TH;
dkato 0:853f5b7408a7 148 GPIO.PFCE5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 149 reg_data = (uint32_t)GPIO.PFC5 & (uint32_t)~LCD_PORT5_7TH;
dkato 0:853f5b7408a7 150 GPIO.PFC5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 151 /* PFCAE5, PFCE5, PFC5 ... 2nd alternative function
dkato 0:853f5b7408a7 152 b7:b0 : P5_7 ~ P5_0 */
dkato 0:853f5b7408a7 153 reg_data = (uint32_t)GPIO.PFCAE5 & (uint32_t)~LCD_PORT5_2ND;
dkato 0:853f5b7408a7 154 GPIO.PFCAE5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 155 reg_data = (uint32_t)GPIO.PFCE5 & (uint32_t)~LCD_PORT5_2ND;
dkato 0:853f5b7408a7 156 GPIO.PFCE5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 157 reg_data = (uint32_t)GPIO.PFC5 | (uint32_t)LCD_PORT5_2ND;
dkato 0:853f5b7408a7 158 GPIO.PFC5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 159 /* PIPC5, PMC5
dkato 0:853f5b7408a7 160 b10:b9 : P5_10 ~ P5_9
dkato 0:853f5b7408a7 161 b7:b0 : P5_7 ~ P5_0 */
dkato 0:853f5b7408a7 162 reg_data = (uint32_t)GPIO.PIPC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
dkato 0:853f5b7408a7 163 GPIO.PIPC5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 164 reg_data = (uint32_t)GPIO.PMC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
dkato 0:853f5b7408a7 165 GPIO.PMC5 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 166
dkato 0:853f5b7408a7 167 /* Port 2 */
dkato 0:853f5b7408a7 168 reg_data = (uint32_t)GPIO.PMC2 & (uint32_t)~(LCD_PORT2_7TH|LCD_PORT2_6TH);
dkato 0:853f5b7408a7 169 GPIO.PMC2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 170 reg_data = (uint32_t)GPIO.PMC2;
dkato 0:853f5b7408a7 171 dummy_read = reg_data;
dkato 0:853f5b7408a7 172 /* PFCAE2, PFCE2, PFC2 ... 7th alternative function
dkato 0:853f5b7408a7 173 b15:b12 : P2_15 ~ P2_12 */
dkato 0:853f5b7408a7 174 reg_data = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_7TH;
dkato 0:853f5b7408a7 175 GPIO.PFCAE2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 176 reg_data = (uint32_t)GPIO.PFCE2 | (uint32_t)LCD_PORT2_7TH;
dkato 0:853f5b7408a7 177 GPIO.PFCE2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 178 reg_data = (uint32_t)GPIO.PFC2 & (uint32_t)~LCD_PORT2_7TH;
dkato 0:853f5b7408a7 179 GPIO.PFC2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 180 /* PFCAE2, PFCE2, PFC2 ... 6th alternative function
dkato 0:853f5b7408a7 181 b11:b8 : P2_11 ~ P2_8 */
dkato 0:853f5b7408a7 182 reg_data = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_6TH;
dkato 0:853f5b7408a7 183 GPIO.PFCAE2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 184 reg_data = (uint32_t)GPIO.PFCE2 & (uint32_t)~LCD_PORT2_6TH;
dkato 0:853f5b7408a7 185 GPIO.PFCE2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 186 reg_data = (uint32_t)GPIO.PFC2 | (uint32_t)LCD_PORT2_6TH;
dkato 0:853f5b7408a7 187 GPIO.PFC2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 188 /* PIPC2, PMC2
dkato 0:853f5b7408a7 189 b15:b8 : P2_15 ~ P2_8 */
dkato 0:853f5b7408a7 190 reg_data = (uint32_t)GPIO.PIPC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
dkato 0:853f5b7408a7 191 GPIO.PIPC2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 192 reg_data = (uint32_t)GPIO.PMC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
dkato 0:853f5b7408a7 193 GPIO.PMC2 = (uint16_t)reg_data;
dkato 0:853f5b7408a7 194 } /* End of function GRAPHICS_SetLcdPanel_Ch1() */
dkato 0:853f5b7408a7 195
dkato 0:853f5b7408a7 196 /**************************************************************************//**
dkato 0:853f5b7408a7 197 * @brief LCD TCON setup parameter acquisition processing (VDC5 channel 1)
dkato 0:853f5b7408a7 198 * @param[out] outctrl : Address of the area for storing the LCD TCON timing setup data table
dkato 0:853f5b7408a7 199 * @retval None
dkato 0:853f5b7408a7 200 ******************************************************************************/
dkato 0:853f5b7408a7 201 void GRAPHICS_SetLcdTconSettings_Ch1 (const vdc5_lcd_tcon_timing_t * * const outctrl)
dkato 0:853f5b7408a7 202 {
dkato 0:853f5b7408a7 203 /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */
dkato 0:853f5b7408a7 204 /* TCON timing setting, VS */
dkato 0:853f5b7408a7 205 static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS = {
dkato 0:853f5b7408a7 206 (uint16_t)(LCD_CH1_S_VSYNC * FH_1_2_CYCLE), /* Signal pulse start position */
dkato 0:853f5b7408a7 207 (uint16_t)(LCD_CH1_W_VSYNC * FH_1_2_CYCLE), /* Pulse width */
dkato 0:853f5b7408a7 208 VDC5_LCD_TCON_POLMD_NORMAL,
dkato 0:853f5b7408a7 209 VDC5_LCD_TCON_REFSEL_HSYNC,
dkato 0:853f5b7408a7 210 LCD_CH1_POL_VSYNC, /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 211 VDC5_LCD_TCON_PIN_1, /* Output pin for LCD driving signal */
dkato 0:853f5b7408a7 212 LCD_CH1_OUT_EDGE /* Output phase control of signal */
dkato 0:853f5b7408a7 213 };
dkato 0:853f5b7408a7 214 /* TCON timing setting, HS */
dkato 0:853f5b7408a7 215 static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS = {
dkato 0:853f5b7408a7 216 (uint16_t)LCD_CH1_S_HSYNC, /* Signal pulse start position */
dkato 0:853f5b7408a7 217 (uint16_t)LCD_CH1_W_HSYNC, /* Pulse width */
dkato 0:853f5b7408a7 218 VDC5_LCD_TCON_POLMD_NORMAL,
dkato 0:853f5b7408a7 219 VDC5_LCD_TCON_REFSEL_HSYNC, /* Signal operating reference select */
dkato 0:853f5b7408a7 220 LCD_CH1_POL_HSYNC, /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 221 VDC5_LCD_TCON_PIN_5, /* Output pin for LCD driving signal */
dkato 0:853f5b7408a7 222 LCD_CH1_OUT_EDGE /* Output phase control of signal */
dkato 0:853f5b7408a7 223 };
dkato 0:853f5b7408a7 224
dkato 0:853f5b7408a7 225 if (outctrl != NULL) {
dkato 0:853f5b7408a7 226 outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */
dkato 0:853f5b7408a7 227 outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used */
dkato 0:853f5b7408a7 228 outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */
dkato 0:853f5b7408a7 229 outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
dkato 0:853f5b7408a7 230 outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL; /* CPV/GCK: Not used */
dkato 0:853f5b7408a7 231 outctrl[VDC5_LCD_TCONSIG_POLA] = NULL; /* POLA: Not used */
dkato 0:853f5b7408a7 232 outctrl[VDC5_LCD_TCONSIG_POLB] = NULL; /* POLB: Not used */
dkato 0:853f5b7408a7 233 outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE: Not used */
dkato 0:853f5b7408a7 234 }
dkato 0:853f5b7408a7 235 } /* End of function GRAPHICS_SetLcdTconSettings_Ch1() */
dkato 0:853f5b7408a7 236
dkato 0:853f5b7408a7 237 #endif /* LCD_VDC5_CH1_PANEL==LCD_CH1_PANEL_ANALOG_RGB */
dkato 0:853f5b7408a7 238