Renesas / GR-PEACH_video

Video library for GR-PEACH

Dependents:   Trace_Program2 GR-PEACH_Camera_in_barcode GR-PEACH_LCD_sample GR-PEACH_LCD_4_3inch_sample ... more

Video ｌibrary for GR-PEACH.

Hello World!

Import programGR-PEACH_Camera_in

Camera in sample for GR-PEACH. This sample works on GR-LYCHEE besides GR-PEACH.

Last commit 28 Dec 2018 by Renesas

API

Import library
GR-PEACH_video - DisplayBase Class Reference

Data Structures

struct lcd_config_t
LCD configuration. More...
struct rect_t
The relative position within the graphics display area. More...
struct video_ext_in_config_t
Digital Video Input configuration. More...

Public Types

enum video_input_channel_t { VIDEO_INPUT_CHANNEL_0 = 0, VIDEO_INPUT_CHANNEL_1 }

Video input channel select.

More...
enum graphics_layer_t { GRAPHICS_LAYER_0 = 0, GRAPHICS_LAYER_1 , GRAPHICS_LAYER_2 , GRAPHICS_LAYER_3 }

Graphics layer select.

More...
enum graphics_error_t {
GRAPHICS_OK = 0, GRAPHICS_VDC5_ERR = -1, GRAPHICS_FORMA_ERR = -2, GRAPHICS_LAYER_ERR = -3,
GRAPHICS_CHANNLE_ERR = -4, GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, GRAPHICS_PARAM_RANGE_ERR = -7
}

Error codes.

More...
enum graphics_format_t { GRAPHICS_FORMAT_YCBCR422 = 0, GRAPHICS_FORMAT_RGB565 , GRAPHICS_FORMAT_RGB888 , GRAPHICS_FORMAT_ARGB8888 }

Graphics layer read format selects.

More...
enum video_format_t { VIDEO_FORMAT_YCBCR422 = 0, VIDEO_FORMAT_RGB565 , VIDEO_FORMAT_RGB888 }

Video writing format selects.

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enum wr_rd_swa_t {
WR_RD_WRSWA_NON = 0, WR_RD_WRSWA_8BIT , WR_RD_WRSWA_16BIT , WR_RD_WRSWA_16_8BIT ,
WR_RD_WRSWA_32BIT , WR_RD_WRSWA_32_8BIT , WR_RD_WRSWA_32_16BIT , WR_RD_WRSWA_32_16_8BIT
}

Frame buffer swap setting.

More...
enum lcd_tcon_pin_t { LCD_TCON_PIN_NON = -1, LCD_TCON_PIN_0 , LCD_TCON_PIN_1 , LCD_TCON_PIN_2 }

LCD tcon output pin selects.

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enum lcd_outformat_t { LCD_OUTFORMAT_RGB888 = 0, LCD_OUTFORMAT_RGB666 , LCD_OUTFORMAT_RGB565 }

LCD output format selects.

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enum edge_t { EDGE_RISING = 0, EDGE_FALLING = 1 }

Edge of a signal.

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enum lcd_type_t { LCD_TYPE_LVDS = 0, LCD_TYPE_PARALLEL_RGB }

LCD type.

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enum sig_pol_t { SIG_POL_NOT_INVERTED = 0, SIG_POL_INVERTED }

Polarity of a signal.

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enum int_type_t {
INT_TYPE_S0_VI_VSYNC = 0, INT_TYPE_S0_LO_VSYNC , INT_TYPE_S0_VSYNCERR , INT_TYPE_VLINE ,
INT_TYPE_S0_VFIELD , INT_TYPE_IV1_VBUFERR , INT_TYPE_IV3_VBUFERR , INT_TYPE_IV5_VBUFERR ,
INT_TYPE_IV6_VBUFERR , INT_TYPE_S0_WLINE , INT_TYPE_S1_VI_VSYNC , INT_TYPE_S1_LO_VSYNC ,
INT_TYPE_S1_VSYNCERR , INT_TYPE_S1_VFIELD , INT_TYPE_IV2_VBUFERR , INT_TYPE_IV4_VBUFERR ,
INT_TYPE_S1_WLINE , INT_TYPE_OIR_VI_VSYNC , INT_TYPE_OIR_LO_VSYNC , INT_TYPE_OIR_VLINE ,
INT_TYPE_OIR_VFIELD , INT_TYPE_IV7_VBUFERR , INT_TYPE_IV8_VBUFERR , INT_TYPE_NUM
}

Interrupt type.

More...
enum graphics_video_col_sys_t {
COL_SYS_NTSC_358 = 0, COL_SYS_NTSC_443 = 1, COL_SYS_PAL_443 = 2, COL_SYS_PAL_M = 3,
COL_SYS_PAL_N = 4, COL_SYS_SECAM = 5, COL_SYS_NTSC_443_60 = 6, COL_SYS_PAL_60 = 7
}

Video color system.

More...
enum video_input_sel_t { INPUT_SEL_VDEC = 0, INPUT_SEL_EXT = 1 }

External Input select.

More...
enum video_extin_format_t {
VIDEO_EXTIN_FORMAT_RGB888 = 0, VIDEO_EXTIN_FORMAT_RGB666 , VIDEO_EXTIN_FORMAT_RGB565 , VIDEO_EXTIN_FORMAT_BT656 ,
VIDEO_EXTIN_FORMAT_BT601 , VIDEO_EXTIN_FORMAT_YCBCR422 , VIDEO_EXTIN_FORMAT_YCBCR444
}

External input format select.

More...
enum onoff_t { OFF = 0, ON = 1 }

On/off.

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enum extin_input_line_t { EXTIN_LINE_525 = 0, EXTIN_LINE_625 = 1 }

Number of lines for BT.656 external input.

More...
enum extin_h_pos_t { EXTIN_H_POS_CBYCRY = 0, EXTIN_H_POS_YCRYCB , EXTIN_H_POS_CRYCBY , EXTIN_H_POS_YCBYCR }

Y/Cb/Y/Cr data string start timing.

More...

Public Member Functions

DisplayBase (void)
Constructor method of display base object.
graphics_error_t Graphics_init ( lcd_config_t *lcd_config)
Graphics initialization processing
If not using display, set NULL in parameter.
graphics_error_t Graphics_Video_init ( video_input_sel_t video_input_sel, video_ext_in_config_t *video_ext_in_config)
Graphics Video initialization processing
If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
graphics_error_t Graphics_Lcd_Port_Init (PinName *pin, unsigned int pin_count)
LCD output port initialization processing.
graphics_error_t Graphics_Lvds_Port_Init (PinName *pin, unsigned int pin_count)
LVDS output port initialization processing.
graphics_error_t Graphics_Dvinput_Port_Init (PinName *pin, unsigned int pin_count)
Digital video input port initialization processing.
graphics_error_t Graphics_Irq_Handler_Set ( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void(*callback)( int_type_t ))
Interrupt callback setup This function performs the following processing:

  • Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.

graphics_error_t Graphics_Start ( graphics_layer_t layer_id)
Start the graphics surface read process.
graphics_error_t Graphics_Stop ( graphics_layer_t layer_id)
Stop the graphics surface read process.
graphics_error_t Video_Start ( video_input_channel_t video_input_channel)
Start the video surface write process.
graphics_error_t Video_Stop ( video_input_channel_t video_input_channel)
Stop the video surface write process.
graphics_error_t Graphics_Read_Setting ( graphics_layer_t layer_id, void *framebuff, unsigned int fb_stride, graphics_format_t gr_format, wr_rd_swa_t wr_rd_swa, rect_t *gr_rect)
Graphics surface read process setting.
graphics_error_t Graphics_Read_Change ( graphics_layer_t layer_id, void *framebuff)
Graphics surface read buffer change process.
graphics_error_t Video_Write_Setting ( video_input_channel_t video_input_channel, graphics_video_col_sys_t col_sys, void *framebuff, unsigned int fb_stride, video_format_t video_format, wr_rd_swa_t wr_rd_swa, unsigned short video_write_buff_vw, unsigned short video_write_buff_hw)
Video surface write process setting.
graphics_error_t Video_Write_Change ( video_input_channel_t video_input_channel, void *framebuff, uint32_t fb_stride)
Video surface write buffer change process.

Interface

See the Pinout page for more details

inc/lcd_analog_rgb.h@0:853f5b7408a7, 2015-06-26 (annotated)

Committer:
dkato
Date:
Fri Jun 26 02:17:53 2015 +0000
Revision:
0:853f5b7408a7
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file lcd_analog_rgb.h
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief LCD panel definition header
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #ifndef LCD_ANALOG_RGB_H
dkato 0:853f5b7408a7 32 #define LCD_ANALOG_RGB_H
dkato 0:853f5b7408a7 33
dkato 0:853f5b7408a7 34 /******************************************************************************
dkato 0:853f5b7408a7 35 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 36 ******************************************************************************/
dkato 0:853f5b7408a7 37 #include <stdlib.h>
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39 #include "r_typedefs.h"
dkato 0:853f5b7408a7 40
dkato 0:853f5b7408a7 41 #include "r_vdc5.h"
dkato 0:853f5b7408a7 42
dkato 0:853f5b7408a7 43
dkato 0:853f5b7408a7 44 /******************************************************************************
dkato 0:853f5b7408a7 45 Macro definitions
dkato 0:853f5b7408a7 46 ******************************************************************************/
dkato 0:853f5b7408a7 47 /* SVGA signal 800x600
dkato 0:853f5b7408a7 48 Pixel clock frequency: 40.0 MHz
dkato 0:853f5b7408a7 49 Refresh rate: 60.3 Hz
dkato 0:853f5b7408a7 50 Polarity of horizontal sync pulse: Positive
dkato 0:853f5b7408a7 51 Polarity of vertical sync pulse: Positive
dkato 0:853f5b7408a7 52 */
dkato 0:853f5b7408a7 53 #define LCD_SVGA_H_VISIBLE_AREA (800u) /* Horizontal visible area [pixel] */
dkato 0:853f5b7408a7 54 #define LCD_SVGA_H_FRONT_PORCH (40u) /* Horizontal front porch [pixel] */
dkato 0:853f5b7408a7 55 #define LCD_SVGA_H_SYNC_WIDTH (128u) /* Horizontal sync pulse width [pixel] */
dkato 0:853f5b7408a7 56 #define LCD_SVGA_H_BACK_PORCH (88u) /* Horizontal back porch [pixel] */
dkato 0:853f5b7408a7 57 /* Horizontal total (one line) [pixel] */
dkato 0:853f5b7408a7 58 #define LCD_SVGA_H_TOTAL (LCD_SVGA_H_VISIBLE_AREA +\
dkato 0:853f5b7408a7 59 LCD_SVGA_H_FRONT_PORCH +\
dkato 0:853f5b7408a7 60 LCD_SVGA_H_SYNC_WIDTH +\
dkato 0:853f5b7408a7 61 LCD_SVGA_H_BACK_PORCH)
dkato 0:853f5b7408a7 62 #define LCD_SVGA_H_POLARITY (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of horizontal sync pulse */
dkato 0:853f5b7408a7 63
dkato 0:853f5b7408a7 64 #define LCD_SVGA_V_VISIBLE_AREA (600u) /* Vertical visible area [line] */
dkato 0:853f5b7408a7 65 #define LCD_SVGA_V_FRONT_PORCH (1u) /* Vertical front porch [line] */
dkato 0:853f5b7408a7 66 #define LCD_SVGA_V_SYNC_WIDTH (4u) /* Vertical sync pulse width [line] */
dkato 0:853f5b7408a7 67 #define LCD_SVGA_V_BACK_PORCH (23u) /* Vertical back porch [line] */
dkato 0:853f5b7408a7 68 /* Vertical total (one frame) [line] */
dkato 0:853f5b7408a7 69 #define LCD_SVGA_V_TOTAL (LCD_SVGA_V_VISIBLE_AREA +\
dkato 0:853f5b7408a7 70 LCD_SVGA_V_FRONT_PORCH +\
dkato 0:853f5b7408a7 71 LCD_SVGA_V_SYNC_WIDTH +\
dkato 0:853f5b7408a7 72 LCD_SVGA_V_BACK_PORCH)
dkato 0:853f5b7408a7 73 #define LCD_SVGA_V_POLARITY (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of vertical sync pulse */
dkato 0:853f5b7408a7 74
dkato 0:853f5b7408a7 75
dkato 0:853f5b7408a7 76 /* XGA signal 1024x768
dkato 0:853f5b7408a7 77 Pixel clock frequency: 65.0 MHz
dkato 0:853f5b7408a7 78 Refresh rate: 60.0 Hz
dkato 0:853f5b7408a7 79 Polarity of horizontal sync pulse: Negative
dkato 0:853f5b7408a7 80 Polarity of vertical sync pulse: Negative
dkato 0:853f5b7408a7 81 */
dkato 0:853f5b7408a7 82 #define LCD_XGA_H_VISIBLE_AREA (1024u) /* Horizontal visible area [pixel] */
dkato 0:853f5b7408a7 83 #define LCD_XGA_H_FRONT_PORCH (24u) /* Horizontal front porch [pixel] */
dkato 0:853f5b7408a7 84 #define LCD_XGA_H_SYNC_WIDTH (136u) /* Horizontal sync pulse width [pixel] */
dkato 0:853f5b7408a7 85 #define LCD_XGA_H_BACK_PORCH (160u) /* Horizontal back porch [pixel] */
dkato 0:853f5b7408a7 86 /* Horizontal total (one line) [pixel] */
dkato 0:853f5b7408a7 87 #define LCD_XGA_H_TOTAL (LCD_XGA_H_VISIBLE_AREA +\
dkato 0:853f5b7408a7 88 LCD_XGA_H_FRONT_PORCH +\
dkato 0:853f5b7408a7 89 LCD_XGA_H_SYNC_WIDTH +\
dkato 0:853f5b7408a7 90 LCD_XGA_H_BACK_PORCH)
dkato 0:853f5b7408a7 91 #define LCD_XGA_H_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of horizontal sync pulse */
dkato 0:853f5b7408a7 92
dkato 0:853f5b7408a7 93 #define LCD_XGA_V_VISIBLE_AREA (768u) /* Vertical visible area [line] */
dkato 0:853f5b7408a7 94 #define LCD_XGA_V_FRONT_PORCH (3u) /* Vertical front porch [line] */
dkato 0:853f5b7408a7 95 #define LCD_XGA_V_SYNC_WIDTH (6u) /* Vertical sync pulse width [line] */
dkato 0:853f5b7408a7 96 #define LCD_XGA_V_BACK_PORCH (29u) /* Vertical back porch [line] */
dkato 0:853f5b7408a7 97 /* Vertical total (one frame) [line] */
dkato 0:853f5b7408a7 98 #define LCD_XGA_V_TOTAL (LCD_XGA_V_VISIBLE_AREA +\
dkato 0:853f5b7408a7 99 LCD_XGA_V_FRONT_PORCH +\
dkato 0:853f5b7408a7 100 LCD_XGA_V_SYNC_WIDTH +\
dkato 0:853f5b7408a7 101 LCD_XGA_V_BACK_PORCH)
dkato 0:853f5b7408a7 102 #define LCD_XGA_V_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of vertical sync pulse */
dkato 0:853f5b7408a7 103
dkato 0:853f5b7408a7 104
dkato 0:853f5b7408a7 105 /* VGA signal 640x480
dkato 0:853f5b7408a7 106 Pixel clock frequency: 25.175 MHz
dkato 0:853f5b7408a7 107 Refresh rate: 59.94 Hz
dkato 0:853f5b7408a7 108 Polarity of horizontal sync pulse: Negative
dkato 0:853f5b7408a7 109 Polarity of vertical sync pulse: Negative
dkato 0:853f5b7408a7 110 */
dkato 0:853f5b7408a7 111 #define LCD_VGA_H_VISIBLE_AREA (640u) /* Horizontal visible area [pixel] */
dkato 0:853f5b7408a7 112 #define LCD_VGA_H_FRONT_PORCH (16u) /* Horizontal front porch [pixel] */
dkato 0:853f5b7408a7 113 #define LCD_VGA_H_SYNC_WIDTH (96u) /* Horizontal sync pulse width [pixel] */
dkato 0:853f5b7408a7 114 #define LCD_VGA_H_BACK_PORCH (48u) /* Horizontal back porch [pixel] */
dkato 0:853f5b7408a7 115 /* Horizontal total (one line) [pixel] */
dkato 0:853f5b7408a7 116 #define LCD_VGA_H_TOTAL (LCD_VGA_H_VISIBLE_AREA +\
dkato 0:853f5b7408a7 117 LCD_VGA_H_FRONT_PORCH +\
dkato 0:853f5b7408a7 118 LCD_VGA_H_SYNC_WIDTH +\
dkato 0:853f5b7408a7 119 LCD_VGA_H_BACK_PORCH)
dkato 0:853f5b7408a7 120 #define LCD_VGA_H_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of horizontal sync pulse */
dkato 0:853f5b7408a7 121
dkato 0:853f5b7408a7 122 #define LCD_VGA_V_VISIBLE_AREA (480u) /* Vertical visible area [line] */
dkato 0:853f5b7408a7 123 #define LCD_VGA_V_FRONT_PORCH (10u) /* Vertical front porch [line] */
dkato 0:853f5b7408a7 124 #define LCD_VGA_V_SYNC_WIDTH (2u) /* Vertical sync pulse width [line] */
dkato 0:853f5b7408a7 125 #define LCD_VGA_V_BACK_PORCH (33u) /* Vertical back porch [line] */
dkato 0:853f5b7408a7 126 /* Vertical total (one frame) [line] */
dkato 0:853f5b7408a7 127 #define LCD_VGA_V_TOTAL (LCD_VGA_V_VISIBLE_AREA +\
dkato 0:853f5b7408a7 128 LCD_VGA_V_FRONT_PORCH +\
dkato 0:853f5b7408a7 129 LCD_VGA_V_SYNC_WIDTH +\
dkato 0:853f5b7408a7 130 LCD_VGA_V_BACK_PORCH)
dkato 0:853f5b7408a7 131 #define LCD_VGA_V_POLARITY (VDC5_SIG_POL_INVERTED) /* Polarity of vertical sync pulse */
dkato 0:853f5b7408a7 132
dkato 0:853f5b7408a7 133
dkato 0:853f5b7408a7 134 #endif /* LCD_ANALOG_RGB_H */