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gr_peach_vdc5.c
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00001 /******************************************************************************* 00002 * DISCLAIMER 00003 * This software is supplied by Renesas Electronics Corporation and is only 00004 * intended for use with Renesas products. No other uses are authorized. This 00005 * software is owned by Renesas Electronics Corporation and is protected under 00006 * all applicable laws, including copyright laws. 00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING 00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT 00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. 00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR 00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE 00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00016 * Renesas reserves the right, without notice, to make changes to this software 00017 * and to discontinue the availability of this software. By using this software, 00018 * you agree to the additional terms and conditions found by accessing the 00019 * following link: 00020 * http://www.renesas.com/disclaimer 00021 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. 00022 *******************************************************************************/ 00023 /**************************************************************************//** 00024 * @file gr_peach_vdc5.c 00025 * @version 00026 * $Rev: 00027 * $Date:: 00028 * @brief VDC5 driver API wrapper function in C interface 00029 ******************************************************************************/ 00030 00031 /****************************************************************************** 00032 Includes <System Includes> , "Project Includes" 00033 ******************************************************************************/ 00034 #include <stdio.h> 00035 #include <string.h> 00036 00037 #include "r_typedefs.h" 00038 #include "r_vdc5.h" 00039 #include "video_decoder.h" 00040 #include "lvds_pll_calc.h" 00041 #include "gr_peach_vdc5.h" 00042 00043 #include "mbed_assert.h" 00044 #include "pinmap.h" 00045 00046 /****************************************************************************** 00047 Macro definitions 00048 ******************************************************************************/ 00049 #define STP91_BIT (0x02u) 00050 #define STP90_BIT (0x01u) 00051 #define STBRQ25_BIT (0x20u) 00052 #define STBAK25_BIT (0x20u) 00053 #define STBRQ24_BIT (0x10u) 00054 #define STBAK24_BIT (0x10u) 00055 00056 /****************************************************************************** 00057 Typedef definitions 00058 ******************************************************************************/ 00059 typedef enum { 00060 VDC5_CH0, 00061 VDC5_CH1, 00062 } VDC5Name; 00063 00064 /****************************************************************************** 00065 Imported global variables and functions (from other files) 00066 ******************************************************************************/ 00067 00068 /****************************************************************************** 00069 Exported global variables (to be accessed by other files) 00070 ******************************************************************************/ 00071 static const PinMap PinMap_DV_INPUT_PIN[] = { 00072 {P8_11 , VDC5_CH0, 8}, /* DV0_CLK */ 00073 {P10_0 , VDC5_CH0, 1}, /* DV0_CLK */ 00074 {P1_12 , VDC5_CH0, 2}, /* DV0_VSYNC */ 00075 {P1_13 , VDC5_CH0, 2}, /* DV0_HSYNC */ 00076 {P1_1 , VDC5_CH0, 6}, /* DV0_HSYNC */ 00077 {P1_0 , VDC5_CH0, 6}, /* DV0_VSYNC */ 00078 {P1_9 , VDC5_CH0, 6}, /* DV0_DATA15 */ 00079 {P2_15 , VDC5_CH0, 3}, /* DV0_DATA15 */ 00080 {P4_7 , VDC5_CH0, 7}, /* DV0_DATA15 */ 00081 {P5_7 , VDC5_CH0, 4}, /* DV0_DATA15 */ 00082 {P1_8 , VDC5_CH0, 6}, /* DV0_DATA14 */ 00083 {P2_14 , VDC5_CH0, 3}, /* DV0_DATA14 */ 00084 {P4_6 , VDC5_CH0, 7}, /* DV0_DATA14 */ 00085 {P5_6 , VDC5_CH0, 4}, /* DV0_DATA14 */ 00086 {P1_7 , VDC5_CH0, 6}, /* DV0_DATA13 */ 00087 {P2_13 , VDC5_CH0, 3}, /* DV0_DATA13 */ 00088 {P4_5 , VDC5_CH0, 7}, /* DV0_DATA13 */ 00089 {P5_5 , VDC5_CH0, 4}, /* DV0_DATA13 */ 00090 {P1_6 , VDC5_CH0, 6}, /* DV0_DATA12 */ 00091 {P4_4 , VDC5_CH0, 7}, /* DV0_DATA12 */ 00092 {P5_4 , VDC5_CH0, 4}, /* DV0_DATA12 */ 00093 {P10_5 , VDC5_CH0, 1}, /* DV0_DATA11 */ 00094 {P2_10 , VDC5_CH0, 3}, /* DV0_DATA10 */ 00095 {P10_14, VDC5_CH0, 1}, /* DV0_DATA10 */ 00096 {P2_9 , VDC5_CH0, 3}, /* DV0_DATA9 */ 00097 {P10_13, VDC5_CH0, 1}, /* DV0_DATA9 */ 00098 {P10_12, VDC5_CH0, 1}, /* DV0_DATA8 */ 00099 {P2_7 , VDC5_CH0, 3}, /* DV0_DATA7 */ 00100 {P2_6 , VDC5_CH0, 3}, /* DV0_DATA6 */ 00101 {P2_5 , VDC5_CH0, 3}, /* DV0_DATA5 */ 00102 {P2_4 , VDC5_CH0, 3}, /* DV0_DATA4 */ 00103 {P2_3 , VDC5_CH0, 3}, /* DV0_DATA3 */ 00104 {P2_2 , VDC5_CH0, 3}, /* DV0_DATA2 */ 00105 {P2_1 , VDC5_CH0, 3}, /* DV0_DATA1 */ 00106 {P2_0 , VDC5_CH0, 3}, /* DV0_DATA0 */ 00107 {NC , NC , 0} 00108 }; 00109 00110 static const PinMap PinMap_LCD_DISP_PIN[] = { 00111 {P2_7 , VDC5_CH0, 8}, /* LCD0_DATA23 */ 00112 {P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23 */ 00113 {P10_0 , VDC5_CH0, 5}, /* LCD0_DATA23 */ 00114 {P2_6 , VDC5_CH0, 8}, /* LCD0_DATA22 */ 00115 {P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22 */ 00116 {P10_1 , VDC5_CH0, 5}, /* LCD0_DATA22 */ 00117 {P2_5 , VDC5_CH0, 8}, /* LCD0_DATA21 */ 00118 {P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21 */ 00119 {P10_2 , VDC5_CH0, 5}, /* LCD0_DATA21 */ 00120 {P2_4 , VDC5_CH0, 8}, /* LCD0_DATA20 */ 00121 {P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20 */ 00122 {P10_3 , VDC5_CH0, 5}, /* LCD0_DATA20 */ 00123 {P2_3 , VDC5_CH0, 8}, /* LCD0_DATA19 */ 00124 {P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19 */ 00125 {P10_4 , VDC5_CH0, 5}, /* LCD0_DATA19 */ 00126 {P2_2 , VDC5_CH0, 8}, /* LCD0_DATA18 */ 00127 {P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18 */ 00128 {P10_5 , VDC5_CH0, 5}, /* LCD0_DATA18 */ 00129 {P2_1 , VDC5_CH0, 8}, /* LCD0_DATA17 */ 00130 {P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17 */ 00131 {P10_7 , VDC5_CH0, 5}, /* LCD0_DATA17 */ 00132 {P2_0 , VDC5_CH0, 8}, /* LCD0_DATA16 */ 00133 {P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16 */ 00134 {P10_6 , VDC5_CH0, 5}, /* LCD0_DATA16 */ 00135 {P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */ 00136 {P10_8 , VDC5_CH0, 5}, /* LCD0_DATA15 */ 00137 {P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */ 00138 {P10_9 , VDC5_CH0, 5}, /* LCD0_DATA14 */ 00139 {P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */ 00140 {P10_10, VDC5_CH0, 5}, /* LCD0_DATA13 */ 00141 {P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */ 00142 {P10_11, VDC5_CH0, 5}, /* LCD0_DATA12 */ 00143 {P10_12, VDC5_CH0, 5}, /* LCD0_DATA11 */ 00144 {P10_13, VDC5_CH0, 5}, /* LCD0_DATA10 */ 00145 {P10_14, VDC5_CH0, 5}, /* LCD0_DATA9 */ 00146 {P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8 */ 00147 {P10_15, VDC5_CH0, 5}, /* LCD0_DATA8 */ 00148 {P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7 */ 00149 {P11_0 , VDC5_CH0, 5}, /* LCD0_DATA7 */ 00150 {P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6 */ 00151 {P11_1 , VDC5_CH0, 5}, /* LCD0_DATA6 */ 00152 {P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5 */ 00153 {P11_2 , VDC5_CH0, 5}, /* LCD0_DATA5 */ 00154 {P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4 */ 00155 {P11_3 , VDC5_CH0, 5}, /* LCD0_DATA4 */ 00156 {P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3 */ 00157 {P11_4 , VDC5_CH0, 5}, /* LCD0_DATA3 */ 00158 {P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2 */ 00159 {P11_5 , VDC5_CH0, 5}, /* LCD0_DATA2 */ 00160 {P3_9 , VDC5_CH0, 1}, /* LCD0_DATA1 */ 00161 {P11_6 , VDC5_CH0, 5}, /* LCD0_DATA1 */ 00162 {P3_8 , VDC5_CH0, 1}, /* LCD0_DATA0 */ 00163 {P11_7 , VDC5_CH0, 5}, /* LCD0_DATA0 */ 00164 {P11_10, VDC5_CH0, 5}, /* LCD0_TCON4 */ 00165 {P11_11, VDC5_CH0, 5}, /* LCD0_TCON3 */ 00166 {P11_12, VDC5_CH0, 5}, /* LCD0_TCON2 */ 00167 {P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1 */ 00168 {P11_13, VDC5_CH0, 5}, /* LCD0_TCON1 */ 00169 {P11_14, VDC5_CH0, 5}, /* LCD0_TCON0 */ 00170 {P11_15, VDC5_CH0, 5}, /* LCD0_CLK */ 00171 {NC , NC , 0} 00172 }; 00173 00174 static const PinMap PinMap_LVDS_DISP_PIN[] = { 00175 {P5_7 , VDC5_CH0, 1}, /* TXOUT0M */ 00176 {P5_6 , VDC5_CH0, 1}, /* TXOUT0P */ 00177 {P5_5 , VDC5_CH0, 1}, /* TXOUT1M */ 00178 {P5_4 , VDC5_CH0, 1}, /* TXOUT1P */ 00179 {P5_3 , VDC5_CH0, 1}, /* TXOUT2M */ 00180 {P5_2 , VDC5_CH0, 1}, /* TXOUT2P */ 00181 {P5_1 , VDC5_CH0, 1}, /* TXCLKOUTM */ 00182 {P5_0 , VDC5_CH0, 1}, /* TXCLKOUTP */ 00183 {NC , NC , 0} 00184 }; 00185 00186 static const IRQn_Type vdc5_irq_set_tbl[] = { 00187 S0_VI_VSYNC0_IRQn, 00188 S0_LO_VSYNC0_IRQn, 00189 S0_VSYNCERR0_IRQn, 00190 GR3_VLINE0_IRQn, 00191 S0_VFIELD0_IRQn, 00192 IV1_VBUFERR0_IRQn, 00193 IV3_VBUFERR0_IRQn, 00194 IV5_VBUFERR0_IRQn, 00195 IV6_VBUFERR0_IRQn, 00196 S0_WLINE0_IRQn, 00197 S1_VI_VSYNC0_IRQn, 00198 S1_LO_VSYNC0_IRQn, 00199 S1_VSYNCERR0_IRQn, 00200 S1_VFIELD0_IRQn, 00201 IV2_VBUFERR0_IRQn, 00202 IV4_VBUFERR0_IRQn, 00203 S1_WLINE0_IRQn, 00204 OIR_VI_VSYNC0_IRQn, 00205 OIR_LO_VSYNC0_IRQn, 00206 OIR_VSYNCERR0_IRQn, 00207 OIR_VFIELD0_IRQn, 00208 IV7_VBUFERR0_IRQn, 00209 IV8_VBUFERR0_IRQn 00210 }; 00211 00212 /****************************************************************************** 00213 Private global variables and functions 00214 ******************************************************************************/ 00215 static void init_func (const uint32_t user_num); 00216 static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable); 00217 00218 /**************************************************************************//** 00219 * @brief User-defined function within R_VDC5_Initialize 00220 * @param[in] user_num : VDC5 channel 00221 * @retval None 00222 ******************************************************************************/ 00223 static void init_func (const uint32_t user_num) 00224 { 00225 uint32_t reg_data; 00226 volatile uint8_t dummy_read; 00227 00228 if ((vdc5_channel_t )user_num == VDC5_CHANNEL_0 ) { 00229 00230 /* Standby control register 9 (STBCR9) 00231 b1 ------0-; MSTP91 : 0 : Video display controller channel 0 & LVDS enable */ 00232 reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~STP91_BIT; 00233 CPG.STBCR9 = (uint8_t)reg_data; 00234 /* In order to reflect the change, a dummy read should be done. */ 00235 dummy_read = CPG.STBCR9; 00236 00237 /* Standby Request Register 2 (STBREQ2) 00238 b5 --0-----; STBRQ25 : The standby request to VDC5 channel 0 is invalid. */ 00239 reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ25_BIT; 00240 CPG.STBREQ2 = (uint8_t)reg_data; 00241 /* Standby Acknowledge Register 2 (STBACK2) 00242 b5 --*-----; STBAK25 : Standby acknowledgement from VDC5 channel 0. */ 00243 while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK25_BIT) != 0u) { 00244 /* Wait for the STBAK25 to be cleared to 0. */ 00245 } 00246 00247 /* Standby control register 9 (STBCR9) 00248 b0 -------0; MSTP90 : 0 : Video display controller channel 1 enable */ 00249 reg_data = (uint32_t)CPG.STBCR9 & (uint32_t)~(STP91_BIT|STP90_BIT); 00250 CPG.STBCR9 = (uint8_t)reg_data; 00251 /* In order to reflect the change, a dummy read should be done. */ 00252 dummy_read = CPG.STBCR9; 00253 00254 /* Standby Request Register 2 (STBREQ2) 00255 b4 ---0----; STBRQ24 : The standby request to VDC5 channel 1 is invalid. */ 00256 reg_data = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ24_BIT; 00257 CPG.STBREQ2 = (uint8_t)reg_data; 00258 /* Standby Acknowledge Register 2 (STBACK2) 00259 b4 ---*----; STBAK24 : Standby acknowledgement from VDC5 channel 1. */ 00260 while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK24_BIT) != 0u) { 00261 /* Wait for the STBAK24 to be cleared to 0. */ 00262 } 00263 } 00264 } /* End of function init_func() */ 00265 00266 /**************************************************************************//** 00267 * @brief Interrupt service routine acquisition processing 00268 * 00269 * Description:<br> 00270 * This function returns the function pointer to the specified interrupt service routine. 00271 * @param[in] irq : VDC5 interrupt type 00272 * @param[in] enable : VDC5 interrupt enable 00273 * @retval None 00274 ******************************************************************************/ 00275 static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable) 00276 { 00277 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00278 IRQn_Type IRQn; 00279 IRQHandler handler; 00280 00281 IRQn = vdc5_irq_set_tbl[irq]; 00282 handler = R_VDC5_GetISR(ch, irq); 00283 00284 if (enable) { 00285 InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); 00286 GIC_SetPriority(IRQn, 5); 00287 GIC_EnableIRQ(IRQn); 00288 } else { 00289 GIC_DisableIRQ(IRQn); 00290 } 00291 } /* End of function DRV_Graphics_Irq_Set() */ 00292 00293 /**************************************************************************//** 00294 * @brief Interrupt callback setup 00295 * This function performs the following processing: 00296 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified. 00297 * - Registers the specified interrupt callback function. 00298 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not 00299 * specified. 00300 * @param[in] irq : VDC5 interrupt type 00301 * @param[in] num : Interrupt line number 00302 * @param[in] * callback : Interrupt callback function pointer 00303 * @retval Error code 00304 ******************************************************************************/ 00305 drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( 00306 vdc5_int_type_t irq, 00307 uint16_t num, 00308 void (* callback)(vdc5_int_type_t ) ) 00309 { 00310 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00311 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00312 vdc5_error_t error; 00313 vdc5_int_t interrupt; 00314 00315 if( callback == NULL ) { 00316 DRV_Graphics_Irq_Set( irq, 0 ); 00317 } else { 00318 DRV_Graphics_Irq_Set( irq, 1 ); 00319 } 00320 00321 /* Interrupt parameter */ 00322 interrupt.type = irq; /* Interrupt type */ 00323 interrupt.line_num = num ; /* Line number */ 00324 00325 /* Interrupt parameter */ 00326 interrupt.callback = callback; /* Callback function pointer */ 00327 /* Set interrupt service routine */ 00328 error = R_VDC5_CallbackISR(ch, &interrupt); 00329 if (error != VDC5_OK ) { 00330 drv_error = DRV_GRAPHICS_VDC5_ERR; 00331 } 00332 return drv_error ; 00333 } /* End of function DRV_Graphics_Irq_Handler_Set() */ 00334 00335 /**************************************************************************//** 00336 * @brief LCD output port initialization processing 00337 * @param[in] pin : Pin assign for LCD output 00338 * @param[in] pin_count : Total number of pin assign 00339 * @retval Error code 00340 ******************************************************************************/ 00341 drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count ) 00342 { 00343 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00344 uint32_t count; 00345 00346 for( count = 0 ; count < pin_count ; count++ ) { 00347 pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN); 00348 pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN); 00349 } 00350 return drv_error; 00351 } /* End of function DRV_Graphics_Lcd_Port_Init() */ 00352 00353 /**************************************************************************//** 00354 * @brief LVDS output port initialization processing 00355 * @param[in] pin : Pin assign for LVDS output 00356 * @param[in] pin_count : Total number of pin assign 00357 * @retval Error code 00358 ******************************************************************************/ 00359 drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count ) 00360 { 00361 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00362 uint32_t count; 00363 00364 for( count = 0 ; count < pin_count ; count++ ) { 00365 pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN); 00366 pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN); 00367 } 00368 return drv_error; 00369 } /* End of function DRV_Graphics_Lvds_Port_Init() */ 00370 00371 /**************************************************************************//** 00372 * @brief Digital video inpout port initialization processing 00373 * @param[in] pin : Pin assign for digital video input port 00374 * @param[in] pin_count : Total number of pin assign 00375 * @retval Error code 00376 ******************************************************************************/ 00377 drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count ) 00378 { 00379 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00380 uint32_t count; 00381 00382 for( count = 0 ; count < pin_count ; count++ ) { 00383 pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN); 00384 pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN); 00385 } 00386 return drv_error; 00387 } /* End of function DRV_Graphics_Dvinput_Port_Init() */ 00388 00389 /**************************************************************************//** 00390 * @brief Graphics initialization processing 00391 * @param[in] drv_lcd_config : LCD configuration 00392 * @retval Error code 00393 ******************************************************************************/ 00394 drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config ) 00395 { 00396 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00397 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00398 vdc5_error_t error; 00399 vdc5_init_t init; 00400 vdc5_lvds_t vdc5_lvds; 00401 pll_parameter_t pll_parameter; 00402 double InputClock = DEFAULT_INPUT_CLOCK; 00403 double OutputClock = DEFAULT_OUTPUT_CLOCK; 00404 uint32_t LvdsUsed = LVDS_IF_USE; 00405 00406 /* Initialization parameter */ 00407 init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS ; /* Panel clock select */ 00408 init.panel_dcdr = VDC5_PANEL_CLKDIV_1_1 ; /* Panel clock frequency division ratio */ 00409 00410 if( drv_lcd_config != NULL ) { 00411 InputClock = drv_lcd_config->intputClock; 00412 OutputClock = drv_lcd_config->outputClock; 00413 00414 /* LVDS PLL Setting Calculation */ 00415 if( drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS ) { 00416 LvdsUsed = LVDS_IF_USE; 00417 init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS_DIV7 ; /* Panel clock select */ 00418 } else { 00419 LvdsUsed = LVDS_IF_NOT_USE; 00420 } 00421 } 00422 lvds_pll_calc( InputClock, OutputClock, LvdsUsed, &pll_parameter ); 00423 00424 vdc5_lvds.lvds_in_clk_sel = VDC5_LVDS_INCLK_SEL_PERI ; /* P1 */ 00425 vdc5_lvds.lvds_idiv_set = (vdc5_lvds_ndiv_t )pll_parameter.nidiv; 00426 vdc5_lvds.lvdspll_tst = 16u; 00427 vdc5_lvds.lvds_odiv_set = (vdc5_lvds_ndiv_t )pll_parameter.nodiv; 00428 vdc5_lvds.lvdspll_tst = 16u; 00429 vdc5_lvds.lvds_vdc_sel = ch; 00430 vdc5_lvds.lvdspll_fd = pll_parameter.nfd; 00431 vdc5_lvds.lvdspll_rd = pll_parameter.nrd; 00432 vdc5_lvds.lvdspll_od = (vdc5_lvds_pll_nod_t )pll_parameter.nod; 00433 init.lvds = &vdc5_lvds; /* LVDS parameter */ 00434 00435 /* Initialize (Set module clock to VDC5) */ 00436 error = R_VDC5_Initialize( ch, &init, &init_func, (uint32_t)ch ); 00437 if (error != VDC5_OK ) { 00438 drv_error = DRV_GRAPHICS_VDC5_ERR; 00439 } 00440 00441 if ( drv_error == DRV_GRAPHICS_OK ) { 00442 vdc5_sync_ctrl_t sync_ctrl; 00443 00444 /* Sync signal control */ 00445 sync_ctrl.res_vs_sel = VDC5_ON ; /* Vsync signal output select (free-running Vsync on/off control) */ 00446 /* Sync signal output and full-screen enable signal select */ 00447 sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0 ; 00448 sync_ctrl.res_fv = drv_lcd_config->v_toatal_period-1; /* Free-running Vsync period setting */ 00449 sync_ctrl.res_fh = drv_lcd_config->h_toatal_period-1; /* Hsync period setting */ 00450 sync_ctrl.res_vsdly = (uint16_t)0u; /* Vsync signal delay control */ 00451 /* Full-screen enable control */ 00452 sync_ctrl.res_f .vs = (drv_lcd_config->v_back_porch); 00453 sync_ctrl.res_f .vw = (drv_lcd_config->v_disp_widht); 00454 sync_ctrl.res_f .hs = (drv_lcd_config->h_back_porch); 00455 sync_ctrl.res_f .hw = (drv_lcd_config->h_disp_widht); 00456 sync_ctrl.vsync_cpmpe = NULL; /* Vsync signal compensation */ 00457 /* Sync control */ 00458 error = R_VDC5_SyncControl( ch, &sync_ctrl ); 00459 if (error != VDC5_OK ) { 00460 drv_error = DRV_GRAPHICS_VDC5_ERR; 00461 } 00462 } 00463 00464 if ( drv_error == DRV_GRAPHICS_OK ) { 00465 vdc5_output_t output; 00466 vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS; 00467 vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE; 00468 vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS; 00469 vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE; 00470 vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE; 00471 00472 /* Output parameter */ 00473 output.tcon_half = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */ 00474 output.tcon_offset = 0; /* TCON reference timing, offset Hsync signal timing */ 00475 00476 /* LCD TCON timing setting */ 00477 if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) { 00478 lcd_tcon_timing_VS.tcon_hsvs = 0u; 00479 lcd_tcon_timing_VS.tcon_hwvw = (drv_lcd_config->v_sync_width * 2u); 00480 lcd_tcon_timing_VS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL ; 00481 lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC ; 00482 lcd_tcon_timing_VS.tcon_inv = (vdc5_sig_pol_t )drv_lcd_config->v_sync_port_polarity; 00483 lcd_tcon_timing_VS.tcon_pin = (vdc5_lcd_tcon_pin_t )drv_lcd_config->v_sync_port; 00484 lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING ; 00485 output.outctrl [VDC5_LCD_TCONSIG_STVA_VS ] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync */ 00486 } else { 00487 output.outctrl [VDC5_LCD_TCONSIG_STVA_VS ] = NULL; /* STVA/VS: Vsync */ 00488 } 00489 00490 if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) { 00491 lcd_tcon_timing_HS.tcon_hsvs = 0u; 00492 lcd_tcon_timing_HS.tcon_hwvw = drv_lcd_config->h_sync_width; 00493 lcd_tcon_timing_HS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL ; 00494 lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC ; 00495 lcd_tcon_timing_HS.tcon_inv = (vdc5_sig_pol_t )drv_lcd_config->h_sync_port_polarity; 00496 lcd_tcon_timing_HS.tcon_pin = (vdc5_lcd_tcon_pin_t )drv_lcd_config->h_sync_port; 00497 lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING ; 00498 output.outctrl [VDC5_LCD_TCONSIG_STH_SP_HS ] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync */ 00499 } else { 00500 output.outctrl [VDC5_LCD_TCONSIG_STH_SP_HS ] = NULL; /* STH/SP/HS: Hsync */ 00501 } 00502 00503 if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) { 00504 lcd_tcon_timing_VE.tcon_hsvs = (drv_lcd_config->v_back_porch * 2u); 00505 lcd_tcon_timing_VE.tcon_hwvw = (drv_lcd_config->v_disp_widht * 2u); 00506 lcd_tcon_timing_VE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL ; 00507 lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC ; 00508 lcd_tcon_timing_VE.tcon_inv = (vdc5_sig_pol_t )drv_lcd_config->de_port_polarity; 00509 lcd_tcon_timing_VE.tcon_pin = VDC5_LCD_TCON_PIN_NON ; 00510 lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING ; 00511 output.outctrl [VDC5_LCD_TCONSIG_STVB_VE ] = &lcd_tcon_timing_VE; /* STVB/VE: Not used */ 00512 00513 lcd_tcon_timing_HE.tcon_hsvs = drv_lcd_config->h_back_porch; 00514 lcd_tcon_timing_HE.tcon_hwvw = drv_lcd_config->h_disp_widht; 00515 lcd_tcon_timing_HE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL ; 00516 lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC ; 00517 lcd_tcon_timing_HE.tcon_inv = (vdc5_sig_pol_t )drv_lcd_config->de_port_polarity; 00518 lcd_tcon_timing_HE.tcon_pin = VDC5_LCD_TCON_PIN_NON ; 00519 lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING ; 00520 output.outctrl [VDC5_LCD_TCONSIG_STB_LP_HE ] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */ 00521 00522 lcd_tcon_timing_DE.tcon_hsvs = 0u; 00523 lcd_tcon_timing_DE.tcon_hwvw = 0u; 00524 lcd_tcon_timing_DE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL ; 00525 lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC ; 00526 lcd_tcon_timing_DE.tcon_inv = (vdc5_sig_pol_t )drv_lcd_config->de_port_polarity; 00527 lcd_tcon_timing_DE.tcon_pin = (vdc5_lcd_tcon_pin_t )drv_lcd_config->de_port; 00528 lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING ; 00529 output.outctrl [VDC5_LCD_TCONSIG_DE ] = &lcd_tcon_timing_DE; /* DE */ 00530 } else { 00531 output.outctrl [VDC5_LCD_TCONSIG_STVB_VE ] = NULL; /* STVB/VE: Not used */ 00532 output.outctrl [VDC5_LCD_TCONSIG_STB_LP_HE ] = NULL; /* STB/LP/HE: Not used */ 00533 output.outctrl [VDC5_LCD_TCONSIG_DE ] = NULL; /* DE */ 00534 } 00535 00536 output.outctrl [VDC5_LCD_TCONSIG_CPV_GCK ] = NULL; 00537 output.outctrl [VDC5_LCD_TCONSIG_POLA ] = NULL; 00538 output.outctrl [VDC5_LCD_TCONSIG_POLB ] = NULL; 00539 00540 output.outcnt_lcd_edge = (vdc5_edge_t )drv_lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */ 00541 output.out_endian_on = VDC5_OFF ; /* Bit endian change on/off control */ 00542 output.out_swap_on = VDC5_OFF ; /* B/R signal swap on/off control */ 00543 output.out_format = (vdc5_lcd_outformat_t )drv_lcd_config->lcd_outformat; /* Output format select */ 00544 output.out_frq_sel = VDC5_LCD_PARALLEL_CLKFRQ_1 ; /* Clock frequency control */ 00545 output.out_dir_sel = VDC5_LCD_SERIAL_SCAN_FORWARD ; /* Scan direction select */ 00546 output.out_phase = VDC5_LCD_SERIAL_CLKPHASE_0 ; /* Clock phase adjustment */ 00547 output.bg_color = (uint32_t)0x00000000u; /* Background color in 24-bit RGB color format */ 00548 /* Display output */ 00549 error = R_VDC5_DisplayOutput( ch, &output ); 00550 if (error != VDC5_OK ) { 00551 drv_error = DRV_GRAPHICS_VDC5_ERR; 00552 } 00553 } 00554 return drv_error; 00555 } /* End of function DRV_Graphics_Init() */ 00556 00557 /**************************************************************************//** 00558 * @brief Video initialization processing 00559 * @param[in] drv_video_ext_in_config : Video configuration 00560 * @retval Error code 00561 ******************************************************************************/ 00562 drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config ) 00563 { 00564 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00565 vdc5_error_t error; 00566 vdc5_input_t input; 00567 vdc5_ext_in_sig_t ext_in_sig; 00568 vdc5_sync_delay_t sync_delay; 00569 00570 input.inp_sel = (vdc5_input_sel_t )drv_video_input_sel; /* Input select */ 00571 input.inp_fh50 = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */ 00572 input.inp_fh25 = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */ 00573 00574 if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) { 00575 input.dly = NULL; /* Sync signal delay adjustment */ 00576 input.ext_sig = NULL; /* External input signal */ 00577 } else { 00578 ext_in_sig.inp_format = (vdc5_extin_format_t )drv_video_ext_in_config->inp_format; 00579 ext_in_sig.inp_pxd_edge = (vdc5_edge_t )drv_video_ext_in_config->inp_pxd_edge; 00580 ext_in_sig.inp_vs_edge = (vdc5_edge_t )drv_video_ext_in_config->inp_vs_edge; 00581 ext_in_sig.inp_hs_edge = (vdc5_edge_t )drv_video_ext_in_config->inp_hs_edge; 00582 ext_in_sig.inp_endian_on = (vdc5_onoff_t )drv_video_ext_in_config->inp_endian_on; 00583 ext_in_sig.inp_swap_on = (vdc5_onoff_t )drv_video_ext_in_config->inp_swap_on; 00584 ext_in_sig.inp_vs_inv = (vdc5_sig_pol_t )drv_video_ext_in_config->inp_vs_inv; 00585 ext_in_sig.inp_hs_inv = (vdc5_sig_pol_t )drv_video_ext_in_config->inp_hs_inv; 00586 ext_in_sig.inp_h_edge_sel = (vdc5_extin_ref_hsync_t )drv_video_ext_in_config->inp_hs_edge; 00587 ext_in_sig.inp_f525_625 = (vdc5_extin_input_line_t )drv_video_ext_in_config->inp_f525_625; 00588 ext_in_sig.inp_h_pos = (vdc5_extin_h_pos_t )drv_video_ext_in_config->inp_h_pos; 00589 00590 sync_delay.inp_vs_dly_l = 0u; 00591 sync_delay.inp_vs_dly = 16u; 00592 sync_delay.inp_hs_dly = 16u; 00593 sync_delay.inp_fld_dly = 16u; 00594 00595 input.dly = &sync_delay; /* Sync signal delay adjustment */ 00596 input.ext_sig = &ext_in_sig; /* External input signal */ 00597 } 00598 /* Video input 0ch */ 00599 error = R_VDC5_VideoInput( VDC5_CHANNEL_0 , &input ); 00600 if (error != VDC5_OK ) { 00601 drv_error = DRV_GRAPHICS_VDC5_ERR; 00602 } 00603 00604 if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) { 00605 if ( drv_error == DRV_GRAPHICS_OK ) { 00606 /* Video input 1ch */ 00607 error = R_VDC5_VideoInput( VDC5_CHANNEL_1 , &input ); 00608 if (error != VDC5_OK ) { 00609 drv_error = DRV_GRAPHICS_VDC5_ERR; 00610 } 00611 } 00612 } 00613 return drv_error; 00614 } /* End of function DRV_Video_Init() */ 00615 00616 /**************************************************************************//** 00617 * @brief Start the graphics surface read process 00618 * @param[in] layer_id : Graphics layer ID 00619 * @retval drv_graphics_error_t 00620 ******************************************************************************/ 00621 drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id ) 00622 { 00623 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00624 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00625 vdc5_error_t error; 00626 vdc5_start_t start; 00627 vdc5_gr_disp_sel_t gr_disp_sel; 00628 vdc5_layer_id_t vdc5_layer_id; 00629 00630 switch( layer_id ) { 00631 case DRV_GRAPHICS_LAYER_0: 00632 vdc5_layer_id = VDC5_LAYER_ID_0_RD ; 00633 gr_disp_sel = VDC5_DISPSEL_CURRENT ; 00634 break; 00635 case DRV_GRAPHICS_LAYER_1: 00636 vdc5_layer_id = VDC5_LAYER_ID_1_RD ; 00637 gr_disp_sel = VDC5_DISPSEL_BLEND ; 00638 break; 00639 case DRV_GRAPHICS_LAYER_2: 00640 vdc5_layer_id = VDC5_LAYER_ID_2_RD ; 00641 gr_disp_sel = VDC5_DISPSEL_BLEND ; 00642 break; 00643 case DRV_GRAPHICS_LAYER_3: 00644 vdc5_layer_id = VDC5_LAYER_ID_3_RD ; 00645 gr_disp_sel = VDC5_DISPSEL_BLEND ; 00646 break; 00647 default: 00648 drv_error = DRV_GRAPHICS_LAYER_ERR; 00649 break; 00650 } 00651 00652 if( drv_error == DRV_GRAPHICS_OK ) { 00653 /* Start process */ 00654 start.gr_disp_sel = &gr_disp_sel; 00655 error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start ); 00656 if (error != VDC5_OK ) { 00657 drv_error = DRV_GRAPHICS_VDC5_ERR; 00658 } 00659 } 00660 return drv_error; 00661 } /* End of function DRV_Graphics_Start() */ 00662 00663 /**************************************************************************//** 00664 * @brief Stop the graphics surface read process 00665 * @param[in] layer_id : Graphics layer ID 00666 * @retval Error code 00667 ******************************************************************************/ 00668 drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id ) 00669 { 00670 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00671 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00672 vdc5_error_t error; 00673 vdc5_layer_id_t vdc5_layer_id; 00674 00675 switch( layer_id ) { 00676 case DRV_GRAPHICS_LAYER_0: 00677 vdc5_layer_id = VDC5_LAYER_ID_0_RD ; 00678 break; 00679 case DRV_GRAPHICS_LAYER_1: 00680 vdc5_layer_id = VDC5_LAYER_ID_1_RD ; 00681 break; 00682 case DRV_GRAPHICS_LAYER_2: 00683 vdc5_layer_id = VDC5_LAYER_ID_2_RD ; 00684 break; 00685 case DRV_GRAPHICS_LAYER_3: 00686 vdc5_layer_id = VDC5_LAYER_ID_3_RD ; 00687 break; 00688 default: 00689 drv_error = DRV_GRAPHICS_LAYER_ERR; 00690 break; 00691 } 00692 00693 if( drv_error == DRV_GRAPHICS_OK ) { 00694 /* Stop process */ 00695 error = R_VDC5_StopProcess ( ch, vdc5_layer_id ); 00696 if (error != VDC5_OK ) { 00697 drv_error = DRV_GRAPHICS_VDC5_ERR; 00698 } 00699 } 00700 return drv_error; 00701 } /* End of function DRV_Graphics_Stop() */ 00702 00703 /**************************************************************************//** 00704 * @brief Start the video surface write process 00705 * @param[in] video_input_ch : Video input channel 00706 * @retval Error code 00707 ******************************************************************************/ 00708 drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch ) 00709 { 00710 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00711 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00712 vdc5_error_t error; 00713 vdc5_start_t start; 00714 vdc5_gr_disp_sel_t gr_disp_sel; 00715 vdc5_layer_id_t vdc5_layer_id; 00716 00717 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) { 00718 vdc5_layer_id = VDC5_LAYER_ID_0_WR ; 00719 } else if ( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) { 00720 vdc5_layer_id = VDC5_LAYER_ID_1_WR ; 00721 } else { 00722 drv_error = DRV_GRAPHICS_LAYER_ERR; 00723 } 00724 00725 if( drv_error == DRV_GRAPHICS_OK ) { 00726 /* Start process */ 00727 gr_disp_sel = VDC5_DISPSEL_CURRENT ; /* CURRENT fixed for weave input mode */ 00728 start.gr_disp_sel = &gr_disp_sel; 00729 error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start ); 00730 if (error != VDC5_OK ) { 00731 drv_error = DRV_GRAPHICS_VDC5_ERR; 00732 } 00733 } 00734 return drv_error; 00735 } /* End of function DRV_Video_Start() */ 00736 00737 /**************************************************************************//** 00738 * @brief Stop the video surface write process 00739 * @param[in] video_input_ch : Video input channel 00740 * @retval Error code 00741 ******************************************************************************/ 00742 drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch ) 00743 { 00744 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00745 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00746 vdc5_error_t error; 00747 vdc5_layer_id_t vdc5_layer_id; 00748 00749 switch (video_input_ch) { 00750 case DRV_VIDEO_INPUT_CHANNEL_0: 00751 vdc5_layer_id = VDC5_LAYER_ID_0_WR ; 00752 break; 00753 case DRV_VIDEO_INPUT_CHANNEL_1: 00754 vdc5_layer_id = VDC5_LAYER_ID_1_WR ; 00755 break; 00756 default: 00757 drv_error = DRV_GRAPHICS_LAYER_ERR; 00758 break; 00759 } 00760 00761 if( drv_error == DRV_GRAPHICS_OK ) { 00762 /* Stop process */ 00763 error = R_VDC5_StopProcess ( ch, vdc5_layer_id ); 00764 if (error != VDC5_OK ) { 00765 drv_error = DRV_GRAPHICS_VDC5_ERR; 00766 } 00767 } 00768 return drv_error; 00769 } /* End of function DRV_Video_Stop() */ 00770 00771 /**************************************************************************//** 00772 * @brief Graphics surface read process setting 00773 * 00774 * Description:<br> 00775 * This function supports the following 4 image format. 00776 * YCbCr422, RGB565, RGB888, ARGB8888 00777 * @param[in] layer_id : Graphics layer ID 00778 * @param[in] framebuff : Base address of the frame buffer 00779 * @param[in] fb_stride : Line offset address of the frame buffer 00780 * @param[in] gr_format : Format of the frame buffer read signal 00781 * @param[in] gr_rect : Graphics display area 00782 * @retval Error code 00783 ******************************************************************************/ 00784 drv_graphics_error_t DRV_Graphics_Read_Setting ( 00785 drv_graphics_layer_t layer_id, 00786 void * framebuff, 00787 uint32_t fb_stride, 00788 drv_graphics_format_t gr_format, 00789 drv_wr_rd_swa_t wr_rd_swa, 00790 drv_rect_t * gr_rect ) 00791 { 00792 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00793 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00794 vdc5_error_t error; 00795 vdc5_layer_id_t vdc5_layer_id; 00796 vdc5_gr_format_t vdc5_gr_format; 00797 vdc5_read_t read; 00798 00799 switch(layer_id) { 00800 case DRV_GRAPHICS_LAYER_0: 00801 vdc5_layer_id = VDC5_LAYER_ID_0_RD ; 00802 break; 00803 case DRV_GRAPHICS_LAYER_1: 00804 vdc5_layer_id = VDC5_LAYER_ID_1_RD ; 00805 break; 00806 case DRV_GRAPHICS_LAYER_2: 00807 vdc5_layer_id = VDC5_LAYER_ID_2_RD ; 00808 break; 00809 case DRV_GRAPHICS_LAYER_3: 00810 vdc5_layer_id = VDC5_LAYER_ID_3_RD ; 00811 break; 00812 default: 00813 drv_error = DRV_GRAPHICS_LAYER_ERR; 00814 break; 00815 } 00816 00817 if( drv_error == DRV_GRAPHICS_OK ) { 00818 switch( gr_format ) { 00819 case DRV_GRAPHICS_FORMAT_YCBCR422: 00820 vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422 ; 00821 break; 00822 case DRV_GRAPHICS_FORMAT_RGB565: 00823 vdc5_gr_format = VDC5_GR_FORMAT_RGB565 ; 00824 break; 00825 case DRV_GRAPHICS_FORMAT_RGB888: 00826 vdc5_gr_format = VDC5_GR_FORMAT_RGB888 ; 00827 break; 00828 case DRV_GRAPHICS_FORMAT_ARGB8888: 00829 vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888 ; 00830 break; 00831 case DRV_GRAPHICS_FORMAT_ARGB4444: 00832 vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444 ; 00833 break; 00834 default: 00835 drv_error = DRV_GRAPHICS_FORMAT_ERR; 00836 break; 00837 } 00838 } 00839 00840 if( drv_error == DRV_GRAPHICS_OK ) { 00841 /* Read data parameter */ 00842 read.gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC ; /* Line offset address direction of the frame buffer */ 00843 read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM ; /* Selects a frame buffer address setting signal */ 00844 read.gr_imr_flm_inv = VDC5_OFF ; /* Frame buffer number for distortion correction */ 00845 read.gr_bst_md = VDC5_BST_MD_32BYTE ; /* Frame buffer burst transfer mode */ 00846 read.gr_base = framebuff; /* Frame buffer base address */ 00847 read.gr_ln_off = fb_stride; /* Frame buffer line offset address */ 00848 00849 read.width_read_fb = NULL; /* Width of the image read from frame buffer */ 00850 00851 read.adj_sel = VDC5_OFF ; /* Measures to decrease the influence 00852 by folding pixels/lines (on/off) */ 00853 read.gr_format = vdc5_gr_format; /* Format of the frame buffer read signal */ 00854 read.gr_ycc_swap = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer 00855 in the YCbCr422 format */ 00856 read.gr_rdswa = (vdc5_wr_rd_swa_t )wr_rd_swa; /* Frame buffer swap setting */ 00857 /* Display area */ 00858 read.gr_grc .vs = gr_rect->vs; 00859 read.gr_grc .vw = gr_rect->vw; 00860 read.gr_grc .hs = gr_rect->hs; 00861 read.gr_grc .hw = gr_rect->hw; 00862 00863 /* Read data control */ 00864 error = R_VDC5_ReadDataControl( ch, vdc5_layer_id, &read ); 00865 if (error != VDC5_OK ) { 00866 drv_error = DRV_GRAPHICS_VDC5_ERR; 00867 } 00868 } 00869 return drv_error; 00870 } /* End of function DRV_Graphics_Read_Setting() */ 00871 00872 /**************************************************************************//** 00873 * @brief Graphics surface read buffer change process 00874 * @param[in] layer_id : Graphics layer ID 00875 * @param[in] framebuff : Base address of the frame buffer 00876 * @retval Error code 00877 ******************************************************************************/ 00878 drv_graphics_error_t DRV_Graphics_Read_Change ( 00879 drv_graphics_layer_t layer_id, 00880 void * framebuff) 00881 { 00882 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00883 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00884 vdc5_error_t error; 00885 vdc5_layer_id_t vdc5_layer_id; 00886 vdc5_read_chg_t read_chg; 00887 00888 switch(layer_id) { 00889 case DRV_GRAPHICS_LAYER_0: 00890 vdc5_layer_id = VDC5_LAYER_ID_0_RD ; 00891 break; 00892 case DRV_GRAPHICS_LAYER_1: 00893 vdc5_layer_id = VDC5_LAYER_ID_1_RD ; 00894 break; 00895 case DRV_GRAPHICS_LAYER_2: 00896 vdc5_layer_id = VDC5_LAYER_ID_2_RD ; 00897 break; 00898 case DRV_GRAPHICS_LAYER_3: 00899 vdc5_layer_id = VDC5_LAYER_ID_3_RD ; 00900 break; 00901 default: 00902 drv_error = DRV_GRAPHICS_LAYER_ERR; 00903 break; 00904 } 00905 00906 if( drv_error == DRV_GRAPHICS_OK ) { 00907 /* Read data parameter */ 00908 read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */ 00909 read_chg.gr_grc = NULL; /* Display area */ 00910 read_chg.gr_disp_sel = NULL; /* Graphics display mode */ 00911 read_chg.gr_base = framebuff; /* Frame buffer base address */ 00912 00913 /* Change read process */ 00914 error = R_VDC5_ChangeReadProcess( ch, vdc5_layer_id, &read_chg ); 00915 if (error != VDC5_OK ) { 00916 drv_error = DRV_GRAPHICS_VDC5_ERR; 00917 } 00918 } 00919 return drv_error; 00920 } /* End of function DRV_Graphics_Read_Change() */ 00921 00922 /**************************************************************************//** 00923 * @brief Video surface write process setting 00924 * 00925 * Description:<br> 00926 * This function set the video write process. Input form is weave 00927 * (progressive) mode fixed. 00928 * This function supports the following 3 image format. 00929 * YCbCr422, RGB565, RGB888 00930 * @param[in] video_input_ch : Video input channel 00931 * @param[in] col_sys : Analog video signal color system 00932 * @param[in] adc_vinsel : Video input pin 00933 * @param[in] framebuff : Base address of the frame buffer 00934 * @param[in] fb_stride [byte] : Line offset address of the frame buffer 00935 * @param[in] video_format : Frame buffer video-signal writing format 00936 * @param[in] wr_rd_swa : Frame buffer swap setting 00937 * @param[in] video_write_size_vw [px]: output height 00938 * @param[in] video_write_size_hw [px]: output width 00939 * @param[in] video_adc_vinsel : Input pin control 00940 * @retval Error code 00941 ******************************************************************************/ 00942 drv_graphics_error_t DRV_Video_Write_Setting ( 00943 drv_video_input_channel_t video_input_ch, 00944 drv_graphics_video_col_sys_t col_sys, 00945 void * framebuff, 00946 uint32_t fb_stride, 00947 drv_video_format_t video_format, 00948 drv_wr_rd_swa_t wr_rd_swa, 00949 uint16_t video_write_buff_vw, 00950 uint16_t video_write_buff_hw, 00951 drv_video_adc_vinsel_t video_adc_vinsel ) 00952 { 00953 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 00954 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 00955 vdc5_error_t error; 00956 vdc5_layer_id_t vdc5_layer_id; 00957 vdc5_write_t write; 00958 vdc5_scalingdown_rot_t * scldw_rot; 00959 vdc5_res_md_t res_md; 00960 drv_rect_t video_in_rect; 00961 uint8_t * framebuffer_t; 00962 uint8_t * framebuffer_b; 00963 00964 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) { 00965 GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t )video_adc_vinsel, VDEC_CHANNEL_0 , (graphics_col_sys_t )col_sys ); 00966 } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) { 00967 GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t )video_adc_vinsel, VDEC_CHANNEL_1 , (graphics_col_sys_t )col_sys ); 00968 } else { 00969 drv_error = DRV_GRAPHICS_CHANNEL_ERR; 00970 } 00971 00972 if( drv_error == DRV_GRAPHICS_OK ) { 00973 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) { 00974 vdc5_layer_id = VDC5_LAYER_ID_0_WR ; 00975 } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) { 00976 vdc5_layer_id = VDC5_LAYER_ID_1_WR ; 00977 } else { 00978 drv_error = DRV_GRAPHICS_CHANNEL_ERR; 00979 } 00980 } 00981 00982 if( drv_error == DRV_GRAPHICS_OK ) { 00983 if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) { 00984 res_md = VDC5_RES_MD_YCBCR422 ; 00985 } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) { 00986 res_md = VDC5_RES_MD_RGB888 ; 00987 } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) { 00988 res_md = VDC5_RES_MD_RGB565 ; 00989 } else { 00990 drv_error = DRV_GRAPHICS_FORMAT_ERR; 00991 } 00992 } 00993 00994 if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) { 00995 video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2; 00996 video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2; 00997 video_in_rect.vs = IMGCAP_SIZE_NTSC_VS; 00998 video_in_rect.vw = IMGCAP_SIZE_NTSC_VW; 00999 } else { 01000 video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2; 01001 video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2; 01002 video_in_rect.vs = IMGCAP_SIZE_PAL_VS; 01003 video_in_rect.vw = IMGCAP_SIZE_PAL_VW; 01004 } 01005 01006 if( drv_error == DRV_GRAPHICS_OK ) { 01007 if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) { 01008 if( (video_write_buff_vw / 2u) > video_in_rect.vw ) { 01009 drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR; 01010 } 01011 } else { 01012 if( (video_write_buff_vw / 2u) > video_in_rect.vw ) { 01013 drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR; 01014 } 01015 } 01016 } 01017 01018 if( drv_error == DRV_GRAPHICS_OK ) { 01019 if( video_write_buff_hw > 800 ) { 01020 drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR; 01021 } 01022 } 01023 01024 if( drv_error == DRV_GRAPHICS_OK ) { 01025 /* Scaling-down and rotation parameter */ 01026 scldw_rot = &write.scalingdown_rot ; 01027 /* Image area to be captured */ 01028 scldw_rot->res .vs = (uint16_t)((uint32_t)video_in_rect.vs - 1u); 01029 scldw_rot->res .vw = video_in_rect.vw; 01030 scldw_rot->res .hs = video_in_rect.hs; 01031 scldw_rot->res .hw = video_in_rect.hw; 01032 01033 /* Write data parameter */ 01034 framebuffer_t = framebuff; 01035 framebuffer_b = &framebuffer_t[fb_stride]; 01036 scldw_rot->res_pfil_sel = VDC5_ON ; /* Prefilter mode select for brightness signals (on/off) */ 01037 scldw_rot->res_out_vw = video_write_buff_vw / 2u; /* Number of valid lines in vertical direction 01038 output by scaling-down control block */ 01039 scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels 01040 output by scaling-down control block */ 01041 scldw_rot->adj_sel = VDC5_ON ; /* Measures to decrease the influence 01042 by lack of last-input line (on/off) */ 01043 scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL ; /* Frame buffer writing mode */ 01044 write.res_wrswa = (vdc5_wr_rd_swa_t )wr_rd_swa; /* Frame buffer swap setting */ 01045 write.res_md = res_md; /* Frame buffer video-signal writing format */ 01046 write.res_bst_md = VDC5_BST_MD_32BYTE ; /* Transfer burst length for frame buffer */ 01047 write.res_inter = VDC5_RES_INTER_PROGRESSIVE ; /* Field operating mode select */ 01048 write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */ 01049 write.res_fld_sel = VDC5_RES_FLD_SEL_TOP ; /* Write field select */ 01050 write.res_dth_on = VDC5_ON ; /* Dither correction on/off */ 01051 write.base = framebuff; /* Frame buffer base address */ 01052 write.ln_off = fb_stride * 2u; /* Frame buffer line offset address [byte] */ 01053 write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */ 01054 /* Frame buffer frame offset address */ 01055 write.flm_off = fb_stride * 2u * (uint32_t)scldw_rot->res_out_vw ; 01056 write.btm_base = framebuffer_b; /* Frame buffer base address for bottom */ 01057 01058 /* Write data control */ 01059 error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write ); 01060 if (error != VDC5_OK ) { 01061 drv_error = DRV_GRAPHICS_VDC5_ERR; 01062 } 01063 } 01064 return drv_error; 01065 } /* End of function DRV_Video_Write_Setting() */ 01066 01067 /**************************************************************************//** 01068 * @brief Video surface write process setting for digital input 01069 * 01070 * Description:<br> 01071 * This function set the video write process for digital input. 01072 * This function supports the following 3 image format. 01073 * YCbCr422, RGB565, RGB888 01074 * @param[in] framebuff : Base address of the frame buffer 01075 * @param[in] fb_stride [byte] : Line offset address of the frame buffer 01076 * @param[in] video_format : Frame buffer video-signal writing format 01077 * @param[in] wr_rd_swa : Frame buffer swap setting 01078 * @param[in] video_write_size_vw [px]: output height 01079 * @param[in] video_write_size_hw [px]: output width 01080 * @param[in] cap_area : Capture area 01081 * @retval Error code 01082 ******************************************************************************/ 01083 drv_graphics_error_t DRV_Video_Write_Setting_Digital ( 01084 void * framebuff, 01085 uint32_t fb_stride, 01086 drv_video_format_t video_format, 01087 drv_wr_rd_swa_t wr_rd_swa, 01088 uint16_t video_write_buff_vw, 01089 uint16_t video_write_buff_hw, 01090 drv_rect_t * cap_area ) 01091 { 01092 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 01093 vdc5_channel_t ch = VDC5_CHANNEL_0 ; 01094 vdc5_error_t error; 01095 vdc5_layer_id_t vdc5_layer_id; 01096 vdc5_write_t write; 01097 vdc5_scalingdown_rot_t * scldw_rot; 01098 vdc5_res_md_t res_md; 01099 01100 vdc5_layer_id = VDC5_LAYER_ID_0_WR ; 01101 01102 if( drv_error == DRV_GRAPHICS_OK ) { 01103 if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) { 01104 res_md = VDC5_RES_MD_YCBCR422 ; 01105 } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) { 01106 res_md = VDC5_RES_MD_RGB888 ; 01107 } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) { 01108 res_md = VDC5_RES_MD_RGB565 ; 01109 } else { 01110 drv_error = DRV_GRAPHICS_FORMAT_ERR; 01111 } 01112 } 01113 01114 if( drv_error == DRV_GRAPHICS_OK ) { 01115 /* Scaling-down and rotation parameter */ 01116 scldw_rot = &write.scalingdown_rot ; 01117 /* Image area to be captured */ 01118 scldw_rot->res .vs = (uint16_t)((uint32_t)cap_area->vs - 1u); 01119 scldw_rot->res .vw = cap_area->vw; 01120 scldw_rot->res .hs = cap_area->hs; 01121 scldw_rot->res .hw = cap_area->hw; 01122 01123 /* Write data parameter */ 01124 scldw_rot->res_pfil_sel = VDC5_ON ; /* Prefilter mode select for brightness signals (on/off) */ 01125 scldw_rot->res_out_vw = video_write_buff_vw ; /* Number of valid lines in vertical direction 01126 output by scaling-down control block */ 01127 scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels 01128 output by scaling-down control block */ 01129 scldw_rot->adj_sel = VDC5_ON ; /* Measures to decrease the influence 01130 by lack of last-input line (on/off) */ 01131 scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL ; /* Frame buffer writing mode */ 01132 write.res_wrswa = (vdc5_wr_rd_swa_t )wr_rd_swa; /* Frame buffer swap setting */ 01133 write.res_md = res_md; /* Frame buffer video-signal writing format */ 01134 write.res_bst_md = VDC5_BST_MD_32BYTE ; /* Transfer burst length for frame buffer */ 01135 write.res_inter = VDC5_RES_INTER_PROGRESSIVE ; /* Field operating mode select */ 01136 write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */ 01137 write.res_fld_sel = VDC5_RES_FLD_SEL_TOP ; /* Write field select */ 01138 write.res_dth_on = VDC5_ON ; /* Dither correction on/off */ 01139 write.base = framebuff; /* Frame buffer base address */ 01140 write.ln_off = fb_stride; 01141 /* Frame buffer line offset address [byte] */ 01142 write.flm_num = (uint32_t)(1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */ 01143 /* Frame buffer frame offset address */ 01144 write.flm_off = fb_stride * (uint32_t)scldw_rot->res_out_vw ; 01145 write.btm_base = NULL; /* Frame buffer base address for bottom */ 01146 01147 /* Write data control */ 01148 error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write ); 01149 if (error != VDC5_OK ) { 01150 drv_error = DRV_GRAPHICS_VDC5_ERR; 01151 } 01152 } 01153 return drv_error; 01154 } /* End of function DRV_Video_Write_Setting_Digital() */ 01155 01156 /**************************************************************************//** 01157 * @brief Video surface write buffer change process 01158 * @param[in] video_input_ch : Video input channle 01159 * @param[in] framebuff : Base address of the frame buffer 01160 * @param[in] fb_stride : Line offset address of the frame buffer 01161 * @retval Error code 01162 ******************************************************************************/ 01163 drv_graphics_error_t DRV_Video_Write_Change ( 01164 drv_video_input_channel_t video_input_ch, 01165 void * framebuff, 01166 uint32_t fb_stride ) 01167 { 01168 drv_graphics_error_t drv_error = DRV_GRAPHICS_OK; 01169 uint8_t * framebuffer_t; 01170 uint8_t * framebuffer_b; 01171 01172 framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F); 01173 framebuffer_b = &framebuffer_t[fb_stride]; 01174 01175 if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) { 01176 VDC50.SC0_SCL1_WR2 = (uint32_t)framebuffer_t; 01177 VDC50.SC0_SCL1_WR8 = (uint32_t)framebuffer_b; 01178 VDC50.SC0_SCL1_UPDATE = 0x10; 01179 } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) { 01180 VDC50.SC1_SCL1_WR2 = (uint32_t)framebuffer_t; 01181 VDC50.SC1_SCL1_WR8 = (uint32_t)framebuffer_b; 01182 VDC50.SC1_SCL1_UPDATE = 0x10; 01183 } else { 01184 drv_error = DRV_GRAPHICS_CHANNEL_ERR; 01185 } 01186 return drv_error; 01187 } /* End of function DRV_Video_Write_Change() */ 01188 01189 /* End of file */
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