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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_nor.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief NOR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive NOR memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control NOR flash memories. It uses the FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with NOR devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
<> 144:ef7eb2e8f9f7 21 with control and timing parameters for both normal and extended mode.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
<> 144:ef7eb2e8f9f7 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
<> 144:ef7eb2e8f9f7 25 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) Access NOR flash memory by read/write data unit operations using the functions
<> 144:ef7eb2e8f9f7 28 HAL_NOR_Read(), HAL_NOR_Program().
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (+) Perform NOR flash erase block/chip operations using the functions
<> 144:ef7eb2e8f9f7 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
<> 144:ef7eb2e8f9f7 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
<> 144:ef7eb2e8f9f7 35 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) You can monitor the NOR device HAL state by calling the function
<> 144:ef7eb2e8f9f7 41 HAL_NOR_GetState()
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
<> 144:ef7eb2e8f9f7 44 If a NOR flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 45 it should be implemented separately.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 *** NOR HAL driver macros list ***
<> 144:ef7eb2e8f9f7 48 =============================================
<> 144:ef7eb2e8f9f7 49 [..]
<> 144:ef7eb2e8f9f7 50 Below the list of most used macros in NOR HAL driver.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (+) NOR_WRITE : NOR memory write data to specified address
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 @endverbatim
<> 144:ef7eb2e8f9f7 55 ******************************************************************************
<> 144:ef7eb2e8f9f7 56 * @attention
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 61 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 62 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 66 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 68 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 69 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 ******************************************************************************
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_NOR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @defgroup NOR NOR
<> 144:ef7eb2e8f9f7 96 * @brief NOR driver modules
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /** @defgroup NOR_Private_Constants NOR Private Constants
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Constants to define address to set to write a command */
<> 144:ef7eb2e8f9f7 106 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 107 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 108 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
<> 144:ef7eb2e8f9f7 109 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 110 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 111 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
<> 144:ef7eb2e8f9f7 112 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Constants to define data to program a command */
<> 144:ef7eb2e8f9f7 115 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
<> 144:ef7eb2e8f9f7 116 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
<> 144:ef7eb2e8f9f7 117 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 118 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
<> 144:ef7eb2e8f9f7 119 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
<> 144:ef7eb2e8f9f7 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
<> 144:ef7eb2e8f9f7 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
<> 144:ef7eb2e8f9f7 122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 123 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
<> 144:ef7eb2e8f9f7 124 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
<> 144:ef7eb2e8f9f7 127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
<> 144:ef7eb2e8f9f7 128 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Mask on NOR STATUS REGISTER */
<> 144:ef7eb2e8f9f7 131 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
<> 144:ef7eb2e8f9f7 132 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @defgroup NOR_Private_Macros NOR Private Macros
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup NOR_Private_Variables NOR Private Variables
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 167 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 168 *
<> 144:ef7eb2e8f9f7 169 @verbatim
<> 144:ef7eb2e8f9f7 170 ==============================================================================
<> 144:ef7eb2e8f9f7 171 ##### NOR Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 172 ==============================================================================
<> 144:ef7eb2e8f9f7 173 [..]
<> 144:ef7eb2e8f9f7 174 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 175 the NOR memory
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 @endverbatim
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief Perform the NOR memory Initialization sequence
<> 144:ef7eb2e8f9f7 183 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 184 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 185 * @param Timing: pointer to NOR control timing structure
<> 144:ef7eb2e8f9f7 186 * @param ExtTiming: pointer to NOR extended mode timing structure
<> 144:ef7eb2e8f9f7 187 * @retval HAL status
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /* Check the NOR handle parameter */
<> 144:ef7eb2e8f9f7 192 if(hnor == NULL)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 if(hnor->State == HAL_NOR_STATE_RESET)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 200 hnor->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 203 HAL_NOR_MspInit(hnor);
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Initialize NOR control Interface */
<> 144:ef7eb2e8f9f7 207 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Initialize NOR timing Interface */
<> 144:ef7eb2e8f9f7 210 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Initialize NOR extended mode timing Interface */
<> 144:ef7eb2e8f9f7 213 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 216 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Initialize NOR Memory Data Width*/
<> 144:ef7eb2e8f9f7 219 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 else
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 uwNORMemoryDataWidth = NOR_MEMORY_16B;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 229 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 return HAL_OK;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief Perform NOR memory De-Initialization sequence
<> 144:ef7eb2e8f9f7 236 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 237 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 238 * @retval HAL status
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 243 HAL_NOR_MspDeInit(hnor);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Configure the NOR registers with their reset values */
<> 144:ef7eb2e8f9f7 246 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 249 hnor->State = HAL_NOR_STATE_RESET;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Release Lock */
<> 144:ef7eb2e8f9f7 252 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 return HAL_OK;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief NOR MSP Init
<> 144:ef7eb2e8f9f7 259 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 260 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 261 * @retval None
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 266 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 267 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 268 the HAL_NOR_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief NOR MSP DeInit
<> 144:ef7eb2e8f9f7 274 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 275 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 276 * @retval None
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 281 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 282 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 283 the HAL_NOR_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @brief NOR MSP Wait fro Ready/Busy signal
<> 144:ef7eb2e8f9f7 289 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 290 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 291 * @param Timeout: Maximum timeout value
<> 144:ef7eb2e8f9f7 292 * @retval None
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 297 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 298 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 299 the HAL_NOR_MspWait could be implemented in the user file
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 308 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 309 *
<> 144:ef7eb2e8f9f7 310 @verbatim
<> 144:ef7eb2e8f9f7 311 ==============================================================================
<> 144:ef7eb2e8f9f7 312 ##### NOR Input and Output functions #####
<> 144:ef7eb2e8f9f7 313 ==============================================================================
<> 144:ef7eb2e8f9f7 314 [..]
<> 144:ef7eb2e8f9f7 315 This section provides functions allowing to use and control the NOR memory
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 @endverbatim
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief Read NOR flash IDs
<> 144:ef7eb2e8f9f7 323 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 324 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 325 * @param pNOR_ID : pointer to NOR ID structure
<> 144:ef7eb2e8f9f7 326 * @retval HAL status
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Process Locked */
<> 144:ef7eb2e8f9f7 333 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 336 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 342 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 351 {
<> 144:ef7eb2e8f9f7 352 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 360 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Send read ID command */
<> 144:ef7eb2e8f9f7 363 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 364 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 365 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Read the NOR IDs */
<> 144:ef7eb2e8f9f7 368 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
<> 144:ef7eb2e8f9f7 369 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
<> 144:ef7eb2e8f9f7 370 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
<> 144:ef7eb2e8f9f7 371 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 374 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Process unlocked */
<> 144:ef7eb2e8f9f7 377 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 return HAL_OK;
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @brief Returns the NOR memory to Read mode.
<> 144:ef7eb2e8f9f7 384 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 385 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 386 * @retval HAL status
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Process Locked */
<> 144:ef7eb2e8f9f7 393 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 396 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 402 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 422 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Process unlocked */
<> 144:ef7eb2e8f9f7 425 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 return HAL_OK;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /**
<> 144:ef7eb2e8f9f7 431 * @brief Read data from NOR memory
<> 144:ef7eb2e8f9f7 432 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 433 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 434 * @param pAddress: pointer to Device address
<> 144:ef7eb2e8f9f7 435 * @param pData : pointer to read data
<> 144:ef7eb2e8f9f7 436 * @retval HAL status
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Process Locked */
<> 144:ef7eb2e8f9f7 443 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 446 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 452 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 470 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Send read data command */
<> 144:ef7eb2e8f9f7 473 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 474 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 475 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Read the data */
<> 144:ef7eb2e8f9f7 478 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 481 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Process unlocked */
<> 144:ef7eb2e8f9f7 484 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 return HAL_OK;
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @brief Program data to NOR memory
<> 144:ef7eb2e8f9f7 491 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 492 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 493 * @param pAddress: Device address
<> 144:ef7eb2e8f9f7 494 * @param pData : pointer to the data to write
<> 144:ef7eb2e8f9f7 495 * @retval HAL status
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Process Locked */
<> 144:ef7eb2e8f9f7 502 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 505 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 511 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 529 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Send program data command */
<> 144:ef7eb2e8f9f7 532 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 533 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 534 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Write the data */
<> 144:ef7eb2e8f9f7 537 NOR_WRITE(pAddress, *pData);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 540 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Process unlocked */
<> 144:ef7eb2e8f9f7 543 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 return HAL_OK;
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /**
<> 144:ef7eb2e8f9f7 549 * @brief Reads a block of data from the FSMC NOR memory.
<> 144:ef7eb2e8f9f7 550 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 551 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 552 * @param uwAddress: NOR memory internal address to read from.
<> 144:ef7eb2e8f9f7 553 * @param pData: pointer to the buffer that receives the data read from the
<> 144:ef7eb2e8f9f7 554 * NOR memory.
<> 144:ef7eb2e8f9f7 555 * @param uwBufferSize : number of Half word to read.
<> 144:ef7eb2e8f9f7 556 * @retval HAL status
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Process Locked */
<> 144:ef7eb2e8f9f7 563 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 566 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 572 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 590 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Send read data command */
<> 144:ef7eb2e8f9f7 593 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 594 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 595 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Read buffer */
<> 144:ef7eb2e8f9f7 598 while( uwBufferSize > 0)
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 *pData++ = *(__IO uint16_t *)uwAddress;
<> 144:ef7eb2e8f9f7 601 uwAddress += 2;
<> 144:ef7eb2e8f9f7 602 uwBufferSize--;
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 606 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Process unlocked */
<> 144:ef7eb2e8f9f7 609 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 return HAL_OK;
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
<> 144:ef7eb2e8f9f7 616 * must be used only with S29GL128P NOR memory.
<> 144:ef7eb2e8f9f7 617 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 618 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 619 * @param uwAddress: NOR memory internal address from which the data
<> 144:ef7eb2e8f9f7 620 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
<> 144:ef7eb2e8f9f7 621 * 64 bytes boundary for example).
<> 144:ef7eb2e8f9f7 622 * @param pData: pointer to source data buffer.
<> 144:ef7eb2e8f9f7 623 * @param uwBufferSize: number of Half words to write.
<> 144:ef7eb2e8f9f7 624 * @note The maximum buffer size allowed is NOR memory dependent
<> 144:ef7eb2e8f9f7 625 * (can be 64 Bytes max for example).
<> 144:ef7eb2e8f9f7 626 * @retval HAL status
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 uint16_t * p_currentaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 631 uint16_t * p_endaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 632 uint32_t lastloadedaddress = 0, deviceaddress = 0;
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Process Locked */
<> 144:ef7eb2e8f9f7 635 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 638 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 639 {
<> 144:ef7eb2e8f9f7 640 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 644 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 662 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Initialize variables */
<> 144:ef7eb2e8f9f7 665 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
<> 144:ef7eb2e8f9f7 666 p_endaddress = p_currentaddress + (uwBufferSize-1);
<> 144:ef7eb2e8f9f7 667 lastloadedaddress = (uint32_t)(uwAddress);
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Issue unlock command sequence */
<> 144:ef7eb2e8f9f7 670 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 671 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Write Buffer Load Command */
<> 144:ef7eb2e8f9f7 674 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
<> 144:ef7eb2e8f9f7 675 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Load Data into NOR Buffer */
<> 144:ef7eb2e8f9f7 678 while(p_currentaddress <= p_endaddress)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Store last loaded address & data value (for polling) */
<> 144:ef7eb2e8f9f7 681 lastloadedaddress = (uint32_t)p_currentaddress;
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 NOR_WRITE(p_currentaddress, *pData++);
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 p_currentaddress++;
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 691 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Process unlocked */
<> 144:ef7eb2e8f9f7 694 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 return HAL_OK;
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief Erase the specified block of the NOR memory
<> 144:ef7eb2e8f9f7 702 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 703 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 704 * @param BlockAddress : Block to erase address
<> 144:ef7eb2e8f9f7 705 * @param Address: Device address
<> 144:ef7eb2e8f9f7 706 * @retval HAL status
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Process Locked */
<> 144:ef7eb2e8f9f7 713 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 716 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 722 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 740 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Send block erase command sequence */
<> 144:ef7eb2e8f9f7 743 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 744 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 745 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 746 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 747 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 748 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 751 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Process unlocked */
<> 144:ef7eb2e8f9f7 754 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 return HAL_OK;
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /**
<> 144:ef7eb2e8f9f7 761 * @brief Erase the entire NOR chip.
<> 144:ef7eb2e8f9f7 762 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 763 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 764 * @param Address : Device address
<> 144:ef7eb2e8f9f7 765 * @retval HAL status
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Process Locked */
<> 144:ef7eb2e8f9f7 772 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 775 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 781 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 784 }
<> 144:ef7eb2e8f9f7 785 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 799 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Send NOR chip erase command sequence */
<> 144:ef7eb2e8f9f7 802 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 803 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 804 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 805 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 806 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 807 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 810 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Process unlocked */
<> 144:ef7eb2e8f9f7 813 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 return HAL_OK;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @brief Read NOR flash CFI IDs
<> 144:ef7eb2e8f9f7 820 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 821 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 822 * @param pNOR_CFI : pointer to NOR CFI IDs structure
<> 144:ef7eb2e8f9f7 823 * @retval HAL status
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Process Locked */
<> 144:ef7eb2e8f9f7 830 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 833 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 839 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 857 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /* Send read CFI query command */
<> 144:ef7eb2e8f9f7 860 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* read the NOR CFI information */
<> 144:ef7eb2e8f9f7 863 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
<> 144:ef7eb2e8f9f7 864 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
<> 144:ef7eb2e8f9f7 865 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
<> 144:ef7eb2e8f9f7 866 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 869 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Process unlocked */
<> 144:ef7eb2e8f9f7 872 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 return HAL_OK;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @}
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /** @defgroup NOR_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 882 * @brief management functions
<> 144:ef7eb2e8f9f7 883 *
<> 144:ef7eb2e8f9f7 884 @verbatim
<> 144:ef7eb2e8f9f7 885 ==============================================================================
<> 144:ef7eb2e8f9f7 886 ##### NOR Control functions #####
<> 144:ef7eb2e8f9f7 887 ==============================================================================
<> 144:ef7eb2e8f9f7 888 [..]
<> 144:ef7eb2e8f9f7 889 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 890 the NOR interface.
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 @endverbatim
<> 144:ef7eb2e8f9f7 893 * @{
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @brief Enables dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 898 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 899 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 900 * @retval HAL status
<> 144:ef7eb2e8f9f7 901 */
<> 144:ef7eb2e8f9f7 902 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 /* Process Locked */
<> 144:ef7eb2e8f9f7 905 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Enable write operation */
<> 144:ef7eb2e8f9f7 908 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 911 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Process unlocked */
<> 144:ef7eb2e8f9f7 914 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 return HAL_OK;
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /**
<> 144:ef7eb2e8f9f7 920 * @brief Disables dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 921 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 922 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 923 * @retval HAL status
<> 144:ef7eb2e8f9f7 924 */
<> 144:ef7eb2e8f9f7 925 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 /* Process Locked */
<> 144:ef7eb2e8f9f7 928 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 931 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /* Disable write operation */
<> 144:ef7eb2e8f9f7 934 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 937 hnor->State = HAL_NOR_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Process unlocked */
<> 144:ef7eb2e8f9f7 940 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 return HAL_OK;
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /**
<> 144:ef7eb2e8f9f7 946 * @}
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /** @defgroup NOR_Exported_Functions_Group4 State functions
<> 144:ef7eb2e8f9f7 950 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 951 *
<> 144:ef7eb2e8f9f7 952 @verbatim
<> 144:ef7eb2e8f9f7 953 ==============================================================================
<> 144:ef7eb2e8f9f7 954 ##### NOR State functions #####
<> 144:ef7eb2e8f9f7 955 ==============================================================================
<> 144:ef7eb2e8f9f7 956 [..]
<> 144:ef7eb2e8f9f7 957 This subsection permits to get in run-time the status of the NOR controller
<> 144:ef7eb2e8f9f7 958 and the data flow.
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 @endverbatim
<> 144:ef7eb2e8f9f7 961 * @{
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /**
<> 144:ef7eb2e8f9f7 965 * @brief return the NOR controller state
<> 144:ef7eb2e8f9f7 966 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 967 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 968 * @retval NOR controller state
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 return hnor->State;
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /**
<> 144:ef7eb2e8f9f7 976 * @brief Returns the NOR operation status.
<> 144:ef7eb2e8f9f7 977 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 978 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 979 * @param Address: Device address
<> 144:ef7eb2e8f9f7 980 * @param Timeout: NOR progamming Timeout
<> 144:ef7eb2e8f9f7 981 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
<> 144:ef7eb2e8f9f7 982 * or HAL_NOR_STATUS_TIMEOUT
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 987 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
<> 144:ef7eb2e8f9f7 988 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
<> 144:ef7eb2e8f9f7 991 HAL_NOR_MspWait(hnor, Timeout);
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /* Get tick */
<> 144:ef7eb2e8f9f7 994 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 995 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 998 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1001 {
<> 144:ef7eb2e8f9f7 1002 status = HAL_NOR_STATUS_TIMEOUT;
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* Read NOR status register (DQ6 and DQ5) */
<> 144:ef7eb2e8f9f7 1007 tmp_sr1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1008 tmp_sr2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 144:ef7eb2e8f9f7 1011 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1012 {
<> 144:ef7eb2e8f9f7 1013 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 tmp_sr1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1022 tmp_sr2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 144:ef7eb2e8f9f7 1025 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1028 }
<> 144:ef7eb2e8f9f7 1029 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1030 {
<> 144:ef7eb2e8f9f7 1031 return HAL_NOR_STATUS_ERROR;
<> 144:ef7eb2e8f9f7 1032 }
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /* Return the operation status */
<> 144:ef7eb2e8f9f7 1036 return status;
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /**
<> 144:ef7eb2e8f9f7 1040 * @}
<> 144:ef7eb2e8f9f7 1041 */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**
<> 144:ef7eb2e8f9f7 1044 * @}
<> 144:ef7eb2e8f9f7 1045 */
<> 144:ef7eb2e8f9f7 1046 /**
<> 144:ef7eb2e8f9f7 1047 * @}
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
<> 144:ef7eb2e8f9f7 1050 #endif /* HAL_NOR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /**
<> 144:ef7eb2e8f9f7 1053 * @}
<> 144:ef7eb2e8f9f7 1054 */
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/