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GR-PEACH_video/DisplayBase.cpp@167:2ee3e82cb6f5, 2017-07-21 (annotated)

Committer:
thedo
Date:
Fri Jul 21 01:26:54 2017 +0000
Revision:
167:2ee3e82cb6f5
Parent:
166:240bc5a0f42a 
gr-peach-opencv-project-sd-card

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thedo 166:240bc5a0f42a 1 /*******************************************************************************
thedo 166:240bc5a0f42a 2 * DISCLAIMER
thedo 166:240bc5a0f42a 3 * This software is supplied by Renesas Electronics Corporation and is only
thedo 166:240bc5a0f42a 4 * intended for use with Renesas products. No other uses are authorized. This
thedo 166:240bc5a0f42a 5 * software is owned by Renesas Electronics Corporation and is protected under
thedo 166:240bc5a0f42a 6 * all applicable laws, including copyright laws.
thedo 166:240bc5a0f42a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
thedo 166:240bc5a0f42a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
thedo 166:240bc5a0f42a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
thedo 166:240bc5a0f42a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
thedo 166:240bc5a0f42a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
thedo 166:240bc5a0f42a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
thedo 166:240bc5a0f42a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
thedo 166:240bc5a0f42a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
thedo 166:240bc5a0f42a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
thedo 166:240bc5a0f42a 16 * Renesas reserves the right, without notice, to make changes to this software
thedo 166:240bc5a0f42a 17 * and to discontinue the availability of this software. By using this software,
thedo 166:240bc5a0f42a 18 * you agree to the additional terms and conditions found by accessing the
thedo 166:240bc5a0f42a 19 * following link:
thedo 166:240bc5a0f42a 20 * http://www.renesas.com/disclaimer
thedo 166:240bc5a0f42a 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
thedo 166:240bc5a0f42a 22 *******************************************************************************/
thedo 166:240bc5a0f42a 23 #include <string.h>
thedo 166:240bc5a0f42a 24 #include "DisplayBace.h"
thedo 166:240bc5a0f42a 25 #include "gr_peach_vdc5.h"
thedo 166:240bc5a0f42a 26
thedo 166:240bc5a0f42a 27 /**************************************************************************//**
thedo 166:240bc5a0f42a 28 * @brief Constructor of the DisplayBase class
thedo 166:240bc5a0f42a 29 * @param[in] None
thedo 166:240bc5a0f42a 30 * @retval None
thedo 166:240bc5a0f42a 31 ******************************************************************************/
thedo 166:240bc5a0f42a 32 DisplayBase::DisplayBase( void )
thedo 166:240bc5a0f42a 33 {
thedo 166:240bc5a0f42a 34 /* Lcd setting (default) */
thedo 166:240bc5a0f42a 35 _lcd_config.lcd_type = LCD_TYPE_PARALLEL_RGB; /* LVDS or Pararel RGB */
thedo 166:240bc5a0f42a 36 _lcd_config.intputClock = 66.67f; /* P1 clk [MHz] ex. 66.67 */
thedo 166:240bc5a0f42a 37 _lcd_config.outputClock = 40.00f; /* LCD clk [MHz] ex. 33.33 */
thedo 166:240bc5a0f42a 38
thedo 166:240bc5a0f42a 39 _lcd_config.lcd_outformat = LCD_OUTFORMAT_RGB888; /* Output format select */
thedo 166:240bc5a0f42a 40 _lcd_config.lcd_edge = EDGE_FALLING; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
thedo 166:240bc5a0f42a 41
thedo 166:240bc5a0f42a 42 _lcd_config.h_toatal_period = (800u + 40u + 128u+ 88u); /* Free-running Hsync period */
thedo 166:240bc5a0f42a 43 _lcd_config.v_toatal_period = (600u + 1u + 4u + 23u); /* Free-running Vsync period */
thedo 166:240bc5a0f42a 44 _lcd_config.h_disp_widht = 800u; /* LCD display area size, horizontal width */
thedo 166:240bc5a0f42a 45 _lcd_config.v_disp_widht = 600u; /* LCD display area size, vertical width */
thedo 166:240bc5a0f42a 46 _lcd_config.h_back_porch = (128u+ 88u); /* LCD display horizontal back porch period */
thedo 166:240bc5a0f42a 47 _lcd_config.v_back_porch = (4u + 23u); /* LCD display vertical back porch period */
thedo 166:240bc5a0f42a 48
thedo 166:240bc5a0f42a 49 _lcd_config.h_sync_port = LCD_TCON_PIN_0; /* TCONn or Not use(-1) */
thedo 166:240bc5a0f42a 50 _lcd_config.h_sync_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
thedo 166:240bc5a0f42a 51 _lcd_config.h_sync_width = 128u; /* Hsync width */
thedo 166:240bc5a0f42a 52
thedo 166:240bc5a0f42a 53 _lcd_config.v_sync_port = LCD_TCON_PIN_1; /* TCONn or Not use(-1) */
thedo 166:240bc5a0f42a 54 _lcd_config.v_sync_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
thedo 166:240bc5a0f42a 55 _lcd_config.v_sync_width = 4u; /* Vsync width */
thedo 166:240bc5a0f42a 56
thedo 166:240bc5a0f42a 57 _lcd_config.de_port = LCD_TCON_PIN_NON; /* TCONn or Not use(-1) */
thedo 166:240bc5a0f42a 58 _lcd_config.de_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
thedo 166:240bc5a0f42a 59
thedo 166:240bc5a0f42a 60 /* Digital video input setting (default) */
thedo 166:240bc5a0f42a 61 _video_input_sel = INPUT_SEL_VDEC; /* Video decoder output signals */
thedo 166:240bc5a0f42a 62 _video_ext_in_config.inp_format = VIDEO_EXTIN_FORMAT_BT601;
thedo 166:240bc5a0f42a 63 _video_ext_in_config.inp_pxd_edge = EDGE_RISING; /* Clock edge select for capturing data */
thedo 166:240bc5a0f42a 64 _video_ext_in_config.inp_vs_edge = EDGE_RISING; /* Clock edge select for capturing Vsync signals */
thedo 166:240bc5a0f42a 65 _video_ext_in_config.inp_hs_edge = EDGE_RISING; /* Clock edge select for capturing Hsync signals */
thedo 166:240bc5a0f42a 66 _video_ext_in_config.inp_endian_on = OFF; /* External input bit endian change on/off */
thedo 166:240bc5a0f42a 67 _video_ext_in_config.inp_swap_on = OFF; /* External input B/R signal swap on/off */
thedo 166:240bc5a0f42a 68 _video_ext_in_config.inp_vs_inv = SIG_POL_NOT_INVERTED; /* External input DV_VSYNC inversion control */
thedo 166:240bc5a0f42a 69 _video_ext_in_config.inp_hs_inv = SIG_POL_INVERTED; /* External input DV_HSYNC inversion control */
thedo 166:240bc5a0f42a 70 _video_ext_in_config.inp_f525_625 = EXTIN_LINE_525; /* Number of lines for BT.656 external input */
thedo 166:240bc5a0f42a 71 _video_ext_in_config.inp_h_pos = EXTIN_H_POS_CRYCBY; /* Y/Cb/Y/Cr data string start timing to Hsync reference */
thedo 166:240bc5a0f42a 72 _video_ext_in_config.cap_vs_pos = 6u; /* Capture start position from Vsync */
thedo 166:240bc5a0f42a 73 _video_ext_in_config.cap_hs_pos = 302u; /* Capture start position form Hsync */
thedo 166:240bc5a0f42a 74 _video_ext_in_config.cap_width = 640u; /* Capture width */
thedo 166:240bc5a0f42a 75 _video_ext_in_config.cap_height = 468u; /* Capture height should be a multiple of 4 */
thedo 166:240bc5a0f42a 76 } /* End of constructor method () */
thedo 166:240bc5a0f42a 77
thedo 166:240bc5a0f42a 78 /**************************************************************************//**
thedo 166:240bc5a0f42a 79 * @brief Graphics initialization processing
thedo 166:240bc5a0f42a 80 * @param[in] lcd_config : LCD configuration
thedo 166:240bc5a0f42a 81 * @retval error code
thedo 166:240bc5a0f42a 82 ******************************************************************************/
thedo 166:240bc5a0f42a 83 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 84 DisplayBase::Graphics_init( lcd_config_t * lcd_config )
thedo 166:240bc5a0f42a 85 {
thedo 166:240bc5a0f42a 86 if( lcd_config != NULL ) {
thedo 166:240bc5a0f42a 87 _lcd_config.lcd_type = lcd_config->lcd_type; /* LVDS or Pararel RGB */
thedo 166:240bc5a0f42a 88 _lcd_config.intputClock = lcd_config->intputClock; /* P1 clk [MHz] ex. 66.67 */
thedo 166:240bc5a0f42a 89 _lcd_config.outputClock = lcd_config->outputClock; /* LCD clk [MHz] ex. 33.33 */
thedo 166:240bc5a0f42a 90
thedo 166:240bc5a0f42a 91 _lcd_config.lcd_outformat = lcd_config->lcd_outformat; /* Output format select */
thedo 166:240bc5a0f42a 92 _lcd_config.lcd_edge = lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
thedo 166:240bc5a0f42a 93
thedo 166:240bc5a0f42a 94 _lcd_config.h_toatal_period = lcd_config->h_toatal_period; /* Free-running Hsync period */
thedo 166:240bc5a0f42a 95 _lcd_config.v_toatal_period = lcd_config->v_toatal_period; /* Free-running Vsync period */
thedo 166:240bc5a0f42a 96 _lcd_config.h_disp_widht = lcd_config->h_disp_widht; /* LCD display area size, horizontal width */
thedo 166:240bc5a0f42a 97 _lcd_config.v_disp_widht = lcd_config->v_disp_widht; /* LCD display area size, vertical width */
thedo 166:240bc5a0f42a 98 _lcd_config.h_back_porch = lcd_config->h_back_porch; /* LCD display horizontal back porch period */
thedo 166:240bc5a0f42a 99 _lcd_config.v_back_porch = lcd_config->v_back_porch; /* LCD display vertical back porch period */
thedo 166:240bc5a0f42a 100
thedo 166:240bc5a0f42a 101 _lcd_config.h_sync_port = lcd_config->h_sync_port; /* TCONn or Not use(-1) */
thedo 166:240bc5a0f42a 102 _lcd_config.h_sync_port_polarity = lcd_config->h_sync_port_polarity;/* Polarity inversion control of signal */
thedo 166:240bc5a0f42a 103 _lcd_config.h_sync_width = lcd_config->h_sync_width; /* Hsync width */
thedo 166:240bc5a0f42a 104
thedo 166:240bc5a0f42a 105 _lcd_config.v_sync_port = lcd_config->v_sync_port; /* TCONn or Not use(-1) */
thedo 166:240bc5a0f42a 106 _lcd_config.v_sync_port_polarity = lcd_config->v_sync_port_polarity;/* Polarity inversion control of signal */
thedo 166:240bc5a0f42a 107 _lcd_config.v_sync_width = lcd_config->v_sync_width; /* Vsync width */
thedo 166:240bc5a0f42a 108
thedo 166:240bc5a0f42a 109 _lcd_config.de_port = lcd_config->de_port; /* TCONn or Not use(-1) */
thedo 166:240bc5a0f42a 110 _lcd_config.de_port_polarity = lcd_config->de_port_polarity; /* Polarity inversion control of signal */
thedo 166:240bc5a0f42a 111 }
thedo 166:240bc5a0f42a 112
thedo 166:240bc5a0f42a 113 return (graphics_error_t)DRV_Graphics_Init( (drv_lcd_config_t *)&_lcd_config );
thedo 166:240bc5a0f42a 114 } /* End of method Graphics_init() */
thedo 166:240bc5a0f42a 115
thedo 166:240bc5a0f42a 116 /**************************************************************************//**
thedo 166:240bc5a0f42a 117 * @brief Graphics Video initialization processing
thedo 166:240bc5a0f42a 118 * @param[in] video_input_sel : Input select
thedo 166:240bc5a0f42a 119 * @param[in] video_ext_in_config : Digtal video input configuration
thedo 166:240bc5a0f42a 120 * @retval error code
thedo 166:240bc5a0f42a 121 ******************************************************************************/
thedo 166:240bc5a0f42a 122 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 123 DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config )
thedo 166:240bc5a0f42a 124 {
thedo 166:240bc5a0f42a 125 graphics_error_t error = GRAPHICS_OK;
thedo 166:240bc5a0f42a 126
thedo 166:240bc5a0f42a 127 if( _video_input_sel == INPUT_SEL_VDEC || _video_input_sel == INPUT_SEL_EXT ) {
thedo 166:240bc5a0f42a 128 _video_input_sel = video_input_sel;
thedo 166:240bc5a0f42a 129 } else {
thedo 166:240bc5a0f42a 130 error = GRAPHICS_PARAM_RANGE_ERR;
thedo 166:240bc5a0f42a 131 }
thedo 166:240bc5a0f42a 132
thedo 166:240bc5a0f42a 133 if( error == GRAPHICS_OK ) {
thedo 166:240bc5a0f42a 134 if( video_ext_in_config != NULL ) {
thedo 166:240bc5a0f42a 135 /* Signals supplied via the external input pins */
thedo 166:240bc5a0f42a 136 /* if using Video decoder output signals, not using value. */
thedo 166:240bc5a0f42a 137 _video_ext_in_config.inp_format = video_ext_in_config->inp_format;
thedo 166:240bc5a0f42a 138 _video_ext_in_config.inp_pxd_edge = video_ext_in_config->inp_pxd_edge;
thedo 166:240bc5a0f42a 139 _video_ext_in_config.inp_vs_edge = video_ext_in_config->inp_vs_edge;
thedo 166:240bc5a0f42a 140 _video_ext_in_config.inp_hs_edge = video_ext_in_config->inp_hs_edge;
thedo 166:240bc5a0f42a 141 _video_ext_in_config.inp_endian_on = video_ext_in_config->inp_endian_on;
thedo 166:240bc5a0f42a 142 _video_ext_in_config.inp_swap_on = video_ext_in_config->inp_swap_on;
thedo 166:240bc5a0f42a 143 _video_ext_in_config.inp_vs_inv = video_ext_in_config->inp_vs_inv;
thedo 166:240bc5a0f42a 144 _video_ext_in_config.inp_hs_inv = video_ext_in_config->inp_hs_inv;
thedo 166:240bc5a0f42a 145 _video_ext_in_config.inp_f525_625 = video_ext_in_config->inp_f525_625;
thedo 166:240bc5a0f42a 146 _video_ext_in_config.inp_h_pos = video_ext_in_config->inp_h_pos;
thedo 166:240bc5a0f42a 147 _video_ext_in_config.cap_vs_pos = video_ext_in_config->cap_vs_pos;
thedo 166:240bc5a0f42a 148 _video_ext_in_config.cap_hs_pos = video_ext_in_config->cap_hs_pos;
thedo 166:240bc5a0f42a 149 _video_ext_in_config.cap_width = video_ext_in_config->cap_width;
thedo 166:240bc5a0f42a 150 _video_ext_in_config.cap_height = video_ext_in_config->cap_height;
thedo 166:240bc5a0f42a 151 }
thedo 166:240bc5a0f42a 152 }
thedo 166:240bc5a0f42a 153 return (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
thedo 166:240bc5a0f42a 154 (drv_video_ext_in_config_t *)&_video_ext_in_config );
thedo 166:240bc5a0f42a 155 } /* End of method Graphics_Video_init() */
thedo 166:240bc5a0f42a 156
thedo 166:240bc5a0f42a 157 /**************************************************************************//**
thedo 166:240bc5a0f42a 158 * @brief LCD I/O initialization processing
thedo 166:240bc5a0f42a 159 * @param[in] pin : Pointer of the pin assignment
thedo 166:240bc5a0f42a 160 * @param[in] pin_count : Total number of the pin assignment
thedo 166:240bc5a0f42a 161 * @retval error code
thedo 166:240bc5a0f42a 162 ******************************************************************************/
thedo 166:240bc5a0f42a 163 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 164 DisplayBase::Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count )
thedo 166:240bc5a0f42a 165 {
thedo 166:240bc5a0f42a 166 return (graphics_error_t)DRV_Graphics_Lcd_Port_Init( pin, pin_count );
thedo 166:240bc5a0f42a 167 } /* End of method Graphics_Lcd_Port_Init() */
thedo 166:240bc5a0f42a 168
thedo 166:240bc5a0f42a 169 /**************************************************************************//**
thedo 166:240bc5a0f42a 170 * @brief LVDS I/O port initialization processing
thedo 166:240bc5a0f42a 171 * @param[in] pin : Pointer of the pin assignment
thedo 166:240bc5a0f42a 172 * @param[in] pin_count : Total number of the pin assignment
thedo 166:240bc5a0f42a 173 * @retval error code
thedo 166:240bc5a0f42a 174 ******************************************************************************/
thedo 166:240bc5a0f42a 175 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 176 DisplayBase::Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count )
thedo 166:240bc5a0f42a 177 {
thedo 166:240bc5a0f42a 178 return (graphics_error_t)DRV_Graphics_Lvds_Port_Init( pin, pin_count );
thedo 166:240bc5a0f42a 179 } /* End of method Graphics_Lvds_Port_Init() */
thedo 166:240bc5a0f42a 180
thedo 166:240bc5a0f42a 181 /**************************************************************************//**
thedo 166:240bc5a0f42a 182 * @brief Digital video input I/O port initialization processing
thedo 166:240bc5a0f42a 183 * @param[in] pin : Pointer of the pin assignment
thedo 166:240bc5a0f42a 184 * @param[in] pin_count : Total number of the pin assignment
thedo 166:240bc5a0f42a 185 * @retval error code
thedo 166:240bc5a0f42a 186 ******************************************************************************/
thedo 166:240bc5a0f42a 187 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 188 DisplayBase::Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count )
thedo 166:240bc5a0f42a 189 {
thedo 166:240bc5a0f42a 190 return (graphics_error_t)DRV_Graphics_Dvinput_Port_Init( pin, pin_count );
thedo 166:240bc5a0f42a 191 } /* End of method Graphics_Dvinput_Port_Init() */
thedo 166:240bc5a0f42a 192
thedo 166:240bc5a0f42a 193 /**************************************************************************//**
thedo 166:240bc5a0f42a 194 * @brief IRQ interrupt handler setting
thedo 166:240bc5a0f42a 195 * @param[in] irq : VDC5 interrupt type
thedo 166:240bc5a0f42a 196 * @param[in] num : Interrupt line number
thedo 166:240bc5a0f42a 197 * @param[in] * callback : Interrupt callback function pointer
thedo 166:240bc5a0f42a 198 * @retval error code
thedo 166:240bc5a0f42a 199 ******************************************************************************/
thedo 166:240bc5a0f42a 200 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 201 DisplayBase::Graphics_Irq_Handler_Set( int_type_t irq, unsigned short num, void (* callback)(int_type_t) )
thedo 166:240bc5a0f42a 202 {
thedo 166:240bc5a0f42a 203 return (graphics_error_t)DRV_Graphics_Irq_Handler_Set( (vdc5_int_type_t)irq, num, (void (*)(vdc5_int_type_t))callback );
thedo 166:240bc5a0f42a 204 } /* End of method Graphics_Irq_Handler_Set() */
thedo 166:240bc5a0f42a 205
thedo 166:240bc5a0f42a 206 /**************************************************************************//**
thedo 166:240bc5a0f42a 207 * @brief Graphics surface read start processing
thedo 166:240bc5a0f42a 208 * @param[in] layer_id : Graphics layer ID
thedo 166:240bc5a0f42a 209 * @retval error code
thedo 166:240bc5a0f42a 210 ******************************************************************************/
thedo 166:240bc5a0f42a 211 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 212 DisplayBase::Graphics_Start( graphics_layer_t layer_id )
thedo 166:240bc5a0f42a 213 {
thedo 166:240bc5a0f42a 214 return (graphics_error_t)DRV_Graphics_Start( (drv_graphics_layer_t)layer_id );
thedo 166:240bc5a0f42a 215 } /* End of method Graphics_Start() */
thedo 166:240bc5a0f42a 216
thedo 166:240bc5a0f42a 217 /**************************************************************************//**
thedo 166:240bc5a0f42a 218 * @brief Graphics surface read stop processing
thedo 166:240bc5a0f42a 219 * @param[in] layer_id : Graphics layer ID
thedo 166:240bc5a0f42a 220 * @retval error code
thedo 166:240bc5a0f42a 221 ******************************************************************************/
thedo 166:240bc5a0f42a 222 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 223 DisplayBase::Graphics_Stop( graphics_layer_t layer_id )
thedo 166:240bc5a0f42a 224 {
thedo 166:240bc5a0f42a 225 return (graphics_error_t)DRV_Graphics_Stop( (drv_graphics_layer_t)layer_id );
thedo 166:240bc5a0f42a 226 } /* End of method Graphics_Stop() */
thedo 166:240bc5a0f42a 227
thedo 166:240bc5a0f42a 228 /**************************************************************************//**
thedo 166:240bc5a0f42a 229 * @brief Video surface write start processing
thedo 166:240bc5a0f42a 230 * @param[in] video_input_channel : Video input channel
thedo 166:240bc5a0f42a 231 * @retval error code
thedo 166:240bc5a0f42a 232 ******************************************************************************/
thedo 166:240bc5a0f42a 233 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 234 DisplayBase::Video_Start( video_input_channel_t video_input_channel )
thedo 166:240bc5a0f42a 235 {
thedo 166:240bc5a0f42a 236 graphics_error_t error = GRAPHICS_OK;
thedo 166:240bc5a0f42a 237
thedo 166:240bc5a0f42a 238 /* Digital video inputs : supporting video_input_channel 0 only. */
thedo 166:240bc5a0f42a 239 if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
thedo 166:240bc5a0f42a 240 error = GRAPHICS_PARAM_RANGE_ERR;
thedo 166:240bc5a0f42a 241 }
thedo 166:240bc5a0f42a 242
thedo 166:240bc5a0f42a 243 if( error == GRAPHICS_OK ) {
thedo 166:240bc5a0f42a 244 error = (graphics_error_t)DRV_Video_Start( (drv_video_input_channel_t)video_input_channel );
thedo 166:240bc5a0f42a 245 }
thedo 166:240bc5a0f42a 246 return error;
thedo 166:240bc5a0f42a 247 } /* End of method Video_Start() */
thedo 166:240bc5a0f42a 248
thedo 166:240bc5a0f42a 249 /**************************************************************************//**
thedo 166:240bc5a0f42a 250 * @brief Video surface write stop processing
thedo 166:240bc5a0f42a 251 * @param[in] video_input_channel : Video input channel
thedo 166:240bc5a0f42a 252 * @retval error code
thedo 166:240bc5a0f42a 253 ******************************************************************************/
thedo 166:240bc5a0f42a 254 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 255 DisplayBase::Video_Stop( video_input_channel_t video_input_channel )
thedo 166:240bc5a0f42a 256 {
thedo 166:240bc5a0f42a 257 graphics_error_t error = GRAPHICS_OK;
thedo 166:240bc5a0f42a 258
thedo 166:240bc5a0f42a 259 /* Digital video inputs : supporting video_input_channel 0 only. */
thedo 166:240bc5a0f42a 260 if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
thedo 166:240bc5a0f42a 261 error = GRAPHICS_PARAM_RANGE_ERR;
thedo 166:240bc5a0f42a 262 }
thedo 166:240bc5a0f42a 263
thedo 166:240bc5a0f42a 264 if( error == GRAPHICS_OK ) {
thedo 166:240bc5a0f42a 265 error = (graphics_error_t)DRV_Video_Stop(
thedo 166:240bc5a0f42a 266 (drv_video_input_channel_t)video_input_channel );
thedo 166:240bc5a0f42a 267 }
thedo 166:240bc5a0f42a 268 return error;
thedo 166:240bc5a0f42a 269 } /* End of method Video_Stop() */
thedo 166:240bc5a0f42a 270
thedo 166:240bc5a0f42a 271 /**************************************************************************//**
thedo 166:240bc5a0f42a 272 * @brief Graphics surface read process setting
thedo 166:240bc5a0f42a 273 *
thedo 166:240bc5a0f42a 274 * Description:<br>
thedo 166:240bc5a0f42a 275 * This function supports the following 4 image format.
thedo 166:240bc5a0f42a 276 * YCbCr422, RGB565, RGB888, ARGB8888
thedo 166:240bc5a0f42a 277 * @param[in] layer_id : Graphics layer ID
thedo 166:240bc5a0f42a 278 * @param[in] framebuff : Base address of the frame buffer
thedo 166:240bc5a0f42a 279 * @param[in] fb_stride : Line offset address of the frame buffer
thedo 166:240bc5a0f42a 280 * @param[in] gr_format : Format of the frame buffer read signal
thedo 166:240bc5a0f42a 281 * @param[in] wr_rd_swa : frame buffer swap setting
thedo 166:240bc5a0f42a 282 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
thedo 166:240bc5a0f42a 283 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
thedo 166:240bc5a0f42a 284 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
thedo 166:240bc5a0f42a 285 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
thedo 166:240bc5a0f42a 286 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
thedo 166:240bc5a0f42a 287 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
thedo 166:240bc5a0f42a 288 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
thedo 166:240bc5a0f42a 289 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
thedo 166:240bc5a0f42a 290 * @param[in] gr_rect : Graphics display area
thedo 166:240bc5a0f42a 291 * @retval Error code
thedo 166:240bc5a0f42a 292 ******************************************************************************/
thedo 166:240bc5a0f42a 293 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 294 DisplayBase::Graphics_Read_Setting(
thedo 166:240bc5a0f42a 295 graphics_layer_t layer_id,
thedo 166:240bc5a0f42a 296 void * framebuff,
thedo 166:240bc5a0f42a 297 unsigned int fb_stride,
thedo 166:240bc5a0f42a 298 graphics_format_t gr_format,
thedo 166:240bc5a0f42a 299 wr_rd_swa_t wr_rd_swa,
thedo 166:240bc5a0f42a 300 rect_t * gr_rect )
thedo 166:240bc5a0f42a 301 {
thedo 166:240bc5a0f42a 302 rect_t rect;
thedo 166:240bc5a0f42a 303
thedo 166:240bc5a0f42a 304 rect.hs = gr_rect->hs + _lcd_config.h_back_porch;
thedo 166:240bc5a0f42a 305 rect.vs = gr_rect->vs + _lcd_config.v_back_porch;
thedo 166:240bc5a0f42a 306 rect.hw = gr_rect->hw;
thedo 166:240bc5a0f42a 307 rect.vw = gr_rect->vw;
thedo 166:240bc5a0f42a 308
thedo 166:240bc5a0f42a 309 return (graphics_error_t)DRV_Graphics_Read_Setting(
thedo 166:240bc5a0f42a 310 (drv_graphics_layer_t)layer_id,
thedo 166:240bc5a0f42a 311 framebuff,
thedo 166:240bc5a0f42a 312 fb_stride,
thedo 166:240bc5a0f42a 313 (drv_graphics_format_t)gr_format,
thedo 166:240bc5a0f42a 314 (drv_wr_rd_swa_t)wr_rd_swa,
thedo 166:240bc5a0f42a 315 (drv_rect_t *)&rect );
thedo 166:240bc5a0f42a 316 } /* End of method Graphics_Read_Setting() */
thedo 166:240bc5a0f42a 317
thedo 166:240bc5a0f42a 318 /**************************************************************************//**
thedo 166:240bc5a0f42a 319 * @brief Graphics surface read process changing
thedo 166:240bc5a0f42a 320 *
thedo 166:240bc5a0f42a 321 * Description:<br>
thedo 166:240bc5a0f42a 322 * This function is used to swap buffers.
thedo 166:240bc5a0f42a 323 *
thedo 166:240bc5a0f42a 324 * @param[in] layer_id : Graphics layer ID
thedo 166:240bc5a0f42a 325 * @param[in] framebuff : Base address of the frame buffer
thedo 166:240bc5a0f42a 326 * @retval Error code
thedo 166:240bc5a0f42a 327 ******************************************************************************/
thedo 166:240bc5a0f42a 328 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 329 DisplayBase::Graphics_Read_Change ( graphics_layer_t layer_id, void * framebuff)
thedo 166:240bc5a0f42a 330 {
thedo 166:240bc5a0f42a 331 return (graphics_error_t)DRV_Graphics_Read_Change(
thedo 166:240bc5a0f42a 332 (drv_graphics_layer_t)layer_id, framebuff );
thedo 166:240bc5a0f42a 333 } /* End of method Graphics_Read_Change() */
thedo 166:240bc5a0f42a 334
thedo 166:240bc5a0f42a 335 /**************************************************************************//**
thedo 166:240bc5a0f42a 336 * @brief Video surface write process setting
thedo 166:240bc5a0f42a 337 * This function set the video write process. Input form is weave
thedo 166:240bc5a0f42a 338 * (progressive) mode fixed.
thedo 166:240bc5a0f42a 339 * This function supports the following 3 image format.
thedo 166:240bc5a0f42a 340 * YCbCr422, RGB565, RGB888
thedo 166:240bc5a0f42a 341 * @param[in] video_input_ch : Video input channel
thedo 166:240bc5a0f42a 342 * @param[in] col_sys : Analog video signal color system
thedo 166:240bc5a0f42a 343 * @param[in] adc_vinsel : Video input pin
thedo 166:240bc5a0f42a 344 * @param[in] framebuff : Base address of the frame buffer
thedo 166:240bc5a0f42a 345 * @param[in] fb_stride [byte] : Line offset address of the frame buffer
thedo 166:240bc5a0f42a 346 * @param[in] video_format : Frame buffer video-signal writing format
thedo 166:240bc5a0f42a 347 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
thedo 166:240bc5a0f42a 348 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
thedo 166:240bc5a0f42a 349 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
thedo 166:240bc5a0f42a 350 * @param[in] wr_rd_swa : frame buffer swap setting
thedo 166:240bc5a0f42a 351 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
thedo 166:240bc5a0f42a 352 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
thedo 166:240bc5a0f42a 353 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
thedo 166:240bc5a0f42a 354 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
thedo 166:240bc5a0f42a 355 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
thedo 166:240bc5a0f42a 356 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
thedo 166:240bc5a0f42a 357 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
thedo 166:240bc5a0f42a 358 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
thedo 166:240bc5a0f42a 359 * @param[in] video_write_size_vw [px]: output v width
thedo 166:240bc5a0f42a 360 * @param[in] video_write_size_hw [px]: output h width
thedo 166:240bc5a0f42a 361 * @param[in] video_adc_vinsel : Input pin control
thedo 166:240bc5a0f42a 362 * @retval Error code
thedo 166:240bc5a0f42a 363 ******************************************************************************/
thedo 166:240bc5a0f42a 364 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 365 DisplayBase::Video_Write_Setting(
thedo 166:240bc5a0f42a 366 video_input_channel_t video_input_channel,
thedo 166:240bc5a0f42a 367 graphics_video_col_sys_t col_sys,
thedo 166:240bc5a0f42a 368 void * framebuff,
thedo 166:240bc5a0f42a 369 unsigned int fb_stride,
thedo 166:240bc5a0f42a 370 video_format_t video_format,
thedo 166:240bc5a0f42a 371 wr_rd_swa_t wr_rd_swa,
thedo 166:240bc5a0f42a 372 unsigned short write_buff_vw,
thedo 166:240bc5a0f42a 373 unsigned short write_buff_hw,
thedo 166:240bc5a0f42a 374 video_adc_vinsel_t video_adc_vinsel )
thedo 166:240bc5a0f42a 375
thedo 166:240bc5a0f42a 376 {
thedo 166:240bc5a0f42a 377 graphics_error_t error = GRAPHICS_OK;
thedo 166:240bc5a0f42a 378
thedo 166:240bc5a0f42a 379 if( _video_input_sel == INPUT_SEL_VDEC ) {
thedo 166:240bc5a0f42a 380 if( col_sys == COL_SYS_NTSC_358 || col_sys == COL_SYS_NTSC_443 || col_sys == COL_SYS_NTSC_443_60 ) {
thedo 166:240bc5a0f42a 381 if( (write_buff_vw / 2u) > 240u ) {
thedo 166:240bc5a0f42a 382 error = GRAPHICS_VIDEO_NTSC_SIZE_ERR;
thedo 166:240bc5a0f42a 383 }
thedo 166:240bc5a0f42a 384 } else {
thedo 166:240bc5a0f42a 385 if( (write_buff_vw / 2u) > 280u ) {
thedo 166:240bc5a0f42a 386 error = GRAPHICS_VIDEO_PAL_SIZE_ERR;
thedo 166:240bc5a0f42a 387 }
thedo 166:240bc5a0f42a 388 }
thedo 166:240bc5a0f42a 389
thedo 166:240bc5a0f42a 390 if( write_buff_hw > 800u ) {
thedo 166:240bc5a0f42a 391 error = GRAPHICS_PARAM_RANGE_ERR;
thedo 166:240bc5a0f42a 392 }
thedo 166:240bc5a0f42a 393 if( error == GRAPHICS_OK ) {
thedo 166:240bc5a0f42a 394 error = (graphics_error_t)DRV_Video_Write_Setting(
thedo 166:240bc5a0f42a 395 (drv_video_input_channel_t)video_input_channel,
thedo 166:240bc5a0f42a 396 (drv_graphics_video_col_sys_t)col_sys,
thedo 166:240bc5a0f42a 397 framebuff,
thedo 166:240bc5a0f42a 398 fb_stride,
thedo 166:240bc5a0f42a 399 (drv_video_format_t)video_format,
thedo 166:240bc5a0f42a 400 (drv_wr_rd_swa_t)wr_rd_swa,
thedo 166:240bc5a0f42a 401 write_buff_vw,
thedo 166:240bc5a0f42a 402 write_buff_hw,
thedo 166:240bc5a0f42a 403 (drv_video_adc_vinsel_t)video_adc_vinsel);
thedo 166:240bc5a0f42a 404 }
thedo 166:240bc5a0f42a 405 } else if( _video_input_sel == INPUT_SEL_EXT ) {
thedo 166:240bc5a0f42a 406 rect_t cap_area;
thedo 166:240bc5a0f42a 407
thedo 166:240bc5a0f42a 408 cap_area.hs = _video_ext_in_config.cap_hs_pos * 2;
thedo 166:240bc5a0f42a 409 cap_area.hw = _video_ext_in_config.cap_width * 2;
thedo 166:240bc5a0f42a 410 cap_area.vs = _video_ext_in_config.cap_vs_pos;
thedo 166:240bc5a0f42a 411 cap_area.vw = _video_ext_in_config.cap_height;
thedo 166:240bc5a0f42a 412
thedo 166:240bc5a0f42a 413 error = (graphics_error_t) DRV_Video_Write_Setting_Digital(
thedo 166:240bc5a0f42a 414 framebuff,
thedo 166:240bc5a0f42a 415 fb_stride,
thedo 166:240bc5a0f42a 416 (drv_video_format_t)video_format,
thedo 166:240bc5a0f42a 417 (drv_wr_rd_swa_t)wr_rd_swa,
thedo 166:240bc5a0f42a 418 write_buff_vw,
thedo 166:240bc5a0f42a 419 write_buff_hw,
thedo 166:240bc5a0f42a 420 (drv_rect_t *)&cap_area );
thedo 166:240bc5a0f42a 421 } else {
thedo 166:240bc5a0f42a 422 error = GRAPHICS_PARAM_RANGE_ERR;
thedo 166:240bc5a0f42a 423 }
thedo 166:240bc5a0f42a 424 return error;
thedo 166:240bc5a0f42a 425 } /* End of method Video_Write_Setting() */
thedo 166:240bc5a0f42a 426
thedo 166:240bc5a0f42a 427 /**************************************************************************//**
thedo 166:240bc5a0f42a 428 * @brief Graphics surface write process changing
thedo 166:240bc5a0f42a 429 * This function is used to swap buffers of the weave write processing.
thedo 166:240bc5a0f42a 430 * @param[in] video_input_ch : Video input channle
thedo 166:240bc5a0f42a 431 * @param[in] framebuff : Base address of the frame buffer
thedo 166:240bc5a0f42a 432 * @param[in] fb_stride : Line offset address of the frame buffer
thedo 166:240bc5a0f42a 433 * @retval Error code
thedo 166:240bc5a0f42a 434 ******************************************************************************/
thedo 166:240bc5a0f42a 435 DisplayBase::graphics_error_t
thedo 166:240bc5a0f42a 436 DisplayBase::Video_Write_Change (
thedo 166:240bc5a0f42a 437 video_input_channel_t video_input_channel, void * framebuff, uint32_t fb_stride )
thedo 166:240bc5a0f42a 438 {
thedo 166:240bc5a0f42a 439 return (graphics_error_t)DRV_Video_Write_Change(
thedo 166:240bc5a0f42a 440 (drv_video_input_channel_t)video_input_channel, framebuff, fb_stride );
thedo 166:240bc5a0f42a 441 } /* End of method Video_Write_Change() */
thedo 166:240bc5a0f42a 442
thedo 166:240bc5a0f42a 443 /* End of file */