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Dependencies:   BufferedSerial FatFileSystemCpp mbed

USBHostLite/usbhost_lpc17xx.cpp@9:7214e3c3e5f8, 2021-02-18 (annotated)

Committer:
AndyA
Date:
Thu Feb 18 18:15:48 2021 +0000
Revision:
9:7214e3c3e5f8
Child:
15:830fc953edd9
massive ripup and redesign; currently has file system build errors

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AndyA 9:7214e3c3e5f8 1 /*
AndyA 9:7214e3c3e5f8 2 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 3 * NXP USB Host Stack
AndyA 9:7214e3c3e5f8 4 *
AndyA 9:7214e3c3e5f8 5 * (c) Copyright 2008, NXP SemiConductors
AndyA 9:7214e3c3e5f8 6 * (c) Copyright 2008, OnChip Technologies LLC
AndyA 9:7214e3c3e5f8 7 * All Rights Reserved
AndyA 9:7214e3c3e5f8 8 *
AndyA 9:7214e3c3e5f8 9 * www.nxp.com
AndyA 9:7214e3c3e5f8 10 * www.onchiptech.com
AndyA 9:7214e3c3e5f8 11 *
AndyA 9:7214e3c3e5f8 12 * File : usbhost_lpc17xx.c
AndyA 9:7214e3c3e5f8 13 * Programmer(s) : Ravikanth.P
AndyA 9:7214e3c3e5f8 14 * Version :
AndyA 9:7214e3c3e5f8 15 *
AndyA 9:7214e3c3e5f8 16 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 17 */
AndyA 9:7214e3c3e5f8 18
AndyA 9:7214e3c3e5f8 19 /*
AndyA 9:7214e3c3e5f8 20 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 21 * INCLUDE HEADER FILES
AndyA 9:7214e3c3e5f8 22 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 23 */
AndyA 9:7214e3c3e5f8 24
AndyA 9:7214e3c3e5f8 25 #include "usbhost_lpc17xx.h"
AndyA 9:7214e3c3e5f8 26
AndyA 9:7214e3c3e5f8 27 /*
AndyA 9:7214e3c3e5f8 28 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 29 * GLOBAL VARIABLES
AndyA 9:7214e3c3e5f8 30 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 31 */
AndyA 9:7214e3c3e5f8 32 int gUSBConnected;
AndyA 9:7214e3c3e5f8 33
AndyA 9:7214e3c3e5f8 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
AndyA 9:7214e3c3e5f8 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
AndyA 9:7214e3c3e5f8 36 volatile USB_INT08U HOST_TDControlStatus = 0;
AndyA 9:7214e3c3e5f8 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
AndyA 9:7214e3c3e5f8 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
AndyA 9:7214e3c3e5f8 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
AndyA 9:7214e3c3e5f8 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
AndyA 9:7214e3c3e5f8 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
AndyA 9:7214e3c3e5f8 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
AndyA 9:7214e3c3e5f8 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
AndyA 9:7214e3c3e5f8 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
AndyA 9:7214e3c3e5f8 45
AndyA 9:7214e3c3e5f8 46 // USB host structures
AndyA 9:7214e3c3e5f8 47 // AHB SRAM block 1
AndyA 9:7214e3c3e5f8 48 #define HOSTBASEADDR 0x2007C000
AndyA 9:7214e3c3e5f8 49 // reserve memory for the linker
AndyA 9:7214e3c3e5f8 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
AndyA 9:7214e3c3e5f8 51 /*
AndyA 9:7214e3c3e5f8 52 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 53 * DELAY IN MILLI SECONDS
AndyA 9:7214e3c3e5f8 54 *
AndyA 9:7214e3c3e5f8 55 * Description: This function provides a delay in milli seconds
AndyA 9:7214e3c3e5f8 56 *
AndyA 9:7214e3c3e5f8 57 * Arguments : delay The delay required
AndyA 9:7214e3c3e5f8 58 *
AndyA 9:7214e3c3e5f8 59 * Returns : None
AndyA 9:7214e3c3e5f8 60 *
AndyA 9:7214e3c3e5f8 61 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 62 */
AndyA 9:7214e3c3e5f8 63
AndyA 9:7214e3c3e5f8 64 void Host_DelayMS (USB_INT32U delay)
AndyA 9:7214e3c3e5f8 65 {
AndyA 9:7214e3c3e5f8 66 volatile USB_INT32U i;
AndyA 9:7214e3c3e5f8 67
AndyA 9:7214e3c3e5f8 68
AndyA 9:7214e3c3e5f8 69 for (i = 0; i < delay; i++) {
AndyA 9:7214e3c3e5f8 70 Host_DelayUS(1000);
AndyA 9:7214e3c3e5f8 71 }
AndyA 9:7214e3c3e5f8 72 }
AndyA 9:7214e3c3e5f8 73
AndyA 9:7214e3c3e5f8 74 /*
AndyA 9:7214e3c3e5f8 75 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 76 * DELAY IN MICRO SECONDS
AndyA 9:7214e3c3e5f8 77 *
AndyA 9:7214e3c3e5f8 78 * Description: This function provides a delay in micro seconds
AndyA 9:7214e3c3e5f8 79 *
AndyA 9:7214e3c3e5f8 80 * Arguments : delay The delay required
AndyA 9:7214e3c3e5f8 81 *
AndyA 9:7214e3c3e5f8 82 * Returns : None
AndyA 9:7214e3c3e5f8 83 *
AndyA 9:7214e3c3e5f8 84 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 85 */
AndyA 9:7214e3c3e5f8 86
AndyA 9:7214e3c3e5f8 87 void Host_DelayUS (USB_INT32U delay)
AndyA 9:7214e3c3e5f8 88 {
AndyA 9:7214e3c3e5f8 89 volatile USB_INT32U i;
AndyA 9:7214e3c3e5f8 90
AndyA 9:7214e3c3e5f8 91
AndyA 9:7214e3c3e5f8 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
AndyA 9:7214e3c3e5f8 93 ;
AndyA 9:7214e3c3e5f8 94 }
AndyA 9:7214e3c3e5f8 95 }
AndyA 9:7214e3c3e5f8 96
AndyA 9:7214e3c3e5f8 97 // bits of the USB/OTG clock control register
AndyA 9:7214e3c3e5f8 98 #define HOST_CLK_EN (1<<0)
AndyA 9:7214e3c3e5f8 99 #define DEV_CLK_EN (1<<1)
AndyA 9:7214e3c3e5f8 100 #define PORTSEL_CLK_EN (1<<3)
AndyA 9:7214e3c3e5f8 101 #define AHB_CLK_EN (1<<4)
AndyA 9:7214e3c3e5f8 102
AndyA 9:7214e3c3e5f8 103 // bits of the USB/OTG clock status register
AndyA 9:7214e3c3e5f8 104 #define HOST_CLK_ON (1<<0)
AndyA 9:7214e3c3e5f8 105 #define DEV_CLK_ON (1<<1)
AndyA 9:7214e3c3e5f8 106 #define PORTSEL_CLK_ON (1<<3)
AndyA 9:7214e3c3e5f8 107 #define AHB_CLK_ON (1<<4)
AndyA 9:7214e3c3e5f8 108
AndyA 9:7214e3c3e5f8 109 // we need host clock, OTG/portsel clock and AHB clock
AndyA 9:7214e3c3e5f8 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
AndyA 9:7214e3c3e5f8 111
AndyA 9:7214e3c3e5f8 112 /*
AndyA 9:7214e3c3e5f8 113 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 114 * INITIALIZE THE HOST CONTROLLER
AndyA 9:7214e3c3e5f8 115 *
AndyA 9:7214e3c3e5f8 116 * Description: This function initializes lpc17xx host controller
AndyA 9:7214e3c3e5f8 117 *
AndyA 9:7214e3c3e5f8 118 * Arguments : None
AndyA 9:7214e3c3e5f8 119 *
AndyA 9:7214e3c3e5f8 120 * Returns :
AndyA 9:7214e3c3e5f8 121 *
AndyA 9:7214e3c3e5f8 122 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 123 */
AndyA 9:7214e3c3e5f8 124 void Host_Init (void)
AndyA 9:7214e3c3e5f8 125 {
AndyA 9:7214e3c3e5f8 126 PRINT_Log("In Host_Init\n");
AndyA 9:7214e3c3e5f8 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
AndyA 9:7214e3c3e5f8 128
AndyA 9:7214e3c3e5f8 129 // turn on power for USB
AndyA 9:7214e3c3e5f8 130 LPC_SC->PCONP |= (1UL<<31);
AndyA 9:7214e3c3e5f8 131 // Enable USB host clock, port selection and AHB clock
AndyA 9:7214e3c3e5f8 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
AndyA 9:7214e3c3e5f8 133 // Wait for clocks to become available
AndyA 9:7214e3c3e5f8 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
AndyA 9:7214e3c3e5f8 135 ;
AndyA 9:7214e3c3e5f8 136
AndyA 9:7214e3c3e5f8 137 // it seems the bits[0:1] mean the following
AndyA 9:7214e3c3e5f8 138 // 0: U1=device, U2=host
AndyA 9:7214e3c3e5f8 139 // 1: U1=host, U2=host
AndyA 9:7214e3c3e5f8 140 // 2: reserved
AndyA 9:7214e3c3e5f8 141 // 3: U1=host, U2=device
AndyA 9:7214e3c3e5f8 142 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
AndyA 9:7214e3c3e5f8 143 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
AndyA 9:7214e3c3e5f8 144 LPC_USB->OTGStCtrl |= 1;
AndyA 9:7214e3c3e5f8 145
AndyA 9:7214e3c3e5f8 146 // now that we've configured the ports, we can turn off the portsel clock
AndyA 9:7214e3c3e5f8 147 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
AndyA 9:7214e3c3e5f8 148
AndyA 9:7214e3c3e5f8 149 // power pins are not connected on mbed, so we can skip them
AndyA 9:7214e3c3e5f8 150 /* P1[18] = USB_UP_LED, 01 */
AndyA 9:7214e3c3e5f8 151 /* P1[19] = /USB_PPWR, 10 */
AndyA 9:7214e3c3e5f8 152 /* P1[22] = USB_PWRD, 10 */
AndyA 9:7214e3c3e5f8 153 /* P1[27] = /USB_OVRCR, 10 */
AndyA 9:7214e3c3e5f8 154 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
AndyA 9:7214e3c3e5f8 155 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
AndyA 9:7214e3c3e5f8 156 */
AndyA 9:7214e3c3e5f8 157
AndyA 9:7214e3c3e5f8 158 // configure USB D+/D- pins
AndyA 9:7214e3c3e5f8 159 /* P0[29] = USB_D+, 01 */
AndyA 9:7214e3c3e5f8 160 /* P0[30] = USB_D-, 01 */
AndyA 9:7214e3c3e5f8 161 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
AndyA 9:7214e3c3e5f8 162 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
AndyA 9:7214e3c3e5f8 163
AndyA 9:7214e3c3e5f8 164 PRINT_Log("Initializing Host Stack\n");
AndyA 9:7214e3c3e5f8 165
AndyA 9:7214e3c3e5f8 166 Hcca = (volatile HCCA *)(HostBuf+0x000);
AndyA 9:7214e3c3e5f8 167 TDHead = (volatile HCTD *)(HostBuf+0x100);
AndyA 9:7214e3c3e5f8 168 TDTail = (volatile HCTD *)(HostBuf+0x110);
AndyA 9:7214e3c3e5f8 169 EDCtrl = (volatile HCED *)(HostBuf+0x120);
AndyA 9:7214e3c3e5f8 170 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
AndyA 9:7214e3c3e5f8 171 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
AndyA 9:7214e3c3e5f8 172 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
AndyA 9:7214e3c3e5f8 173
AndyA 9:7214e3c3e5f8 174 /* Initialize all the TDs, EDs and HCCA to 0 */
AndyA 9:7214e3c3e5f8 175 Host_EDInit(EDCtrl);
AndyA 9:7214e3c3e5f8 176 Host_EDInit(EDBulkIn);
AndyA 9:7214e3c3e5f8 177 Host_EDInit(EDBulkOut);
AndyA 9:7214e3c3e5f8 178 Host_TDInit(TDHead);
AndyA 9:7214e3c3e5f8 179 Host_TDInit(TDTail);
AndyA 9:7214e3c3e5f8 180 Host_HCCAInit(Hcca);
AndyA 9:7214e3c3e5f8 181
AndyA 9:7214e3c3e5f8 182 Host_DelayMS(50); /* Wait 50 ms before apply reset */
AndyA 9:7214e3c3e5f8 183 LPC_USB->HcControl = 0; /* HARDWARE RESET */
AndyA 9:7214e3c3e5f8 184 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
AndyA 9:7214e3c3e5f8 185 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
AndyA 9:7214e3c3e5f8 186
AndyA 9:7214e3c3e5f8 187 /* SOFTWARE RESET */
AndyA 9:7214e3c3e5f8 188 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
AndyA 9:7214e3c3e5f8 189 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
AndyA 9:7214e3c3e5f8 190
AndyA 9:7214e3c3e5f8 191 /* Put HC in operational state */
AndyA 9:7214e3c3e5f8 192 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
AndyA 9:7214e3c3e5f8 193 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
AndyA 9:7214e3c3e5f8 194
AndyA 9:7214e3c3e5f8 195 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
AndyA 9:7214e3c3e5f8 196 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
AndyA 9:7214e3c3e5f8 197
AndyA 9:7214e3c3e5f8 198
AndyA 9:7214e3c3e5f8 199 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
AndyA 9:7214e3c3e5f8 200 OR_INTR_ENABLE_WDH |
AndyA 9:7214e3c3e5f8 201 OR_INTR_ENABLE_RHSC;
AndyA 9:7214e3c3e5f8 202
AndyA 9:7214e3c3e5f8 203 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
AndyA 9:7214e3c3e5f8 204 /* Enable the USB Interrupt */
AndyA 9:7214e3c3e5f8 205 NVIC_EnableIRQ(USB_IRQn);
AndyA 9:7214e3c3e5f8 206 PRINT_Log("Host Initialized\n");
AndyA 9:7214e3c3e5f8 207 }
AndyA 9:7214e3c3e5f8 208
AndyA 9:7214e3c3e5f8 209 /*
AndyA 9:7214e3c3e5f8 210 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 211 * INTERRUPT SERVICE ROUTINE
AndyA 9:7214e3c3e5f8 212 *
AndyA 9:7214e3c3e5f8 213 * Description: This function services the interrupt caused by host controller
AndyA 9:7214e3c3e5f8 214 *
AndyA 9:7214e3c3e5f8 215 * Arguments : None
AndyA 9:7214e3c3e5f8 216 *
AndyA 9:7214e3c3e5f8 217 * Returns : None
AndyA 9:7214e3c3e5f8 218 *
AndyA 9:7214e3c3e5f8 219 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 220 */
AndyA 9:7214e3c3e5f8 221
AndyA 9:7214e3c3e5f8 222 void USB_IRQHandler (void) __irq
AndyA 9:7214e3c3e5f8 223 {
AndyA 9:7214e3c3e5f8 224 USB_INT32U int_status;
AndyA 9:7214e3c3e5f8 225 USB_INT32U ie_status;
AndyA 9:7214e3c3e5f8 226
AndyA 9:7214e3c3e5f8 227 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
AndyA 9:7214e3c3e5f8 228 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
AndyA 9:7214e3c3e5f8 229
AndyA 9:7214e3c3e5f8 230 if (!(int_status & ie_status)) {
AndyA 9:7214e3c3e5f8 231 return;
AndyA 9:7214e3c3e5f8 232 } else {
AndyA 9:7214e3c3e5f8 233
AndyA 9:7214e3c3e5f8 234 int_status = int_status & ie_status;
AndyA 9:7214e3c3e5f8 235 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
AndyA 9:7214e3c3e5f8 236 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
AndyA 9:7214e3c3e5f8 237 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
AndyA 9:7214e3c3e5f8 238 /*
AndyA 9:7214e3c3e5f8 239 * When DRWE is on, Connect Status Change
AndyA 9:7214e3c3e5f8 240 * means a remote wakeup event.
AndyA 9:7214e3c3e5f8 241 */
AndyA 9:7214e3c3e5f8 242 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
AndyA 9:7214e3c3e5f8 243 }
AndyA 9:7214e3c3e5f8 244 else {
AndyA 9:7214e3c3e5f8 245 /*
AndyA 9:7214e3c3e5f8 246 * When DRWE is off, Connect Status Change
AndyA 9:7214e3c3e5f8 247 * is NOT a remote wakeup event
AndyA 9:7214e3c3e5f8 248 */
AndyA 9:7214e3c3e5f8 249 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
AndyA 9:7214e3c3e5f8 250 if (!gUSBConnected) {
AndyA 9:7214e3c3e5f8 251 HOST_TDControlStatus = 0;
AndyA 9:7214e3c3e5f8 252 HOST_WdhIntr = 0;
AndyA 9:7214e3c3e5f8 253 HOST_RhscIntr = 1;
AndyA 9:7214e3c3e5f8 254 gUSBConnected = 1;
AndyA 9:7214e3c3e5f8 255 }
AndyA 9:7214e3c3e5f8 256 else
AndyA 9:7214e3c3e5f8 257 PRINT_Log("Spurious status change (connected)?\n");
AndyA 9:7214e3c3e5f8 258 } else {
AndyA 9:7214e3c3e5f8 259 if (gUSBConnected) {
AndyA 9:7214e3c3e5f8 260 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
AndyA 9:7214e3c3e5f8 261 HOST_RhscIntr = 0;
AndyA 9:7214e3c3e5f8 262 gUSBConnected = 0;
AndyA 9:7214e3c3e5f8 263 }
AndyA 9:7214e3c3e5f8 264 else
AndyA 9:7214e3c3e5f8 265 PRINT_Log("Spurious status change (disconnected)?\n");
AndyA 9:7214e3c3e5f8 266 }
AndyA 9:7214e3c3e5f8 267 }
AndyA 9:7214e3c3e5f8 268 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
AndyA 9:7214e3c3e5f8 269 }
AndyA 9:7214e3c3e5f8 270 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
AndyA 9:7214e3c3e5f8 271 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
AndyA 9:7214e3c3e5f8 272 }
AndyA 9:7214e3c3e5f8 273 }
AndyA 9:7214e3c3e5f8 274 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
AndyA 9:7214e3c3e5f8 275 HOST_WdhIntr = 1;
AndyA 9:7214e3c3e5f8 276 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
AndyA 9:7214e3c3e5f8 277 }
AndyA 9:7214e3c3e5f8 278 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
AndyA 9:7214e3c3e5f8 279 }
AndyA 9:7214e3c3e5f8 280 return;
AndyA 9:7214e3c3e5f8 281 }
AndyA 9:7214e3c3e5f8 282
AndyA 9:7214e3c3e5f8 283 /*
AndyA 9:7214e3c3e5f8 284 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 285 * PROCESS TRANSFER DESCRIPTOR
AndyA 9:7214e3c3e5f8 286 *
AndyA 9:7214e3c3e5f8 287 * Description: This function processes the transfer descriptor
AndyA 9:7214e3c3e5f8 288 *
AndyA 9:7214e3c3e5f8 289 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
AndyA 9:7214e3c3e5f8 290 * token SETUP, IN, OUT
AndyA 9:7214e3c3e5f8 291 * buffer Current Buffer Pointer of the transfer descriptor
AndyA 9:7214e3c3e5f8 292 * buffer_len Length of the buffer
AndyA 9:7214e3c3e5f8 293 *
AndyA 9:7214e3c3e5f8 294 * Returns : OK if TD submission is successful
AndyA 9:7214e3c3e5f8 295 * ERROR if TD submission fails
AndyA 9:7214e3c3e5f8 296 *
AndyA 9:7214e3c3e5f8 297 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 298 */
AndyA 9:7214e3c3e5f8 299
AndyA 9:7214e3c3e5f8 300 USB_INT32S Host_ProcessTD (volatile HCED *ed,
AndyA 9:7214e3c3e5f8 301 volatile USB_INT32U token,
AndyA 9:7214e3c3e5f8 302 volatile USB_INT08U *buffer,
AndyA 9:7214e3c3e5f8 303 USB_INT32U buffer_len)
AndyA 9:7214e3c3e5f8 304 {
AndyA 9:7214e3c3e5f8 305 volatile USB_INT32U td_toggle;
AndyA 9:7214e3c3e5f8 306
AndyA 9:7214e3c3e5f8 307
AndyA 9:7214e3c3e5f8 308 if (ed == EDCtrl) {
AndyA 9:7214e3c3e5f8 309 if (token == TD_SETUP) {
AndyA 9:7214e3c3e5f8 310 td_toggle = TD_TOGGLE_0;
AndyA 9:7214e3c3e5f8 311 } else {
AndyA 9:7214e3c3e5f8 312 td_toggle = TD_TOGGLE_1;
AndyA 9:7214e3c3e5f8 313 }
AndyA 9:7214e3c3e5f8 314 } else {
AndyA 9:7214e3c3e5f8 315 td_toggle = 0;
AndyA 9:7214e3c3e5f8 316 }
AndyA 9:7214e3c3e5f8 317 TDHead->Control = (TD_ROUNDING |
AndyA 9:7214e3c3e5f8 318 token |
AndyA 9:7214e3c3e5f8 319 TD_DELAY_INT(0) |
AndyA 9:7214e3c3e5f8 320 td_toggle |
AndyA 9:7214e3c3e5f8 321 TD_CC);
AndyA 9:7214e3c3e5f8 322 TDTail->Control = 0;
AndyA 9:7214e3c3e5f8 323 TDHead->CurrBufPtr = (USB_INT32U) buffer;
AndyA 9:7214e3c3e5f8 324 TDTail->CurrBufPtr = 0;
AndyA 9:7214e3c3e5f8 325 TDHead->Next = (USB_INT32U) TDTail;
AndyA 9:7214e3c3e5f8 326 TDTail->Next = 0;
AndyA 9:7214e3c3e5f8 327 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
AndyA 9:7214e3c3e5f8 328 TDTail->BufEnd = 0;
AndyA 9:7214e3c3e5f8 329
AndyA 9:7214e3c3e5f8 330 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
AndyA 9:7214e3c3e5f8 331 ed->TailTd = (USB_INT32U)TDTail;
AndyA 9:7214e3c3e5f8 332 ed->Next = 0;
AndyA 9:7214e3c3e5f8 333
AndyA 9:7214e3c3e5f8 334 if (ed == EDCtrl) {
AndyA 9:7214e3c3e5f8 335 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
AndyA 9:7214e3c3e5f8 336 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
AndyA 9:7214e3c3e5f8 337 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
AndyA 9:7214e3c3e5f8 338 } else {
AndyA 9:7214e3c3e5f8 339 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
AndyA 9:7214e3c3e5f8 340 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
AndyA 9:7214e3c3e5f8 341 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
AndyA 9:7214e3c3e5f8 342 }
AndyA 9:7214e3c3e5f8 343
AndyA 9:7214e3c3e5f8 344 Host_WDHWait();
AndyA 9:7214e3c3e5f8 345
AndyA 9:7214e3c3e5f8 346 // if (!(TDHead->Control & 0xF0000000)) {
AndyA 9:7214e3c3e5f8 347 if (!HOST_TDControlStatus) {
AndyA 9:7214e3c3e5f8 348 return (OK);
AndyA 9:7214e3c3e5f8 349 } else {
AndyA 9:7214e3c3e5f8 350 return (ERR_TD_FAIL);
AndyA 9:7214e3c3e5f8 351 }
AndyA 9:7214e3c3e5f8 352 }
AndyA 9:7214e3c3e5f8 353
AndyA 9:7214e3c3e5f8 354 /*
AndyA 9:7214e3c3e5f8 355 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 356 * ENUMERATE THE DEVICE
AndyA 9:7214e3c3e5f8 357 *
AndyA 9:7214e3c3e5f8 358 * Description: This function is used to enumerate the device connected
AndyA 9:7214e3c3e5f8 359 *
AndyA 9:7214e3c3e5f8 360 * Arguments : None
AndyA 9:7214e3c3e5f8 361 *
AndyA 9:7214e3c3e5f8 362 * Returns : None
AndyA 9:7214e3c3e5f8 363 *
AndyA 9:7214e3c3e5f8 364 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 365 */
AndyA 9:7214e3c3e5f8 366
AndyA 9:7214e3c3e5f8 367 USB_INT32S Host_EnumDev (void)
AndyA 9:7214e3c3e5f8 368 {
AndyA 9:7214e3c3e5f8 369 USB_INT32S rc;
AndyA 9:7214e3c3e5f8 370
AndyA 9:7214e3c3e5f8 371 PRINT_Log("Connect a Mass Storage device\n");
AndyA 9:7214e3c3e5f8 372 while (!HOST_RhscIntr)
AndyA 9:7214e3c3e5f8 373 __WFI();
AndyA 9:7214e3c3e5f8 374 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
AndyA 9:7214e3c3e5f8 375 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
AndyA 9:7214e3c3e5f8 376 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
AndyA 9:7214e3c3e5f8 377 __WFI(); // Wait for port reset to complete...
AndyA 9:7214e3c3e5f8 378 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
AndyA 9:7214e3c3e5f8 379 Host_DelayMS(200); /* Wait for 100 MS after port reset */
AndyA 9:7214e3c3e5f8 380
AndyA 9:7214e3c3e5f8 381 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
AndyA 9:7214e3c3e5f8 382 /* Read first 8 bytes of device desc */
AndyA 9:7214e3c3e5f8 383 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
AndyA 9:7214e3c3e5f8 384 if (rc != OK) {
AndyA 9:7214e3c3e5f8 385 PRINT_Err(rc);
AndyA 9:7214e3c3e5f8 386 return (rc);
AndyA 9:7214e3c3e5f8 387 }
AndyA 9:7214e3c3e5f8 388 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
AndyA 9:7214e3c3e5f8 389 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
AndyA 9:7214e3c3e5f8 390 if (rc != OK) {
AndyA 9:7214e3c3e5f8 391 PRINT_Err(rc);
AndyA 9:7214e3c3e5f8 392 return (rc);
AndyA 9:7214e3c3e5f8 393 }
AndyA 9:7214e3c3e5f8 394 Host_DelayMS(2);
AndyA 9:7214e3c3e5f8 395 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
AndyA 9:7214e3c3e5f8 396 /* Get the configuration descriptor */
AndyA 9:7214e3c3e5f8 397 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
AndyA 9:7214e3c3e5f8 398 if (rc != OK) {
AndyA 9:7214e3c3e5f8 399 PRINT_Err(rc);
AndyA 9:7214e3c3e5f8 400 return (rc);
AndyA 9:7214e3c3e5f8 401 }
AndyA 9:7214e3c3e5f8 402 /* Get the first configuration data */
AndyA 9:7214e3c3e5f8 403 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
AndyA 9:7214e3c3e5f8 404 if (rc != OK) {
AndyA 9:7214e3c3e5f8 405 PRINT_Err(rc);
AndyA 9:7214e3c3e5f8 406 return (rc);
AndyA 9:7214e3c3e5f8 407 }
AndyA 9:7214e3c3e5f8 408 rc = MS_ParseConfiguration(); /* Parse the configuration */
AndyA 9:7214e3c3e5f8 409 if (rc != OK) {
AndyA 9:7214e3c3e5f8 410 PRINT_Err(rc);
AndyA 9:7214e3c3e5f8 411 return (rc);
AndyA 9:7214e3c3e5f8 412 }
AndyA 9:7214e3c3e5f8 413 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
AndyA 9:7214e3c3e5f8 414 if (rc != OK) {
AndyA 9:7214e3c3e5f8 415 PRINT_Err(rc);
AndyA 9:7214e3c3e5f8 416 }
AndyA 9:7214e3c3e5f8 417 Host_DelayMS(100); /* Some devices may require this delay */
AndyA 9:7214e3c3e5f8 418 return (rc);
AndyA 9:7214e3c3e5f8 419 }
AndyA 9:7214e3c3e5f8 420
AndyA 9:7214e3c3e5f8 421 /*
AndyA 9:7214e3c3e5f8 422 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 423 * RECEIVE THE CONTROL INFORMATION
AndyA 9:7214e3c3e5f8 424 *
AndyA 9:7214e3c3e5f8 425 * Description: This function is used to receive the control information
AndyA 9:7214e3c3e5f8 426 *
AndyA 9:7214e3c3e5f8 427 * Arguments : bm_request_type
AndyA 9:7214e3c3e5f8 428 * b_request
AndyA 9:7214e3c3e5f8 429 * w_value
AndyA 9:7214e3c3e5f8 430 * w_index
AndyA 9:7214e3c3e5f8 431 * w_length
AndyA 9:7214e3c3e5f8 432 * buffer
AndyA 9:7214e3c3e5f8 433 *
AndyA 9:7214e3c3e5f8 434 * Returns : OK if Success
AndyA 9:7214e3c3e5f8 435 * ERROR if Failed
AndyA 9:7214e3c3e5f8 436 *
AndyA 9:7214e3c3e5f8 437 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 438 */
AndyA 9:7214e3c3e5f8 439
AndyA 9:7214e3c3e5f8 440 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
AndyA 9:7214e3c3e5f8 441 USB_INT08U b_request,
AndyA 9:7214e3c3e5f8 442 USB_INT16U w_value,
AndyA 9:7214e3c3e5f8 443 USB_INT16U w_index,
AndyA 9:7214e3c3e5f8 444 USB_INT16U w_length,
AndyA 9:7214e3c3e5f8 445 volatile USB_INT08U *buffer)
AndyA 9:7214e3c3e5f8 446 {
AndyA 9:7214e3c3e5f8 447 USB_INT32S rc;
AndyA 9:7214e3c3e5f8 448
AndyA 9:7214e3c3e5f8 449
AndyA 9:7214e3c3e5f8 450 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
AndyA 9:7214e3c3e5f8 451 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
AndyA 9:7214e3c3e5f8 452 if (rc == OK) {
AndyA 9:7214e3c3e5f8 453 if (w_length) {
AndyA 9:7214e3c3e5f8 454 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
AndyA 9:7214e3c3e5f8 455 }
AndyA 9:7214e3c3e5f8 456 if (rc == OK) {
AndyA 9:7214e3c3e5f8 457 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
AndyA 9:7214e3c3e5f8 458 }
AndyA 9:7214e3c3e5f8 459 }
AndyA 9:7214e3c3e5f8 460 return (rc);
AndyA 9:7214e3c3e5f8 461 }
AndyA 9:7214e3c3e5f8 462
AndyA 9:7214e3c3e5f8 463 /*
AndyA 9:7214e3c3e5f8 464 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 465 * SEND THE CONTROL INFORMATION
AndyA 9:7214e3c3e5f8 466 *
AndyA 9:7214e3c3e5f8 467 * Description: This function is used to send the control information
AndyA 9:7214e3c3e5f8 468 *
AndyA 9:7214e3c3e5f8 469 * Arguments : None
AndyA 9:7214e3c3e5f8 470 *
AndyA 9:7214e3c3e5f8 471 * Returns : OK if Success
AndyA 9:7214e3c3e5f8 472 * ERR_INVALID_BOOTSIG if Failed
AndyA 9:7214e3c3e5f8 473 *
AndyA 9:7214e3c3e5f8 474 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 475 */
AndyA 9:7214e3c3e5f8 476
AndyA 9:7214e3c3e5f8 477 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
AndyA 9:7214e3c3e5f8 478 USB_INT08U b_request,
AndyA 9:7214e3c3e5f8 479 USB_INT16U w_value,
AndyA 9:7214e3c3e5f8 480 USB_INT16U w_index,
AndyA 9:7214e3c3e5f8 481 USB_INT16U w_length,
AndyA 9:7214e3c3e5f8 482 volatile USB_INT08U *buffer)
AndyA 9:7214e3c3e5f8 483 {
AndyA 9:7214e3c3e5f8 484 USB_INT32S rc;
AndyA 9:7214e3c3e5f8 485
AndyA 9:7214e3c3e5f8 486
AndyA 9:7214e3c3e5f8 487 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
AndyA 9:7214e3c3e5f8 488
AndyA 9:7214e3c3e5f8 489 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
AndyA 9:7214e3c3e5f8 490 if (rc == OK) {
AndyA 9:7214e3c3e5f8 491 if (w_length) {
AndyA 9:7214e3c3e5f8 492 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
AndyA 9:7214e3c3e5f8 493 }
AndyA 9:7214e3c3e5f8 494 if (rc == OK) {
AndyA 9:7214e3c3e5f8 495 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
AndyA 9:7214e3c3e5f8 496 }
AndyA 9:7214e3c3e5f8 497 }
AndyA 9:7214e3c3e5f8 498 return (rc);
AndyA 9:7214e3c3e5f8 499 }
AndyA 9:7214e3c3e5f8 500
AndyA 9:7214e3c3e5f8 501 /*
AndyA 9:7214e3c3e5f8 502 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 503 * FILL SETUP PACKET
AndyA 9:7214e3c3e5f8 504 *
AndyA 9:7214e3c3e5f8 505 * Description: This function is used to fill the setup packet
AndyA 9:7214e3c3e5f8 506 *
AndyA 9:7214e3c3e5f8 507 * Arguments : None
AndyA 9:7214e3c3e5f8 508 *
AndyA 9:7214e3c3e5f8 509 * Returns : OK if Success
AndyA 9:7214e3c3e5f8 510 * ERR_INVALID_BOOTSIG if Failed
AndyA 9:7214e3c3e5f8 511 *
AndyA 9:7214e3c3e5f8 512 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 513 */
AndyA 9:7214e3c3e5f8 514
AndyA 9:7214e3c3e5f8 515 void Host_FillSetup (USB_INT08U bm_request_type,
AndyA 9:7214e3c3e5f8 516 USB_INT08U b_request,
AndyA 9:7214e3c3e5f8 517 USB_INT16U w_value,
AndyA 9:7214e3c3e5f8 518 USB_INT16U w_index,
AndyA 9:7214e3c3e5f8 519 USB_INT16U w_length)
AndyA 9:7214e3c3e5f8 520 {
AndyA 9:7214e3c3e5f8 521 int i;
AndyA 9:7214e3c3e5f8 522 for (i=0;i<w_length;i++)
AndyA 9:7214e3c3e5f8 523 TDBuffer[i] = 0;
AndyA 9:7214e3c3e5f8 524
AndyA 9:7214e3c3e5f8 525 TDBuffer[0] = bm_request_type;
AndyA 9:7214e3c3e5f8 526 TDBuffer[1] = b_request;
AndyA 9:7214e3c3e5f8 527 WriteLE16U(&TDBuffer[2], w_value);
AndyA 9:7214e3c3e5f8 528 WriteLE16U(&TDBuffer[4], w_index);
AndyA 9:7214e3c3e5f8 529 WriteLE16U(&TDBuffer[6], w_length);
AndyA 9:7214e3c3e5f8 530 }
AndyA 9:7214e3c3e5f8 531
AndyA 9:7214e3c3e5f8 532
AndyA 9:7214e3c3e5f8 533
AndyA 9:7214e3c3e5f8 534 /*
AndyA 9:7214e3c3e5f8 535 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 536 * INITIALIZE THE TRANSFER DESCRIPTOR
AndyA 9:7214e3c3e5f8 537 *
AndyA 9:7214e3c3e5f8 538 * Description: This function initializes transfer descriptor
AndyA 9:7214e3c3e5f8 539 *
AndyA 9:7214e3c3e5f8 540 * Arguments : Pointer to TD structure
AndyA 9:7214e3c3e5f8 541 *
AndyA 9:7214e3c3e5f8 542 * Returns : None
AndyA 9:7214e3c3e5f8 543 *
AndyA 9:7214e3c3e5f8 544 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 545 */
AndyA 9:7214e3c3e5f8 546
AndyA 9:7214e3c3e5f8 547 void Host_TDInit (volatile HCTD *td)
AndyA 9:7214e3c3e5f8 548 {
AndyA 9:7214e3c3e5f8 549
AndyA 9:7214e3c3e5f8 550 td->Control = 0;
AndyA 9:7214e3c3e5f8 551 td->CurrBufPtr = 0;
AndyA 9:7214e3c3e5f8 552 td->Next = 0;
AndyA 9:7214e3c3e5f8 553 td->BufEnd = 0;
AndyA 9:7214e3c3e5f8 554 }
AndyA 9:7214e3c3e5f8 555
AndyA 9:7214e3c3e5f8 556 /*
AndyA 9:7214e3c3e5f8 557 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 558 * INITIALIZE THE ENDPOINT DESCRIPTOR
AndyA 9:7214e3c3e5f8 559 *
AndyA 9:7214e3c3e5f8 560 * Description: This function initializes endpoint descriptor
AndyA 9:7214e3c3e5f8 561 *
AndyA 9:7214e3c3e5f8 562 * Arguments : Pointer to ED strcuture
AndyA 9:7214e3c3e5f8 563 *
AndyA 9:7214e3c3e5f8 564 * Returns : None
AndyA 9:7214e3c3e5f8 565 *
AndyA 9:7214e3c3e5f8 566 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 567 */
AndyA 9:7214e3c3e5f8 568
AndyA 9:7214e3c3e5f8 569 void Host_EDInit (volatile HCED *ed)
AndyA 9:7214e3c3e5f8 570 {
AndyA 9:7214e3c3e5f8 571
AndyA 9:7214e3c3e5f8 572 ed->Control = 0;
AndyA 9:7214e3c3e5f8 573 ed->TailTd = 0;
AndyA 9:7214e3c3e5f8 574 ed->HeadTd = 0;
AndyA 9:7214e3c3e5f8 575 ed->Next = 0;
AndyA 9:7214e3c3e5f8 576 }
AndyA 9:7214e3c3e5f8 577
AndyA 9:7214e3c3e5f8 578 /*
AndyA 9:7214e3c3e5f8 579 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 580 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
AndyA 9:7214e3c3e5f8 581 *
AndyA 9:7214e3c3e5f8 582 * Description: This function initializes host controller communications area
AndyA 9:7214e3c3e5f8 583 *
AndyA 9:7214e3c3e5f8 584 * Arguments : Pointer to HCCA
AndyA 9:7214e3c3e5f8 585 *
AndyA 9:7214e3c3e5f8 586 * Returns :
AndyA 9:7214e3c3e5f8 587 *
AndyA 9:7214e3c3e5f8 588 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 589 */
AndyA 9:7214e3c3e5f8 590
AndyA 9:7214e3c3e5f8 591 void Host_HCCAInit (volatile HCCA *hcca)
AndyA 9:7214e3c3e5f8 592 {
AndyA 9:7214e3c3e5f8 593 USB_INT32U i;
AndyA 9:7214e3c3e5f8 594
AndyA 9:7214e3c3e5f8 595
AndyA 9:7214e3c3e5f8 596 for (i = 0; i < 32; i++) {
AndyA 9:7214e3c3e5f8 597
AndyA 9:7214e3c3e5f8 598 hcca->IntTable[i] = 0;
AndyA 9:7214e3c3e5f8 599 hcca->FrameNumber = 0;
AndyA 9:7214e3c3e5f8 600 hcca->DoneHead = 0;
AndyA 9:7214e3c3e5f8 601 }
AndyA 9:7214e3c3e5f8 602
AndyA 9:7214e3c3e5f8 603 }
AndyA 9:7214e3c3e5f8 604
AndyA 9:7214e3c3e5f8 605 /*
AndyA 9:7214e3c3e5f8 606 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 607 * WAIT FOR WDH INTERRUPT
AndyA 9:7214e3c3e5f8 608 *
AndyA 9:7214e3c3e5f8 609 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
AndyA 9:7214e3c3e5f8 610 *
AndyA 9:7214e3c3e5f8 611 * Arguments : None
AndyA 9:7214e3c3e5f8 612 *
AndyA 9:7214e3c3e5f8 613 * Returns : None
AndyA 9:7214e3c3e5f8 614 *
AndyA 9:7214e3c3e5f8 615 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 616 */
AndyA 9:7214e3c3e5f8 617
AndyA 9:7214e3c3e5f8 618 void Host_WDHWait (void)
AndyA 9:7214e3c3e5f8 619 {
AndyA 9:7214e3c3e5f8 620 while (!HOST_WdhIntr)
AndyA 9:7214e3c3e5f8 621 __WFI();
AndyA 9:7214e3c3e5f8 622
AndyA 9:7214e3c3e5f8 623 HOST_WdhIntr = 0;
AndyA 9:7214e3c3e5f8 624 }
AndyA 9:7214e3c3e5f8 625
AndyA 9:7214e3c3e5f8 626 /*
AndyA 9:7214e3c3e5f8 627 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 628 * READ LE 32U
AndyA 9:7214e3c3e5f8 629 *
AndyA 9:7214e3c3e5f8 630 * Description: This function is used to read an unsigned integer from a character buffer in the platform
AndyA 9:7214e3c3e5f8 631 * containing little endian processor
AndyA 9:7214e3c3e5f8 632 *
AndyA 9:7214e3c3e5f8 633 * Arguments : pmem Pointer to the character buffer
AndyA 9:7214e3c3e5f8 634 *
AndyA 9:7214e3c3e5f8 635 * Returns : val Unsigned integer
AndyA 9:7214e3c3e5f8 636 *
AndyA 9:7214e3c3e5f8 637 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 638 */
AndyA 9:7214e3c3e5f8 639
AndyA 9:7214e3c3e5f8 640 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
AndyA 9:7214e3c3e5f8 641 {
AndyA 9:7214e3c3e5f8 642 USB_INT32U val = *(USB_INT32U*)pmem;
AndyA 9:7214e3c3e5f8 643 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 644 return __REV(val);
AndyA 9:7214e3c3e5f8 645 #else
AndyA 9:7214e3c3e5f8 646 return val;
AndyA 9:7214e3c3e5f8 647 #endif
AndyA 9:7214e3c3e5f8 648 }
AndyA 9:7214e3c3e5f8 649
AndyA 9:7214e3c3e5f8 650 /*
AndyA 9:7214e3c3e5f8 651 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 652 * WRITE LE 32U
AndyA 9:7214e3c3e5f8 653 *
AndyA 9:7214e3c3e5f8 654 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
AndyA 9:7214e3c3e5f8 655 * containing little endian processor.
AndyA 9:7214e3c3e5f8 656 *
AndyA 9:7214e3c3e5f8 657 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 658 * val Integer value to be placed in the charecter buffer
AndyA 9:7214e3c3e5f8 659 *
AndyA 9:7214e3c3e5f8 660 * Returns : None
AndyA 9:7214e3c3e5f8 661 *
AndyA 9:7214e3c3e5f8 662 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 663 */
AndyA 9:7214e3c3e5f8 664
AndyA 9:7214e3c3e5f8 665 void WriteLE32U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 666 USB_INT32U val)
AndyA 9:7214e3c3e5f8 667 {
AndyA 9:7214e3c3e5f8 668 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 669 *(USB_INT32U*)pmem = __REV(val);
AndyA 9:7214e3c3e5f8 670 #else
AndyA 9:7214e3c3e5f8 671 *(USB_INT32U*)pmem = val;
AndyA 9:7214e3c3e5f8 672 #endif
AndyA 9:7214e3c3e5f8 673 }
AndyA 9:7214e3c3e5f8 674
AndyA 9:7214e3c3e5f8 675 /*
AndyA 9:7214e3c3e5f8 676 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 677 * READ LE 16U
AndyA 9:7214e3c3e5f8 678 *
AndyA 9:7214e3c3e5f8 679 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
AndyA 9:7214e3c3e5f8 680 * containing little endian processor
AndyA 9:7214e3c3e5f8 681 *
AndyA 9:7214e3c3e5f8 682 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 683 *
AndyA 9:7214e3c3e5f8 684 * Returns : val Unsigned short integer
AndyA 9:7214e3c3e5f8 685 *
AndyA 9:7214e3c3e5f8 686 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 687 */
AndyA 9:7214e3c3e5f8 688
AndyA 9:7214e3c3e5f8 689 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
AndyA 9:7214e3c3e5f8 690 {
AndyA 9:7214e3c3e5f8 691 USB_INT16U val = *(USB_INT16U*)pmem;
AndyA 9:7214e3c3e5f8 692 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 693 return __REV16(val);
AndyA 9:7214e3c3e5f8 694 #else
AndyA 9:7214e3c3e5f8 695 return val;
AndyA 9:7214e3c3e5f8 696 #endif
AndyA 9:7214e3c3e5f8 697 }
AndyA 9:7214e3c3e5f8 698
AndyA 9:7214e3c3e5f8 699 /*
AndyA 9:7214e3c3e5f8 700 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 701 * WRITE LE 16U
AndyA 9:7214e3c3e5f8 702 *
AndyA 9:7214e3c3e5f8 703 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
AndyA 9:7214e3c3e5f8 704 * platform containing little endian processor
AndyA 9:7214e3c3e5f8 705 *
AndyA 9:7214e3c3e5f8 706 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 707 * val Value to be placed in the charecter buffer
AndyA 9:7214e3c3e5f8 708 *
AndyA 9:7214e3c3e5f8 709 * Returns : None
AndyA 9:7214e3c3e5f8 710 *
AndyA 9:7214e3c3e5f8 711 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 712 */
AndyA 9:7214e3c3e5f8 713
AndyA 9:7214e3c3e5f8 714 void WriteLE16U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 715 USB_INT16U val)
AndyA 9:7214e3c3e5f8 716 {
AndyA 9:7214e3c3e5f8 717 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 718 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
AndyA 9:7214e3c3e5f8 719 #else
AndyA 9:7214e3c3e5f8 720 *(USB_INT16U*)pmem = val;
AndyA 9:7214e3c3e5f8 721 #endif
AndyA 9:7214e3c3e5f8 722 }
AndyA 9:7214e3c3e5f8 723
AndyA 9:7214e3c3e5f8 724 /*
AndyA 9:7214e3c3e5f8 725 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 726 * READ BE 32U
AndyA 9:7214e3c3e5f8 727 *
AndyA 9:7214e3c3e5f8 728 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
AndyA 9:7214e3c3e5f8 729 * containing big endian processor
AndyA 9:7214e3c3e5f8 730 *
AndyA 9:7214e3c3e5f8 731 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 732 *
AndyA 9:7214e3c3e5f8 733 * Returns : val Unsigned integer
AndyA 9:7214e3c3e5f8 734 *
AndyA 9:7214e3c3e5f8 735 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 736 */
AndyA 9:7214e3c3e5f8 737
AndyA 9:7214e3c3e5f8 738 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
AndyA 9:7214e3c3e5f8 739 {
AndyA 9:7214e3c3e5f8 740 USB_INT32U val = *(USB_INT32U*)pmem;
AndyA 9:7214e3c3e5f8 741 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 742 return val;
AndyA 9:7214e3c3e5f8 743 #else
AndyA 9:7214e3c3e5f8 744 return __REV(val);
AndyA 9:7214e3c3e5f8 745 #endif
AndyA 9:7214e3c3e5f8 746 }
AndyA 9:7214e3c3e5f8 747
AndyA 9:7214e3c3e5f8 748 /*
AndyA 9:7214e3c3e5f8 749 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 750 * WRITE BE 32U
AndyA 9:7214e3c3e5f8 751 *
AndyA 9:7214e3c3e5f8 752 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
AndyA 9:7214e3c3e5f8 753 * containing big endian processor
AndyA 9:7214e3c3e5f8 754 *
AndyA 9:7214e3c3e5f8 755 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 756 * val Value to be placed in the charecter buffer
AndyA 9:7214e3c3e5f8 757 *
AndyA 9:7214e3c3e5f8 758 * Returns : None
AndyA 9:7214e3c3e5f8 759 *
AndyA 9:7214e3c3e5f8 760 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 761 */
AndyA 9:7214e3c3e5f8 762
AndyA 9:7214e3c3e5f8 763 void WriteBE32U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 764 USB_INT32U val)
AndyA 9:7214e3c3e5f8 765 {
AndyA 9:7214e3c3e5f8 766 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 767 *(USB_INT32U*)pmem = val;
AndyA 9:7214e3c3e5f8 768 #else
AndyA 9:7214e3c3e5f8 769 *(USB_INT32U*)pmem = __REV(val);
AndyA 9:7214e3c3e5f8 770 #endif
AndyA 9:7214e3c3e5f8 771 }
AndyA 9:7214e3c3e5f8 772
AndyA 9:7214e3c3e5f8 773 /*
AndyA 9:7214e3c3e5f8 774 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 775 * READ BE 16U
AndyA 9:7214e3c3e5f8 776 *
AndyA 9:7214e3c3e5f8 777 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
AndyA 9:7214e3c3e5f8 778 * containing big endian processor
AndyA 9:7214e3c3e5f8 779 *
AndyA 9:7214e3c3e5f8 780 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 781 *
AndyA 9:7214e3c3e5f8 782 * Returns : val Unsigned short integer
AndyA 9:7214e3c3e5f8 783 *
AndyA 9:7214e3c3e5f8 784 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 785 */
AndyA 9:7214e3c3e5f8 786
AndyA 9:7214e3c3e5f8 787 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
AndyA 9:7214e3c3e5f8 788 {
AndyA 9:7214e3c3e5f8 789 USB_INT16U val = *(USB_INT16U*)pmem;
AndyA 9:7214e3c3e5f8 790 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 791 return val;
AndyA 9:7214e3c3e5f8 792 #else
AndyA 9:7214e3c3e5f8 793 return __REV16(val);
AndyA 9:7214e3c3e5f8 794 #endif
AndyA 9:7214e3c3e5f8 795 }
AndyA 9:7214e3c3e5f8 796
AndyA 9:7214e3c3e5f8 797 /*
AndyA 9:7214e3c3e5f8 798 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 799 * WRITE BE 16U
AndyA 9:7214e3c3e5f8 800 *
AndyA 9:7214e3c3e5f8 801 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
AndyA 9:7214e3c3e5f8 802 * platform containing big endian processor
AndyA 9:7214e3c3e5f8 803 *
AndyA 9:7214e3c3e5f8 804 * Arguments : pmem Pointer to the charecter buffer
AndyA 9:7214e3c3e5f8 805 * val Value to be placed in the charecter buffer
AndyA 9:7214e3c3e5f8 806 *
AndyA 9:7214e3c3e5f8 807 * Returns : None
AndyA 9:7214e3c3e5f8 808 *
AndyA 9:7214e3c3e5f8 809 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 810 */
AndyA 9:7214e3c3e5f8 811
AndyA 9:7214e3c3e5f8 812 void WriteBE16U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 813 USB_INT16U val)
AndyA 9:7214e3c3e5f8 814 {
AndyA 9:7214e3c3e5f8 815 #ifdef __BIG_ENDIAN
AndyA 9:7214e3c3e5f8 816 *(USB_INT16U*)pmem = val;
AndyA 9:7214e3c3e5f8 817 #else
AndyA 9:7214e3c3e5f8 818 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
AndyA 9:7214e3c3e5f8 819 #endif
AndyA 9:7214e3c3e5f8 820 }