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Dependencies:   BufferedSerial FatFileSystemCpp mbed

USBHostLite/usbhost_lpc17xx.h@9:7214e3c3e5f8, 2021-02-18 (annotated)

Committer:
AndyA
Date:
Thu Feb 18 18:15:48 2021 +0000
Revision:
9:7214e3c3e5f8
massive ripup and redesign; currently has file system build errors

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AndyA 9:7214e3c3e5f8 1 /*
AndyA 9:7214e3c3e5f8 2 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 3 * NXP USB Host Stack
AndyA 9:7214e3c3e5f8 4 *
AndyA 9:7214e3c3e5f8 5 * (c) Copyright 2008, NXP SemiConductors
AndyA 9:7214e3c3e5f8 6 * (c) Copyright 2008, OnChip Technologies LLC
AndyA 9:7214e3c3e5f8 7 * All Rights Reserved
AndyA 9:7214e3c3e5f8 8 *
AndyA 9:7214e3c3e5f8 9 * www.nxp.com
AndyA 9:7214e3c3e5f8 10 * www.onchiptech.com
AndyA 9:7214e3c3e5f8 11 *
AndyA 9:7214e3c3e5f8 12 * File : usbhost_lpc17xx.h
AndyA 9:7214e3c3e5f8 13 * Programmer(s) : Ravikanth.P
AndyA 9:7214e3c3e5f8 14 * Version :
AndyA 9:7214e3c3e5f8 15 *
AndyA 9:7214e3c3e5f8 16 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 17 */
AndyA 9:7214e3c3e5f8 18
AndyA 9:7214e3c3e5f8 19 #ifndef USBHOST_LPC17xx_H
AndyA 9:7214e3c3e5f8 20 #define USBHOST_LPC17xx_H
AndyA 9:7214e3c3e5f8 21
AndyA 9:7214e3c3e5f8 22 /*
AndyA 9:7214e3c3e5f8 23 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 24 * INCLUDE HEADER FILES
AndyA 9:7214e3c3e5f8 25 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 26 */
AndyA 9:7214e3c3e5f8 27
AndyA 9:7214e3c3e5f8 28 #include "usbhost_inc.h"
AndyA 9:7214e3c3e5f8 29
AndyA 9:7214e3c3e5f8 30 /*
AndyA 9:7214e3c3e5f8 31 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 32 * PRINT CONFIGURATION
AndyA 9:7214e3c3e5f8 33 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 34 */
AndyA 9:7214e3c3e5f8 35
AndyA 9:7214e3c3e5f8 36 #define PRINT_ENABLE 1
AndyA 9:7214e3c3e5f8 37
AndyA 9:7214e3c3e5f8 38 #if PRINT_ENABLE
AndyA 9:7214e3c3e5f8 39 #define PRINT_Log(...) printf(__VA_ARGS__)
AndyA 9:7214e3c3e5f8 40 #define PRINT_Err(rc) printf("ERROR: In %s at Line %u - rc = %d\n", __FUNCTION__, __LINE__, rc)
AndyA 9:7214e3c3e5f8 41
AndyA 9:7214e3c3e5f8 42 #else
AndyA 9:7214e3c3e5f8 43 #define PRINT_Log(...) do {} while(0)
AndyA 9:7214e3c3e5f8 44 #define PRINT_Err(rc) do {} while(0)
AndyA 9:7214e3c3e5f8 45
AndyA 9:7214e3c3e5f8 46 #endif
AndyA 9:7214e3c3e5f8 47
AndyA 9:7214e3c3e5f8 48 /*
AndyA 9:7214e3c3e5f8 49 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 50 * GENERAL DEFINITIONS
AndyA 9:7214e3c3e5f8 51 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 52 */
AndyA 9:7214e3c3e5f8 53
AndyA 9:7214e3c3e5f8 54 #define DESC_LENGTH(x) x[0]
AndyA 9:7214e3c3e5f8 55 #define DESC_TYPE(x) x[1]
AndyA 9:7214e3c3e5f8 56
AndyA 9:7214e3c3e5f8 57
AndyA 9:7214e3c3e5f8 58 #define HOST_GET_DESCRIPTOR(descType, descIndex, data, length) \
AndyA 9:7214e3c3e5f8 59 Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE, GET_DESCRIPTOR, \
AndyA 9:7214e3c3e5f8 60 (descType << 8)|(descIndex), 0, length, data)
AndyA 9:7214e3c3e5f8 61
AndyA 9:7214e3c3e5f8 62 #define HOST_SET_ADDRESS(new_addr) \
AndyA 9:7214e3c3e5f8 63 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_ADDRESS, \
AndyA 9:7214e3c3e5f8 64 new_addr, 0, 0, NULL)
AndyA 9:7214e3c3e5f8 65
AndyA 9:7214e3c3e5f8 66 #define USBH_SET_CONFIGURATION(configNum) \
AndyA 9:7214e3c3e5f8 67 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_CONFIGURATION, \
AndyA 9:7214e3c3e5f8 68 configNum, 0, 0, NULL)
AndyA 9:7214e3c3e5f8 69
AndyA 9:7214e3c3e5f8 70 #define USBH_SET_INTERFACE(ifNum, altNum) \
AndyA 9:7214e3c3e5f8 71 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE, SET_INTERFACE, \
AndyA 9:7214e3c3e5f8 72 altNum, ifNum, 0, NULL)
AndyA 9:7214e3c3e5f8 73
AndyA 9:7214e3c3e5f8 74 /*
AndyA 9:7214e3c3e5f8 75 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 76 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
AndyA 9:7214e3c3e5f8 77 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 78 */
AndyA 9:7214e3c3e5f8 79
AndyA 9:7214e3c3e5f8 80 /* ------------------ HcControl Register --------------------- */
AndyA 9:7214e3c3e5f8 81 #define OR_CONTROL_CLE 0x00000010
AndyA 9:7214e3c3e5f8 82 #define OR_CONTROL_BLE 0x00000020
AndyA 9:7214e3c3e5f8 83 #define OR_CONTROL_HCFS 0x000000C0
AndyA 9:7214e3c3e5f8 84 #define OR_CONTROL_HC_OPER 0x00000080
AndyA 9:7214e3c3e5f8 85 /* ----------------- HcCommandStatus Register ----------------- */
AndyA 9:7214e3c3e5f8 86 #define OR_CMD_STATUS_HCR 0x00000001
AndyA 9:7214e3c3e5f8 87 #define OR_CMD_STATUS_CLF 0x00000002
AndyA 9:7214e3c3e5f8 88 #define OR_CMD_STATUS_BLF 0x00000004
AndyA 9:7214e3c3e5f8 89 /* --------------- HcInterruptStatus Register ----------------- */
AndyA 9:7214e3c3e5f8 90 #define OR_INTR_STATUS_WDH 0x00000002
AndyA 9:7214e3c3e5f8 91 #define OR_INTR_STATUS_RHSC 0x00000040
AndyA 9:7214e3c3e5f8 92 /* --------------- HcInterruptEnable Register ----------------- */
AndyA 9:7214e3c3e5f8 93 #define OR_INTR_ENABLE_WDH 0x00000002
AndyA 9:7214e3c3e5f8 94 #define OR_INTR_ENABLE_RHSC 0x00000040
AndyA 9:7214e3c3e5f8 95 #define OR_INTR_ENABLE_MIE 0x80000000
AndyA 9:7214e3c3e5f8 96 /* ---------------- HcRhDescriptorA Register ------------------ */
AndyA 9:7214e3c3e5f8 97 #define OR_RH_STATUS_LPSC 0x00010000
AndyA 9:7214e3c3e5f8 98 #define OR_RH_STATUS_DRWE 0x00008000
AndyA 9:7214e3c3e5f8 99 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
AndyA 9:7214e3c3e5f8 100 #define OR_RH_PORT_CCS 0x00000001
AndyA 9:7214e3c3e5f8 101 #define OR_RH_PORT_PRS 0x00000010
AndyA 9:7214e3c3e5f8 102 #define OR_RH_PORT_CSC 0x00010000
AndyA 9:7214e3c3e5f8 103 #define OR_RH_PORT_PRSC 0x00100000
AndyA 9:7214e3c3e5f8 104
AndyA 9:7214e3c3e5f8 105
AndyA 9:7214e3c3e5f8 106 /*
AndyA 9:7214e3c3e5f8 107 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 108 * FRAME INTERVAL
AndyA 9:7214e3c3e5f8 109 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 110 */
AndyA 9:7214e3c3e5f8 111
AndyA 9:7214e3c3e5f8 112 #define FI 0x2EDF /* 12000 bits per frame (-1) */
AndyA 9:7214e3c3e5f8 113 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
AndyA 9:7214e3c3e5f8 114
AndyA 9:7214e3c3e5f8 115 /*
AndyA 9:7214e3c3e5f8 116 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 117 * TRANSFER DESCRIPTOR CONTROL FIELDS
AndyA 9:7214e3c3e5f8 118 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 119 */
AndyA 9:7214e3c3e5f8 120
AndyA 9:7214e3c3e5f8 121 #define TD_ROUNDING (USB_INT32U) (0x00040000) /* Buffer Rounding */
AndyA 9:7214e3c3e5f8 122 #define TD_SETUP (USB_INT32U)(0) /* Direction of Setup Packet */
AndyA 9:7214e3c3e5f8 123 #define TD_IN (USB_INT32U)(0x00100000) /* Direction In */
AndyA 9:7214e3c3e5f8 124 #define TD_OUT (USB_INT32U)(0x00080000) /* Direction Out */
AndyA 9:7214e3c3e5f8 125 #define TD_DELAY_INT(x) (USB_INT32U)((x) << 21) /* Delay Interrupt */
AndyA 9:7214e3c3e5f8 126 #define TD_TOGGLE_0 (USB_INT32U)(0x02000000) /* Toggle 0 */
AndyA 9:7214e3c3e5f8 127 #define TD_TOGGLE_1 (USB_INT32U)(0x03000000) /* Toggle 1 */
AndyA 9:7214e3c3e5f8 128 #define TD_CC (USB_INT32U)(0xF0000000) /* Completion Code */
AndyA 9:7214e3c3e5f8 129
AndyA 9:7214e3c3e5f8 130 /*
AndyA 9:7214e3c3e5f8 131 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 132 * USB STANDARD REQUEST DEFINITIONS
AndyA 9:7214e3c3e5f8 133 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 134 */
AndyA 9:7214e3c3e5f8 135
AndyA 9:7214e3c3e5f8 136 #define USB_DESCRIPTOR_TYPE_DEVICE 1
AndyA 9:7214e3c3e5f8 137 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
AndyA 9:7214e3c3e5f8 138 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
AndyA 9:7214e3c3e5f8 139 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
AndyA 9:7214e3c3e5f8 140 /* ----------- Control RequestType Fields ----------- */
AndyA 9:7214e3c3e5f8 141 #define USB_DEVICE_TO_HOST 0x80
AndyA 9:7214e3c3e5f8 142 #define USB_HOST_TO_DEVICE 0x00
AndyA 9:7214e3c3e5f8 143 #define USB_REQUEST_TYPE_CLASS 0x20
AndyA 9:7214e3c3e5f8 144 #define USB_RECIPIENT_DEVICE 0x00
AndyA 9:7214e3c3e5f8 145 #define USB_RECIPIENT_INTERFACE 0x01
AndyA 9:7214e3c3e5f8 146 /* -------------- USB Standard Requests -------------- */
AndyA 9:7214e3c3e5f8 147 #define SET_ADDRESS 5
AndyA 9:7214e3c3e5f8 148 #define GET_DESCRIPTOR 6
AndyA 9:7214e3c3e5f8 149 #define SET_CONFIGURATION 9
AndyA 9:7214e3c3e5f8 150 #define SET_INTERFACE 11
AndyA 9:7214e3c3e5f8 151
AndyA 9:7214e3c3e5f8 152 /*
AndyA 9:7214e3c3e5f8 153 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 154 * TYPE DEFINITIONS
AndyA 9:7214e3c3e5f8 155 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 156 */
AndyA 9:7214e3c3e5f8 157
AndyA 9:7214e3c3e5f8 158 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
AndyA 9:7214e3c3e5f8 159 volatile USB_INT32U Control; /* Endpoint descriptor control */
AndyA 9:7214e3c3e5f8 160 volatile USB_INT32U TailTd; /* Physical address of tail in Transfer descriptor list */
AndyA 9:7214e3c3e5f8 161 volatile USB_INT32U HeadTd; /* Physcial address of head in Transfer descriptor list */
AndyA 9:7214e3c3e5f8 162 volatile USB_INT32U Next; /* Physical address of next Endpoint descriptor */
AndyA 9:7214e3c3e5f8 163 } HCED;
AndyA 9:7214e3c3e5f8 164
AndyA 9:7214e3c3e5f8 165 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
AndyA 9:7214e3c3e5f8 166 volatile USB_INT32U Control; /* Transfer descriptor control */
AndyA 9:7214e3c3e5f8 167 volatile USB_INT32U CurrBufPtr; /* Physical address of current buffer pointer */
AndyA 9:7214e3c3e5f8 168 volatile USB_INT32U Next; /* Physical pointer to next Transfer Descriptor */
AndyA 9:7214e3c3e5f8 169 volatile USB_INT32U BufEnd; /* Physical address of end of buffer */
AndyA 9:7214e3c3e5f8 170 } HCTD;
AndyA 9:7214e3c3e5f8 171
AndyA 9:7214e3c3e5f8 172 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
AndyA 9:7214e3c3e5f8 173 volatile USB_INT32U IntTable[32]; /* Interrupt Table */
AndyA 9:7214e3c3e5f8 174 volatile USB_INT32U FrameNumber; /* Frame Number */
AndyA 9:7214e3c3e5f8 175 volatile USB_INT32U DoneHead; /* Done Head */
AndyA 9:7214e3c3e5f8 176 volatile USB_INT08U Reserved[116]; /* Reserved for future use */
AndyA 9:7214e3c3e5f8 177 volatile USB_INT08U Unknown[4]; /* Unused */
AndyA 9:7214e3c3e5f8 178 } HCCA;
AndyA 9:7214e3c3e5f8 179
AndyA 9:7214e3c3e5f8 180 /*
AndyA 9:7214e3c3e5f8 181 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 182 * EXTERN DECLARATIONS
AndyA 9:7214e3c3e5f8 183 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 184 */
AndyA 9:7214e3c3e5f8 185
AndyA 9:7214e3c3e5f8 186 extern volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
AndyA 9:7214e3c3e5f8 187 extern volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
AndyA 9:7214e3c3e5f8 188 extern volatile HCTD *TDHead; /* Head transfer descriptor structure */
AndyA 9:7214e3c3e5f8 189 extern volatile HCTD *TDTail; /* Tail transfer descriptor structure */
AndyA 9:7214e3c3e5f8 190 extern volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
AndyA 9:7214e3c3e5f8 191
AndyA 9:7214e3c3e5f8 192 /*
AndyA 9:7214e3c3e5f8 193 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 194 * FUNCTION PROTOTYPES
AndyA 9:7214e3c3e5f8 195 **************************************************************************************************************
AndyA 9:7214e3c3e5f8 196 */
AndyA 9:7214e3c3e5f8 197
AndyA 9:7214e3c3e5f8 198 void Host_Init (void);
AndyA 9:7214e3c3e5f8 199
AndyA 9:7214e3c3e5f8 200 extern "C" void USB_IRQHandler(void) __irq;
AndyA 9:7214e3c3e5f8 201
AndyA 9:7214e3c3e5f8 202 USB_INT32S Host_EnumDev (void);
AndyA 9:7214e3c3e5f8 203
AndyA 9:7214e3c3e5f8 204 USB_INT32S Host_ProcessTD(volatile HCED *ed,
AndyA 9:7214e3c3e5f8 205 volatile USB_INT32U token,
AndyA 9:7214e3c3e5f8 206 volatile USB_INT08U *buffer,
AndyA 9:7214e3c3e5f8 207 USB_INT32U buffer_len);
AndyA 9:7214e3c3e5f8 208
AndyA 9:7214e3c3e5f8 209 void Host_DelayUS ( USB_INT32U delay);
AndyA 9:7214e3c3e5f8 210 void Host_DelayMS ( USB_INT32U delay);
AndyA 9:7214e3c3e5f8 211
AndyA 9:7214e3c3e5f8 212
AndyA 9:7214e3c3e5f8 213 void Host_TDInit (volatile HCTD *td);
AndyA 9:7214e3c3e5f8 214 void Host_EDInit (volatile HCED *ed);
AndyA 9:7214e3c3e5f8 215 void Host_HCCAInit (volatile HCCA *hcca);
AndyA 9:7214e3c3e5f8 216
AndyA 9:7214e3c3e5f8 217 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
AndyA 9:7214e3c3e5f8 218 USB_INT08U b_request,
AndyA 9:7214e3c3e5f8 219 USB_INT16U w_value,
AndyA 9:7214e3c3e5f8 220 USB_INT16U w_index,
AndyA 9:7214e3c3e5f8 221 USB_INT16U w_length,
AndyA 9:7214e3c3e5f8 222 volatile USB_INT08U *buffer);
AndyA 9:7214e3c3e5f8 223
AndyA 9:7214e3c3e5f8 224 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
AndyA 9:7214e3c3e5f8 225 USB_INT08U b_request,
AndyA 9:7214e3c3e5f8 226 USB_INT16U w_value,
AndyA 9:7214e3c3e5f8 227 USB_INT16U w_index,
AndyA 9:7214e3c3e5f8 228 USB_INT16U w_length,
AndyA 9:7214e3c3e5f8 229 volatile USB_INT08U *buffer);
AndyA 9:7214e3c3e5f8 230
AndyA 9:7214e3c3e5f8 231 void Host_FillSetup( USB_INT08U bm_request_type,
AndyA 9:7214e3c3e5f8 232 USB_INT08U b_request,
AndyA 9:7214e3c3e5f8 233 USB_INT16U w_value,
AndyA 9:7214e3c3e5f8 234 USB_INT16U w_index,
AndyA 9:7214e3c3e5f8 235 USB_INT16U w_length);
AndyA 9:7214e3c3e5f8 236
AndyA 9:7214e3c3e5f8 237
AndyA 9:7214e3c3e5f8 238 void Host_WDHWait (void);
AndyA 9:7214e3c3e5f8 239
AndyA 9:7214e3c3e5f8 240
AndyA 9:7214e3c3e5f8 241 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem);
AndyA 9:7214e3c3e5f8 242 void WriteLE32U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 243 USB_INT32U val);
AndyA 9:7214e3c3e5f8 244 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem);
AndyA 9:7214e3c3e5f8 245 void WriteLE16U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 246 USB_INT16U val);
AndyA 9:7214e3c3e5f8 247 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem);
AndyA 9:7214e3c3e5f8 248 void WriteBE32U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 249 USB_INT32U val);
AndyA 9:7214e3c3e5f8 250 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem);
AndyA 9:7214e3c3e5f8 251 void WriteBE16U (volatile USB_INT08U *pmem,
AndyA 9:7214e3c3e5f8 252 USB_INT16U val);
AndyA 9:7214e3c3e5f8 253
AndyA 9:7214e3c3e5f8 254 #endif