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Fork of MFRC522 by Martin Olejar

MFRC522.h@1:63d729186747, 2014-01-06 (annotated)

Committer:
AtomX
Date:
Mon Jan 06 15:00:15 2014 +0000
Revision:
1:63d729186747
Parent:
0:efd786b99a72 
updated coments

Who changed what in which revision?

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AtomX 0:efd786b99a72 1 /**
AtomX 0:efd786b99a72 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
AtomX 0:efd786b99a72 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
AtomX 0:efd786b99a72 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
AtomX 0:efd786b99a72 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
AtomX 0:efd786b99a72 6 * Ported to mbed by Martin Olejar, Dec, 2013
AtomX 0:efd786b99a72 7 *
AtomX 0:efd786b99a72 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
AtomX 0:efd786b99a72 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
AtomX 0:efd786b99a72 10 *
AtomX 0:efd786b99a72 11 * There are three hardware components involved:
AtomX 0:efd786b99a72 12 * 1) The micro controller: An Arduino
AtomX 0:efd786b99a72 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
AtomX 0:efd786b99a72 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
AtomX 0:efd786b99a72 15 *
AtomX 0:efd786b99a72 16 * The microcontroller and card reader uses SPI for communication.
AtomX 0:efd786b99a72 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
AtomX 0:efd786b99a72 18 *
AtomX 0:efd786b99a72 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
AtomX 0:efd786b99a72 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
AtomX 0:efd786b99a72 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
AtomX 0:efd786b99a72 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
AtomX 0:efd786b99a72 23 *
AtomX 0:efd786b99a72 24 * If only the PICC UID is wanted, the above documents has all the needed information.
AtomX 0:efd786b99a72 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
AtomX 0:efd786b99a72 26 * The MIFARE Classic chips and protocol is described in the datasheets:
AtomX 0:efd786b99a72 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
AtomX 0:efd786b99a72 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
AtomX 0:efd786b99a72 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
AtomX 0:efd786b99a72 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
AtomX 0:efd786b99a72 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
AtomX 0:efd786b99a72 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
AtomX 0:efd786b99a72 33 *
AtomX 0:efd786b99a72 34 * MIFARE Classic 1K (MF1S503x):
AtomX 0:efd786b99a72 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
AtomX 0:efd786b99a72 36 * The blocks are numbered 0-63.
AtomX 0:efd786b99a72 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
AtomX 0:efd786b99a72 38 * Bytes 0-5: Key A
AtomX 0:efd786b99a72 39 * Bytes 6-8: Access Bits
AtomX 0:efd786b99a72 40 * Bytes 9: User data
AtomX 0:efd786b99a72 41 * Bytes 10-15: Key B (or user data)
AtomX 0:efd786b99a72 42 * Block 0 is read only manufacturer data.
AtomX 0:efd786b99a72 43 * To access a block, an authentication using a key from the block's sector must be performed first.
AtomX 0:efd786b99a72 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
AtomX 0:efd786b99a72 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX 0:efd786b99a72 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
AtomX 0:efd786b99a72 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
AtomX 0:efd786b99a72 48 * MIFARE Classic 4K (MF1S703x):
AtomX 0:efd786b99a72 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
AtomX 0:efd786b99a72 50 * The blocks are numbered 0-255.
AtomX 0:efd786b99a72 51 * The last block in each sector is the Sector Trailer like above.
AtomX 0:efd786b99a72 52 * MIFARE Classic Mini (MF1 IC S20):
AtomX 0:efd786b99a72 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
AtomX 0:efd786b99a72 54 * The blocks are numbered 0-19.
AtomX 0:efd786b99a72 55 * The last block in each sector is the Sector Trailer like above.
AtomX 0:efd786b99a72 56 *
AtomX 0:efd786b99a72 57 * MIFARE Ultralight (MF0ICU1):
AtomX 0:efd786b99a72 58 * Has 16 pages of 4 bytes = 64 bytes.
AtomX 0:efd786b99a72 59 * Pages 0 + 1 is used for the 7-byte UID.
AtomX 0:efd786b99a72 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
AtomX 0:efd786b99a72 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
AtomX 0:efd786b99a72 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
AtomX 0:efd786b99a72 63 * MIFARE Ultralight C (MF0ICU2):
AtomX 0:efd786b99a72 64 * Has 48 pages of 4 bytes = 64 bytes.
AtomX 0:efd786b99a72 65 * Pages 0 + 1 is used for the 7-byte UID.
AtomX 0:efd786b99a72 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
AtomX 0:efd786b99a72 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
AtomX 0:efd786b99a72 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
AtomX 0:efd786b99a72 69 * Page 40 Lock bytes
AtomX 0:efd786b99a72 70 * Page 41 16 bit one way counter
AtomX 0:efd786b99a72 71 * Pages 42-43 Authentication configuration
AtomX 0:efd786b99a72 72 * Pages 44-47 Authentication key
AtomX 0:efd786b99a72 73 */
AtomX 0:efd786b99a72 74 #ifndef MFRC522_h
AtomX 0:efd786b99a72 75 #define MFRC522_h
AtomX 0:efd786b99a72 76
AtomX 0:efd786b99a72 77 #include "mbed.h"
AtomX 0:efd786b99a72 78
AtomX 0:efd786b99a72 79 /**
AtomX 0:efd786b99a72 80 * MFRC522 example
AtomX 0:efd786b99a72 81 *
AtomX 0:efd786b99a72 82 * @code
AtomX 0:efd786b99a72 83 * #include "mbed.h"
AtomX 0:efd786b99a72 84 * #include "MFRC522.h"
AtomX 0:efd786b99a72 85 *
AtomX 0:efd786b99a72 86 * //KL25Z Pins for MFRC522 SPI interface
AtomX 0:efd786b99a72 87 * #define SPI_MOSI PTC6
AtomX 0:efd786b99a72 88 * #define SPI_MISO PTC7
AtomX 0:efd786b99a72 89 * #define SPI_SCLK PTC5
AtomX 0:efd786b99a72 90 * #define SPI_CS PTC4
AtomX 0:efd786b99a72 91 * // KL25Z Pin for MFRC522 reset
AtomX 0:efd786b99a72 92 * #define MF_RESET PTC3
AtomX 0:efd786b99a72 93 * // KL25Z Pins for Debug UART port
AtomX 0:efd786b99a72 94 * #define UART_RX PTA1
AtomX 0:efd786b99a72 95 * #define UART_TX PTA2
AtomX 0:efd786b99a72 96 *
AtomX 0:efd786b99a72 97 * DigitalOut LedRed (LED_RED);
AtomX 0:efd786b99a72 98 * DigitalOut LedGreen (LED_GREEN);
AtomX 0:efd786b99a72 99 *
AtomX 0:efd786b99a72 100 * Serial DebugUART(UART_TX, UART_RX);
AtomX 0:efd786b99a72 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
AtomX 0:efd786b99a72 102 *
AtomX 0:efd786b99a72 103 * int main(void) {
AtomX 0:efd786b99a72 104 * // Set debug UART speed
AtomX 0:efd786b99a72 105 * DebugUART.baud(115200);
AtomX 0:efd786b99a72 106 *
AtomX 0:efd786b99a72 107 * // Init. RC522 Chip
AtomX 0:efd786b99a72 108 * RfChip.PCD_Init();
AtomX 0:efd786b99a72 109 *
AtomX 0:efd786b99a72 110 * while (true) {
AtomX 0:efd786b99a72 111 * LedRed = 1;
AtomX 0:efd786b99a72 112 * LedGreen = 1;
AtomX 0:efd786b99a72 113 *
AtomX 0:efd786b99a72 114 * // Look for new cards
AtomX 0:efd786b99a72 115 * if ( ! RfChip.PICC_IsNewCardPresent())
AtomX 0:efd786b99a72 116 * {
AtomX 0:efd786b99a72 117 * wait_ms(500);
AtomX 0:efd786b99a72 118 * continue;
AtomX 0:efd786b99a72 119 * }
AtomX 0:efd786b99a72 120 *
AtomX 0:efd786b99a72 121 * LedRed = 0;
AtomX 0:efd786b99a72 122 *
AtomX 0:efd786b99a72 123 * // Select one of the cards
AtomX 0:efd786b99a72 124 * if ( ! RfChip.PICC_ReadCardSerial())
AtomX 0:efd786b99a72 125 * {
AtomX 0:efd786b99a72 126 * wait_ms(500);
AtomX 0:efd786b99a72 127 * continue;
AtomX 0:efd786b99a72 128 * }
AtomX 0:efd786b99a72 129 *
AtomX 0:efd786b99a72 130 * LedRed = 1;
AtomX 0:efd786b99a72 131 * LedGreen = 0;
AtomX 0:efd786b99a72 132 *
AtomX 0:efd786b99a72 133 * // Print Card UID
AtomX 0:efd786b99a72 134 * printf("Card UID: ");
AtomX 0:efd786b99a72 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
AtomX 0:efd786b99a72 136 * {
AtomX 0:efd786b99a72 137 * printf(" %X02", RfChip.uid.uidByte[i]);
AtomX 0:efd786b99a72 138 * }
AtomX 0:efd786b99a72 139 * printf("\n\r");
AtomX 0:efd786b99a72 140 *
AtomX 0:efd786b99a72 141 * // Print Card type
AtomX 0:efd786b99a72 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
AtomX 0:efd786b99a72 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
AtomX 0:efd786b99a72 144 * wait_ms(1000);
AtomX 0:efd786b99a72 145 * }
AtomX 0:efd786b99a72 146 * }
AtomX 0:efd786b99a72 147 * @endcode
AtomX 0:efd786b99a72 148 */
AtomX 1:63d729186747 149
AtomX 0:efd786b99a72 150 class MFRC522 {
AtomX 0:efd786b99a72 151 public:
AtomX 0:efd786b99a72 152
AtomX 1:63d729186747 153 /**
AtomX 1:63d729186747 154 * MFRC522 registers (described in chapter 9 of the datasheet).
AtomX 1:63d729186747 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
AtomX 1:63d729186747 156 */
AtomX 0:efd786b99a72 157 enum PCD_Register {
AtomX 0:efd786b99a72 158 // Page 0: Command and status
AtomX 0:efd786b99a72 159 // 0x00 // reserved for future use
AtomX 0:efd786b99a72 160 CommandReg = 0x01 << 1, // starts and stops command execution
AtomX 0:efd786b99a72 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
AtomX 0:efd786b99a72 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
AtomX 0:efd786b99a72 163 ComIrqReg = 0x04 << 1, // interrupt request bits
AtomX 0:efd786b99a72 164 DivIrqReg = 0x05 << 1, // interrupt request bits
AtomX 0:efd786b99a72 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
AtomX 0:efd786b99a72 166 Status1Reg = 0x07 << 1, // communication status bits
AtomX 0:efd786b99a72 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
AtomX 0:efd786b99a72 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
AtomX 0:efd786b99a72 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
AtomX 0:efd786b99a72 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
AtomX 0:efd786b99a72 171 ControlReg = 0x0C << 1, // miscellaneous control registers
AtomX 0:efd786b99a72 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
AtomX 0:efd786b99a72 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
AtomX 0:efd786b99a72 174 // 0x0F // reserved for future use
AtomX 0:efd786b99a72 175
AtomX 0:efd786b99a72 176 // Page 1:Command
AtomX 0:efd786b99a72 177 // 0x10 // reserved for future use
AtomX 0:efd786b99a72 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
AtomX 0:efd786b99a72 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
AtomX 0:efd786b99a72 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
AtomX 0:efd786b99a72 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
AtomX 0:efd786b99a72 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
AtomX 0:efd786b99a72 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
AtomX 0:efd786b99a72 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
AtomX 0:efd786b99a72 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
AtomX 0:efd786b99a72 186 DemodReg = 0x19 << 1, // defines demodulator settings
AtomX 0:efd786b99a72 187 // 0x1A // reserved for future use
AtomX 0:efd786b99a72 188 // 0x1B // reserved for future use
AtomX 0:efd786b99a72 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
AtomX 0:efd786b99a72 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
AtomX 0:efd786b99a72 191 // 0x1E // reserved for future use
AtomX 0:efd786b99a72 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
AtomX 0:efd786b99a72 193
AtomX 0:efd786b99a72 194 // Page 2: Configuration
AtomX 0:efd786b99a72 195 // 0x20 // reserved for future use
AtomX 0:efd786b99a72 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
AtomX 0:efd786b99a72 197 CRCResultRegL = 0x22 << 1,
AtomX 0:efd786b99a72 198 // 0x23 // reserved for future use
AtomX 0:efd786b99a72 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
AtomX 0:efd786b99a72 200 // 0x25 // reserved for future use
AtomX 0:efd786b99a72 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
AtomX 0:efd786b99a72 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
AtomX 0:efd786b99a72 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
AtomX 0:efd786b99a72 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
AtomX 0:efd786b99a72 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
AtomX 0:efd786b99a72 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
AtomX 0:efd786b99a72 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
AtomX 0:efd786b99a72 208 TReloadRegL = 0x2D << 1,
AtomX 0:efd786b99a72 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
AtomX 0:efd786b99a72 210 TCntValueRegL = 0x2F << 1,
AtomX 0:efd786b99a72 211
AtomX 0:efd786b99a72 212 // Page 3:Test Registers
AtomX 0:efd786b99a72 213 // 0x30 // reserved for future use
AtomX 0:efd786b99a72 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
AtomX 0:efd786b99a72 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
AtomX 0:efd786b99a72 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
AtomX 0:efd786b99a72 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
AtomX 0:efd786b99a72 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
AtomX 0:efd786b99a72 219 AutoTestReg = 0x36 << 1, // controls the digital self test
AtomX 0:efd786b99a72 220 VersionReg = 0x37 << 1, // shows the software version
AtomX 0:efd786b99a72 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
AtomX 0:efd786b99a72 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
AtomX 0:efd786b99a72 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
AtomX 0:efd786b99a72 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
AtomX 0:efd786b99a72 225 // 0x3C // reserved for production tests
AtomX 0:efd786b99a72 226 // 0x3D // reserved for production tests
AtomX 0:efd786b99a72 227 // 0x3E // reserved for production tests
AtomX 0:efd786b99a72 228 // 0x3F // reserved for production tests
AtomX 0:efd786b99a72 229 };
AtomX 0:efd786b99a72 230
AtomX 0:efd786b99a72 231 // MFRC522 commands Described in chapter 10 of the datasheet.
AtomX 0:efd786b99a72 232 enum PCD_Command {
AtomX 0:efd786b99a72 233 PCD_Idle = 0x00, // no action, cancels current command execution
AtomX 0:efd786b99a72 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
AtomX 0:efd786b99a72 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
AtomX 0:efd786b99a72 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
AtomX 0:efd786b99a72 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
AtomX 0:efd786b99a72 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
AtomX 0:efd786b99a72 239 PCD_Receive = 0x08, // activates the receiver circuits
AtomX 0:efd786b99a72 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
AtomX 0:efd786b99a72 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
AtomX 0:efd786b99a72 242 PCD_SoftReset = 0x0F // resets the MFRC522
AtomX 0:efd786b99a72 243 };
AtomX 0:efd786b99a72 244
AtomX 0:efd786b99a72 245 // Commands sent to the PICC.
AtomX 0:efd786b99a72 246 enum PICC_Command {
AtomX 0:efd786b99a72 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
AtomX 0:efd786b99a72 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX 0:efd786b99a72 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX 0:efd786b99a72 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
AtomX 0:efd786b99a72 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
AtomX 0:efd786b99a72 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
AtomX 0:efd786b99a72 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
AtomX 0:efd786b99a72 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
AtomX 0:efd786b99a72 255
AtomX 0:efd786b99a72 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
AtomX 0:efd786b99a72 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
AtomX 0:efd786b99a72 258 // The read/write commands can also be used for MIFARE Ultralight.
AtomX 0:efd786b99a72 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
AtomX 0:efd786b99a72 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
AtomX 0:efd786b99a72 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
AtomX 0:efd786b99a72 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
AtomX 0:efd786b99a72 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
AtomX 0:efd786b99a72 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
AtomX 0:efd786b99a72 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
AtomX 0:efd786b99a72 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
AtomX 0:efd786b99a72 267
AtomX 0:efd786b99a72 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
AtomX 0:efd786b99a72 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
AtomX 0:efd786b99a72 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
AtomX 0:efd786b99a72 271 };
AtomX 0:efd786b99a72 272
AtomX 0:efd786b99a72 273 // MIFARE constants that does not fit anywhere else
AtomX 0:efd786b99a72 274 enum MIFARE_Misc {
AtomX 0:efd786b99a72 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
AtomX 0:efd786b99a72 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
AtomX 0:efd786b99a72 277 };
AtomX 0:efd786b99a72 278
AtomX 0:efd786b99a72 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
AtomX 0:efd786b99a72 280 enum PICC_Type {
AtomX 0:efd786b99a72 281 PICC_TYPE_UNKNOWN = 0,
AtomX 0:efd786b99a72 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
AtomX 0:efd786b99a72 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
AtomX 0:efd786b99a72 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
AtomX 0:efd786b99a72 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
AtomX 0:efd786b99a72 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
AtomX 0:efd786b99a72 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
AtomX 0:efd786b99a72 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
AtomX 0:efd786b99a72 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
AtomX 0:efd786b99a72 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
AtomX 0:efd786b99a72 291 };
AtomX 0:efd786b99a72 292
AtomX 0:efd786b99a72 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
AtomX 0:efd786b99a72 294 enum StatusCode {
AtomX 0:efd786b99a72 295 STATUS_OK = 1, // Success
AtomX 0:efd786b99a72 296 STATUS_ERROR = 2, // Error in communication
AtomX 0:efd786b99a72 297 STATUS_COLLISION = 3, // Collision detected
AtomX 0:efd786b99a72 298 STATUS_TIMEOUT = 4, // Timeout in communication.
AtomX 0:efd786b99a72 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
AtomX 0:efd786b99a72 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
AtomX 0:efd786b99a72 301 STATUS_INVALID = 7, // Invalid argument.
AtomX 0:efd786b99a72 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
AtomX 0:efd786b99a72 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
AtomX 0:efd786b99a72 304 };
AtomX 0:efd786b99a72 305
AtomX 0:efd786b99a72 306 // A struct used for passing the UID of a PICC.
AtomX 0:efd786b99a72 307 typedef struct {
AtomX 0:efd786b99a72 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
AtomX 0:efd786b99a72 309 uint8_t uidByte[10];
AtomX 0:efd786b99a72 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
AtomX 0:efd786b99a72 311 } Uid;
AtomX 0:efd786b99a72 312
AtomX 0:efd786b99a72 313 // A struct used for passing a MIFARE Crypto1 key
AtomX 0:efd786b99a72 314 typedef struct {
AtomX 0:efd786b99a72 315 uint8_t keyByte[MF_KEY_SIZE];
AtomX 0:efd786b99a72 316 } MIFARE_Key;
AtomX 0:efd786b99a72 317
AtomX 0:efd786b99a72 318 // Member variables
AtomX 0:efd786b99a72 319 Uid uid; // Used by PICC_ReadCardSerial().
AtomX 0:efd786b99a72 320
AtomX 0:efd786b99a72 321 // Size of the MFRC522 FIFO
AtomX 0:efd786b99a72 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
AtomX 0:efd786b99a72 323
AtomX 0:efd786b99a72 324 /**
AtomX 0:efd786b99a72 325 * MFRC522 constructor
AtomX 0:efd786b99a72 326 *
AtomX 0:efd786b99a72 327 * @param mosi SPI MOSI pin
AtomX 0:efd786b99a72 328 * @param miso SPI MISO pin
AtomX 0:efd786b99a72 329 * @param sclk SPI SCLK pin
AtomX 0:efd786b99a72 330 * @param cs SPI CS pin
AtomX 0:efd786b99a72 331 * @param reset Reset pin
AtomX 0:efd786b99a72 332 */
AtomX 0:efd786b99a72 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
AtomX 0:efd786b99a72 334
AtomX 0:efd786b99a72 335 /**
AtomX 0:efd786b99a72 336 * MFRC522 destructor
AtomX 0:efd786b99a72 337 */
AtomX 0:efd786b99a72 338 ~MFRC522();
AtomX 1:63d729186747 339
AtomX 1:63d729186747 340
AtomX 1:63d729186747 341 // ************************************************************************************
AtomX 1:63d729186747 342 //! @name Functions for manipulating the MFRC522
AtomX 1:63d729186747 343 // ************************************************************************************
AtomX 1:63d729186747 344 //@{
AtomX 0:efd786b99a72 345
AtomX 0:efd786b99a72 346 /**
AtomX 0:efd786b99a72 347 * Initializes the MFRC522 chip.
AtomX 0:efd786b99a72 348 */
AtomX 0:efd786b99a72 349 void PCD_Init (void);
AtomX 0:efd786b99a72 350
AtomX 0:efd786b99a72 351 /**
AtomX 0:efd786b99a72 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
AtomX 0:efd786b99a72 353 */
AtomX 0:efd786b99a72 354 void PCD_Reset (void);
AtomX 0:efd786b99a72 355
AtomX 0:efd786b99a72 356 /**
AtomX 0:efd786b99a72 357 * Turns the antenna on by enabling pins TX1 and TX2.
AtomX 0:efd786b99a72 358 * After a reset these pins disabled.
AtomX 0:efd786b99a72 359 */
AtomX 0:efd786b99a72 360 void PCD_AntennaOn (void);
AtomX 0:efd786b99a72 361
AtomX 0:efd786b99a72 362 /**
AtomX 0:efd786b99a72 363 * Writes a byte to the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 364 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 365 *
AtomX 0:efd786b99a72 366 * @param reg The register to write to. One of the PCD_Register enums.
AtomX 0:efd786b99a72 367 * @param value The value to write.
AtomX 0:efd786b99a72 368 */
AtomX 0:efd786b99a72 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
AtomX 0:efd786b99a72 370
AtomX 0:efd786b99a72 371 /**
AtomX 0:efd786b99a72 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 373 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 374 *
AtomX 0:efd786b99a72 375 * @param reg The register to write to. One of the PCD_Register enums.
AtomX 0:efd786b99a72 376 * @param count The number of bytes to write to the register
AtomX 0:efd786b99a72 377 * @param values The values to write. Byte array.
AtomX 0:efd786b99a72 378 */
AtomX 0:efd786b99a72 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
AtomX 0:efd786b99a72 380
AtomX 0:efd786b99a72 381 /**
AtomX 0:efd786b99a72 382 * Reads a byte from the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 383 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 384 *
AtomX 0:efd786b99a72 385 * @param reg The register to read from. One of the PCD_Register enums.
AtomX 0:efd786b99a72 386 * @returns Register value
AtomX 0:efd786b99a72 387 */
AtomX 0:efd786b99a72 388 uint8_t PCD_ReadRegister (uint8_t reg);
AtomX 0:efd786b99a72 389
AtomX 0:efd786b99a72 390 /**
AtomX 0:efd786b99a72 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 392 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 393 *
AtomX 0:efd786b99a72 394 * @param reg The register to read from. One of the PCD_Register enums.
AtomX 0:efd786b99a72 395 * @param count The number of bytes to read.
AtomX 0:efd786b99a72 396 * @param values Byte array to store the values in.
AtomX 0:efd786b99a72 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
AtomX 0:efd786b99a72 398 */
AtomX 0:efd786b99a72 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
AtomX 0:efd786b99a72 400
AtomX 0:efd786b99a72 401 /**
AtomX 0:efd786b99a72 402 * Sets the bits given in mask in register reg.
AtomX 0:efd786b99a72 403 *
AtomX 0:efd786b99a72 404 * @param reg The register to update. One of the PCD_Register enums.
AtomX 0:efd786b99a72 405 * @param mask The bits to set.
AtomX 0:efd786b99a72 406 */
AtomX 0:efd786b99a72 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
AtomX 0:efd786b99a72 408
AtomX 0:efd786b99a72 409 /**
AtomX 0:efd786b99a72 410 * Clears the bits given in mask from register reg.
AtomX 0:efd786b99a72 411 *
AtomX 0:efd786b99a72 412 * @param reg The register to update. One of the PCD_Register enums.
AtomX 0:efd786b99a72 413 * @param mask The bits to clear.
AtomX 0:efd786b99a72 414 */
AtomX 0:efd786b99a72 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
AtomX 0:efd786b99a72 416
AtomX 0:efd786b99a72 417 /**
AtomX 0:efd786b99a72 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
AtomX 0:efd786b99a72 419 *
AtomX 0:efd786b99a72 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
AtomX 0:efd786b99a72 421 * @param length The number of bytes to transfer.
AtomX 0:efd786b99a72 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
AtomX 0:efd786b99a72 423 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 424 */
AtomX 0:efd786b99a72 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
AtomX 0:efd786b99a72 426
AtomX 0:efd786b99a72 427 /**
AtomX 0:efd786b99a72 428 * Executes the Transceive command.
AtomX 0:efd786b99a72 429 * CRC validation can only be done if backData and backLen are specified.
AtomX 0:efd786b99a72 430 *
AtomX 0:efd786b99a72 431 * @param sendData Pointer to the data to transfer to the FIFO.
AtomX 0:efd786b99a72 432 * @param sendLen Number of bytes to transfer to the FIFO.
AtomX 0:efd786b99a72 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
AtomX 0:efd786b99a72 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX 0:efd786b99a72 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
AtomX 0:efd786b99a72 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX 0:efd786b99a72 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX 1:63d729186747 438 *
AtomX 0:efd786b99a72 439 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 440 */
AtomX 0:efd786b99a72 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
AtomX 0:efd786b99a72 442 uint8_t sendLen,
AtomX 0:efd786b99a72 443 uint8_t *backData,
AtomX 0:efd786b99a72 444 uint8_t *backLen,
AtomX 0:efd786b99a72 445 uint8_t *validBits = NULL,
AtomX 0:efd786b99a72 446 uint8_t rxAlign = 0,
AtomX 0:efd786b99a72 447 bool checkCRC = false);
AtomX 0:efd786b99a72 448
AtomX 0:efd786b99a72 449
AtomX 1:63d729186747 450 /**
AtomX 1:63d729186747 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
AtomX 1:63d729186747 452 * CRC validation can only be done if backData and backLen are specified.
AtomX 1:63d729186747 453 *
AtomX 1:63d729186747 454 * @param command The command to execute. One of the PCD_Command enums.
AtomX 1:63d729186747 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
AtomX 1:63d729186747 456 * @param sendData Pointer to the data to transfer to the FIFO.
AtomX 1:63d729186747 457 * @param sendLen Number of bytes to transfer to the FIFO.
AtomX 1:63d729186747 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
AtomX 1:63d729186747 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX 1:63d729186747 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
AtomX 1:63d729186747 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX 1:63d729186747 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX 1:63d729186747 463 *
AtomX 1:63d729186747 464 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 465 */
AtomX 0:efd786b99a72 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
AtomX 0:efd786b99a72 467 uint8_t waitIRq,
AtomX 0:efd786b99a72 468 uint8_t *sendData,
AtomX 0:efd786b99a72 469 uint8_t sendLen,
AtomX 0:efd786b99a72 470 uint8_t *backData = NULL,
AtomX 0:efd786b99a72 471 uint8_t *backLen = NULL,
AtomX 0:efd786b99a72 472 uint8_t *validBits = NULL,
AtomX 0:efd786b99a72 473 uint8_t rxAlign = 0,
AtomX 0:efd786b99a72 474 bool checkCRC = false);
AtomX 0:efd786b99a72 475
AtomX 1:63d729186747 476 /**
AtomX 1:63d729186747 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX 1:63d729186747 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 1:63d729186747 479 *
AtomX 1:63d729186747 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
AtomX 1:63d729186747 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
AtomX 1:63d729186747 482 *
AtomX 1:63d729186747 483 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 484 */
AtomX 0:efd786b99a72 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
AtomX 1:63d729186747 486
AtomX 1:63d729186747 487 /**
AtomX 1:63d729186747 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX 1:63d729186747 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 1:63d729186747 490 *
AtomX 1:63d729186747 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
AtomX 1:63d729186747 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
AtomX 1:63d729186747 493 *
AtomX 1:63d729186747 494 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 495 */
AtomX 0:efd786b99a72 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
AtomX 1:63d729186747 497
AtomX 1:63d729186747 498 /**
AtomX 1:63d729186747 499 * Transmits REQA or WUPA commands.
AtomX 1:63d729186747 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 1:63d729186747 501 *
AtomX 1:63d729186747 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
AtomX 1:63d729186747 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
AtomX 1:63d729186747 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
AtomX 1:63d729186747 505 *
AtomX 1:63d729186747 506 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 507 */
AtomX 0:efd786b99a72 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
AtomX 1:63d729186747 509
AtomX 1:63d729186747 510 /**
AtomX 1:63d729186747 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
AtomX 1:63d729186747 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
AtomX 1:63d729186747 513 * On success:
AtomX 1:63d729186747 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
AtomX 1:63d729186747 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
AtomX 1:63d729186747 516 *
AtomX 1:63d729186747 517 * A PICC UID consists of 4, 7 or 10 bytes.
AtomX 1:63d729186747 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
AtomX 1:63d729186747 519 *
AtomX 1:63d729186747 520 * UID size Number of UID bytes Cascade levels Example of PICC
AtomX 1:63d729186747 521 * ======== =================== ============== ===============
AtomX 1:63d729186747 522 * single 4 1 MIFARE Classic
AtomX 1:63d729186747 523 * double 7 2 MIFARE Ultralight
AtomX 1:63d729186747 524 * triple 10 3 Not currently in use?
AtomX 1:63d729186747 525 *
AtomX 1:63d729186747 526 *
AtomX 1:63d729186747 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
AtomX 1:63d729186747 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
AtomX 1:63d729186747 529 *
AtomX 1:63d729186747 530 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 531 */
AtomX 0:efd786b99a72 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
AtomX 1:63d729186747 533
AtomX 1:63d729186747 534 /**
AtomX 1:63d729186747 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
AtomX 1:63d729186747 536 *
AtomX 1:63d729186747 537 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 538 */
AtomX 0:efd786b99a72 539 uint8_t PICC_HaltA (void);
AtomX 1:63d729186747 540
AtomX 1:63d729186747 541 // ************************************************************************************
AtomX 1:63d729186747 542 //@}
AtomX 0:efd786b99a72 543
AtomX 0:efd786b99a72 544
AtomX 1:63d729186747 545 // ************************************************************************************
AtomX 1:63d729186747 546 //! @name Functions for communicating with MIFARE PICCs
AtomX 1:63d729186747 547 // ************************************************************************************
AtomX 1:63d729186747 548 //@{
AtomX 1:63d729186747 549
AtomX 1:63d729186747 550 /**
AtomX 1:63d729186747 551 * Executes the MFRC522 MFAuthent command.
AtomX 1:63d729186747 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
AtomX 1:63d729186747 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
AtomX 1:63d729186747 554 * For use with MIFARE Classic PICCs.
AtomX 1:63d729186747 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
AtomX 1:63d729186747 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
AtomX 1:63d729186747 557 *
AtomX 1:63d729186747 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX 1:63d729186747 559 *
AtomX 1:63d729186747 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
AtomX 1:63d729186747 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
AtomX 1:63d729186747 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
AtomX 1:63d729186747 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
AtomX 1:63d729186747 564 *
AtomX 1:63d729186747 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
AtomX 1:63d729186747 566 */
AtomX 0:efd786b99a72 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
AtomX 1:63d729186747 568
AtomX 1:63d729186747 569 /**
AtomX 1:63d729186747 570 * Used to exit the PCD from its authenticated state.
AtomX 1:63d729186747 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
AtomX 1:63d729186747 572 */
AtomX 0:efd786b99a72 573 void PCD_StopCrypto1 (void);
AtomX 1:63d729186747 574
AtomX 1:63d729186747 575 /**
AtomX 1:63d729186747 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
AtomX 1:63d729186747 577 *
AtomX 1:63d729186747 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX 1:63d729186747 579 *
AtomX 1:63d729186747 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
AtomX 1:63d729186747 581 * The MF0ICU1 returns a NAK for higher addresses.
AtomX 1:63d729186747 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
AtomX 1:63d729186747 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
AtomX 1:63d729186747 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
AtomX 1:63d729186747 585 *
AtomX 1:63d729186747 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
AtomX 1:63d729186747 587 * Checks the CRC_A before returning STATUS_OK.
AtomX 1:63d729186747 588 *
AtomX 1:63d729186747 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
AtomX 1:63d729186747 590 * @param buffer The buffer to store the data in
AtomX 1:63d729186747 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
AtomX 1:63d729186747 592 *
AtomX 1:63d729186747 593 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 594 */
AtomX 0:efd786b99a72 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
AtomX 1:63d729186747 596
AtomX 1:63d729186747 597 /**
AtomX 1:63d729186747 598 * Writes 16 bytes to the active PICC.
AtomX 1:63d729186747 599 *
AtomX 1:63d729186747 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX 1:63d729186747 601 *
AtomX 1:63d729186747 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
AtomX 1:63d729186747 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
AtomX 1:63d729186747 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
AtomX 1:63d729186747 605 *
AtomX 1:63d729186747 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
AtomX 1:63d729186747 607 * @param buffer The 16 bytes to write to the PICC
AtomX 1:63d729186747 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
AtomX 1:63d729186747 609 *
AtomX 1:63d729186747 610 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 611 */
AtomX 0:efd786b99a72 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
AtomX 1:63d729186747 613
AtomX 1:63d729186747 614 /**
AtomX 1:63d729186747 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
AtomX 1:63d729186747 616 *
AtomX 1:63d729186747 617 * @param page The page (2-15) to write to.
AtomX 1:63d729186747 618 * @param buffer The 4 bytes to write to the PICC
AtomX 1:63d729186747 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
AtomX 1:63d729186747 620 *
AtomX 1:63d729186747 621 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 622 */
AtomX 1:63d729186747 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
AtomX 1:63d729186747 624
AtomX 1:63d729186747 625 /**
AtomX 1:63d729186747 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
AtomX 1:63d729186747 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 1:63d729186747 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 1:63d729186747 629 * Use MIFARE_Transfer() to store the result in a block.
AtomX 1:63d729186747 630 *
AtomX 1:63d729186747 631 * @param blockAddr The block (0-0xff) number.
AtomX 1:63d729186747 632 * @param delta This number is subtracted from the value of block blockAddr.
AtomX 1:63d729186747 633 *
AtomX 1:63d729186747 634 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 635 */
AtomX 0:efd786b99a72 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
AtomX 1:63d729186747 637
AtomX 1:63d729186747 638 /**
AtomX 1:63d729186747 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
AtomX 1:63d729186747 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 1:63d729186747 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 1:63d729186747 642 * Use MIFARE_Transfer() to store the result in a block.
AtomX 1:63d729186747 643 *
AtomX 1:63d729186747 644 * @param blockAddr The block (0-0xff) number.
AtomX 1:63d729186747 645 * @param delta This number is added to the value of block blockAddr.
AtomX 1:63d729186747 646 *
AtomX 1:63d729186747 647 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 648 */
AtomX 0:efd786b99a72 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
AtomX 1:63d729186747 650
AtomX 1:63d729186747 651 /**
AtomX 1:63d729186747 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
AtomX 1:63d729186747 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 1:63d729186747 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 1:63d729186747 655 * Use MIFARE_Transfer() to store the result in a block.
AtomX 1:63d729186747 656 *
AtomX 1:63d729186747 657 * @param blockAddr The block (0-0xff) number.
AtomX 1:63d729186747 658 *
AtomX 1:63d729186747 659 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 660 */
AtomX 0:efd786b99a72 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
AtomX 1:63d729186747 662
AtomX 1:63d729186747 663 /**
AtomX 1:63d729186747 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
AtomX 1:63d729186747 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 1:63d729186747 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 1:63d729186747 667 *
AtomX 1:63d729186747 668 * @param blockAddr The block (0-0xff) number.
AtomX 1:63d729186747 669 *
AtomX 1:63d729186747 670 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 671 */
AtomX 0:efd786b99a72 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
AtomX 1:63d729186747 673
AtomX 1:63d729186747 674 // ************************************************************************************
AtomX 1:63d729186747 675 //@}
AtomX 0:efd786b99a72 676
AtomX 0:efd786b99a72 677
AtomX 1:63d729186747 678 // ************************************************************************************
AtomX 1:63d729186747 679 //! @name Support functions
AtomX 1:63d729186747 680 // ************************************************************************************
AtomX 1:63d729186747 681 //@{
AtomX 1:63d729186747 682
AtomX 1:63d729186747 683 /**
AtomX 1:63d729186747 684 * Wrapper for MIFARE protocol communication.
AtomX 1:63d729186747 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
AtomX 1:63d729186747 686 *
AtomX 1:63d729186747 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
AtomX 1:63d729186747 688 * @param sendLen Number of bytes in sendData.
AtomX 1:63d729186747 689 * @param acceptTimeout True => A timeout is also success
AtomX 1:63d729186747 690 *
AtomX 1:63d729186747 691 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 692 */
AtomX 0:efd786b99a72 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
AtomX 1:63d729186747 694
AtomX 1:63d729186747 695 /**
AtomX 1:63d729186747 696 * Translates the SAK (Select Acknowledge) to a PICC type.
AtomX 1:63d729186747 697 *
AtomX 1:63d729186747 698 * @param sak The SAK byte returned from PICC_Select().
AtomX 1:63d729186747 699 *
AtomX 1:63d729186747 700 * @return PICC_Type
AtomX 1:63d729186747 701 */
AtomX 0:efd786b99a72 702 uint8_t PICC_GetType (uint8_t sak);
AtomX 1:63d729186747 703
AtomX 1:63d729186747 704 /**
AtomX 1:63d729186747 705 * Returns a string pointer to the PICC type name.
AtomX 1:63d729186747 706 *
AtomX 1:63d729186747 707 * @param type One of the PICC_Type enums.
AtomX 1:63d729186747 708 *
AtomX 1:63d729186747 709 * @return A string pointer to the PICC type name.
AtomX 1:63d729186747 710 */
AtomX 0:efd786b99a72 711 char* PICC_GetTypeName (uint8_t type);
AtomX 1:63d729186747 712
AtomX 1:63d729186747 713 /**
AtomX 1:63d729186747 714 * Returns a string pointer to a status code name.
AtomX 1:63d729186747 715 *
AtomX 1:63d729186747 716 * @param code One of the StatusCode enums.
AtomX 1:63d729186747 717 *
AtomX 1:63d729186747 718 * @return A string pointer to a status code name.
AtomX 1:63d729186747 719 */
AtomX 0:efd786b99a72 720 char* GetStatusCodeName (uint8_t code);
AtomX 1:63d729186747 721
AtomX 1:63d729186747 722 /**
AtomX 1:63d729186747 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
AtomX 1:63d729186747 724 *
AtomX 1:63d729186747 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
AtomX 1:63d729186747 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
AtomX 1:63d729186747 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
AtomX 1:63d729186747 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
AtomX 1:63d729186747 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
AtomX 1:63d729186747 730 */
AtomX 0:efd786b99a72 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
AtomX 0:efd786b99a72 732 uint8_t g0,
AtomX 0:efd786b99a72 733 uint8_t g1,
AtomX 0:efd786b99a72 734 uint8_t g2,
AtomX 0:efd786b99a72 735 uint8_t g3);
AtomX 1:63d729186747 736
AtomX 1:63d729186747 737 // ************************************************************************************
AtomX 1:63d729186747 738 //@}
AtomX 0:efd786b99a72 739
AtomX 0:efd786b99a72 740
AtomX 1:63d729186747 741 // ************************************************************************************
AtomX 1:63d729186747 742 //! @name Convenience functions - does not add extra functionality
AtomX 1:63d729186747 743 // ************************************************************************************
AtomX 1:63d729186747 744 //@{
AtomX 1:63d729186747 745
AtomX 1:63d729186747 746 /**
AtomX 1:63d729186747 747 * Returns true if a PICC responds to PICC_CMD_REQA.
AtomX 1:63d729186747 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
AtomX 1:63d729186747 749 *
AtomX 1:63d729186747 750 * @return bool
AtomX 1:63d729186747 751 */
AtomX 0:efd786b99a72 752 bool PICC_IsNewCardPresent(void);
AtomX 1:63d729186747 753
AtomX 1:63d729186747 754 /**
AtomX 1:63d729186747 755 * Simple wrapper around PICC_Select.
AtomX 1:63d729186747 756 * Returns true if a UID could be read.
AtomX 1:63d729186747 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
AtomX 1:63d729186747 758 * The read UID is available in the class variable uid.
AtomX 1:63d729186747 759 *
AtomX 1:63d729186747 760 * @return bool
AtomX 1:63d729186747 761 */
AtomX 0:efd786b99a72 762 bool PICC_ReadCardSerial (void);
AtomX 1:63d729186747 763
AtomX 1:63d729186747 764 // ************************************************************************************
AtomX 1:63d729186747 765 //@}
AtomX 0:efd786b99a72 766
AtomX 0:efd786b99a72 767
AtomX 0:efd786b99a72 768 private:
AtomX 0:efd786b99a72 769 SPI m_SPI;
AtomX 0:efd786b99a72 770 DigitalOut m_CS;
AtomX 0:efd786b99a72 771 DigitalOut m_RESET;
AtomX 0:efd786b99a72 772
AtomX 1:63d729186747 773 /**
AtomX 1:63d729186747 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
AtomX 1:63d729186747 775 *
AtomX 1:63d729186747 776 * @param command The command to use
AtomX 1:63d729186747 777 * @param blockAddr The block (0-0xff) number.
AtomX 1:63d729186747 778 * @param data The data to transfer in step 2
AtomX 1:63d729186747 779 *
AtomX 1:63d729186747 780 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 1:63d729186747 781 */
AtomX 0:efd786b99a72 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
AtomX 0:efd786b99a72 783 };
AtomX 0:efd786b99a72 784
AtomX 0:efd786b99a72 785 #endif