RTOS / Mbed OS RTOS_Project

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Dependencies:   mbed-os

Fork of MFRC522 by Martin Olejar

MFRC522.cpp@0:efd786b99a72, 2013-12-18 (annotated)

Committer:
AtomX
Date:
Wed Dec 18 00:39:55 2013 +0000
Revision:
0:efd786b99a72
Child:
1:63d729186747
Created MFRC522 lib

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AtomX 0:efd786b99a72 1 /*
AtomX 0:efd786b99a72 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
AtomX 0:efd786b99a72 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
AtomX 0:efd786b99a72 4 * Released into the public domain.
AtomX 0:efd786b99a72 5 */
AtomX 0:efd786b99a72 6
AtomX 0:efd786b99a72 7 #include "MFRC522.h"
AtomX 0:efd786b99a72 8
AtomX 0:efd786b99a72 9 static const char* const _TypeNamePICC[] =
AtomX 0:efd786b99a72 10 {
AtomX 0:efd786b99a72 11 "Unknown type",
AtomX 0:efd786b99a72 12 "PICC compliant with ISO/IEC 14443-4",
AtomX 0:efd786b99a72 13 "PICC compliant with ISO/IEC 18092 (NFC)",
AtomX 0:efd786b99a72 14 "MIFARE Mini, 320 bytes",
AtomX 0:efd786b99a72 15 "MIFARE 1KB",
AtomX 0:efd786b99a72 16 "MIFARE 4KB",
AtomX 0:efd786b99a72 17 "MIFARE Ultralight or Ultralight C",
AtomX 0:efd786b99a72 18 "MIFARE Plus",
AtomX 0:efd786b99a72 19 "MIFARE TNP3XXX",
AtomX 0:efd786b99a72 20
AtomX 0:efd786b99a72 21 /* not complete UID */
AtomX 0:efd786b99a72 22 "SAK indicates UID is not complete"
AtomX 0:efd786b99a72 23 };
AtomX 0:efd786b99a72 24
AtomX 0:efd786b99a72 25 static const char* const _ErrorMessage[] =
AtomX 0:efd786b99a72 26 {
AtomX 0:efd786b99a72 27 "Unknown error",
AtomX 0:efd786b99a72 28 "Success",
AtomX 0:efd786b99a72 29 "Error in communication",
AtomX 0:efd786b99a72 30 "Collision detected",
AtomX 0:efd786b99a72 31 "Timeout in communication",
AtomX 0:efd786b99a72 32 "A buffer is not big enough",
AtomX 0:efd786b99a72 33 "Internal error in the code, should not happen",
AtomX 0:efd786b99a72 34 "Invalid argument",
AtomX 0:efd786b99a72 35 "The CRC_A does not match",
AtomX 0:efd786b99a72 36 "A MIFARE PICC responded with NAK"
AtomX 0:efd786b99a72 37 };
AtomX 0:efd786b99a72 38
AtomX 0:efd786b99a72 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
AtomX 0:efd786b99a72 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
AtomX 0:efd786b99a72 41
AtomX 0:efd786b99a72 42 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 43 // Functions for setting up the driver
AtomX 0:efd786b99a72 44 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 45
AtomX 0:efd786b99a72 46 /**
AtomX 0:efd786b99a72 47 * Constructor.
AtomX 0:efd786b99a72 48 * Prepares the output pins.
AtomX 0:efd786b99a72 49 */
AtomX 0:efd786b99a72 50 MFRC522::MFRC522(PinName mosi,
AtomX 0:efd786b99a72 51 PinName miso,
AtomX 0:efd786b99a72 52 PinName sclk,
AtomX 0:efd786b99a72 53 PinName cs,
AtomX 0:efd786b99a72 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
AtomX 0:efd786b99a72 55 {
AtomX 0:efd786b99a72 56 /* Configure SPI bus */
AtomX 0:efd786b99a72 57 m_SPI.format(8, 0);
AtomX 0:efd786b99a72 58 m_SPI.frequency(8000000);
AtomX 0:efd786b99a72 59
AtomX 0:efd786b99a72 60 /* Release SPI-CS pin */
AtomX 0:efd786b99a72 61 m_CS = 1;
AtomX 0:efd786b99a72 62
AtomX 0:efd786b99a72 63 /* Release RESET pin */
AtomX 0:efd786b99a72 64 m_RESET = 1;
AtomX 0:efd786b99a72 65 } // End constructor
AtomX 0:efd786b99a72 66
AtomX 0:efd786b99a72 67
AtomX 0:efd786b99a72 68 /**
AtomX 0:efd786b99a72 69 * Destructor.
AtomX 0:efd786b99a72 70 */
AtomX 0:efd786b99a72 71 MFRC522::~MFRC522()
AtomX 0:efd786b99a72 72 {
AtomX 0:efd786b99a72 73
AtomX 0:efd786b99a72 74 }
AtomX 0:efd786b99a72 75
AtomX 0:efd786b99a72 76
AtomX 0:efd786b99a72 77 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 78 // Basic interface functions for communicating with the MFRC522
AtomX 0:efd786b99a72 79 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 80
AtomX 0:efd786b99a72 81 /**
AtomX 0:efd786b99a72 82 * Writes a byte to the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 83 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 84 */
AtomX 0:efd786b99a72 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
AtomX 0:efd786b99a72 86 {
AtomX 0:efd786b99a72 87 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:efd786b99a72 88
AtomX 0:efd786b99a72 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:efd786b99a72 90 (void) m_SPI.write(reg & 0x7E);
AtomX 0:efd786b99a72 91 (void) m_SPI.write(value);
AtomX 0:efd786b99a72 92
AtomX 0:efd786b99a72 93 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:efd786b99a72 94 } // End PCD_WriteRegister()
AtomX 0:efd786b99a72 95
AtomX 0:efd786b99a72 96 /**
AtomX 0:efd786b99a72 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 98 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 99 */
AtomX 0:efd786b99a72 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
AtomX 0:efd786b99a72 101 {
AtomX 0:efd786b99a72 102 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:efd786b99a72 103
AtomX 0:efd786b99a72 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:efd786b99a72 105 (void) m_SPI.write(reg & 0x7E);
AtomX 0:efd786b99a72 106 for (uint8_t index = 0; index < count; index++)
AtomX 0:efd786b99a72 107 {
AtomX 0:efd786b99a72 108 (void) m_SPI.write(values[index]);
AtomX 0:efd786b99a72 109 }
AtomX 0:efd786b99a72 110
AtomX 0:efd786b99a72 111 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:efd786b99a72 112 } // End PCD_WriteRegister()
AtomX 0:efd786b99a72 113
AtomX 0:efd786b99a72 114 /**
AtomX 0:efd786b99a72 115 * Reads a byte from the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 116 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 117 */
AtomX 0:efd786b99a72 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
AtomX 0:efd786b99a72 119 {
AtomX 0:efd786b99a72 120 uint8_t value;
AtomX 0:efd786b99a72 121 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:efd786b99a72 122
AtomX 0:efd786b99a72 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:efd786b99a72 124 (void) m_SPI.write(0x80 | reg);
AtomX 0:efd786b99a72 125
AtomX 0:efd786b99a72 126 // Read the value back. Send 0 to stop reading.
AtomX 0:efd786b99a72 127 value = m_SPI.write(0);
AtomX 0:efd786b99a72 128
AtomX 0:efd786b99a72 129 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:efd786b99a72 130
AtomX 0:efd786b99a72 131 return value;
AtomX 0:efd786b99a72 132 } // End PCD_ReadRegister()
AtomX 0:efd786b99a72 133
AtomX 0:efd786b99a72 134 /**
AtomX 0:efd786b99a72 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
AtomX 0:efd786b99a72 136 * The interface is described in the datasheet section 8.1.2.
AtomX 0:efd786b99a72 137 */
AtomX 0:efd786b99a72 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
AtomX 0:efd786b99a72 139 {
AtomX 0:efd786b99a72 140 if (count == 0) { return; }
AtomX 0:efd786b99a72 141
AtomX 0:efd786b99a72 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:efd786b99a72 143 uint8_t index = 0; // Index in values array.
AtomX 0:efd786b99a72 144
AtomX 0:efd786b99a72 145 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:efd786b99a72 146 count--; // One read is performed outside of the loop
AtomX 0:efd786b99a72 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
AtomX 0:efd786b99a72 148
AtomX 0:efd786b99a72 149 while (index < count)
AtomX 0:efd786b99a72 150 {
AtomX 0:efd786b99a72 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
AtomX 0:efd786b99a72 152 {
AtomX 0:efd786b99a72 153 // Create bit mask for bit positions rxAlign..7
AtomX 0:efd786b99a72 154 uint8_t mask = 0;
AtomX 0:efd786b99a72 155 for (uint8_t i = rxAlign; i <= 7; i++)
AtomX 0:efd786b99a72 156 {
AtomX 0:efd786b99a72 157 mask |= (1 << i);
AtomX 0:efd786b99a72 158 }
AtomX 0:efd786b99a72 159
AtomX 0:efd786b99a72 160 // Read value and tell that we want to read the same address again.
AtomX 0:efd786b99a72 161 uint8_t value = m_SPI.write(address);
AtomX 0:efd786b99a72 162
AtomX 0:efd786b99a72 163 // Apply mask to both current value of values[0] and the new data in value.
AtomX 0:efd786b99a72 164 values[0] = (values[index] & ~mask) | (value & mask);
AtomX 0:efd786b99a72 165 }
AtomX 0:efd786b99a72 166 else
AtomX 0:efd786b99a72 167 {
AtomX 0:efd786b99a72 168 // Read value and tell that we want to read the same address again.
AtomX 0:efd786b99a72 169 values[index] = m_SPI.write(address);
AtomX 0:efd786b99a72 170 }
AtomX 0:efd786b99a72 171
AtomX 0:efd786b99a72 172 index++;
AtomX 0:efd786b99a72 173 }
AtomX 0:efd786b99a72 174
AtomX 0:efd786b99a72 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
AtomX 0:efd786b99a72 176
AtomX 0:efd786b99a72 177 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:efd786b99a72 178 } // End PCD_ReadRegister()
AtomX 0:efd786b99a72 179
AtomX 0:efd786b99a72 180 /**
AtomX 0:efd786b99a72 181 * Sets the bits given in mask in register reg.
AtomX 0:efd786b99a72 182 */
AtomX 0:efd786b99a72 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
AtomX 0:efd786b99a72 184 {
AtomX 0:efd786b99a72 185 uint8_t tmp = PCD_ReadRegister(reg);
AtomX 0:efd786b99a72 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
AtomX 0:efd786b99a72 187 } // End PCD_SetRegisterBitMask()
AtomX 0:efd786b99a72 188
AtomX 0:efd786b99a72 189 /**
AtomX 0:efd786b99a72 190 * Clears the bits given in mask from register reg.
AtomX 0:efd786b99a72 191 */
AtomX 0:efd786b99a72 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
AtomX 0:efd786b99a72 193 {
AtomX 0:efd786b99a72 194 uint8_t tmp = PCD_ReadRegister(reg);
AtomX 0:efd786b99a72 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
AtomX 0:efd786b99a72 196 } // End PCD_ClearRegisterBitMask()
AtomX 0:efd786b99a72 197
AtomX 0:efd786b99a72 198
AtomX 0:efd786b99a72 199 /**
AtomX 0:efd786b99a72 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
AtomX 0:efd786b99a72 201 */
AtomX 0:efd786b99a72 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
AtomX 0:efd786b99a72 203 {
AtomX 0:efd786b99a72 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
AtomX 0:efd786b99a72 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
AtomX 0:efd786b99a72 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
AtomX 0:efd786b99a72 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
AtomX 0:efd786b99a72 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
AtomX 0:efd786b99a72 209
AtomX 0:efd786b99a72 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73�s.
AtomX 0:efd786b99a72 211 uint16_t i = 5000;
AtomX 0:efd786b99a72 212 uint8_t n;
AtomX 0:efd786b99a72 213 while (1)
AtomX 0:efd786b99a72 214 {
AtomX 0:efd786b99a72 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
AtomX 0:efd786b99a72 216 if (n & 0x04)
AtomX 0:efd786b99a72 217 {
AtomX 0:efd786b99a72 218 // CRCIRq bit set - calculation done
AtomX 0:efd786b99a72 219 break;
AtomX 0:efd786b99a72 220 }
AtomX 0:efd786b99a72 221 if (--i == 0)
AtomX 0:efd786b99a72 222 {
AtomX 0:efd786b99a72 223 // The emergency break. We will eventually terminate on this one after 89ms.
AtomX 0:efd786b99a72 224 // Communication with the MFRC522 might be down.
AtomX 0:efd786b99a72 225 return STATUS_TIMEOUT;
AtomX 0:efd786b99a72 226 }
AtomX 0:efd786b99a72 227 }
AtomX 0:efd786b99a72 228
AtomX 0:efd786b99a72 229 // Stop calculating CRC for new content in the FIFO.
AtomX 0:efd786b99a72 230 PCD_WriteRegister(CommandReg, PCD_Idle);
AtomX 0:efd786b99a72 231
AtomX 0:efd786b99a72 232 // Transfer the result from the registers to the result buffer
AtomX 0:efd786b99a72 233 result[0] = PCD_ReadRegister(CRCResultRegL);
AtomX 0:efd786b99a72 234 result[1] = PCD_ReadRegister(CRCResultRegH);
AtomX 0:efd786b99a72 235 return STATUS_OK;
AtomX 0:efd786b99a72 236 } // End PCD_CalculateCRC()
AtomX 0:efd786b99a72 237
AtomX 0:efd786b99a72 238
AtomX 0:efd786b99a72 239 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 240 // Functions for manipulating the MFRC522
AtomX 0:efd786b99a72 241 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 242
AtomX 0:efd786b99a72 243 /**
AtomX 0:efd786b99a72 244 * Initializes the MFRC522 chip.
AtomX 0:efd786b99a72 245 */
AtomX 0:efd786b99a72 246 void MFRC522::PCD_Init()
AtomX 0:efd786b99a72 247 {
AtomX 0:efd786b99a72 248 /* Reset MFRC522 */
AtomX 0:efd786b99a72 249 m_RESET = 0;
AtomX 0:efd786b99a72 250 wait_ms(10);
AtomX 0:efd786b99a72 251 m_RESET = 1;
AtomX 0:efd786b99a72 252 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74�s. Let us be generous: 50ms.
AtomX 0:efd786b99a72 253 wait_ms(50);
AtomX 0:efd786b99a72 254
AtomX 0:efd786b99a72 255 // When communicating with a PICC we need a timeout if something goes wrong.
AtomX 0:efd786b99a72 256 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
AtomX 0:efd786b99a72 257 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
AtomX 0:efd786b99a72 258 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
AtomX 0:efd786b99a72 259 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25�s.
AtomX 0:efd786b99a72 260 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
AtomX 0:efd786b99a72 261 PCD_WriteRegister(TReloadRegL, 0xE8);
AtomX 0:efd786b99a72 262
AtomX 0:efd786b99a72 263 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
AtomX 0:efd786b99a72 264 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
AtomX 0:efd786b99a72 265
AtomX 0:efd786b99a72 266 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
AtomX 0:efd786b99a72 267
AtomX 0:efd786b99a72 268 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
AtomX 0:efd786b99a72 269 } // End PCD_Init()
AtomX 0:efd786b99a72 270
AtomX 0:efd786b99a72 271 /**
AtomX 0:efd786b99a72 272 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
AtomX 0:efd786b99a72 273 */
AtomX 0:efd786b99a72 274 void MFRC522::PCD_Reset()
AtomX 0:efd786b99a72 275 {
AtomX 0:efd786b99a72 276 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
AtomX 0:efd786b99a72 277 // The datasheet does not mention how long the SoftRest command takes to complete.
AtomX 0:efd786b99a72 278 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
AtomX 0:efd786b99a72 279 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74�s. Let us be generous: 50ms.
AtomX 0:efd786b99a72 280 wait_ms(50);
AtomX 0:efd786b99a72 281
AtomX 0:efd786b99a72 282 // Wait for the PowerDown bit in CommandReg to be cleared
AtomX 0:efd786b99a72 283 while (PCD_ReadRegister(CommandReg) & (1<<4))
AtomX 0:efd786b99a72 284 {
AtomX 0:efd786b99a72 285 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
AtomX 0:efd786b99a72 286 }
AtomX 0:efd786b99a72 287 } // End PCD_Reset()
AtomX 0:efd786b99a72 288
AtomX 0:efd786b99a72 289 /**
AtomX 0:efd786b99a72 290 * Turns the antenna on by enabling pins TX1 and TX2.
AtomX 0:efd786b99a72 291 * After a reset these pins disabled.
AtomX 0:efd786b99a72 292 */
AtomX 0:efd786b99a72 293 void MFRC522::PCD_AntennaOn()
AtomX 0:efd786b99a72 294 {
AtomX 0:efd786b99a72 295 uint8_t value = PCD_ReadRegister(TxControlReg);
AtomX 0:efd786b99a72 296 if ((value & 0x03) != 0x03)
AtomX 0:efd786b99a72 297 {
AtomX 0:efd786b99a72 298 PCD_WriteRegister(TxControlReg, value | 0x03);
AtomX 0:efd786b99a72 299 }
AtomX 0:efd786b99a72 300 } // End PCD_AntennaOn()
AtomX 0:efd786b99a72 301
AtomX 0:efd786b99a72 302 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 303 // Functions for communicating with PICCs
AtomX 0:efd786b99a72 304 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 305
AtomX 0:efd786b99a72 306 /**
AtomX 0:efd786b99a72 307 * Executes the Transceive command.
AtomX 0:efd786b99a72 308 * CRC validation can only be done if backData and backLen are specified.
AtomX 0:efd786b99a72 309 *
AtomX 0:efd786b99a72 310 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 311 */
AtomX 0:efd786b99a72 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData, ///< Pointer to the data to transfer to the FIFO.
AtomX 0:efd786b99a72 313 uint8_t sendLen, ///< Number of bytes to transfer to the FIFO.
AtomX 0:efd786b99a72 314 uint8_t *backData, ///< NULL or pointer to buffer if data should be read back after executing the command.
AtomX 0:efd786b99a72 315 uint8_t *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX 0:efd786b99a72 316 uint8_t *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
AtomX 0:efd786b99a72 317 uint8_t rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX 0:efd786b99a72 318 bool checkCRC) ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX 0:efd786b99a72 319 {
AtomX 0:efd786b99a72 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
AtomX 0:efd786b99a72 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
AtomX 0:efd786b99a72 322 } // End PCD_TransceiveData()
AtomX 0:efd786b99a72 323
AtomX 0:efd786b99a72 324 /**
AtomX 0:efd786b99a72 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
AtomX 0:efd786b99a72 326 * CRC validation can only be done if backData and backLen are specified.
AtomX 0:efd786b99a72 327 *
AtomX 0:efd786b99a72 328 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 329 */
AtomX 0:efd786b99a72 330 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command, ///< The command to execute. One of the PCD_Command enums.
AtomX 0:efd786b99a72 331 uint8_t waitIRq, ///< The bits in the ComIrqReg register that signals successful completion of the command.
AtomX 0:efd786b99a72 332 uint8_t *sendData, ///< Pointer to the data to transfer to the FIFO.
AtomX 0:efd786b99a72 333 uint8_t sendLen, ///< Number of bytes to transfer to the FIFO.
AtomX 0:efd786b99a72 334 uint8_t *backData, ///< NULL or pointer to buffer if data should be read back after executing the command.
AtomX 0:efd786b99a72 335 uint8_t *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX 0:efd786b99a72 336 uint8_t *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
AtomX 0:efd786b99a72 337 uint8_t rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX 0:efd786b99a72 338 bool checkCRC) ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX 0:efd786b99a72 339 {
AtomX 0:efd786b99a72 340 uint8_t n, _validBits = 0;
AtomX 0:efd786b99a72 341 uint32_t i;
AtomX 0:efd786b99a72 342
AtomX 0:efd786b99a72 343 // Prepare values for BitFramingReg
AtomX 0:efd786b99a72 344 uint8_t txLastBits = validBits ? *validBits : 0;
AtomX 0:efd786b99a72 345 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
AtomX 0:efd786b99a72 346
AtomX 0:efd786b99a72 347 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
AtomX 0:efd786b99a72 348 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
AtomX 0:efd786b99a72 349 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
AtomX 0:efd786b99a72 350 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
AtomX 0:efd786b99a72 351 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
AtomX 0:efd786b99a72 352 PCD_WriteRegister(CommandReg, command); // Execute the command
AtomX 0:efd786b99a72 353 if (command == PCD_Transceive)
AtomX 0:efd786b99a72 354 {
AtomX 0:efd786b99a72 355 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
AtomX 0:efd786b99a72 356 }
AtomX 0:efd786b99a72 357
AtomX 0:efd786b99a72 358 // Wait for the command to complete.
AtomX 0:efd786b99a72 359 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
AtomX 0:efd786b99a72 360 // Each iteration of the do-while-loop takes 17.86�s.
AtomX 0:efd786b99a72 361 i = 2000;
AtomX 0:efd786b99a72 362 while (1)
AtomX 0:efd786b99a72 363 {
AtomX 0:efd786b99a72 364 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
AtomX 0:efd786b99a72 365 if (n & waitIRq)
AtomX 0:efd786b99a72 366 { // One of the interrupts that signal success has been set.
AtomX 0:efd786b99a72 367 break;
AtomX 0:efd786b99a72 368 }
AtomX 0:efd786b99a72 369
AtomX 0:efd786b99a72 370 if (n & 0x01)
AtomX 0:efd786b99a72 371 { // Timer interrupt - nothing received in 25ms
AtomX 0:efd786b99a72 372 return STATUS_TIMEOUT;
AtomX 0:efd786b99a72 373 }
AtomX 0:efd786b99a72 374
AtomX 0:efd786b99a72 375 if (--i == 0)
AtomX 0:efd786b99a72 376 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
AtomX 0:efd786b99a72 377 return STATUS_TIMEOUT;
AtomX 0:efd786b99a72 378 }
AtomX 0:efd786b99a72 379 }
AtomX 0:efd786b99a72 380
AtomX 0:efd786b99a72 381 // Stop now if any errors except collisions were detected.
AtomX 0:efd786b99a72 382 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
AtomX 0:efd786b99a72 383 if (errorRegValue & 0x13)
AtomX 0:efd786b99a72 384 { // BufferOvfl ParityErr ProtocolErr
AtomX 0:efd786b99a72 385 return STATUS_ERROR;
AtomX 0:efd786b99a72 386 }
AtomX 0:efd786b99a72 387
AtomX 0:efd786b99a72 388 // If the caller wants data back, get it from the MFRC522.
AtomX 0:efd786b99a72 389 if (backData && backLen)
AtomX 0:efd786b99a72 390 {
AtomX 0:efd786b99a72 391 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
AtomX 0:efd786b99a72 392 if (n > *backLen)
AtomX 0:efd786b99a72 393 {
AtomX 0:efd786b99a72 394 return STATUS_NO_ROOM;
AtomX 0:efd786b99a72 395 }
AtomX 0:efd786b99a72 396
AtomX 0:efd786b99a72 397 *backLen = n; // Number of bytes returned
AtomX 0:efd786b99a72 398 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
AtomX 0:efd786b99a72 399 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
AtomX 0:efd786b99a72 400 if (validBits)
AtomX 0:efd786b99a72 401 {
AtomX 0:efd786b99a72 402 *validBits = _validBits;
AtomX 0:efd786b99a72 403 }
AtomX 0:efd786b99a72 404 }
AtomX 0:efd786b99a72 405
AtomX 0:efd786b99a72 406 // Tell about collisions
AtomX 0:efd786b99a72 407 if (errorRegValue & 0x08)
AtomX 0:efd786b99a72 408 { // CollErr
AtomX 0:efd786b99a72 409 return STATUS_COLLISION;
AtomX 0:efd786b99a72 410 }
AtomX 0:efd786b99a72 411
AtomX 0:efd786b99a72 412 // Perform CRC_A validation if requested.
AtomX 0:efd786b99a72 413 if (backData && backLen && checkCRC)
AtomX 0:efd786b99a72 414 {
AtomX 0:efd786b99a72 415 // In this case a MIFARE Classic NAK is not OK.
AtomX 0:efd786b99a72 416 if ((*backLen == 1) && (_validBits == 4))
AtomX 0:efd786b99a72 417 {
AtomX 0:efd786b99a72 418 return STATUS_MIFARE_NACK;
AtomX 0:efd786b99a72 419 }
AtomX 0:efd786b99a72 420
AtomX 0:efd786b99a72 421 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
AtomX 0:efd786b99a72 422 if ((*backLen < 2) || (_validBits != 0))
AtomX 0:efd786b99a72 423 {
AtomX 0:efd786b99a72 424 return STATUS_CRC_WRONG;
AtomX 0:efd786b99a72 425 }
AtomX 0:efd786b99a72 426
AtomX 0:efd786b99a72 427 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
AtomX 0:efd786b99a72 428 uint8_t controlBuffer[2];
AtomX 0:efd786b99a72 429 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
AtomX 0:efd786b99a72 430 if (n != STATUS_OK)
AtomX 0:efd786b99a72 431 {
AtomX 0:efd786b99a72 432 return n;
AtomX 0:efd786b99a72 433 }
AtomX 0:efd786b99a72 434
AtomX 0:efd786b99a72 435 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
AtomX 0:efd786b99a72 436 {
AtomX 0:efd786b99a72 437 return STATUS_CRC_WRONG;
AtomX 0:efd786b99a72 438 }
AtomX 0:efd786b99a72 439 }
AtomX 0:efd786b99a72 440
AtomX 0:efd786b99a72 441 return STATUS_OK;
AtomX 0:efd786b99a72 442 } // End PCD_CommunicateWithPICC()
AtomX 0:efd786b99a72 443
AtomX 0:efd786b99a72 444 /**
AtomX 0:efd786b99a72 445 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX 0:efd786b99a72 446 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 0:efd786b99a72 447 *
AtomX 0:efd786b99a72 448 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 449 */
AtomX 0:efd786b99a72 450 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
AtomX 0:efd786b99a72 451 {
AtomX 0:efd786b99a72 452 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
AtomX 0:efd786b99a72 453 } // End PICC_RequestA()
AtomX 0:efd786b99a72 454
AtomX 0:efd786b99a72 455 /**
AtomX 0:efd786b99a72 456 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX 0:efd786b99a72 457 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 0:efd786b99a72 458 *
AtomX 0:efd786b99a72 459 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 460 */
AtomX 0:efd786b99a72 461 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
AtomX 0:efd786b99a72 462 {
AtomX 0:efd786b99a72 463 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
AtomX 0:efd786b99a72 464 } // End PICC_WakeupA()
AtomX 0:efd786b99a72 465
AtomX 0:efd786b99a72 466 /**
AtomX 0:efd786b99a72 467 * Transmits REQA or WUPA commands.
AtomX 0:efd786b99a72 468 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 0:efd786b99a72 469 *
AtomX 0:efd786b99a72 470 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 471 */
AtomX 0:efd786b99a72 472 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
AtomX 0:efd786b99a72 473 {
AtomX 0:efd786b99a72 474 uint8_t validBits;
AtomX 0:efd786b99a72 475 uint8_t status;
AtomX 0:efd786b99a72 476
AtomX 0:efd786b99a72 477 if (bufferATQA == NULL || *bufferSize < 2)
AtomX 0:efd786b99a72 478 { // The ATQA response is 2 bytes long.
AtomX 0:efd786b99a72 479 return STATUS_NO_ROOM;
AtomX 0:efd786b99a72 480 }
AtomX 0:efd786b99a72 481
AtomX 0:efd786b99a72 482 // ValuesAfterColl=1 => Bits received after collision are cleared.
AtomX 0:efd786b99a72 483 PCD_ClrRegisterBits(CollReg, 0x80);
AtomX 0:efd786b99a72 484
AtomX 0:efd786b99a72 485 // For REQA and WUPA we need the short frame format
AtomX 0:efd786b99a72 486 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
AtomX 0:efd786b99a72 487 validBits = 7;
AtomX 0:efd786b99a72 488
AtomX 0:efd786b99a72 489 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
AtomX 0:efd786b99a72 490 if (status != STATUS_OK)
AtomX 0:efd786b99a72 491 {
AtomX 0:efd786b99a72 492 return status;
AtomX 0:efd786b99a72 493 }
AtomX 0:efd786b99a72 494
AtomX 0:efd786b99a72 495 if ((*bufferSize != 2) || (validBits != 0))
AtomX 0:efd786b99a72 496 { // ATQA must be exactly 16 bits.
AtomX 0:efd786b99a72 497 return STATUS_ERROR;
AtomX 0:efd786b99a72 498 }
AtomX 0:efd786b99a72 499
AtomX 0:efd786b99a72 500 return STATUS_OK;
AtomX 0:efd786b99a72 501 } // End PICC_REQA_or_WUPA()
AtomX 0:efd786b99a72 502
AtomX 0:efd786b99a72 503 /**
AtomX 0:efd786b99a72 504 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
AtomX 0:efd786b99a72 505 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
AtomX 0:efd786b99a72 506 * On success:
AtomX 0:efd786b99a72 507 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
AtomX 0:efd786b99a72 508 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
AtomX 0:efd786b99a72 509 *
AtomX 0:efd786b99a72 510 * A PICC UID consists of 4, 7 or 10 bytes.
AtomX 0:efd786b99a72 511 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
AtomX 0:efd786b99a72 512 * UID size Number of UID bytes Cascade levels Example of PICC
AtomX 0:efd786b99a72 513 * ======== =================== ============== ===============
AtomX 0:efd786b99a72 514 * single 4 1 MIFARE Classic
AtomX 0:efd786b99a72 515 * double 7 2 MIFARE Ultralight
AtomX 0:efd786b99a72 516 * triple 10 3 Not currently in use?
AtomX 0:efd786b99a72 517 *
AtomX 0:efd786b99a72 518 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 519 */
AtomX 0:efd786b99a72 520 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
AtomX 0:efd786b99a72 521 {
AtomX 0:efd786b99a72 522 bool uidComplete;
AtomX 0:efd786b99a72 523 bool selectDone;
AtomX 0:efd786b99a72 524 bool useCascadeTag;
AtomX 0:efd786b99a72 525 uint8_t cascadeLevel = 1;
AtomX 0:efd786b99a72 526 uint8_t result;
AtomX 0:efd786b99a72 527 uint8_t count;
AtomX 0:efd786b99a72 528 uint8_t index;
AtomX 0:efd786b99a72 529 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
AtomX 0:efd786b99a72 530 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
AtomX 0:efd786b99a72 531 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
AtomX 0:efd786b99a72 532 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
AtomX 0:efd786b99a72 533 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
AtomX 0:efd786b99a72 534 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
AtomX 0:efd786b99a72 535 uint8_t *responseBuffer;
AtomX 0:efd786b99a72 536 uint8_t responseLength;
AtomX 0:efd786b99a72 537
AtomX 0:efd786b99a72 538 // Description of buffer structure:
AtomX 0:efd786b99a72 539 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
AtomX 0:efd786b99a72 540 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
AtomX 0:efd786b99a72 541 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
AtomX 0:efd786b99a72 542 // Byte 3: UID-data
AtomX 0:efd786b99a72 543 // Byte 4: UID-data
AtomX 0:efd786b99a72 544 // Byte 5: UID-data
AtomX 0:efd786b99a72 545 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
AtomX 0:efd786b99a72 546 // Byte 7: CRC_A
AtomX 0:efd786b99a72 547 // Byte 8: CRC_A
AtomX 0:efd786b99a72 548 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
AtomX 0:efd786b99a72 549 //
AtomX 0:efd786b99a72 550 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
AtomX 0:efd786b99a72 551 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
AtomX 0:efd786b99a72 552 // ======== ============= ===== ===== ===== =====
AtomX 0:efd786b99a72 553 // 4 bytes 1 uid0 uid1 uid2 uid3
AtomX 0:efd786b99a72 554 // 7 bytes 1 CT uid0 uid1 uid2
AtomX 0:efd786b99a72 555 // 2 uid3 uid4 uid5 uid6
AtomX 0:efd786b99a72 556 // 10 bytes 1 CT uid0 uid1 uid2
AtomX 0:efd786b99a72 557 // 2 CT uid3 uid4 uid5
AtomX 0:efd786b99a72 558 // 3 uid6 uid7 uid8 uid9
AtomX 0:efd786b99a72 559
AtomX 0:efd786b99a72 560 // Sanity checks
AtomX 0:efd786b99a72 561 if (validBits > 80)
AtomX 0:efd786b99a72 562 {
AtomX 0:efd786b99a72 563 return STATUS_INVALID;
AtomX 0:efd786b99a72 564 }
AtomX 0:efd786b99a72 565
AtomX 0:efd786b99a72 566 // Prepare MFRC522
AtomX 0:efd786b99a72 567 // ValuesAfterColl=1 => Bits received after collision are cleared.
AtomX 0:efd786b99a72 568 PCD_ClrRegisterBits(CollReg, 0x80);
AtomX 0:efd786b99a72 569
AtomX 0:efd786b99a72 570 // Repeat Cascade Level loop until we have a complete UID.
AtomX 0:efd786b99a72 571 uidComplete = false;
AtomX 0:efd786b99a72 572 while ( ! uidComplete)
AtomX 0:efd786b99a72 573 {
AtomX 0:efd786b99a72 574 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
AtomX 0:efd786b99a72 575 switch (cascadeLevel)
AtomX 0:efd786b99a72 576 {
AtomX 0:efd786b99a72 577 case 1:
AtomX 0:efd786b99a72 578 buffer[0] = PICC_CMD_SEL_CL1;
AtomX 0:efd786b99a72 579 uidIndex = 0;
AtomX 0:efd786b99a72 580 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
AtomX 0:efd786b99a72 581 break;
AtomX 0:efd786b99a72 582
AtomX 0:efd786b99a72 583 case 2:
AtomX 0:efd786b99a72 584 buffer[0] = PICC_CMD_SEL_CL2;
AtomX 0:efd786b99a72 585 uidIndex = 3;
AtomX 0:efd786b99a72 586 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
AtomX 0:efd786b99a72 587 break;
AtomX 0:efd786b99a72 588
AtomX 0:efd786b99a72 589 case 3:
AtomX 0:efd786b99a72 590 buffer[0] = PICC_CMD_SEL_CL3;
AtomX 0:efd786b99a72 591 uidIndex = 6;
AtomX 0:efd786b99a72 592 useCascadeTag = false; // Never used in CL3.
AtomX 0:efd786b99a72 593 break;
AtomX 0:efd786b99a72 594
AtomX 0:efd786b99a72 595 default:
AtomX 0:efd786b99a72 596 return STATUS_INTERNAL_ERROR;
AtomX 0:efd786b99a72 597 //break;
AtomX 0:efd786b99a72 598 }
AtomX 0:efd786b99a72 599
AtomX 0:efd786b99a72 600 // How many UID bits are known in this Cascade Level?
AtomX 0:efd786b99a72 601 if(validBits > (8 * uidIndex))
AtomX 0:efd786b99a72 602 {
AtomX 0:efd786b99a72 603 currentLevelKnownBits = validBits - (8 * uidIndex);
AtomX 0:efd786b99a72 604 }
AtomX 0:efd786b99a72 605 else
AtomX 0:efd786b99a72 606 {
AtomX 0:efd786b99a72 607 currentLevelKnownBits = 0;
AtomX 0:efd786b99a72 608 }
AtomX 0:efd786b99a72 609
AtomX 0:efd786b99a72 610 // Copy the known bits from uid->uidByte[] to buffer[]
AtomX 0:efd786b99a72 611 index = 2; // destination index in buffer[]
AtomX 0:efd786b99a72 612 if (useCascadeTag)
AtomX 0:efd786b99a72 613 {
AtomX 0:efd786b99a72 614 buffer[index++] = PICC_CMD_CT;
AtomX 0:efd786b99a72 615 }
AtomX 0:efd786b99a72 616
AtomX 0:efd786b99a72 617 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
AtomX 0:efd786b99a72 618 if (bytesToCopy)
AtomX 0:efd786b99a72 619 {
AtomX 0:efd786b99a72 620 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
AtomX 0:efd786b99a72 621 uint8_t maxBytes = useCascadeTag ? 3 : 4;
AtomX 0:efd786b99a72 622 if (bytesToCopy > maxBytes)
AtomX 0:efd786b99a72 623 {
AtomX 0:efd786b99a72 624 bytesToCopy = maxBytes;
AtomX 0:efd786b99a72 625 }
AtomX 0:efd786b99a72 626
AtomX 0:efd786b99a72 627 for (count = 0; count < bytesToCopy; count++)
AtomX 0:efd786b99a72 628 {
AtomX 0:efd786b99a72 629 buffer[index++] = uid->uidByte[uidIndex + count];
AtomX 0:efd786b99a72 630 }
AtomX 0:efd786b99a72 631 }
AtomX 0:efd786b99a72 632
AtomX 0:efd786b99a72 633 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
AtomX 0:efd786b99a72 634 if (useCascadeTag)
AtomX 0:efd786b99a72 635 {
AtomX 0:efd786b99a72 636 currentLevelKnownBits += 8;
AtomX 0:efd786b99a72 637 }
AtomX 0:efd786b99a72 638
AtomX 0:efd786b99a72 639 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
AtomX 0:efd786b99a72 640 selectDone = false;
AtomX 0:efd786b99a72 641 while ( ! selectDone)
AtomX 0:efd786b99a72 642 {
AtomX 0:efd786b99a72 643 // Find out how many bits and bytes to send and receive.
AtomX 0:efd786b99a72 644 if (currentLevelKnownBits >= 32)
AtomX 0:efd786b99a72 645 { // All UID bits in this Cascade Level are known. This is a SELECT.
AtomX 0:efd786b99a72 646 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
AtomX 0:efd786b99a72 647 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
AtomX 0:efd786b99a72 648
AtomX 0:efd786b99a72 649 // Calulate BCC - Block Check Character
AtomX 0:efd786b99a72 650 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
AtomX 0:efd786b99a72 651
AtomX 0:efd786b99a72 652 // Calculate CRC_A
AtomX 0:efd786b99a72 653 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
AtomX 0:efd786b99a72 654 if (result != STATUS_OK)
AtomX 0:efd786b99a72 655 {
AtomX 0:efd786b99a72 656 return result;
AtomX 0:efd786b99a72 657 }
AtomX 0:efd786b99a72 658
AtomX 0:efd786b99a72 659 txLastBits = 0; // 0 => All 8 bits are valid.
AtomX 0:efd786b99a72 660 bufferUsed = 9;
AtomX 0:efd786b99a72 661
AtomX 0:efd786b99a72 662 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
AtomX 0:efd786b99a72 663 responseBuffer = &buffer[6];
AtomX 0:efd786b99a72 664 responseLength = 3;
AtomX 0:efd786b99a72 665 }
AtomX 0:efd786b99a72 666 else
AtomX 0:efd786b99a72 667 { // This is an ANTICOLLISION.
AtomX 0:efd786b99a72 668 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
AtomX 0:efd786b99a72 669 txLastBits = currentLevelKnownBits % 8;
AtomX 0:efd786b99a72 670 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
AtomX 0:efd786b99a72 671 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
AtomX 0:efd786b99a72 672 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
AtomX 0:efd786b99a72 673 bufferUsed = index + (txLastBits ? 1 : 0);
AtomX 0:efd786b99a72 674
AtomX 0:efd786b99a72 675 // Store response in the unused part of buffer
AtomX 0:efd786b99a72 676 responseBuffer = &buffer[index];
AtomX 0:efd786b99a72 677 responseLength = sizeof(buffer) - index;
AtomX 0:efd786b99a72 678 }
AtomX 0:efd786b99a72 679
AtomX 0:efd786b99a72 680 // Set bit adjustments
AtomX 0:efd786b99a72 681 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
AtomX 0:efd786b99a72 682 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
AtomX 0:efd786b99a72 683
AtomX 0:efd786b99a72 684 // Transmit the buffer and receive the response.
AtomX 0:efd786b99a72 685 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
AtomX 0:efd786b99a72 686 if (result == STATUS_COLLISION)
AtomX 0:efd786b99a72 687 { // More than one PICC in the field => collision.
AtomX 0:efd786b99a72 688 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
AtomX 0:efd786b99a72 689 if (result & 0x20)
AtomX 0:efd786b99a72 690 { // CollPosNotValid
AtomX 0:efd786b99a72 691 return STATUS_COLLISION; // Without a valid collision position we cannot continue
AtomX 0:efd786b99a72 692 }
AtomX 0:efd786b99a72 693
AtomX 0:efd786b99a72 694 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
AtomX 0:efd786b99a72 695 if (collisionPos == 0)
AtomX 0:efd786b99a72 696 {
AtomX 0:efd786b99a72 697 collisionPos = 32;
AtomX 0:efd786b99a72 698 }
AtomX 0:efd786b99a72 699
AtomX 0:efd786b99a72 700 if (collisionPos <= currentLevelKnownBits)
AtomX 0:efd786b99a72 701 { // No progress - should not happen
AtomX 0:efd786b99a72 702 return STATUS_INTERNAL_ERROR;
AtomX 0:efd786b99a72 703 }
AtomX 0:efd786b99a72 704
AtomX 0:efd786b99a72 705 // Choose the PICC with the bit set.
AtomX 0:efd786b99a72 706 currentLevelKnownBits = collisionPos;
AtomX 0:efd786b99a72 707 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
AtomX 0:efd786b99a72 708 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
AtomX 0:efd786b99a72 709 buffer[index] |= (1 << count);
AtomX 0:efd786b99a72 710 }
AtomX 0:efd786b99a72 711 else if (result != STATUS_OK)
AtomX 0:efd786b99a72 712 {
AtomX 0:efd786b99a72 713 return result;
AtomX 0:efd786b99a72 714 }
AtomX 0:efd786b99a72 715 else
AtomX 0:efd786b99a72 716 { // STATUS_OK
AtomX 0:efd786b99a72 717 if (currentLevelKnownBits >= 32)
AtomX 0:efd786b99a72 718 { // This was a SELECT.
AtomX 0:efd786b99a72 719 selectDone = true; // No more anticollision
AtomX 0:efd786b99a72 720 // We continue below outside the while.
AtomX 0:efd786b99a72 721 }
AtomX 0:efd786b99a72 722 else
AtomX 0:efd786b99a72 723 { // This was an ANTICOLLISION.
AtomX 0:efd786b99a72 724 // We now have all 32 bits of the UID in this Cascade Level
AtomX 0:efd786b99a72 725 currentLevelKnownBits = 32;
AtomX 0:efd786b99a72 726 // Run loop again to do the SELECT.
AtomX 0:efd786b99a72 727 }
AtomX 0:efd786b99a72 728 }
AtomX 0:efd786b99a72 729 } // End of while ( ! selectDone)
AtomX 0:efd786b99a72 730
AtomX 0:efd786b99a72 731 // We do not check the CBB - it was constructed by us above.
AtomX 0:efd786b99a72 732
AtomX 0:efd786b99a72 733 // Copy the found UID bytes from buffer[] to uid->uidByte[]
AtomX 0:efd786b99a72 734 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
AtomX 0:efd786b99a72 735 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
AtomX 0:efd786b99a72 736 for (count = 0; count < bytesToCopy; count++)
AtomX 0:efd786b99a72 737 {
AtomX 0:efd786b99a72 738 uid->uidByte[uidIndex + count] = buffer[index++];
AtomX 0:efd786b99a72 739 }
AtomX 0:efd786b99a72 740
AtomX 0:efd786b99a72 741 // Check response SAK (Select Acknowledge)
AtomX 0:efd786b99a72 742 if (responseLength != 3 || txLastBits != 0)
AtomX 0:efd786b99a72 743 { // SAK must be exactly 24 bits (1 byte + CRC_A).
AtomX 0:efd786b99a72 744 return STATUS_ERROR;
AtomX 0:efd786b99a72 745 }
AtomX 0:efd786b99a72 746
AtomX 0:efd786b99a72 747 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
AtomX 0:efd786b99a72 748 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
AtomX 0:efd786b99a72 749 if (result != STATUS_OK)
AtomX 0:efd786b99a72 750 {
AtomX 0:efd786b99a72 751 return result;
AtomX 0:efd786b99a72 752 }
AtomX 0:efd786b99a72 753
AtomX 0:efd786b99a72 754 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
AtomX 0:efd786b99a72 755 {
AtomX 0:efd786b99a72 756 return STATUS_CRC_WRONG;
AtomX 0:efd786b99a72 757 }
AtomX 0:efd786b99a72 758
AtomX 0:efd786b99a72 759 if (responseBuffer[0] & 0x04)
AtomX 0:efd786b99a72 760 { // Cascade bit set - UID not complete yes
AtomX 0:efd786b99a72 761 cascadeLevel++;
AtomX 0:efd786b99a72 762 }
AtomX 0:efd786b99a72 763 else
AtomX 0:efd786b99a72 764 {
AtomX 0:efd786b99a72 765 uidComplete = true;
AtomX 0:efd786b99a72 766 uid->sak = responseBuffer[0];
AtomX 0:efd786b99a72 767 }
AtomX 0:efd786b99a72 768 } // End of while ( ! uidComplete)
AtomX 0:efd786b99a72 769
AtomX 0:efd786b99a72 770 // Set correct uid->size
AtomX 0:efd786b99a72 771 uid->size = 3 * cascadeLevel + 1;
AtomX 0:efd786b99a72 772
AtomX 0:efd786b99a72 773 return STATUS_OK;
AtomX 0:efd786b99a72 774 } // End PICC_Select()
AtomX 0:efd786b99a72 775
AtomX 0:efd786b99a72 776 /**
AtomX 0:efd786b99a72 777 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
AtomX 0:efd786b99a72 778 *
AtomX 0:efd786b99a72 779 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 780 */
AtomX 0:efd786b99a72 781 uint8_t MFRC522::PICC_HaltA()
AtomX 0:efd786b99a72 782 {
AtomX 0:efd786b99a72 783 uint8_t result;
AtomX 0:efd786b99a72 784 uint8_t buffer[4];
AtomX 0:efd786b99a72 785
AtomX 0:efd786b99a72 786 // Build command buffer
AtomX 0:efd786b99a72 787 buffer[0] = PICC_CMD_HLTA;
AtomX 0:efd786b99a72 788 buffer[1] = 0;
AtomX 0:efd786b99a72 789
AtomX 0:efd786b99a72 790 // Calculate CRC_A
AtomX 0:efd786b99a72 791 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
AtomX 0:efd786b99a72 792 if (result == STATUS_OK)
AtomX 0:efd786b99a72 793 {
AtomX 0:efd786b99a72 794 // Send the command.
AtomX 0:efd786b99a72 795 // The standard says:
AtomX 0:efd786b99a72 796 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
AtomX 0:efd786b99a72 797 // HLTA command, this response shall be interpreted as 'not acknowledge'.
AtomX 0:efd786b99a72 798 // We interpret that this way: Only STATUS_TIMEOUT is an success.
AtomX 0:efd786b99a72 799 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
AtomX 0:efd786b99a72 800 if (result == STATUS_TIMEOUT)
AtomX 0:efd786b99a72 801 {
AtomX 0:efd786b99a72 802 result = STATUS_OK;
AtomX 0:efd786b99a72 803 }
AtomX 0:efd786b99a72 804 else if (result == STATUS_OK)
AtomX 0:efd786b99a72 805 { // That is ironically NOT ok in this case ;-)
AtomX 0:efd786b99a72 806 result = STATUS_ERROR;
AtomX 0:efd786b99a72 807 }
AtomX 0:efd786b99a72 808 }
AtomX 0:efd786b99a72 809
AtomX 0:efd786b99a72 810 return result;
AtomX 0:efd786b99a72 811 } // End PICC_HaltA()
AtomX 0:efd786b99a72 812
AtomX 0:efd786b99a72 813
AtomX 0:efd786b99a72 814 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 815 // Functions for communicating with MIFARE PICCs
AtomX 0:efd786b99a72 816 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 817
AtomX 0:efd786b99a72 818 /**
AtomX 0:efd786b99a72 819 * Executes the MFRC522 MFAuthent command.
AtomX 0:efd786b99a72 820 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
AtomX 0:efd786b99a72 821 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
AtomX 0:efd786b99a72 822 * For use with MIFARE Classic PICCs.
AtomX 0:efd786b99a72 823 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
AtomX 0:efd786b99a72 824 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
AtomX 0:efd786b99a72 825 *
AtomX 0:efd786b99a72 826 * All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX 0:efd786b99a72 827 *
AtomX 0:efd786b99a72 828 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
AtomX 0:efd786b99a72 829 */
AtomX 0:efd786b99a72 830 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
AtomX 0:efd786b99a72 831 {
AtomX 0:efd786b99a72 832 uint8_t i, waitIRq = 0x10; // IdleIRq
AtomX 0:efd786b99a72 833
AtomX 0:efd786b99a72 834 // Build command buffer
AtomX 0:efd786b99a72 835 uint8_t sendData[12];
AtomX 0:efd786b99a72 836 sendData[0] = command;
AtomX 0:efd786b99a72 837 sendData[1] = blockAddr;
AtomX 0:efd786b99a72 838
AtomX 0:efd786b99a72 839 for (i = 0; i < MF_KEY_SIZE; i++)
AtomX 0:efd786b99a72 840 { // 6 key bytes
AtomX 0:efd786b99a72 841 sendData[2+i] = key->keyByte[i];
AtomX 0:efd786b99a72 842 }
AtomX 0:efd786b99a72 843
AtomX 0:efd786b99a72 844 for (i = 0; i < 4; i++)
AtomX 0:efd786b99a72 845 { // The first 4 bytes of the UID
AtomX 0:efd786b99a72 846 sendData[8+i] = uid->uidByte[i];
AtomX 0:efd786b99a72 847 }
AtomX 0:efd786b99a72 848
AtomX 0:efd786b99a72 849 // Start the authentication.
AtomX 0:efd786b99a72 850 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
AtomX 0:efd786b99a72 851 } // End PCD_Authenticate()
AtomX 0:efd786b99a72 852
AtomX 0:efd786b99a72 853 /**
AtomX 0:efd786b99a72 854 * Used to exit the PCD from its authenticated state.
AtomX 0:efd786b99a72 855 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
AtomX 0:efd786b99a72 856 */
AtomX 0:efd786b99a72 857 void MFRC522::PCD_StopCrypto1()
AtomX 0:efd786b99a72 858 {
AtomX 0:efd786b99a72 859 // Clear MFCrypto1On bit
AtomX 0:efd786b99a72 860 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
AtomX 0:efd786b99a72 861 } // End PCD_StopCrypto1()
AtomX 0:efd786b99a72 862
AtomX 0:efd786b99a72 863 /**
AtomX 0:efd786b99a72 864 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
AtomX 0:efd786b99a72 865 *
AtomX 0:efd786b99a72 866 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX 0:efd786b99a72 867 *
AtomX 0:efd786b99a72 868 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
AtomX 0:efd786b99a72 869 * The MF0ICU1 returns a NAK for higher addresses.
AtomX 0:efd786b99a72 870 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
AtomX 0:efd786b99a72 871 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
AtomX 0:efd786b99a72 872 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
AtomX 0:efd786b99a72 873 *
AtomX 0:efd786b99a72 874 * The buffer must be at least 18 bytes because a CRC_A is also returned.
AtomX 0:efd786b99a72 875 * Checks the CRC_A before returning STATUS_OK.
AtomX 0:efd786b99a72 876 *
AtomX 0:efd786b99a72 877 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 878 */
AtomX 0:efd786b99a72 879 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
AtomX 0:efd786b99a72 880 {
AtomX 0:efd786b99a72 881 uint8_t result = STATUS_NO_ROOM;
AtomX 0:efd786b99a72 882
AtomX 0:efd786b99a72 883 // Sanity check
AtomX 0:efd786b99a72 884 if ((buffer == NULL) || (*bufferSize < 18))
AtomX 0:efd786b99a72 885 {
AtomX 0:efd786b99a72 886 return result;
AtomX 0:efd786b99a72 887 }
AtomX 0:efd786b99a72 888
AtomX 0:efd786b99a72 889 // Build command buffer
AtomX 0:efd786b99a72 890 buffer[0] = PICC_CMD_MF_READ;
AtomX 0:efd786b99a72 891 buffer[1] = blockAddr;
AtomX 0:efd786b99a72 892
AtomX 0:efd786b99a72 893 // Calculate CRC_A
AtomX 0:efd786b99a72 894 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
AtomX 0:efd786b99a72 895 if (result != STATUS_OK)
AtomX 0:efd786b99a72 896 {
AtomX 0:efd786b99a72 897 return result;
AtomX 0:efd786b99a72 898 }
AtomX 0:efd786b99a72 899
AtomX 0:efd786b99a72 900 // Transmit the buffer and receive the response, validate CRC_A.
AtomX 0:efd786b99a72 901 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
AtomX 0:efd786b99a72 902 } // End MIFARE_Read()
AtomX 0:efd786b99a72 903
AtomX 0:efd786b99a72 904 /**
AtomX 0:efd786b99a72 905 * Writes 16 bytes to the active PICC.
AtomX 0:efd786b99a72 906 *
AtomX 0:efd786b99a72 907 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX 0:efd786b99a72 908 *
AtomX 0:efd786b99a72 909 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
AtomX 0:efd786b99a72 910 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
AtomX 0:efd786b99a72 911 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
AtomX 0:efd786b99a72 912 * *
AtomX 0:efd786b99a72 913 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 914 */
AtomX 0:efd786b99a72 915 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
AtomX 0:efd786b99a72 916 {
AtomX 0:efd786b99a72 917 uint8_t result;
AtomX 0:efd786b99a72 918
AtomX 0:efd786b99a72 919 // Sanity check
AtomX 0:efd786b99a72 920 if (buffer == NULL || bufferSize < 16)
AtomX 0:efd786b99a72 921 {
AtomX 0:efd786b99a72 922 return STATUS_INVALID;
AtomX 0:efd786b99a72 923 }
AtomX 0:efd786b99a72 924
AtomX 0:efd786b99a72 925 // Mifare Classic protocol requires two communications to perform a write.
AtomX 0:efd786b99a72 926 // Step 1: Tell the PICC we want to write to block blockAddr.
AtomX 0:efd786b99a72 927 uint8_t cmdBuffer[2];
AtomX 0:efd786b99a72 928 cmdBuffer[0] = PICC_CMD_MF_WRITE;
AtomX 0:efd786b99a72 929 cmdBuffer[1] = blockAddr;
AtomX 0:efd786b99a72 930 // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:efd786b99a72 931 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
AtomX 0:efd786b99a72 932 if (result != STATUS_OK)
AtomX 0:efd786b99a72 933 {
AtomX 0:efd786b99a72 934 return result;
AtomX 0:efd786b99a72 935 }
AtomX 0:efd786b99a72 936
AtomX 0:efd786b99a72 937 // Step 2: Transfer the data
AtomX 0:efd786b99a72 938 // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:efd786b99a72 939 result = PCD_MIFARE_Transceive(buffer, bufferSize);
AtomX 0:efd786b99a72 940 if (result != STATUS_OK)
AtomX 0:efd786b99a72 941 {
AtomX 0:efd786b99a72 942 return result;
AtomX 0:efd786b99a72 943 }
AtomX 0:efd786b99a72 944
AtomX 0:efd786b99a72 945 return STATUS_OK;
AtomX 0:efd786b99a72 946 } // End MIFARE_Write()
AtomX 0:efd786b99a72 947
AtomX 0:efd786b99a72 948 /**
AtomX 0:efd786b99a72 949 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
AtomX 0:efd786b99a72 950 *
AtomX 0:efd786b99a72 951 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 952 */
AtomX 0:efd786b99a72 953 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
AtomX 0:efd786b99a72 954 {
AtomX 0:efd786b99a72 955 uint8_t result;
AtomX 0:efd786b99a72 956
AtomX 0:efd786b99a72 957 // Sanity check
AtomX 0:efd786b99a72 958 if (buffer == NULL || bufferSize < 4)
AtomX 0:efd786b99a72 959 {
AtomX 0:efd786b99a72 960 return STATUS_INVALID;
AtomX 0:efd786b99a72 961 }
AtomX 0:efd786b99a72 962
AtomX 0:efd786b99a72 963 // Build commmand buffer
AtomX 0:efd786b99a72 964 uint8_t cmdBuffer[6];
AtomX 0:efd786b99a72 965 cmdBuffer[0] = PICC_CMD_UL_WRITE;
AtomX 0:efd786b99a72 966 cmdBuffer[1] = page;
AtomX 0:efd786b99a72 967 memcpy(&cmdBuffer[2], buffer, 4);
AtomX 0:efd786b99a72 968
AtomX 0:efd786b99a72 969 // Perform the write
AtomX 0:efd786b99a72 970 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:efd786b99a72 971 if (result != STATUS_OK)
AtomX 0:efd786b99a72 972 {
AtomX 0:efd786b99a72 973 return result;
AtomX 0:efd786b99a72 974 }
AtomX 0:efd786b99a72 975
AtomX 0:efd786b99a72 976 return STATUS_OK;
AtomX 0:efd786b99a72 977 } // End MIFARE_Ultralight_Write()
AtomX 0:efd786b99a72 978
AtomX 0:efd786b99a72 979 /**
AtomX 0:efd786b99a72 980 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
AtomX 0:efd786b99a72 981 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:efd786b99a72 982 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:efd786b99a72 983 * Use MIFARE_Transfer() to store the result in a block.
AtomX 0:efd786b99a72 984 *
AtomX 0:efd786b99a72 985 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 986 */
AtomX 0:efd786b99a72 987 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
AtomX 0:efd786b99a72 988 {
AtomX 0:efd786b99a72 989 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
AtomX 0:efd786b99a72 990 } // End MIFARE_Decrement()
AtomX 0:efd786b99a72 991
AtomX 0:efd786b99a72 992 /**
AtomX 0:efd786b99a72 993 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
AtomX 0:efd786b99a72 994 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:efd786b99a72 995 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:efd786b99a72 996 * Use MIFARE_Transfer() to store the result in a block.
AtomX 0:efd786b99a72 997 *
AtomX 0:efd786b99a72 998 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 999 */
AtomX 0:efd786b99a72 1000 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
AtomX 0:efd786b99a72 1001 {
AtomX 0:efd786b99a72 1002 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
AtomX 0:efd786b99a72 1003 } // End MIFARE_Increment()
AtomX 0:efd786b99a72 1004
AtomX 0:efd786b99a72 1005 /**
AtomX 0:efd786b99a72 1006 * MIFARE Restore copies the value of the addressed block into a volatile memory.
AtomX 0:efd786b99a72 1007 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:efd786b99a72 1008 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:efd786b99a72 1009 * Use MIFARE_Transfer() to store the result in a block.
AtomX 0:efd786b99a72 1010 *
AtomX 0:efd786b99a72 1011 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 1012 */
AtomX 0:efd786b99a72 1013 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
AtomX 0:efd786b99a72 1014 {
AtomX 0:efd786b99a72 1015 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
AtomX 0:efd786b99a72 1016 // Doing only a single step does not work, so I chose to transfer 0L in step two.
AtomX 0:efd786b99a72 1017 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
AtomX 0:efd786b99a72 1018 } // End MIFARE_Restore()
AtomX 0:efd786b99a72 1019
AtomX 0:efd786b99a72 1020 /**
AtomX 0:efd786b99a72 1021 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
AtomX 0:efd786b99a72 1022 *
AtomX 0:efd786b99a72 1023 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 1024 */
AtomX 0:efd786b99a72 1025 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
AtomX 0:efd786b99a72 1026 {
AtomX 0:efd786b99a72 1027 uint8_t result;
AtomX 0:efd786b99a72 1028 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
AtomX 0:efd786b99a72 1029
AtomX 0:efd786b99a72 1030 // Step 1: Tell the PICC the command and block address
AtomX 0:efd786b99a72 1031 cmdBuffer[0] = command;
AtomX 0:efd786b99a72 1032 cmdBuffer[1] = blockAddr;
AtomX 0:efd786b99a72 1033
AtomX 0:efd786b99a72 1034 // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:efd786b99a72 1035 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
AtomX 0:efd786b99a72 1036 if (result != STATUS_OK)
AtomX 0:efd786b99a72 1037 {
AtomX 0:efd786b99a72 1038 return result;
AtomX 0:efd786b99a72 1039 }
AtomX 0:efd786b99a72 1040
AtomX 0:efd786b99a72 1041 // Step 2: Transfer the data
AtomX 0:efd786b99a72 1042 // Adds CRC_A and accept timeout as success.
AtomX 0:efd786b99a72 1043 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
AtomX 0:efd786b99a72 1044 if (result != STATUS_OK)
AtomX 0:efd786b99a72 1045 {
AtomX 0:efd786b99a72 1046 return result;
AtomX 0:efd786b99a72 1047 }
AtomX 0:efd786b99a72 1048
AtomX 0:efd786b99a72 1049 return STATUS_OK;
AtomX 0:efd786b99a72 1050 } // End MIFARE_TwoStepHelper()
AtomX 0:efd786b99a72 1051
AtomX 0:efd786b99a72 1052 /**
AtomX 0:efd786b99a72 1053 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
AtomX 0:efd786b99a72 1054 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:efd786b99a72 1055 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:efd786b99a72 1056 *
AtomX 0:efd786b99a72 1057 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 1058 */
AtomX 0:efd786b99a72 1059 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
AtomX 0:efd786b99a72 1060 {
AtomX 0:efd786b99a72 1061 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
AtomX 0:efd786b99a72 1062
AtomX 0:efd786b99a72 1063 // Tell the PICC we want to transfer the result into block blockAddr.
AtomX 0:efd786b99a72 1064 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
AtomX 0:efd786b99a72 1065 cmdBuffer[1] = blockAddr;
AtomX 0:efd786b99a72 1066
AtomX 0:efd786b99a72 1067 // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:efd786b99a72 1068 return PCD_MIFARE_Transceive(cmdBuffer, 2);
AtomX 0:efd786b99a72 1069 } // End MIFARE_Transfer()
AtomX 0:efd786b99a72 1070
AtomX 0:efd786b99a72 1071
AtomX 0:efd786b99a72 1072 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 1073 // Support functions
AtomX 0:efd786b99a72 1074 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 1075
AtomX 0:efd786b99a72 1076 /**
AtomX 0:efd786b99a72 1077 * Wrapper for MIFARE protocol communication.
AtomX 0:efd786b99a72 1078 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
AtomX 0:efd786b99a72 1079 *
AtomX 0:efd786b99a72 1080 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:efd786b99a72 1081 */
AtomX 0:efd786b99a72 1082 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
AtomX 0:efd786b99a72 1083 {
AtomX 0:efd786b99a72 1084 uint8_t result;
AtomX 0:efd786b99a72 1085 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
AtomX 0:efd786b99a72 1086
AtomX 0:efd786b99a72 1087 // Sanity check
AtomX 0:efd786b99a72 1088 if (sendData == NULL || sendLen > 16)
AtomX 0:efd786b99a72 1089 {
AtomX 0:efd786b99a72 1090 return STATUS_INVALID;
AtomX 0:efd786b99a72 1091 }
AtomX 0:efd786b99a72 1092
AtomX 0:efd786b99a72 1093 // Copy sendData[] to cmdBuffer[] and add CRC_A
AtomX 0:efd786b99a72 1094 memcpy(cmdBuffer, sendData, sendLen);
AtomX 0:efd786b99a72 1095 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
AtomX 0:efd786b99a72 1096 if (result != STATUS_OK)
AtomX 0:efd786b99a72 1097 {
AtomX 0:efd786b99a72 1098 return result;
AtomX 0:efd786b99a72 1099 }
AtomX 0:efd786b99a72 1100
AtomX 0:efd786b99a72 1101 sendLen += 2;
AtomX 0:efd786b99a72 1102
AtomX 0:efd786b99a72 1103 // Transceive the data, store the reply in cmdBuffer[]
AtomX 0:efd786b99a72 1104 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
AtomX 0:efd786b99a72 1105 uint8_t cmdBufferSize = sizeof(cmdBuffer);
AtomX 0:efd786b99a72 1106 uint8_t validBits = 0;
AtomX 0:efd786b99a72 1107 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
AtomX 0:efd786b99a72 1108 if (acceptTimeout && result == STATUS_TIMEOUT)
AtomX 0:efd786b99a72 1109 {
AtomX 0:efd786b99a72 1110 return STATUS_OK;
AtomX 0:efd786b99a72 1111 }
AtomX 0:efd786b99a72 1112
AtomX 0:efd786b99a72 1113 if (result != STATUS_OK)
AtomX 0:efd786b99a72 1114 {
AtomX 0:efd786b99a72 1115 return result;
AtomX 0:efd786b99a72 1116 }
AtomX 0:efd786b99a72 1117
AtomX 0:efd786b99a72 1118 // The PICC must reply with a 4 bit ACK
AtomX 0:efd786b99a72 1119 if (cmdBufferSize != 1 || validBits != 4)
AtomX 0:efd786b99a72 1120 {
AtomX 0:efd786b99a72 1121 return STATUS_ERROR;
AtomX 0:efd786b99a72 1122 }
AtomX 0:efd786b99a72 1123
AtomX 0:efd786b99a72 1124 if (cmdBuffer[0] != MF_ACK)
AtomX 0:efd786b99a72 1125 {
AtomX 0:efd786b99a72 1126 return STATUS_MIFARE_NACK;
AtomX 0:efd786b99a72 1127 }
AtomX 0:efd786b99a72 1128
AtomX 0:efd786b99a72 1129 return STATUS_OK;
AtomX 0:efd786b99a72 1130 } // End PCD_MIFARE_Transceive()
AtomX 0:efd786b99a72 1131
AtomX 0:efd786b99a72 1132
AtomX 0:efd786b99a72 1133 /**
AtomX 0:efd786b99a72 1134 * Translates the SAK (Select Acknowledge) to a PICC type.
AtomX 0:efd786b99a72 1135 *
AtomX 0:efd786b99a72 1136 * @return PICC_Type
AtomX 0:efd786b99a72 1137 */
AtomX 0:efd786b99a72 1138 uint8_t MFRC522::PICC_GetType(uint8_t sak)
AtomX 0:efd786b99a72 1139 {
AtomX 0:efd786b99a72 1140 uint8_t retType = PICC_TYPE_UNKNOWN;
AtomX 0:efd786b99a72 1141
AtomX 0:efd786b99a72 1142 if (sak & 0x04)
AtomX 0:efd786b99a72 1143 { // UID not complete
AtomX 0:efd786b99a72 1144 retType = PICC_TYPE_NOT_COMPLETE;
AtomX 0:efd786b99a72 1145 }
AtomX 0:efd786b99a72 1146 else
AtomX 0:efd786b99a72 1147 {
AtomX 0:efd786b99a72 1148 switch (sak)
AtomX 0:efd786b99a72 1149 {
AtomX 0:efd786b99a72 1150 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
AtomX 0:efd786b99a72 1151 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
AtomX 0:efd786b99a72 1152 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
AtomX 0:efd786b99a72 1153 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
AtomX 0:efd786b99a72 1154 case 0x10:
AtomX 0:efd786b99a72 1155 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
AtomX 0:efd786b99a72 1156 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
AtomX 0:efd786b99a72 1157 default:
AtomX 0:efd786b99a72 1158 if (sak & 0x20)
AtomX 0:efd786b99a72 1159 {
AtomX 0:efd786b99a72 1160 retType = PICC_TYPE_ISO_14443_4;
AtomX 0:efd786b99a72 1161 }
AtomX 0:efd786b99a72 1162 else if (sak & 0x40)
AtomX 0:efd786b99a72 1163 {
AtomX 0:efd786b99a72 1164 retType = PICC_TYPE_ISO_18092;
AtomX 0:efd786b99a72 1165 }
AtomX 0:efd786b99a72 1166 break;
AtomX 0:efd786b99a72 1167 }
AtomX 0:efd786b99a72 1168 }
AtomX 0:efd786b99a72 1169
AtomX 0:efd786b99a72 1170 return (retType);
AtomX 0:efd786b99a72 1171 } // End PICC_GetType()
AtomX 0:efd786b99a72 1172
AtomX 0:efd786b99a72 1173 /**
AtomX 0:efd786b99a72 1174 * Returns a string pointer to the PICC type name.
AtomX 0:efd786b99a72 1175 *
AtomX 0:efd786b99a72 1176 */
AtomX 0:efd786b99a72 1177 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
AtomX 0:efd786b99a72 1178 {
AtomX 0:efd786b99a72 1179 if(piccType == PICC_TYPE_NOT_COMPLETE)
AtomX 0:efd786b99a72 1180 {
AtomX 0:efd786b99a72 1181 piccType = MFRC522_MaxPICCs - 1;
AtomX 0:efd786b99a72 1182 }
AtomX 0:efd786b99a72 1183
AtomX 0:efd786b99a72 1184 return((char *) _TypeNamePICC[piccType]);
AtomX 0:efd786b99a72 1185 } // End PICC_GetTypeName()
AtomX 0:efd786b99a72 1186
AtomX 0:efd786b99a72 1187 /**
AtomX 0:efd786b99a72 1188 * Returns a string pointer to a status code name.
AtomX 0:efd786b99a72 1189 *
AtomX 0:efd786b99a72 1190 */
AtomX 0:efd786b99a72 1191 char* MFRC522::GetStatusCodeName(uint8_t code)
AtomX 0:efd786b99a72 1192 {
AtomX 0:efd786b99a72 1193 return((char *) _ErrorMessage[code]);
AtomX 0:efd786b99a72 1194 } // End GetStatusCodeName()
AtomX 0:efd786b99a72 1195
AtomX 0:efd786b99a72 1196 /**
AtomX 0:efd786b99a72 1197 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
AtomX 0:efd786b99a72 1198 */
AtomX 0:efd786b99a72 1199 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer, ///< Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
AtomX 0:efd786b99a72 1200 uint8_t g0, ///< Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
AtomX 0:efd786b99a72 1201 uint8_t g1, ///< Access bits C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
AtomX 0:efd786b99a72 1202 uint8_t g2, ///< Access bits C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
AtomX 0:efd786b99a72 1203 uint8_t g3) ///< Access bits C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
AtomX 0:efd786b99a72 1204 {
AtomX 0:efd786b99a72 1205 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
AtomX 0:efd786b99a72 1206 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
AtomX 0:efd786b99a72 1207 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
AtomX 0:efd786b99a72 1208
AtomX 0:efd786b99a72 1209 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
AtomX 0:efd786b99a72 1210 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
AtomX 0:efd786b99a72 1211 accessBitBuffer[2] = c3 << 4 | c2;
AtomX 0:efd786b99a72 1212 } // End MIFARE_SetAccessBits()
AtomX 0:efd786b99a72 1213
AtomX 0:efd786b99a72 1214 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 1215 // Convenience functions - does not add extra functionality
AtomX 0:efd786b99a72 1216 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:efd786b99a72 1217
AtomX 0:efd786b99a72 1218 /**
AtomX 0:efd786b99a72 1219 * Returns true if a PICC responds to PICC_CMD_REQA.
AtomX 0:efd786b99a72 1220 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
AtomX 0:efd786b99a72 1221 *
AtomX 0:efd786b99a72 1222 * @return bool
AtomX 0:efd786b99a72 1223 */
AtomX 0:efd786b99a72 1224 bool MFRC522::PICC_IsNewCardPresent(void)
AtomX 0:efd786b99a72 1225 {
AtomX 0:efd786b99a72 1226 uint8_t bufferATQA[2];
AtomX 0:efd786b99a72 1227 uint8_t bufferSize = sizeof(bufferATQA);
AtomX 0:efd786b99a72 1228 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
AtomX 0:efd786b99a72 1229 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
AtomX 0:efd786b99a72 1230 } // End PICC_IsNewCardPresent()
AtomX 0:efd786b99a72 1231
AtomX 0:efd786b99a72 1232 /**
AtomX 0:efd786b99a72 1233 * Simple wrapper around PICC_Select.
AtomX 0:efd786b99a72 1234 * Returns true if a UID could be read.
AtomX 0:efd786b99a72 1235 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
AtomX 0:efd786b99a72 1236 * The read UID is available in the class variable uid.
AtomX 0:efd786b99a72 1237 *
AtomX 0:efd786b99a72 1238 * @return bool
AtomX 0:efd786b99a72 1239 */
AtomX 0:efd786b99a72 1240 bool MFRC522::PICC_ReadCardSerial(void)
AtomX 0:efd786b99a72 1241 {
AtomX 0:efd786b99a72 1242 uint8_t result = PICC_Select(&uid);
AtomX 0:efd786b99a72 1243 return (result == STATUS_OK);
AtomX 0:efd786b99a72 1244 } // End PICC_ReadCardSerial()