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Dependencies:   mbed

EncoderCounter.cpp@3:4db174c9e441, 2020-03-25 (annotated)

Committer:
zimmeer1
Date:
Wed Mar 25 16:12:12 2020 +0000
Revision:
3:4db174c9e441
Parent:
0:d8d297847268 
works;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
koenithi 0:d8d297847268 1 /*
koenithi 0:d8d297847268 2 * EncoderCounter.cpp
koenithi 0:d8d297847268 3 * Copyright (c) 2020, ZHAW
koenithi 0:d8d297847268 4 * All rights reserved.
koenithi 0:d8d297847268 5 */
koenithi 0:d8d297847268 6
koenithi 0:d8d297847268 7 #include "EncoderCounter.h"
koenithi 0:d8d297847268 8
koenithi 0:d8d297847268 9 using namespace std;
koenithi 0:d8d297847268 10
koenithi 0:d8d297847268 11 /**
koenithi 0:d8d297847268 12 * Creates and initialises the driver to read the quadrature
koenithi 0:d8d297847268 13 * encoder counter of the STM32 microcontroller.
koenithi 0:d8d297847268 14 * @param a the input pin for the channel A.
koenithi 0:d8d297847268 15 * @param b the input pin for the channel B.
koenithi 0:d8d297847268 16 */
koenithi 0:d8d297847268 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
koenithi 0:d8d297847268 18
koenithi 0:d8d297847268 19 // check pins
koenithi 0:d8d297847268 20
koenithi 0:d8d297847268 21 if ((a == PA_15) && (b == PB_3)) {
koenithi 0:d8d297847268 22
koenithi 0:d8d297847268 23 // pinmap OK for TIM2 CH1 and CH2
koenithi 0:d8d297847268 24
koenithi 0:d8d297847268 25 TIM = TIM2;
koenithi 0:d8d297847268 26
koenithi 0:d8d297847268 27 // configure reset and clock control registers
koenithi 0:d8d297847268 28
koenithi 0:d8d297847268 29 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
koenithi 0:d8d297847268 30
koenithi 0:d8d297847268 31 // configure general purpose I/O registers
koenithi 0:d8d297847268 32
koenithi 0:d8d297847268 33 GPIOA->MODER &= ~GPIO_MODER_MODER15; // reset port A15
koenithi 0:d8d297847268 34 GPIOA->MODER |= GPIO_MODER_MODER15_1; // set alternate mode of port A15
koenithi 0:d8d297847268 35 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR15; // reset pull-up/pull-down on port A15
koenithi 0:d8d297847268 36 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR15_1; // set input as pull-down
koenithi 0:d8d297847268 37 GPIOA->AFR[1] &= ~0xF0000000; // reset alternate function of port A15
koenithi 0:d8d297847268 38 GPIOA->AFR[1] |= 1 << 4*7; // set alternate funtion 1 of port A15
koenithi 0:d8d297847268 39
koenithi 0:d8d297847268 40 GPIOB->MODER &= ~GPIO_MODER_MODER3; // reset port B3
koenithi 0:d8d297847268 41 GPIOB->MODER |= GPIO_MODER_MODER3_1; // set alternate mode of port B3
koenithi 0:d8d297847268 42 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR3; // reset pull-up/pull-down on port B3
koenithi 0:d8d297847268 43 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR3_1; // set input as pull-down
koenithi 0:d8d297847268 44 GPIOB->AFR[0] &= ~(0xF << 4*3); // reset alternate function of port B3
koenithi 0:d8d297847268 45 GPIOB->AFR[0] |= 1 << 4*3; // set alternate funtion 1 of port B3
koenithi 0:d8d297847268 46
koenithi 0:d8d297847268 47 // configure reset and clock control registers
koenithi 0:d8d297847268 48
koenithi 0:d8d297847268 49 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
koenithi 0:d8d297847268 50 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
koenithi 0:d8d297847268 51
koenithi 0:d8d297847268 52 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
koenithi 0:d8d297847268 53
koenithi 0:d8d297847268 54 } else if ((a == PB_4) && (b == PC_7)) {
koenithi 0:d8d297847268 55
koenithi 0:d8d297847268 56 // pinmap OK for TIM3 CH1 and CH2
koenithi 0:d8d297847268 57
koenithi 0:d8d297847268 58 TIM = TIM3;
koenithi 0:d8d297847268 59
koenithi 0:d8d297847268 60 // configure reset and clock control registers
koenithi 0:d8d297847268 61
koenithi 0:d8d297847268 62 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B
koenithi 0:d8d297847268 63 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C
koenithi 0:d8d297847268 64
koenithi 0:d8d297847268 65 // configure general purpose I/O registers
koenithi 0:d8d297847268 66
koenithi 0:d8d297847268 67 GPIOB->MODER &= ~GPIO_MODER_MODER4; // reset port B4
koenithi 0:d8d297847268 68 GPIOB->MODER |= GPIO_MODER_MODER4_1; // set alternate mode of port B4
koenithi 0:d8d297847268 69 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR4; // reset pull-up/pull-down on port B4
koenithi 0:d8d297847268 70 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR4_1; // set input as pull-down
koenithi 0:d8d297847268 71 GPIOB->AFR[0] &= ~(0xF << 4*4); // reset alternate function of port B4
koenithi 0:d8d297847268 72 GPIOB->AFR[0] |= 2 << 4*4; // set alternate funtion 2 of port B4
koenithi 0:d8d297847268 73
koenithi 0:d8d297847268 74 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
koenithi 0:d8d297847268 75 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
koenithi 0:d8d297847268 76 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
koenithi 0:d8d297847268 77 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
koenithi 0:d8d297847268 78 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
koenithi 0:d8d297847268 79 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
koenithi 0:d8d297847268 80
koenithi 0:d8d297847268 81 // configure reset and clock control registers
koenithi 0:d8d297847268 82
koenithi 0:d8d297847268 83 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
koenithi 0:d8d297847268 84 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
koenithi 0:d8d297847268 85
koenithi 0:d8d297847268 86 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
koenithi 0:d8d297847268 87
koenithi 0:d8d297847268 88 } else if ((a == PD_12) && (b == PD_13)) {
koenithi 0:d8d297847268 89
koenithi 0:d8d297847268 90 // pinmap OK for TIM4 CH1 and CH2
koenithi 0:d8d297847268 91
koenithi 0:d8d297847268 92 TIM = TIM4;
koenithi 0:d8d297847268 93
koenithi 0:d8d297847268 94 // configure reset and clock control registers
koenithi 0:d8d297847268 95
koenithi 0:d8d297847268 96 RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; // manually enable port D
koenithi 0:d8d297847268 97
koenithi 0:d8d297847268 98 // configure general purpose I/O registers
koenithi 0:d8d297847268 99
koenithi 0:d8d297847268 100 GPIOD->MODER &= ~GPIO_MODER_MODER12; // reset port D12
koenithi 0:d8d297847268 101 GPIOD->MODER |= GPIO_MODER_MODER12_1; // set alternate mode of port D12
koenithi 0:d8d297847268 102 GPIOD->PUPDR &= ~GPIO_PUPDR_PUPDR12; // reset pull-up/pull-down on port D12
koenithi 0:d8d297847268 103 GPIOD->PUPDR |= GPIO_PUPDR_PUPDR12_1; // set input as pull-down
koenithi 0:d8d297847268 104 GPIOD->AFR[1] &= ~(0xF << 4*4); // reset alternate function of port D12
koenithi 0:d8d297847268 105 GPIOD->AFR[1] |= 2 << 4*4; // set alternate funtion 2 of port D12
koenithi 0:d8d297847268 106
koenithi 0:d8d297847268 107 GPIOD->MODER &= ~GPIO_MODER_MODER13; // reset port D13
koenithi 0:d8d297847268 108 GPIOD->MODER |= GPIO_MODER_MODER13_1; // set alternate mode of port D13
koenithi 0:d8d297847268 109 GPIOD->PUPDR &= ~GPIO_PUPDR_PUPDR13; // reset pull-up/pull-down on port D13
koenithi 0:d8d297847268 110 GPIOD->PUPDR |= GPIO_PUPDR_PUPDR13_1; // set input as pull-down
koenithi 0:d8d297847268 111 GPIOD->AFR[1] &= ~(0xF << 4*5); // reset alternate function of port D13
koenithi 0:d8d297847268 112 GPIOD->AFR[1] |= 2 << 4*5; // set alternate funtion 2 of port D13
koenithi 0:d8d297847268 113
koenithi 0:d8d297847268 114 // configure reset and clock control registers
koenithi 0:d8d297847268 115
koenithi 0:d8d297847268 116 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
koenithi 0:d8d297847268 117 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
koenithi 0:d8d297847268 118
koenithi 0:d8d297847268 119 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
koenithi 0:d8d297847268 120
koenithi 0:d8d297847268 121 } else {
koenithi 0:d8d297847268 122
koenithi 0:d8d297847268 123 printf("pinmap not found for peripheral\n");
koenithi 0:d8d297847268 124
koenithi 0:d8d297847268 125 TIM = NULL;
koenithi 0:d8d297847268 126 }
koenithi 0:d8d297847268 127
koenithi 0:d8d297847268 128 // configure general purpose timer 2, 3 or 4
koenithi 0:d8d297847268 129
koenithi 0:d8d297847268 130 if (TIM != NULL) {
koenithi 0:d8d297847268 131
koenithi 0:d8d297847268 132 TIM->CR1 = 0x0000; // counter disable
koenithi 0:d8d297847268 133 TIM->CR2 = 0x0000; // reset master mode selection
koenithi 0:d8d297847268 134 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
koenithi 0:d8d297847268 135 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
koenithi 0:d8d297847268 136 TIM->CCMR2 = 0x0000; // reset capture mode register 2
koenithi 0:d8d297847268 137 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
koenithi 0:d8d297847268 138 TIM->CNT = 0x0000; // reset counter value
koenithi 0:d8d297847268 139 TIM->ARR = 0xFFFF; // auto reload register
koenithi 0:d8d297847268 140 TIM->CR1 = TIM_CR1_CEN; // counter enable
koenithi 0:d8d297847268 141 }
koenithi 0:d8d297847268 142 }
koenithi 0:d8d297847268 143
koenithi 0:d8d297847268 144 /**
koenithi 0:d8d297847268 145 * Deletes this EncoderCounter object.
koenithi 0:d8d297847268 146 */
koenithi 0:d8d297847268 147 EncoderCounter::~EncoderCounter() {}
koenithi 0:d8d297847268 148
koenithi 0:d8d297847268 149 /**
koenithi 0:d8d297847268 150 * Resets the counter value to zero.
koenithi 0:d8d297847268 151 */
koenithi 0:d8d297847268 152 void EncoderCounter::reset() {
koenithi 0:d8d297847268 153
koenithi 0:d8d297847268 154 TIM->CNT = 0x0000;
koenithi 0:d8d297847268 155 }
koenithi 0:d8d297847268 156
koenithi 0:d8d297847268 157 /**
koenithi 0:d8d297847268 158 * Resets the counter value to a given offset value.
koenithi 0:d8d297847268 159 * @param offset the offset value to reset the counter to.
koenithi 0:d8d297847268 160 */
koenithi 0:d8d297847268 161 void EncoderCounter::reset(short offset) {
koenithi 0:d8d297847268 162
koenithi 0:d8d297847268 163 TIM->CNT = -offset;
koenithi 0:d8d297847268 164 }
koenithi 0:d8d297847268 165
koenithi 0:d8d297847268 166 /**
koenithi 0:d8d297847268 167 * Reads the quadrature encoder counter value.
koenithi 0:d8d297847268 168 * @return the quadrature encoder counter as a signed 16-bit integer value.
koenithi 0:d8d297847268 169 */
koenithi 0:d8d297847268 170 short EncoderCounter::read() {
koenithi 0:d8d297847268 171
koenithi 0:d8d297847268 172 return (short)(-TIM->CNT);
koenithi 0:d8d297847268 173 }
koenithi 0:d8d297847268 174
koenithi 0:d8d297847268 175 /**
koenithi 0:d8d297847268 176 * The empty operator is a shorthand notation of the <code>read()</code> method.
koenithi 0:d8d297847268 177 */
koenithi 0:d8d297847268 178 EncoderCounter::operator short() {
koenithi 0:d8d297847268 179
koenithi 0:d8d297847268 180 return read();
koenithi 0:d8d297847268 181 }
koenithi 0:d8d297847268 182