ROME2 / Mbed 2 deprecated ROME2_P5

ROME_P5

Dependencies:   mbed

EncoderCounter.cpp@0:29be10cb0afc, 2018-04-27 (annotated)

Committer:
Inaueadr
Date:
Fri Apr 27 08:47:34 2018 +0000
Revision:
0:29be10cb0afc
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Inaueadr 0:29be10cb0afc 1 /*
Inaueadr 0:29be10cb0afc 2 * EncoderCounter.cpp
Inaueadr 0:29be10cb0afc 3 * Copyright (c) 2018, ZHAW
Inaueadr 0:29be10cb0afc 4 * All rights reserved.
Inaueadr 0:29be10cb0afc 5 */
Inaueadr 0:29be10cb0afc 6
Inaueadr 0:29be10cb0afc 7 #include "EncoderCounter.h"
Inaueadr 0:29be10cb0afc 8
Inaueadr 0:29be10cb0afc 9 using namespace std;
Inaueadr 0:29be10cb0afc 10
Inaueadr 0:29be10cb0afc 11 /**
Inaueadr 0:29be10cb0afc 12 * Creates and initializes the driver to read the quadrature
Inaueadr 0:29be10cb0afc 13 * encoder counter of the STM32 microcontroller.
Inaueadr 0:29be10cb0afc 14 * @param a the input pin for the channel A.
Inaueadr 0:29be10cb0afc 15 * @param b the input pin for the channel B.
Inaueadr 0:29be10cb0afc 16 */
Inaueadr 0:29be10cb0afc 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
Inaueadr 0:29be10cb0afc 18
Inaueadr 0:29be10cb0afc 19 // check pins
Inaueadr 0:29be10cb0afc 20
Inaueadr 0:29be10cb0afc 21 if ((a == PA_0) && (b == PA_1)) {
Inaueadr 0:29be10cb0afc 22
Inaueadr 0:29be10cb0afc 23 // pinmap OK for TIM2 CH1 and CH2
Inaueadr 0:29be10cb0afc 24
Inaueadr 0:29be10cb0afc 25 TIM = TIM2;
Inaueadr 0:29be10cb0afc 26
Inaueadr 0:29be10cb0afc 27 // configure general purpose I/O registers
Inaueadr 0:29be10cb0afc 28
Inaueadr 0:29be10cb0afc 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
Inaueadr 0:29be10cb0afc 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
Inaueadr 0:29be10cb0afc 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
Inaueadr 0:29be10cb0afc 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
Inaueadr 0:29be10cb0afc 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
Inaueadr 0:29be10cb0afc 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
Inaueadr 0:29be10cb0afc 35
Inaueadr 0:29be10cb0afc 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
Inaueadr 0:29be10cb0afc 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
Inaueadr 0:29be10cb0afc 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
Inaueadr 0:29be10cb0afc 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
Inaueadr 0:29be10cb0afc 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
Inaueadr 0:29be10cb0afc 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
Inaueadr 0:29be10cb0afc 42
Inaueadr 0:29be10cb0afc 43 // configure reset and clock control registers
Inaueadr 0:29be10cb0afc 44
Inaueadr 0:29be10cb0afc 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
Inaueadr 0:29be10cb0afc 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
Inaueadr 0:29be10cb0afc 47
Inaueadr 0:29be10cb0afc 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
Inaueadr 0:29be10cb0afc 49
Inaueadr 0:29be10cb0afc 50 } else if ((a == PA_6) && (b == PC_7)) {
Inaueadr 0:29be10cb0afc 51
Inaueadr 0:29be10cb0afc 52 // pinmap OK for TIM3 CH1 and CH2
Inaueadr 0:29be10cb0afc 53
Inaueadr 0:29be10cb0afc 54 TIM = TIM3;
Inaueadr 0:29be10cb0afc 55
Inaueadr 0:29be10cb0afc 56 // configure reset and clock control registers
Inaueadr 0:29be10cb0afc 57
Inaueadr 0:29be10cb0afc 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
Inaueadr 0:29be10cb0afc 59
Inaueadr 0:29be10cb0afc 60 // configure general purpose I/O registers
Inaueadr 0:29be10cb0afc 61
Inaueadr 0:29be10cb0afc 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
Inaueadr 0:29be10cb0afc 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
Inaueadr 0:29be10cb0afc 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
Inaueadr 0:29be10cb0afc 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
Inaueadr 0:29be10cb0afc 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
Inaueadr 0:29be10cb0afc 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
Inaueadr 0:29be10cb0afc 68
Inaueadr 0:29be10cb0afc 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
Inaueadr 0:29be10cb0afc 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
Inaueadr 0:29be10cb0afc 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
Inaueadr 0:29be10cb0afc 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
Inaueadr 0:29be10cb0afc 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
Inaueadr 0:29be10cb0afc 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
Inaueadr 0:29be10cb0afc 75
Inaueadr 0:29be10cb0afc 76 // configure reset and clock control registers
Inaueadr 0:29be10cb0afc 77
Inaueadr 0:29be10cb0afc 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
Inaueadr 0:29be10cb0afc 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
Inaueadr 0:29be10cb0afc 80
Inaueadr 0:29be10cb0afc 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
Inaueadr 0:29be10cb0afc 82
Inaueadr 0:29be10cb0afc 83 } else if ((a == PB_6) && (b == PB_7)) {
Inaueadr 0:29be10cb0afc 84
Inaueadr 0:29be10cb0afc 85 // pinmap OK for TIM4 CH1 and CH2
Inaueadr 0:29be10cb0afc 86
Inaueadr 0:29be10cb0afc 87 TIM = TIM4;
Inaueadr 0:29be10cb0afc 88
Inaueadr 0:29be10cb0afc 89 // configure reset and clock control registers
Inaueadr 0:29be10cb0afc 90
Inaueadr 0:29be10cb0afc 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
Inaueadr 0:29be10cb0afc 92
Inaueadr 0:29be10cb0afc 93 // configure general purpose I/O registers
Inaueadr 0:29be10cb0afc 94
Inaueadr 0:29be10cb0afc 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
Inaueadr 0:29be10cb0afc 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
Inaueadr 0:29be10cb0afc 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
Inaueadr 0:29be10cb0afc 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
Inaueadr 0:29be10cb0afc 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
Inaueadr 0:29be10cb0afc 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
Inaueadr 0:29be10cb0afc 101
Inaueadr 0:29be10cb0afc 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
Inaueadr 0:29be10cb0afc 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
Inaueadr 0:29be10cb0afc 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
Inaueadr 0:29be10cb0afc 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
Inaueadr 0:29be10cb0afc 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
Inaueadr 0:29be10cb0afc 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
Inaueadr 0:29be10cb0afc 108
Inaueadr 0:29be10cb0afc 109 // configure reset and clock control registers
Inaueadr 0:29be10cb0afc 110
Inaueadr 0:29be10cb0afc 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
Inaueadr 0:29be10cb0afc 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
Inaueadr 0:29be10cb0afc 113
Inaueadr 0:29be10cb0afc 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
Inaueadr 0:29be10cb0afc 115
Inaueadr 0:29be10cb0afc 116 } else {
Inaueadr 0:29be10cb0afc 117
Inaueadr 0:29be10cb0afc 118 printf("pinmap not found for peripheral\n");
Inaueadr 0:29be10cb0afc 119 }
Inaueadr 0:29be10cb0afc 120
Inaueadr 0:29be10cb0afc 121 // configure general purpose timer 3 or 4
Inaueadr 0:29be10cb0afc 122
Inaueadr 0:29be10cb0afc 123 TIM->CR1 = 0x0000; // counter disable
Inaueadr 0:29be10cb0afc 124 TIM->CR2 = 0x0000; // reset master mode selection
Inaueadr 0:29be10cb0afc 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
Inaueadr 0:29be10cb0afc 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
Inaueadr 0:29be10cb0afc 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
Inaueadr 0:29be10cb0afc 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
Inaueadr 0:29be10cb0afc 129 TIM->CNT = 0x0000; // reset counter value
Inaueadr 0:29be10cb0afc 130 TIM->ARR = 0xFFFF; // auto reload register
Inaueadr 0:29be10cb0afc 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
Inaueadr 0:29be10cb0afc 132 }
Inaueadr 0:29be10cb0afc 133
Inaueadr 0:29be10cb0afc 134 EncoderCounter::~EncoderCounter() {}
Inaueadr 0:29be10cb0afc 135
Inaueadr 0:29be10cb0afc 136 /**
Inaueadr 0:29be10cb0afc 137 * Resets the counter value to zero.
Inaueadr 0:29be10cb0afc 138 */
Inaueadr 0:29be10cb0afc 139 void EncoderCounter::reset() {
Inaueadr 0:29be10cb0afc 140
Inaueadr 0:29be10cb0afc 141 TIM->CNT = 0x0000;
Inaueadr 0:29be10cb0afc 142 }
Inaueadr 0:29be10cb0afc 143
Inaueadr 0:29be10cb0afc 144 /**
Inaueadr 0:29be10cb0afc 145 * Resets the counter value to a given offset value.
Inaueadr 0:29be10cb0afc 146 * @param offset the offset value to reset the counter to.
Inaueadr 0:29be10cb0afc 147 */
Inaueadr 0:29be10cb0afc 148 void EncoderCounter::reset(short offset) {
Inaueadr 0:29be10cb0afc 149
Inaueadr 0:29be10cb0afc 150 TIM->CNT = -offset;
Inaueadr 0:29be10cb0afc 151 }
Inaueadr 0:29be10cb0afc 152
Inaueadr 0:29be10cb0afc 153 /**
Inaueadr 0:29be10cb0afc 154 * Reads the quadrature encoder counter value.
Inaueadr 0:29be10cb0afc 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
Inaueadr 0:29be10cb0afc 156 */
Inaueadr 0:29be10cb0afc 157 short EncoderCounter::read() {
Inaueadr 0:29be10cb0afc 158
Inaueadr 0:29be10cb0afc 159 return (short)(-TIM->CNT);
Inaueadr 0:29be10cb0afc 160 }
Inaueadr 0:29be10cb0afc 161
Inaueadr 0:29be10cb0afc 162 /**
Inaueadr 0:29be10cb0afc 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
Inaueadr 0:29be10cb0afc 164 */
Inaueadr 0:29be10cb0afc 165 EncoderCounter::operator short() {
Inaueadr 0:29be10cb0afc 166
Inaueadr 0:29be10cb0afc 167 return read();
Inaueadr 0:29be10cb0afc 168 }
Inaueadr 0:29be10cb0afc 169
Inaueadr 0:29be10cb0afc 170