mbed library sources. Supersedes mbed-src.
Fork of mbed by
targets/cmsis/TARGET_Maxim/TARGET_MAX32620/usb_regs.h@148:4802eb17e82b, 2016-10-17 (annotated)
- Committer:
- rodriguise
- Date:
- Mon Oct 17 18:47:01 2016 +0000
- Revision:
- 148:4802eb17e82b
- Parent:
- 144:ef7eb2e8f9f7
backup
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
<> | 144:ef7eb2e8f9f7 | 5 | * copy of this software and associated documentation files (the "Software"), |
<> | 144:ef7eb2e8f9f7 | 6 | * to deal in the Software without restriction, including without limitation |
<> | 144:ef7eb2e8f9f7 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
<> | 144:ef7eb2e8f9f7 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
<> | 144:ef7eb2e8f9f7 | 9 | * Software is furnished to do so, subject to the following conditions: |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * The above copyright notice and this permission notice shall be included |
<> | 144:ef7eb2e8f9f7 | 12 | * in all copies or substantial portions of the Software. |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
<> | 144:ef7eb2e8f9f7 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
<> | 144:ef7eb2e8f9f7 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
<> | 144:ef7eb2e8f9f7 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
<> | 144:ef7eb2e8f9f7 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
<> | 144:ef7eb2e8f9f7 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
<> | 144:ef7eb2e8f9f7 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
<> | 144:ef7eb2e8f9f7 | 24 | * Products, Inc. Branding Policy. |
<> | 144:ef7eb2e8f9f7 | 25 | * |
<> | 144:ef7eb2e8f9f7 | 26 | * The mere transfer of this software does not imply any licenses |
<> | 144:ef7eb2e8f9f7 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
<> | 144:ef7eb2e8f9f7 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
<> | 144:ef7eb2e8f9f7 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
<> | 144:ef7eb2e8f9f7 | 30 | * ownership rights. |
<> | 144:ef7eb2e8f9f7 | 31 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 32 | */ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #ifndef _MXC_USB_REGS_H_ |
<> | 144:ef7eb2e8f9f7 | 35 | #define _MXC_USB_REGS_H_ |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 38 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 39 | #endif |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | #include <stdint.h> |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /* |
<> | 144:ef7eb2e8f9f7 | 44 | If types are not defined elsewhere (CMSIS) define them here |
<> | 144:ef7eb2e8f9f7 | 45 | */ |
<> | 144:ef7eb2e8f9f7 | 46 | #ifndef __IO |
<> | 144:ef7eb2e8f9f7 | 47 | #define __IO volatile |
<> | 144:ef7eb2e8f9f7 | 48 | #endif |
<> | 144:ef7eb2e8f9f7 | 49 | #ifndef __I |
<> | 144:ef7eb2e8f9f7 | 50 | #define __I volatile const |
<> | 144:ef7eb2e8f9f7 | 51 | #endif |
<> | 144:ef7eb2e8f9f7 | 52 | #ifndef __O |
<> | 144:ef7eb2e8f9f7 | 53 | #define __O volatile |
<> | 144:ef7eb2e8f9f7 | 54 | #endif |
<> | 144:ef7eb2e8f9f7 | 55 | #ifndef __I |
<> | 144:ef7eb2e8f9f7 | 56 | #define __I volatile const |
<> | 144:ef7eb2e8f9f7 | 57 | #endif |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | #define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL) |
<> | 144:ef7eb2e8f9f7 | 61 | #define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL) |
<> | 144:ef7eb2e8f9f7 | 62 | #define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL) |
<> | 144:ef7eb2e8f9f7 | 63 | #define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL) |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | #define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS) |
<> | 144:ef7eb2e8f9f7 | 66 | #define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS) |
<> | 144:ef7eb2e8f9f7 | 67 | #define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS) |
<> | 144:ef7eb2e8f9f7 | 68 | #define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS) |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | /* |
<> | 144:ef7eb2e8f9f7 | 71 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
<> | 144:ef7eb2e8f9f7 | 72 | access to each register in module. |
<> | 144:ef7eb2e8f9f7 | 73 | */ |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | /* Offset Register Description |
<> | 144:ef7eb2e8f9f7 | 76 | ============= ============================================================================ */ |
<> | 144:ef7eb2e8f9f7 | 77 | typedef struct { |
<> | 144:ef7eb2e8f9f7 | 78 | __IO uint32_t cn; /* 0x0000 USB Control Register */ |
<> | 144:ef7eb2e8f9f7 | 79 | __I uint32_t rsv004[127]; /* 0x0004-0x01FC */ |
<> | 144:ef7eb2e8f9f7 | 80 | __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */ |
<> | 144:ef7eb2e8f9f7 | 81 | __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */ |
<> | 144:ef7eb2e8f9f7 | 82 | __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 83 | __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */ |
<> | 144:ef7eb2e8f9f7 | 84 | __I uint32_t rsv210[4]; /* 0x0210-0x021C */ |
<> | 144:ef7eb2e8f9f7 | 85 | __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */ |
<> | 144:ef7eb2e8f9f7 | 86 | __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */ |
<> | 144:ef7eb2e8f9f7 | 87 | __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */ |
<> | 144:ef7eb2e8f9f7 | 88 | __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */ |
<> | 144:ef7eb2e8f9f7 | 89 | __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 90 | __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 91 | __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 92 | __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 93 | __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 94 | __I uint32_t rsv244[7]; /* 0x0244-0x025C */ |
<> | 144:ef7eb2e8f9f7 | 95 | __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */ |
<> | 144:ef7eb2e8f9f7 | 96 | __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */ |
<> | 144:ef7eb2e8f9f7 | 97 | __I uint32_t rsv268[6]; /* 0x0268-0x027C */ |
<> | 144:ef7eb2e8f9f7 | 98 | __IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */ |
<> | 144:ef7eb2e8f9f7 | 99 | } mxc_usb_regs_t; |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | /* |
<> | 144:ef7eb2e8f9f7 | 103 | Register offsets for module USB. |
<> | 144:ef7eb2e8f9f7 | 104 | */ |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | #define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL) |
<> | 144:ef7eb2e8f9f7 | 107 | #define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL) |
<> | 144:ef7eb2e8f9f7 | 108 | #define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL) |
<> | 144:ef7eb2e8f9f7 | 109 | #define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL) |
<> | 144:ef7eb2e8f9f7 | 110 | #define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL) |
<> | 144:ef7eb2e8f9f7 | 111 | #define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL) |
<> | 144:ef7eb2e8f9f7 | 112 | #define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL) |
<> | 144:ef7eb2e8f9f7 | 113 | #define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL) |
<> | 144:ef7eb2e8f9f7 | 114 | #define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL) |
<> | 144:ef7eb2e8f9f7 | 115 | #define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL) |
<> | 144:ef7eb2e8f9f7 | 116 | #define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL) |
<> | 144:ef7eb2e8f9f7 | 117 | #define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL) |
<> | 144:ef7eb2e8f9f7 | 118 | #define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL) |
<> | 144:ef7eb2e8f9f7 | 119 | #define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL) |
<> | 144:ef7eb2e8f9f7 | 120 | #define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL) |
<> | 144:ef7eb2e8f9f7 | 121 | #define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL) |
<> | 144:ef7eb2e8f9f7 | 122 | #define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL) |
<> | 144:ef7eb2e8f9f7 | 123 | #define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL) |
<> | 144:ef7eb2e8f9f7 | 124 | #define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL) |
<> | 144:ef7eb2e8f9f7 | 125 | #define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL) |
<> | 144:ef7eb2e8f9f7 | 126 | #define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL) |
<> | 144:ef7eb2e8f9f7 | 127 | #define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL) |
<> | 144:ef7eb2e8f9f7 | 128 | #define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL) |
<> | 144:ef7eb2e8f9f7 | 129 | #define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL) |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | /* |
<> | 144:ef7eb2e8f9f7 | 133 | Field positions and masks for module USB. |
<> | 144:ef7eb2e8f9f7 | 134 | */ |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | #define MXC_F_USB_CN_USB_EN_POS 0 |
<> | 144:ef7eb2e8f9f7 | 137 | #define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS)) |
<> | 144:ef7eb2e8f9f7 | 138 | #define MXC_F_USB_CN_HOST_POS 1 |
<> | 144:ef7eb2e8f9f7 | 139 | #define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS)) |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | #define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0 |
<> | 144:ef7eb2e8f9f7 | 142 | #define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS)) |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | #define MXC_F_USB_DEV_CN_SIGRWU_POS 2 |
<> | 144:ef7eb2e8f9f7 | 145 | #define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS)) |
<> | 144:ef7eb2e8f9f7 | 146 | #define MXC_F_USB_DEV_CN_CONNECT_POS 3 |
<> | 144:ef7eb2e8f9f7 | 147 | #define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS)) |
<> | 144:ef7eb2e8f9f7 | 148 | #define MXC_F_USB_DEV_CN_ULPM_POS 4 |
<> | 144:ef7eb2e8f9f7 | 149 | #define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS)) |
<> | 144:ef7eb2e8f9f7 | 150 | #define MXC_F_USB_DEV_CN_URST_POS 5 |
<> | 144:ef7eb2e8f9f7 | 151 | #define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS)) |
<> | 144:ef7eb2e8f9f7 | 152 | #define MXC_F_USB_DEV_CN_VBGATE_POS 6 |
<> | 144:ef7eb2e8f9f7 | 153 | #define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS)) |
<> | 144:ef7eb2e8f9f7 | 154 | #define MXC_F_USB_DEV_CN_OSCEN_POS 7 |
<> | 144:ef7eb2e8f9f7 | 155 | #define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS)) |
<> | 144:ef7eb2e8f9f7 | 156 | #define MXC_F_USB_DEV_CN_BACT_OE_POS 8 |
<> | 144:ef7eb2e8f9f7 | 157 | #define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS)) |
<> | 144:ef7eb2e8f9f7 | 158 | #define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9 |
<> | 144:ef7eb2e8f9f7 | 159 | #define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS)) |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | #define MXC_F_USB_DEV_INTFL_DPACT_POS 0 |
<> | 144:ef7eb2e8f9f7 | 162 | #define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS)) |
<> | 144:ef7eb2e8f9f7 | 163 | #define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1 |
<> | 144:ef7eb2e8f9f7 | 164 | #define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS)) |
<> | 144:ef7eb2e8f9f7 | 165 | #define MXC_F_USB_DEV_INTFL_BACT_POS 2 |
<> | 144:ef7eb2e8f9f7 | 166 | #define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS)) |
<> | 144:ef7eb2e8f9f7 | 167 | #define MXC_F_USB_DEV_INTFL_BRST_POS 3 |
<> | 144:ef7eb2e8f9f7 | 168 | #define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS)) |
<> | 144:ef7eb2e8f9f7 | 169 | #define MXC_F_USB_DEV_INTFL_SUSP_POS 4 |
<> | 144:ef7eb2e8f9f7 | 170 | #define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS)) |
<> | 144:ef7eb2e8f9f7 | 171 | #define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5 |
<> | 144:ef7eb2e8f9f7 | 172 | #define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS)) |
<> | 144:ef7eb2e8f9f7 | 173 | #define MXC_F_USB_DEV_INTFL_VBUS_POS 6 |
<> | 144:ef7eb2e8f9f7 | 174 | #define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS)) |
<> | 144:ef7eb2e8f9f7 | 175 | #define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7 |
<> | 144:ef7eb2e8f9f7 | 176 | #define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS)) |
<> | 144:ef7eb2e8f9f7 | 177 | #define MXC_F_USB_DEV_INTFL_SETUP_POS 8 |
<> | 144:ef7eb2e8f9f7 | 178 | #define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS)) |
<> | 144:ef7eb2e8f9f7 | 179 | #define MXC_F_USB_DEV_INTFL_EP_IN_POS 9 |
<> | 144:ef7eb2e8f9f7 | 180 | #define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS)) |
<> | 144:ef7eb2e8f9f7 | 181 | #define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10 |
<> | 144:ef7eb2e8f9f7 | 182 | #define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS)) |
<> | 144:ef7eb2e8f9f7 | 183 | #define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11 |
<> | 144:ef7eb2e8f9f7 | 184 | #define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS)) |
<> | 144:ef7eb2e8f9f7 | 185 | #define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12 |
<> | 144:ef7eb2e8f9f7 | 186 | #define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS)) |
<> | 144:ef7eb2e8f9f7 | 187 | #define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13 |
<> | 144:ef7eb2e8f9f7 | 188 | #define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS)) |
<> | 144:ef7eb2e8f9f7 | 189 | #define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16 |
<> | 144:ef7eb2e8f9f7 | 190 | #define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS)) |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | #define MXC_F_USB_DEV_INTEN_DPACT_POS 0 |
<> | 144:ef7eb2e8f9f7 | 193 | #define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS)) |
<> | 144:ef7eb2e8f9f7 | 194 | #define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1 |
<> | 144:ef7eb2e8f9f7 | 195 | #define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS)) |
<> | 144:ef7eb2e8f9f7 | 196 | #define MXC_F_USB_DEV_INTEN_BACT_POS 2 |
<> | 144:ef7eb2e8f9f7 | 197 | #define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS)) |
<> | 144:ef7eb2e8f9f7 | 198 | #define MXC_F_USB_DEV_INTEN_BRST_POS 3 |
<> | 144:ef7eb2e8f9f7 | 199 | #define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS)) |
<> | 144:ef7eb2e8f9f7 | 200 | #define MXC_F_USB_DEV_INTEN_SUSP_POS 4 |
<> | 144:ef7eb2e8f9f7 | 201 | #define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS)) |
<> | 144:ef7eb2e8f9f7 | 202 | #define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5 |
<> | 144:ef7eb2e8f9f7 | 203 | #define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS)) |
<> | 144:ef7eb2e8f9f7 | 204 | #define MXC_F_USB_DEV_INTEN_VBUS_POS 6 |
<> | 144:ef7eb2e8f9f7 | 205 | #define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS)) |
<> | 144:ef7eb2e8f9f7 | 206 | #define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7 |
<> | 144:ef7eb2e8f9f7 | 207 | #define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS)) |
<> | 144:ef7eb2e8f9f7 | 208 | #define MXC_F_USB_DEV_INTEN_SETUP_POS 8 |
<> | 144:ef7eb2e8f9f7 | 209 | #define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS)) |
<> | 144:ef7eb2e8f9f7 | 210 | #define MXC_F_USB_DEV_INTEN_EP_IN_POS 9 |
<> | 144:ef7eb2e8f9f7 | 211 | #define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS)) |
<> | 144:ef7eb2e8f9f7 | 212 | #define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10 |
<> | 144:ef7eb2e8f9f7 | 213 | #define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS)) |
<> | 144:ef7eb2e8f9f7 | 214 | #define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11 |
<> | 144:ef7eb2e8f9f7 | 215 | #define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS)) |
<> | 144:ef7eb2e8f9f7 | 216 | #define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12 |
<> | 144:ef7eb2e8f9f7 | 217 | #define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS)) |
<> | 144:ef7eb2e8f9f7 | 218 | #define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13 |
<> | 144:ef7eb2e8f9f7 | 219 | #define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS)) |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | #define MXC_F_USB_EP_BASE_EP_BASE_POS 9 |
<> | 144:ef7eb2e8f9f7 | 222 | #define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS)) |
<> | 144:ef7eb2e8f9f7 | 223 | |
<> | 144:ef7eb2e8f9f7 | 224 | #define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0 |
<> | 144:ef7eb2e8f9f7 | 225 | #define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS)) |
<> | 144:ef7eb2e8f9f7 | 226 | #define MXC_F_USB_CUR_BUF_IN_BUF_POS 16 |
<> | 144:ef7eb2e8f9f7 | 227 | #define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS)) |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | #define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0 |
<> | 144:ef7eb2e8f9f7 | 230 | #define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS)) |
<> | 144:ef7eb2e8f9f7 | 231 | #define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16 |
<> | 144:ef7eb2e8f9f7 | 232 | #define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS)) |
<> | 144:ef7eb2e8f9f7 | 233 | |
<> | 144:ef7eb2e8f9f7 | 234 | #define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0 |
<> | 144:ef7eb2e8f9f7 | 235 | #define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS)) |
<> | 144:ef7eb2e8f9f7 | 236 | #define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16 |
<> | 144:ef7eb2e8f9f7 | 237 | #define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS)) |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | #define MXC_F_USB_IN_INT_INBAV_POS 0 |
<> | 144:ef7eb2e8f9f7 | 240 | #define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS)) |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | #define MXC_F_USB_OUT_INT_OUTDAV_POS 0 |
<> | 144:ef7eb2e8f9f7 | 243 | #define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS)) |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | #define MXC_F_USB_NAK_INT_NAK_POS 0 |
<> | 144:ef7eb2e8f9f7 | 246 | #define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS)) |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | #define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0 |
<> | 144:ef7eb2e8f9f7 | 249 | #define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS)) |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | #define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0 |
<> | 144:ef7eb2e8f9f7 | 252 | #define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS)) |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | #define MXC_F_USB_SETUP0_BYTE0_POS 0 |
<> | 144:ef7eb2e8f9f7 | 255 | #define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS)) |
<> | 144:ef7eb2e8f9f7 | 256 | #define MXC_F_USB_SETUP0_BYTE1_POS 8 |
<> | 144:ef7eb2e8f9f7 | 257 | #define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS)) |
<> | 144:ef7eb2e8f9f7 | 258 | #define MXC_F_USB_SETUP0_BYTE2_POS 16 |
<> | 144:ef7eb2e8f9f7 | 259 | #define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS)) |
<> | 144:ef7eb2e8f9f7 | 260 | #define MXC_F_USB_SETUP0_BYTE3_POS 24 |
<> | 144:ef7eb2e8f9f7 | 261 | #define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS)) |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | #define MXC_F_USB_SETUP1_BYTE0_POS 0 |
<> | 144:ef7eb2e8f9f7 | 264 | #define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS)) |
<> | 144:ef7eb2e8f9f7 | 265 | #define MXC_F_USB_SETUP1_BYTE1_POS 8 |
<> | 144:ef7eb2e8f9f7 | 266 | #define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS)) |
<> | 144:ef7eb2e8f9f7 | 267 | #define MXC_F_USB_SETUP1_BYTE2_POS 16 |
<> | 144:ef7eb2e8f9f7 | 268 | #define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS)) |
<> | 144:ef7eb2e8f9f7 | 269 | #define MXC_F_USB_SETUP1_BYTE3_POS 24 |
<> | 144:ef7eb2e8f9f7 | 270 | #define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS)) |
<> | 144:ef7eb2e8f9f7 | 271 | |
<> | 144:ef7eb2e8f9f7 | 272 | #define MXC_F_USB_EP_DIR_POS 0 |
<> | 144:ef7eb2e8f9f7 | 273 | #define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS)) |
<> | 144:ef7eb2e8f9f7 | 274 | #define MXC_F_USB_EP_BUF2_POS 3 |
<> | 144:ef7eb2e8f9f7 | 275 | #define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS)) |
<> | 144:ef7eb2e8f9f7 | 276 | #define MXC_F_USB_EP_INT_EN_POS 4 |
<> | 144:ef7eb2e8f9f7 | 277 | #define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS)) |
<> | 144:ef7eb2e8f9f7 | 278 | #define MXC_F_USB_EP_NAK_EN_POS 5 |
<> | 144:ef7eb2e8f9f7 | 279 | #define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS)) |
<> | 144:ef7eb2e8f9f7 | 280 | #define MXC_F_USB_EP_DT_POS 6 |
<> | 144:ef7eb2e8f9f7 | 281 | #define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS)) |
<> | 144:ef7eb2e8f9f7 | 282 | #define MXC_F_USB_EP_STALL_POS 8 |
<> | 144:ef7eb2e8f9f7 | 283 | #define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS)) |
<> | 144:ef7eb2e8f9f7 | 284 | #define MXC_F_USB_EP_ST_STALL_POS 9 |
<> | 144:ef7eb2e8f9f7 | 285 | #define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS)) |
<> | 144:ef7eb2e8f9f7 | 286 | #define MXC_F_USB_EP_ST_ACK_POS 10 |
<> | 144:ef7eb2e8f9f7 | 287 | #define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS)) |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 292 | } |
<> | 144:ef7eb2e8f9f7 | 293 | #endif |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | #endif /* _MXC_USB_REGS_H_ */ |
<> | 144:ef7eb2e8f9f7 | 296 |