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targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c@119:3921aeca8633, 2016-04-29 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Apr 29 01:15:11 2016 +0100
- Revision:
- 119:3921aeca8633
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270
Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/
[Renesas RZ/A1H] Enable asynchronous communications
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 119:3921aeca8633 | 1 | /* mbed Microcontroller Library |
mbed_official | 119:3921aeca8633 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 119:3921aeca8633 | 3 | * |
mbed_official | 119:3921aeca8633 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 119:3921aeca8633 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 119:3921aeca8633 | 6 | * You may obtain a copy of the License at |
mbed_official | 119:3921aeca8633 | 7 | * |
mbed_official | 119:3921aeca8633 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 119:3921aeca8633 | 9 | * |
mbed_official | 119:3921aeca8633 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 119:3921aeca8633 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 119:3921aeca8633 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 119:3921aeca8633 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 119:3921aeca8633 | 14 | * limitations under the License. |
mbed_official | 119:3921aeca8633 | 15 | */ |
mbed_official | 119:3921aeca8633 | 16 | #include "mbed_assert.h" |
mbed_official | 119:3921aeca8633 | 17 | #include "i2c_api.h" |
mbed_official | 119:3921aeca8633 | 18 | #include "cmsis.h" |
mbed_official | 119:3921aeca8633 | 19 | #include "pinmap.h" |
mbed_official | 119:3921aeca8633 | 20 | #include "r_typedefs.h" |
mbed_official | 119:3921aeca8633 | 21 | |
mbed_official | 119:3921aeca8633 | 22 | #include "riic_iodefine.h" |
mbed_official | 119:3921aeca8633 | 23 | #include "RZ_A1_Init.h" |
mbed_official | 119:3921aeca8633 | 24 | #include "VKRZA1H.h" |
mbed_official | 119:3921aeca8633 | 25 | |
mbed_official | 119:3921aeca8633 | 26 | volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; |
mbed_official | 119:3921aeca8633 | 27 | |
mbed_official | 119:3921aeca8633 | 28 | #define REG(N) \ |
mbed_official | 119:3921aeca8633 | 29 | RIIC[obj->i2c]->RIICn##N |
mbed_official | 119:3921aeca8633 | 30 | |
mbed_official | 119:3921aeca8633 | 31 | /* RIICnCR1 */ |
mbed_official | 119:3921aeca8633 | 32 | #define CR1_RST (1 << 6) |
mbed_official | 119:3921aeca8633 | 33 | #define CR1_ICE (1 << 7) |
mbed_official | 119:3921aeca8633 | 34 | |
mbed_official | 119:3921aeca8633 | 35 | /* RIICnCR2 */ |
mbed_official | 119:3921aeca8633 | 36 | #define CR2_ST (1 << 1) |
mbed_official | 119:3921aeca8633 | 37 | #define CR2_RS (1 << 2) |
mbed_official | 119:3921aeca8633 | 38 | #define CR2_SP (1 << 3) |
mbed_official | 119:3921aeca8633 | 39 | #define CR2_TRS (1 << 5) |
mbed_official | 119:3921aeca8633 | 40 | #define CR2_BBSY (1 << 7) |
mbed_official | 119:3921aeca8633 | 41 | |
mbed_official | 119:3921aeca8633 | 42 | /* RIICnMR3 */ |
mbed_official | 119:3921aeca8633 | 43 | #define MR3_ACKBT (1 << 3) |
mbed_official | 119:3921aeca8633 | 44 | #define MR3_ACKWP (1 << 4) |
mbed_official | 119:3921aeca8633 | 45 | #define MR3_WAIT (1 << 6) |
mbed_official | 119:3921aeca8633 | 46 | |
mbed_official | 119:3921aeca8633 | 47 | /* RIICnSER */ |
mbed_official | 119:3921aeca8633 | 48 | #define SER_SAR0E (1 << 0) |
mbed_official | 119:3921aeca8633 | 49 | |
mbed_official | 119:3921aeca8633 | 50 | /* RIICnSR1 */ |
mbed_official | 119:3921aeca8633 | 51 | #define SR1_AAS0 (1 << 0) |
mbed_official | 119:3921aeca8633 | 52 | |
mbed_official | 119:3921aeca8633 | 53 | /* RIICnSR2 */ |
mbed_official | 119:3921aeca8633 | 54 | #define SR2_START (1 << 2) |
mbed_official | 119:3921aeca8633 | 55 | #define SR2_STOP (1 << 3) |
mbed_official | 119:3921aeca8633 | 56 | #define SR2_NACKF (1 << 4) |
mbed_official | 119:3921aeca8633 | 57 | #define SR2_RDRF (1 << 5) |
mbed_official | 119:3921aeca8633 | 58 | #define SR2_TEND (1 << 6) |
mbed_official | 119:3921aeca8633 | 59 | #define SR2_TDRE (1 << 7) |
mbed_official | 119:3921aeca8633 | 60 | |
mbed_official | 119:3921aeca8633 | 61 | #define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ |
mbed_official | 119:3921aeca8633 | 62 | |
mbed_official | 119:3921aeca8633 | 63 | static const PinMap PinMap_I2C_SDA[] = { |
mbed_official | 119:3921aeca8633 | 64 | {P1_1 , I2C_0, 1}, |
mbed_official | 119:3921aeca8633 | 65 | {P1_3 , I2C_1, 1}, |
mbed_official | 119:3921aeca8633 | 66 | {P1_5 , I2C_2, 1}, |
mbed_official | 119:3921aeca8633 | 67 | {P1_7 , I2C_3, 1}, |
mbed_official | 119:3921aeca8633 | 68 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 69 | }; |
mbed_official | 119:3921aeca8633 | 70 | |
mbed_official | 119:3921aeca8633 | 71 | static const PinMap PinMap_I2C_SCL[] = { |
mbed_official | 119:3921aeca8633 | 72 | {P1_0 , I2C_0, 1}, |
mbed_official | 119:3921aeca8633 | 73 | {P1_2 , I2C_1, 1}, |
mbed_official | 119:3921aeca8633 | 74 | {P1_4 , I2C_2, 1}, |
mbed_official | 119:3921aeca8633 | 75 | {P1_6 , I2C_3, 1}, |
mbed_official | 119:3921aeca8633 | 76 | {NC , NC, 0} |
mbed_official | 119:3921aeca8633 | 77 | }; |
mbed_official | 119:3921aeca8633 | 78 | |
mbed_official | 119:3921aeca8633 | 79 | |
mbed_official | 119:3921aeca8633 | 80 | static inline int i2c_status(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 81 | return REG(SR2.UINT8[0]); |
mbed_official | 119:3921aeca8633 | 82 | } |
mbed_official | 119:3921aeca8633 | 83 | |
mbed_official | 119:3921aeca8633 | 84 | static void i2c_reg_reset(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 85 | /* full reset */ |
mbed_official | 119:3921aeca8633 | 86 | REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off |
mbed_official | 119:3921aeca8633 | 87 | REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on |
mbed_official | 119:3921aeca8633 | 88 | REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on |
mbed_official | 119:3921aeca8633 | 89 | |
mbed_official | 119:3921aeca8633 | 90 | REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack) |
mbed_official | 119:3921aeca8633 | 91 | REG(SER.UINT8[0]) = 0x00; // no slave addr enabled |
mbed_official | 119:3921aeca8633 | 92 | |
mbed_official | 119:3921aeca8633 | 93 | /* set frequency */ |
mbed_official | 119:3921aeca8633 | 94 | REG(MR1.UINT8[0]) |= obj->pclk_bit; |
mbed_official | 119:3921aeca8633 | 95 | REG(BRL.UINT8[0]) = obj->width_low; |
mbed_official | 119:3921aeca8633 | 96 | REG(BRH.UINT8[0]) = obj->width_hi; |
mbed_official | 119:3921aeca8633 | 97 | |
mbed_official | 119:3921aeca8633 | 98 | REG(MR2.UINT8[0]) = 0x07; |
mbed_official | 119:3921aeca8633 | 99 | REG(MR3.UINT8[0]) = 0x00; |
mbed_official | 119:3921aeca8633 | 100 | |
mbed_official | 119:3921aeca8633 | 101 | REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT |
mbed_official | 119:3921aeca8633 | 102 | REG(IER.UINT8[0]) = 0x00; // no interrupt |
mbed_official | 119:3921aeca8633 | 103 | |
mbed_official | 119:3921aeca8633 | 104 | REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset |
mbed_official | 119:3921aeca8633 | 105 | } |
mbed_official | 119:3921aeca8633 | 106 | |
mbed_official | 119:3921aeca8633 | 107 | static inline int i2c_wait_RDRF(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 108 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 109 | |
mbed_official | 119:3921aeca8633 | 110 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 111 | while ((i2c_status(obj) & SR2_RDRF) == 0) { |
mbed_official | 119:3921aeca8633 | 112 | timeout ++; |
mbed_official | 119:3921aeca8633 | 113 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 114 | return -1; |
mbed_official | 119:3921aeca8633 | 115 | } |
mbed_official | 119:3921aeca8633 | 116 | } |
mbed_official | 119:3921aeca8633 | 117 | |
mbed_official | 119:3921aeca8633 | 118 | return 0; |
mbed_official | 119:3921aeca8633 | 119 | } |
mbed_official | 119:3921aeca8633 | 120 | |
mbed_official | 119:3921aeca8633 | 121 | static int i2c_wait_TDRE(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 122 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 123 | |
mbed_official | 119:3921aeca8633 | 124 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 125 | while ((i2c_status(obj) & SR2_TDRE) == 0) { |
mbed_official | 119:3921aeca8633 | 126 | timeout ++; |
mbed_official | 119:3921aeca8633 | 127 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 128 | return -1; |
mbed_official | 119:3921aeca8633 | 129 | } |
mbed_official | 119:3921aeca8633 | 130 | } |
mbed_official | 119:3921aeca8633 | 131 | |
mbed_official | 119:3921aeca8633 | 132 | return 0; |
mbed_official | 119:3921aeca8633 | 133 | } |
mbed_official | 119:3921aeca8633 | 134 | |
mbed_official | 119:3921aeca8633 | 135 | static int i2c_wait_TEND(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 136 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 137 | |
mbed_official | 119:3921aeca8633 | 138 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 139 | while ((i2c_status(obj) & SR2_TEND) == 0) { |
mbed_official | 119:3921aeca8633 | 140 | timeout ++; |
mbed_official | 119:3921aeca8633 | 141 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 142 | return -1; |
mbed_official | 119:3921aeca8633 | 143 | } |
mbed_official | 119:3921aeca8633 | 144 | } |
mbed_official | 119:3921aeca8633 | 145 | |
mbed_official | 119:3921aeca8633 | 146 | return 0; |
mbed_official | 119:3921aeca8633 | 147 | } |
mbed_official | 119:3921aeca8633 | 148 | |
mbed_official | 119:3921aeca8633 | 149 | |
mbed_official | 119:3921aeca8633 | 150 | static int i2c_wait_START(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 151 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 152 | |
mbed_official | 119:3921aeca8633 | 153 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 154 | while ((i2c_status(obj) & SR2_START) == 0) { |
mbed_official | 119:3921aeca8633 | 155 | timeout ++; |
mbed_official | 119:3921aeca8633 | 156 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 157 | return -1; |
mbed_official | 119:3921aeca8633 | 158 | } |
mbed_official | 119:3921aeca8633 | 159 | } |
mbed_official | 119:3921aeca8633 | 160 | |
mbed_official | 119:3921aeca8633 | 161 | return 0; |
mbed_official | 119:3921aeca8633 | 162 | } |
mbed_official | 119:3921aeca8633 | 163 | |
mbed_official | 119:3921aeca8633 | 164 | static int i2c_wait_STOP(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 165 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 166 | |
mbed_official | 119:3921aeca8633 | 167 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 168 | while ((i2c_status(obj) & SR2_STOP) == 0) { |
mbed_official | 119:3921aeca8633 | 169 | timeout ++; |
mbed_official | 119:3921aeca8633 | 170 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 171 | return -1; |
mbed_official | 119:3921aeca8633 | 172 | } |
mbed_official | 119:3921aeca8633 | 173 | } |
mbed_official | 119:3921aeca8633 | 174 | |
mbed_official | 119:3921aeca8633 | 175 | return 0; |
mbed_official | 119:3921aeca8633 | 176 | } |
mbed_official | 119:3921aeca8633 | 177 | |
mbed_official | 119:3921aeca8633 | 178 | static int i2c_set_STOP(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 179 | /* SR2.STOP = 0 */ |
mbed_official | 119:3921aeca8633 | 180 | REG(SR2.UINT32) &= ~SR2_STOP; |
mbed_official | 119:3921aeca8633 | 181 | /* Stop condition */ |
mbed_official | 119:3921aeca8633 | 182 | REG(CR2.UINT32) |= CR2_SP; |
mbed_official | 119:3921aeca8633 | 183 | |
mbed_official | 119:3921aeca8633 | 184 | return 0; |
mbed_official | 119:3921aeca8633 | 185 | } |
mbed_official | 119:3921aeca8633 | 186 | |
mbed_official | 119:3921aeca8633 | 187 | static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 188 | /* SR2.NACKF = 0 */ |
mbed_official | 119:3921aeca8633 | 189 | REG(SR2.UINT32) &= ~SR2_NACKF; |
mbed_official | 119:3921aeca8633 | 190 | /* SR2.STOP = 0 */ |
mbed_official | 119:3921aeca8633 | 191 | REG(SR2.UINT32) &= ~SR2_STOP; |
mbed_official | 119:3921aeca8633 | 192 | } |
mbed_official | 119:3921aeca8633 | 193 | |
mbed_official | 119:3921aeca8633 | 194 | static void i2c_set_MR3_NACK(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 195 | /* send a NOT ACK */ |
mbed_official | 119:3921aeca8633 | 196 | REG(MR3.UINT32) |= MR3_ACKWP; |
mbed_official | 119:3921aeca8633 | 197 | REG(MR3.UINT32) |= MR3_ACKBT; |
mbed_official | 119:3921aeca8633 | 198 | REG(MR3.UINT32) &= ~MR3_ACKWP; |
mbed_official | 119:3921aeca8633 | 199 | } |
mbed_official | 119:3921aeca8633 | 200 | |
mbed_official | 119:3921aeca8633 | 201 | static void i2c_set_MR3_ACK(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 202 | /* send a ACK */ |
mbed_official | 119:3921aeca8633 | 203 | REG(MR3.UINT32) |= MR3_ACKWP; |
mbed_official | 119:3921aeca8633 | 204 | REG(MR3.UINT32) &= ~MR3_ACKBT; |
mbed_official | 119:3921aeca8633 | 205 | REG(MR3.UINT32) &= ~MR3_ACKWP; |
mbed_official | 119:3921aeca8633 | 206 | } |
mbed_official | 119:3921aeca8633 | 207 | |
mbed_official | 119:3921aeca8633 | 208 | static inline void i2c_power_enable(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 209 | volatile uint8_t dummy; |
mbed_official | 119:3921aeca8633 | 210 | switch ((int)obj->i2c) { |
mbed_official | 119:3921aeca8633 | 211 | case I2C_0: |
mbed_official | 119:3921aeca8633 | 212 | CPGSTBCR9 &= ~(0x80); |
mbed_official | 119:3921aeca8633 | 213 | break; |
mbed_official | 119:3921aeca8633 | 214 | case I2C_1: |
mbed_official | 119:3921aeca8633 | 215 | CPGSTBCR9 &= ~(0x40); |
mbed_official | 119:3921aeca8633 | 216 | break; |
mbed_official | 119:3921aeca8633 | 217 | case I2C_2: |
mbed_official | 119:3921aeca8633 | 218 | CPGSTBCR9 &= ~(0x20); |
mbed_official | 119:3921aeca8633 | 219 | break; |
mbed_official | 119:3921aeca8633 | 220 | case I2C_3: |
mbed_official | 119:3921aeca8633 | 221 | CPGSTBCR9 &= ~(0x10); |
mbed_official | 119:3921aeca8633 | 222 | break; |
mbed_official | 119:3921aeca8633 | 223 | } |
mbed_official | 119:3921aeca8633 | 224 | dummy = CPGSTBCR9; |
mbed_official | 119:3921aeca8633 | 225 | } |
mbed_official | 119:3921aeca8633 | 226 | |
mbed_official | 119:3921aeca8633 | 227 | void i2c_init(i2c_t *obj, PinName sda, PinName scl) { |
mbed_official | 119:3921aeca8633 | 228 | /* determine the I2C to use */ |
mbed_official | 119:3921aeca8633 | 229 | I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); |
mbed_official | 119:3921aeca8633 | 230 | I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); |
mbed_official | 119:3921aeca8633 | 231 | obj->i2c = pinmap_merge(i2c_sda, i2c_scl); |
mbed_official | 119:3921aeca8633 | 232 | MBED_ASSERT((int)obj->i2c != NC); |
mbed_official | 119:3921aeca8633 | 233 | |
mbed_official | 119:3921aeca8633 | 234 | /* enable power */ |
mbed_official | 119:3921aeca8633 | 235 | i2c_power_enable(obj); |
mbed_official | 119:3921aeca8633 | 236 | |
mbed_official | 119:3921aeca8633 | 237 | /* set default frequency at 100k */ |
mbed_official | 119:3921aeca8633 | 238 | i2c_frequency(obj, 100000); |
mbed_official | 119:3921aeca8633 | 239 | |
mbed_official | 119:3921aeca8633 | 240 | pinmap_pinout(sda, PinMap_I2C_SDA); |
mbed_official | 119:3921aeca8633 | 241 | pinmap_pinout(scl, PinMap_I2C_SCL); |
mbed_official | 119:3921aeca8633 | 242 | |
mbed_official | 119:3921aeca8633 | 243 | obj->last_stop_flag = 1; |
mbed_official | 119:3921aeca8633 | 244 | } |
mbed_official | 119:3921aeca8633 | 245 | |
mbed_official | 119:3921aeca8633 | 246 | inline int i2c_start(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 247 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 248 | |
mbed_official | 119:3921aeca8633 | 249 | while ((REG(CR2.UINT32) & CR2_BBSY) != 0) { |
mbed_official | 119:3921aeca8633 | 250 | timeout ++; |
mbed_official | 119:3921aeca8633 | 251 | if (timeout >= obj->bbsy_wait_cnt) { |
mbed_official | 119:3921aeca8633 | 252 | break; |
mbed_official | 119:3921aeca8633 | 253 | } |
mbed_official | 119:3921aeca8633 | 254 | } |
mbed_official | 119:3921aeca8633 | 255 | /* Start Condition */ |
mbed_official | 119:3921aeca8633 | 256 | REG(CR2.UINT8[0]) |= CR2_ST; |
mbed_official | 119:3921aeca8633 | 257 | |
mbed_official | 119:3921aeca8633 | 258 | return 0; |
mbed_official | 119:3921aeca8633 | 259 | } |
mbed_official | 119:3921aeca8633 | 260 | |
mbed_official | 119:3921aeca8633 | 261 | static inline int i2c_restart(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 262 | /* SR2.START = 0 */ |
mbed_official | 119:3921aeca8633 | 263 | REG(SR2.UINT32) &= ~SR2_START; |
mbed_official | 119:3921aeca8633 | 264 | /* ReStart condition */ |
mbed_official | 119:3921aeca8633 | 265 | REG(CR2.UINT32) |= CR2_RS; |
mbed_official | 119:3921aeca8633 | 266 | |
mbed_official | 119:3921aeca8633 | 267 | return 0; |
mbed_official | 119:3921aeca8633 | 268 | } |
mbed_official | 119:3921aeca8633 | 269 | |
mbed_official | 119:3921aeca8633 | 270 | inline int i2c_stop(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 271 | (void)i2c_set_STOP(obj); |
mbed_official | 119:3921aeca8633 | 272 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 273 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 274 | |
mbed_official | 119:3921aeca8633 | 275 | return 0; |
mbed_official | 119:3921aeca8633 | 276 | } |
mbed_official | 119:3921aeca8633 | 277 | |
mbed_official | 119:3921aeca8633 | 278 | static void i2c_set_err_noslave(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 279 | (void)i2c_set_STOP(obj); |
mbed_official | 119:3921aeca8633 | 280 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 281 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 282 | obj->last_stop_flag = 1; |
mbed_official | 119:3921aeca8633 | 283 | } |
mbed_official | 119:3921aeca8633 | 284 | |
mbed_official | 119:3921aeca8633 | 285 | static inline int i2c_do_write(i2c_t *obj, int value) { |
mbed_official | 119:3921aeca8633 | 286 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 287 | |
mbed_official | 119:3921aeca8633 | 288 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 289 | while ((i2c_status(obj) & SR2_TDRE) == 0) { |
mbed_official | 119:3921aeca8633 | 290 | timeout ++; |
mbed_official | 119:3921aeca8633 | 291 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 292 | return -1; |
mbed_official | 119:3921aeca8633 | 293 | } |
mbed_official | 119:3921aeca8633 | 294 | } |
mbed_official | 119:3921aeca8633 | 295 | /* write the data */ |
mbed_official | 119:3921aeca8633 | 296 | REG(DRT.UINT32) = value; |
mbed_official | 119:3921aeca8633 | 297 | |
mbed_official | 119:3921aeca8633 | 298 | return 0; |
mbed_official | 119:3921aeca8633 | 299 | } |
mbed_official | 119:3921aeca8633 | 300 | |
mbed_official | 119:3921aeca8633 | 301 | static inline int i2c_read_address_write(i2c_t *obj, int value) { |
mbed_official | 119:3921aeca8633 | 302 | int status; |
mbed_official | 119:3921aeca8633 | 303 | |
mbed_official | 119:3921aeca8633 | 304 | status = i2c_wait_TDRE(obj); |
mbed_official | 119:3921aeca8633 | 305 | if (status == 0) { |
mbed_official | 119:3921aeca8633 | 306 | /* write the data */ |
mbed_official | 119:3921aeca8633 | 307 | REG(DRT.UINT32) = value; |
mbed_official | 119:3921aeca8633 | 308 | } |
mbed_official | 119:3921aeca8633 | 309 | |
mbed_official | 119:3921aeca8633 | 310 | return status; |
mbed_official | 119:3921aeca8633 | 311 | |
mbed_official | 119:3921aeca8633 | 312 | } |
mbed_official | 119:3921aeca8633 | 313 | |
mbed_official | 119:3921aeca8633 | 314 | static inline int i2c_do_read(i2c_t *obj, int last) { |
mbed_official | 119:3921aeca8633 | 315 | if (last == 2) { |
mbed_official | 119:3921aeca8633 | 316 | /* this time is befor last byte read */ |
mbed_official | 119:3921aeca8633 | 317 | /* Set MR3 WAIT bit is 1 */; |
mbed_official | 119:3921aeca8633 | 318 | REG(MR3.UINT32) |= MR3_WAIT; |
mbed_official | 119:3921aeca8633 | 319 | } else if (last == 1) { |
mbed_official | 119:3921aeca8633 | 320 | i2c_set_MR3_NACK(obj); |
mbed_official | 119:3921aeca8633 | 321 | } else { |
mbed_official | 119:3921aeca8633 | 322 | i2c_set_MR3_ACK(obj); |
mbed_official | 119:3921aeca8633 | 323 | } |
mbed_official | 119:3921aeca8633 | 324 | |
mbed_official | 119:3921aeca8633 | 325 | /* return the data */ |
mbed_official | 119:3921aeca8633 | 326 | return (REG(DRR.UINT32) & 0xFF); |
mbed_official | 119:3921aeca8633 | 327 | } |
mbed_official | 119:3921aeca8633 | 328 | |
mbed_official | 119:3921aeca8633 | 329 | void i2c_frequency(i2c_t *obj, int hz) { |
mbed_official | 119:3921aeca8633 | 330 | float64_t pclk_val; |
mbed_official | 119:3921aeca8633 | 331 | float64_t wait_utime; |
mbed_official | 119:3921aeca8633 | 332 | volatile float64_t bps; |
mbed_official | 119:3921aeca8633 | 333 | volatile float64_t L_time; /* H Width period */ |
mbed_official | 119:3921aeca8633 | 334 | volatile float64_t H_time; /* L Width period */ |
mbed_official | 119:3921aeca8633 | 335 | uint32_t tmp_L_width; |
mbed_official | 119:3921aeca8633 | 336 | uint32_t tmp_H_width; |
mbed_official | 119:3921aeca8633 | 337 | uint32_t remainder; |
mbed_official | 119:3921aeca8633 | 338 | uint32_t wk_cks = 0; |
mbed_official | 119:3921aeca8633 | 339 | |
mbed_official | 119:3921aeca8633 | 340 | /* set PCLK */ |
mbed_official | 119:3921aeca8633 | 341 | if (false == RZ_A1_IsClockMode0()) { |
mbed_official | 119:3921aeca8633 | 342 | pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK; |
mbed_official | 119:3921aeca8633 | 343 | } else { |
mbed_official | 119:3921aeca8633 | 344 | pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK; |
mbed_official | 119:3921aeca8633 | 345 | } |
mbed_official | 119:3921aeca8633 | 346 | |
mbed_official | 119:3921aeca8633 | 347 | /* Min 10kHz, Max 400kHz */ |
mbed_official | 119:3921aeca8633 | 348 | if (hz < 10000) { |
mbed_official | 119:3921aeca8633 | 349 | bps = 10000; |
mbed_official | 119:3921aeca8633 | 350 | } else if (hz > 400000) { |
mbed_official | 119:3921aeca8633 | 351 | bps = 400000; |
mbed_official | 119:3921aeca8633 | 352 | } else { |
mbed_official | 119:3921aeca8633 | 353 | bps = (float64_t)hz; |
mbed_official | 119:3921aeca8633 | 354 | } |
mbed_official | 119:3921aeca8633 | 355 | |
mbed_official | 119:3921aeca8633 | 356 | /* Calculation L width time */ |
mbed_official | 119:3921aeca8633 | 357 | L_time = (1 / (2 * bps)); /* Harf period of frequency */ |
mbed_official | 119:3921aeca8633 | 358 | H_time = L_time; |
mbed_official | 119:3921aeca8633 | 359 | |
mbed_official | 119:3921aeca8633 | 360 | /* Check I2C mode of Speed */ |
mbed_official | 119:3921aeca8633 | 361 | if (bps > 100000) { |
mbed_official | 119:3921aeca8633 | 362 | /* Fast-mode */ |
mbed_official | 119:3921aeca8633 | 363 | L_time -= 102E-9; /* Falling time of SCL clock. */ |
mbed_official | 119:3921aeca8633 | 364 | H_time -= 138E-9; /* Rising time of SCL clock. */ |
mbed_official | 119:3921aeca8633 | 365 | /* Check L wideth */ |
mbed_official | 119:3921aeca8633 | 366 | if (L_time < 1.3E-6) { |
mbed_official | 119:3921aeca8633 | 367 | /* Wnen L width less than 1.3us */ |
mbed_official | 119:3921aeca8633 | 368 | /* Subtract Rise up and down time for SCL from H/L width */ |
mbed_official | 119:3921aeca8633 | 369 | L_time = 1.3E-6; |
mbed_official | 119:3921aeca8633 | 370 | H_time = (1 / bps) - L_time - 138E-9 - 102E-9; |
mbed_official | 119:3921aeca8633 | 371 | } |
mbed_official | 119:3921aeca8633 | 372 | } |
mbed_official | 119:3921aeca8633 | 373 | |
mbed_official | 119:3921aeca8633 | 374 | tmp_L_width = (uint32_t)(L_time * pclk_val * 10); |
mbed_official | 119:3921aeca8633 | 375 | tmp_L_width >>= 1; |
mbed_official | 119:3921aeca8633 | 376 | wk_cks++; |
mbed_official | 119:3921aeca8633 | 377 | while (tmp_L_width >= 341) { |
mbed_official | 119:3921aeca8633 | 378 | tmp_L_width >>= 1; |
mbed_official | 119:3921aeca8633 | 379 | wk_cks++; |
mbed_official | 119:3921aeca8633 | 380 | } |
mbed_official | 119:3921aeca8633 | 381 | remainder = tmp_L_width % 10; |
mbed_official | 119:3921aeca8633 | 382 | tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */ |
mbed_official | 119:3921aeca8633 | 383 | |
mbed_official | 119:3921aeca8633 | 384 | tmp_H_width = (uint32_t)(H_time * pclk_val * 10); |
mbed_official | 119:3921aeca8633 | 385 | tmp_H_width >>= wk_cks; |
mbed_official | 119:3921aeca8633 | 386 | if (remainder == 0) { |
mbed_official | 119:3921aeca8633 | 387 | tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */ |
mbed_official | 119:3921aeca8633 | 388 | } else { |
mbed_official | 119:3921aeca8633 | 389 | remainder += tmp_H_width % 10; |
mbed_official | 119:3921aeca8633 | 390 | tmp_H_width = (tmp_H_width / 10) - 3; |
mbed_official | 119:3921aeca8633 | 391 | if (remainder > 10) { |
mbed_official | 119:3921aeca8633 | 392 | tmp_H_width += 1; /* fine adjustment */ |
mbed_official | 119:3921aeca8633 | 393 | } |
mbed_official | 119:3921aeca8633 | 394 | } |
mbed_official | 119:3921aeca8633 | 395 | /* timeout of BBSY bit is minimum low width by frequency */ |
mbed_official | 119:3921aeca8633 | 396 | /* so timeout calculates "(low width) * 2" by frequency */ |
mbed_official | 119:3921aeca8633 | 397 | wait_utime = (L_time * 2) * 1000000; |
mbed_official | 119:3921aeca8633 | 398 | /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ |
mbed_official | 119:3921aeca8633 | 399 | if (wait_utime <= 0.3) { |
mbed_official | 119:3921aeca8633 | 400 | obj->bbsy_wait_cnt = 1; |
mbed_official | 119:3921aeca8633 | 401 | } else { |
mbed_official | 119:3921aeca8633 | 402 | obj->bbsy_wait_cnt = (int)(wait_utime / 0.3); |
mbed_official | 119:3921aeca8633 | 403 | } |
mbed_official | 119:3921aeca8633 | 404 | |
mbed_official | 119:3921aeca8633 | 405 | |
mbed_official | 119:3921aeca8633 | 406 | /* I2C Rate */ |
mbed_official | 119:3921aeca8633 | 407 | obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ |
mbed_official | 119:3921aeca8633 | 408 | obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0); |
mbed_official | 119:3921aeca8633 | 409 | obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0); |
mbed_official | 119:3921aeca8633 | 410 | |
mbed_official | 119:3921aeca8633 | 411 | /* full reset */ |
mbed_official | 119:3921aeca8633 | 412 | i2c_reg_reset(obj); |
mbed_official | 119:3921aeca8633 | 413 | } |
mbed_official | 119:3921aeca8633 | 414 | |
mbed_official | 119:3921aeca8633 | 415 | int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { |
mbed_official | 119:3921aeca8633 | 416 | int count = 0; |
mbed_official | 119:3921aeca8633 | 417 | int status; |
mbed_official | 119:3921aeca8633 | 418 | int value; |
mbed_official | 119:3921aeca8633 | 419 | volatile uint32_t work_reg = 0; |
mbed_official | 119:3921aeca8633 | 420 | |
mbed_official | 119:3921aeca8633 | 421 | if(length <= 0) { |
mbed_official | 119:3921aeca8633 | 422 | return 0; |
mbed_official | 119:3921aeca8633 | 423 | } |
mbed_official | 119:3921aeca8633 | 424 | i2c_set_MR3_ACK(obj); |
mbed_official | 119:3921aeca8633 | 425 | /* There is a STOP condition for last processing */ |
mbed_official | 119:3921aeca8633 | 426 | if (obj->last_stop_flag != 0) { |
mbed_official | 119:3921aeca8633 | 427 | status = i2c_start(obj); |
mbed_official | 119:3921aeca8633 | 428 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 429 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 430 | return I2C_ERROR_BUS_BUSY; |
mbed_official | 119:3921aeca8633 | 431 | } |
mbed_official | 119:3921aeca8633 | 432 | } |
mbed_official | 119:3921aeca8633 | 433 | obj->last_stop_flag = stop; |
mbed_official | 119:3921aeca8633 | 434 | /* Send Slave address */ |
mbed_official | 119:3921aeca8633 | 435 | status = i2c_read_address_write(obj, (address | 0x01)); |
mbed_official | 119:3921aeca8633 | 436 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 437 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 438 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 439 | } |
mbed_official | 119:3921aeca8633 | 440 | /* wait RDRF */ |
mbed_official | 119:3921aeca8633 | 441 | status = i2c_wait_RDRF(obj); |
mbed_official | 119:3921aeca8633 | 442 | /* check ACK/NACK */ |
mbed_official | 119:3921aeca8633 | 443 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { |
mbed_official | 119:3921aeca8633 | 444 | /* Slave sends NACK */ |
mbed_official | 119:3921aeca8633 | 445 | (void)i2c_set_STOP(obj); |
mbed_official | 119:3921aeca8633 | 446 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 447 | value = REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 448 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 449 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 450 | obj->last_stop_flag = 1; |
mbed_official | 119:3921aeca8633 | 451 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 452 | } |
mbed_official | 119:3921aeca8633 | 453 | /* Read in all except last byte */ |
mbed_official | 119:3921aeca8633 | 454 | if (length > 2) { |
mbed_official | 119:3921aeca8633 | 455 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 456 | value = REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 457 | for (count = 0; count < (length - 1); count++) { |
mbed_official | 119:3921aeca8633 | 458 | /* wait for it to arrive */ |
mbed_official | 119:3921aeca8633 | 459 | status = i2c_wait_RDRF(obj); |
mbed_official | 119:3921aeca8633 | 460 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 461 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 462 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 463 | } |
mbed_official | 119:3921aeca8633 | 464 | /* Recieve the data */ |
mbed_official | 119:3921aeca8633 | 465 | if (count == (length - 2)) { |
mbed_official | 119:3921aeca8633 | 466 | value = i2c_do_read(obj, 1); |
mbed_official | 119:3921aeca8633 | 467 | } else if ((length >= 3) && (count == (length - 3))) { |
mbed_official | 119:3921aeca8633 | 468 | value = i2c_do_read(obj, 2); |
mbed_official | 119:3921aeca8633 | 469 | } else { |
mbed_official | 119:3921aeca8633 | 470 | value = i2c_do_read(obj, 0); |
mbed_official | 119:3921aeca8633 | 471 | } |
mbed_official | 119:3921aeca8633 | 472 | data[count] = (char)value; |
mbed_official | 119:3921aeca8633 | 473 | } |
mbed_official | 119:3921aeca8633 | 474 | } else if (length == 2) { |
mbed_official | 119:3921aeca8633 | 475 | /* Set MR3 WATI bit is 1 */ |
mbed_official | 119:3921aeca8633 | 476 | REG(MR3.UINT32) |= MR3_WAIT; |
mbed_official | 119:3921aeca8633 | 477 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 478 | value = REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 479 | /* wait for it to arrive */ |
mbed_official | 119:3921aeca8633 | 480 | status = i2c_wait_RDRF(obj); |
mbed_official | 119:3921aeca8633 | 481 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 482 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 483 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 484 | } |
mbed_official | 119:3921aeca8633 | 485 | i2c_set_MR3_NACK(obj); |
mbed_official | 119:3921aeca8633 | 486 | data[count] = (char)REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 487 | count++; |
mbed_official | 119:3921aeca8633 | 488 | } else { |
mbed_official | 119:3921aeca8633 | 489 | /* length == 1 */ |
mbed_official | 119:3921aeca8633 | 490 | /* Set MR3 WATI bit is 1 */; |
mbed_official | 119:3921aeca8633 | 491 | REG(MR3.UINT32) |= MR3_WAIT; |
mbed_official | 119:3921aeca8633 | 492 | i2c_set_MR3_NACK(obj); |
mbed_official | 119:3921aeca8633 | 493 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 494 | value = REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 495 | } |
mbed_official | 119:3921aeca8633 | 496 | /* wait for it to arrive */ |
mbed_official | 119:3921aeca8633 | 497 | status = i2c_wait_RDRF(obj); |
mbed_official | 119:3921aeca8633 | 498 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 499 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 500 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 501 | } |
mbed_official | 119:3921aeca8633 | 502 | |
mbed_official | 119:3921aeca8633 | 503 | /* If not repeated start, send stop. */ |
mbed_official | 119:3921aeca8633 | 504 | if (stop) { |
mbed_official | 119:3921aeca8633 | 505 | (void)i2c_set_STOP(obj); |
mbed_official | 119:3921aeca8633 | 506 | /* RIICnDRR read */ |
mbed_official | 119:3921aeca8633 | 507 | value = (REG(DRR.UINT32) & 0xFF); |
mbed_official | 119:3921aeca8633 | 508 | data[count] = (char)value; |
mbed_official | 119:3921aeca8633 | 509 | /* RIICnMR3.WAIT = 0 */ |
mbed_official | 119:3921aeca8633 | 510 | REG(MR3.UINT32) &= ~MR3_WAIT; |
mbed_official | 119:3921aeca8633 | 511 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 512 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 513 | } else { |
mbed_official | 119:3921aeca8633 | 514 | (void)i2c_restart(obj); |
mbed_official | 119:3921aeca8633 | 515 | /* RIICnDRR read */ |
mbed_official | 119:3921aeca8633 | 516 | value = (REG(DRR.UINT32) & 0xFF); |
mbed_official | 119:3921aeca8633 | 517 | data[count] = (char)value; |
mbed_official | 119:3921aeca8633 | 518 | /* RIICnMR3.WAIT = 0 */ |
mbed_official | 119:3921aeca8633 | 519 | REG(MR3.UINT32) &= ~MR3_WAIT; |
mbed_official | 119:3921aeca8633 | 520 | (void)i2c_wait_START(obj); |
mbed_official | 119:3921aeca8633 | 521 | /* SR2.START = 0 */ |
mbed_official | 119:3921aeca8633 | 522 | REG(SR2.UINT32) &= ~SR2_START; |
mbed_official | 119:3921aeca8633 | 523 | } |
mbed_official | 119:3921aeca8633 | 524 | |
mbed_official | 119:3921aeca8633 | 525 | return length; |
mbed_official | 119:3921aeca8633 | 526 | } |
mbed_official | 119:3921aeca8633 | 527 | |
mbed_official | 119:3921aeca8633 | 528 | int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { |
mbed_official | 119:3921aeca8633 | 529 | int cnt; |
mbed_official | 119:3921aeca8633 | 530 | int status; |
mbed_official | 119:3921aeca8633 | 531 | |
mbed_official | 119:3921aeca8633 | 532 | if(length <= 0) { |
mbed_official | 119:3921aeca8633 | 533 | return 0; |
mbed_official | 119:3921aeca8633 | 534 | } |
mbed_official | 119:3921aeca8633 | 535 | |
mbed_official | 119:3921aeca8633 | 536 | /* There is a STOP condition for last processing */ |
mbed_official | 119:3921aeca8633 | 537 | if (obj->last_stop_flag != 0) { |
mbed_official | 119:3921aeca8633 | 538 | status = i2c_start(obj); |
mbed_official | 119:3921aeca8633 | 539 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 540 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 541 | return I2C_ERROR_BUS_BUSY; |
mbed_official | 119:3921aeca8633 | 542 | } |
mbed_official | 119:3921aeca8633 | 543 | } |
mbed_official | 119:3921aeca8633 | 544 | obj->last_stop_flag = stop; |
mbed_official | 119:3921aeca8633 | 545 | /* Send Slave address */ |
mbed_official | 119:3921aeca8633 | 546 | status = i2c_do_write(obj, address); |
mbed_official | 119:3921aeca8633 | 547 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 548 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 549 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 550 | } |
mbed_official | 119:3921aeca8633 | 551 | /* Wait send end */ |
mbed_official | 119:3921aeca8633 | 552 | status = i2c_wait_TEND(obj); |
mbed_official | 119:3921aeca8633 | 553 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { |
mbed_official | 119:3921aeca8633 | 554 | /* Slave sends NACK */ |
mbed_official | 119:3921aeca8633 | 555 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 556 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 557 | } |
mbed_official | 119:3921aeca8633 | 558 | /* Send Write data */ |
mbed_official | 119:3921aeca8633 | 559 | for (cnt=0; cnt<length; cnt++) { |
mbed_official | 119:3921aeca8633 | 560 | status = i2c_do_write(obj, data[cnt]); |
mbed_official | 119:3921aeca8633 | 561 | if(status != 0) { |
mbed_official | 119:3921aeca8633 | 562 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 563 | return cnt; |
mbed_official | 119:3921aeca8633 | 564 | } else { |
mbed_official | 119:3921aeca8633 | 565 | /* Wait send end */ |
mbed_official | 119:3921aeca8633 | 566 | status = i2c_wait_TEND(obj); |
mbed_official | 119:3921aeca8633 | 567 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { |
mbed_official | 119:3921aeca8633 | 568 | /* Slave sends NACK */ |
mbed_official | 119:3921aeca8633 | 569 | i2c_set_err_noslave(obj); |
mbed_official | 119:3921aeca8633 | 570 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 571 | } |
mbed_official | 119:3921aeca8633 | 572 | } |
mbed_official | 119:3921aeca8633 | 573 | } |
mbed_official | 119:3921aeca8633 | 574 | /* If not repeated start, send stop. */ |
mbed_official | 119:3921aeca8633 | 575 | if (stop) { |
mbed_official | 119:3921aeca8633 | 576 | (void)i2c_set_STOP(obj); |
mbed_official | 119:3921aeca8633 | 577 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 578 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 579 | } else { |
mbed_official | 119:3921aeca8633 | 580 | (void)i2c_restart(obj); |
mbed_official | 119:3921aeca8633 | 581 | (void)i2c_wait_START(obj); |
mbed_official | 119:3921aeca8633 | 582 | /* SR2.START = 0 */ |
mbed_official | 119:3921aeca8633 | 583 | REG(SR2.UINT32) &= ~SR2_START; |
mbed_official | 119:3921aeca8633 | 584 | |
mbed_official | 119:3921aeca8633 | 585 | } |
mbed_official | 119:3921aeca8633 | 586 | |
mbed_official | 119:3921aeca8633 | 587 | return length; |
mbed_official | 119:3921aeca8633 | 588 | } |
mbed_official | 119:3921aeca8633 | 589 | |
mbed_official | 119:3921aeca8633 | 590 | void i2c_reset(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 591 | (void)i2c_set_STOP(obj); |
mbed_official | 119:3921aeca8633 | 592 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 593 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 594 | } |
mbed_official | 119:3921aeca8633 | 595 | |
mbed_official | 119:3921aeca8633 | 596 | int i2c_byte_read(i2c_t *obj, int last) { |
mbed_official | 119:3921aeca8633 | 597 | int status; |
mbed_official | 119:3921aeca8633 | 598 | int data; |
mbed_official | 119:3921aeca8633 | 599 | |
mbed_official | 119:3921aeca8633 | 600 | data = i2c_do_read(obj, last); |
mbed_official | 119:3921aeca8633 | 601 | /* wait for it to arrive */ |
mbed_official | 119:3921aeca8633 | 602 | status = i2c_wait_RDRF(obj); |
mbed_official | 119:3921aeca8633 | 603 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 604 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 605 | return I2C_ERROR_NO_SLAVE; |
mbed_official | 119:3921aeca8633 | 606 | } |
mbed_official | 119:3921aeca8633 | 607 | |
mbed_official | 119:3921aeca8633 | 608 | return data; |
mbed_official | 119:3921aeca8633 | 609 | } |
mbed_official | 119:3921aeca8633 | 610 | |
mbed_official | 119:3921aeca8633 | 611 | int i2c_byte_write(i2c_t *obj, int data) { |
mbed_official | 119:3921aeca8633 | 612 | int ack = 0; |
mbed_official | 119:3921aeca8633 | 613 | int status; |
mbed_official | 119:3921aeca8633 | 614 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 615 | |
mbed_official | 119:3921aeca8633 | 616 | status = i2c_do_write(obj, (data & 0xFF)); |
mbed_official | 119:3921aeca8633 | 617 | if (status != 0) { |
mbed_official | 119:3921aeca8633 | 618 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 619 | } else { |
mbed_official | 119:3921aeca8633 | 620 | while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) { |
mbed_official | 119:3921aeca8633 | 621 | timeout++; |
mbed_official | 119:3921aeca8633 | 622 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 623 | return ack; |
mbed_official | 119:3921aeca8633 | 624 | } |
mbed_official | 119:3921aeca8633 | 625 | } |
mbed_official | 119:3921aeca8633 | 626 | /* check ACK/NACK */ |
mbed_official | 119:3921aeca8633 | 627 | if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { |
mbed_official | 119:3921aeca8633 | 628 | /* NACK */ |
mbed_official | 119:3921aeca8633 | 629 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 630 | } else { |
mbed_official | 119:3921aeca8633 | 631 | ack = 1; |
mbed_official | 119:3921aeca8633 | 632 | } |
mbed_official | 119:3921aeca8633 | 633 | } |
mbed_official | 119:3921aeca8633 | 634 | |
mbed_official | 119:3921aeca8633 | 635 | return ack; |
mbed_official | 119:3921aeca8633 | 636 | } |
mbed_official | 119:3921aeca8633 | 637 | |
mbed_official | 119:3921aeca8633 | 638 | void i2c_slave_mode(i2c_t *obj, int enable_slave) { |
mbed_official | 119:3921aeca8633 | 639 | if (enable_slave != 0) { |
mbed_official | 119:3921aeca8633 | 640 | REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled |
mbed_official | 119:3921aeca8633 | 641 | } else { |
mbed_official | 119:3921aeca8633 | 642 | REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled |
mbed_official | 119:3921aeca8633 | 643 | } |
mbed_official | 119:3921aeca8633 | 644 | } |
mbed_official | 119:3921aeca8633 | 645 | |
mbed_official | 119:3921aeca8633 | 646 | int i2c_slave_receive(i2c_t *obj) { |
mbed_official | 119:3921aeca8633 | 647 | int status; |
mbed_official | 119:3921aeca8633 | 648 | int retval; |
mbed_official | 119:3921aeca8633 | 649 | |
mbed_official | 119:3921aeca8633 | 650 | status = (REG(SR1.UINT8[0]) & SR1_AAS0); |
mbed_official | 119:3921aeca8633 | 651 | status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4; |
mbed_official | 119:3921aeca8633 | 652 | |
mbed_official | 119:3921aeca8633 | 653 | switch(status) { |
mbed_official | 119:3921aeca8633 | 654 | case 0x01: |
mbed_official | 119:3921aeca8633 | 655 | /* the master is writing to this slave */ |
mbed_official | 119:3921aeca8633 | 656 | retval = 3; |
mbed_official | 119:3921aeca8633 | 657 | break; |
mbed_official | 119:3921aeca8633 | 658 | case 0x02: |
mbed_official | 119:3921aeca8633 | 659 | /* the master is writing to all slave */ |
mbed_official | 119:3921aeca8633 | 660 | retval = 2; |
mbed_official | 119:3921aeca8633 | 661 | break; |
mbed_official | 119:3921aeca8633 | 662 | case 0x03: |
mbed_official | 119:3921aeca8633 | 663 | /* the master has requested a read from this slave */ |
mbed_official | 119:3921aeca8633 | 664 | retval = 1; |
mbed_official | 119:3921aeca8633 | 665 | break; |
mbed_official | 119:3921aeca8633 | 666 | default : |
mbed_official | 119:3921aeca8633 | 667 | /* no data */ |
mbed_official | 119:3921aeca8633 | 668 | retval = 0; |
mbed_official | 119:3921aeca8633 | 669 | break; |
mbed_official | 119:3921aeca8633 | 670 | } |
mbed_official | 119:3921aeca8633 | 671 | |
mbed_official | 119:3921aeca8633 | 672 | return retval; |
mbed_official | 119:3921aeca8633 | 673 | } |
mbed_official | 119:3921aeca8633 | 674 | |
mbed_official | 119:3921aeca8633 | 675 | int i2c_slave_read(i2c_t *obj, char *data, int length) { |
mbed_official | 119:3921aeca8633 | 676 | int timeout = 0; |
mbed_official | 119:3921aeca8633 | 677 | int count; |
mbed_official | 119:3921aeca8633 | 678 | int break_flg = 0; |
mbed_official | 119:3921aeca8633 | 679 | |
mbed_official | 119:3921aeca8633 | 680 | if(length <= 0) { |
mbed_official | 119:3921aeca8633 | 681 | return 0; |
mbed_official | 119:3921aeca8633 | 682 | } |
mbed_official | 119:3921aeca8633 | 683 | for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { |
mbed_official | 119:3921aeca8633 | 684 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
mbed_official | 119:3921aeca8633 | 685 | while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) { |
mbed_official | 119:3921aeca8633 | 686 | if ((i2c_status(obj) & SR2_STOP) != 0) { |
mbed_official | 119:3921aeca8633 | 687 | break_flg = 1; |
mbed_official | 119:3921aeca8633 | 688 | break; |
mbed_official | 119:3921aeca8633 | 689 | } |
mbed_official | 119:3921aeca8633 | 690 | timeout ++; |
mbed_official | 119:3921aeca8633 | 691 | if (timeout >= WAIT_TIMEOUT) { |
mbed_official | 119:3921aeca8633 | 692 | return -1; |
mbed_official | 119:3921aeca8633 | 693 | } |
mbed_official | 119:3921aeca8633 | 694 | } |
mbed_official | 119:3921aeca8633 | 695 | if (break_flg == 0) { |
mbed_official | 119:3921aeca8633 | 696 | if (count == 0) { |
mbed_official | 119:3921aeca8633 | 697 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 698 | (void)REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 699 | } else { |
mbed_official | 119:3921aeca8633 | 700 | data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); |
mbed_official | 119:3921aeca8633 | 701 | } |
mbed_official | 119:3921aeca8633 | 702 | } |
mbed_official | 119:3921aeca8633 | 703 | } |
mbed_official | 119:3921aeca8633 | 704 | if (break_flg == 0) { |
mbed_official | 119:3921aeca8633 | 705 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 706 | } else { |
mbed_official | 119:3921aeca8633 | 707 | if ((i2c_status(obj) & SR2_RDRF) != 0) { |
mbed_official | 119:3921aeca8633 | 708 | if (count <= 1) { |
mbed_official | 119:3921aeca8633 | 709 | /* fail safe */ |
mbed_official | 119:3921aeca8633 | 710 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 711 | (void)REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 712 | } else { |
mbed_official | 119:3921aeca8633 | 713 | data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); |
mbed_official | 119:3921aeca8633 | 714 | } |
mbed_official | 119:3921aeca8633 | 715 | } |
mbed_official | 119:3921aeca8633 | 716 | } |
mbed_official | 119:3921aeca8633 | 717 | /* SR2.STOP = 0 */ |
mbed_official | 119:3921aeca8633 | 718 | REG(SR2.UINT32) &= ~SR2_STOP; |
mbed_official | 119:3921aeca8633 | 719 | |
mbed_official | 119:3921aeca8633 | 720 | return (count - 1); |
mbed_official | 119:3921aeca8633 | 721 | } |
mbed_official | 119:3921aeca8633 | 722 | |
mbed_official | 119:3921aeca8633 | 723 | int i2c_slave_write(i2c_t *obj, const char *data, int length) { |
mbed_official | 119:3921aeca8633 | 724 | int count = 0; |
mbed_official | 119:3921aeca8633 | 725 | int status = 0; |
mbed_official | 119:3921aeca8633 | 726 | |
mbed_official | 119:3921aeca8633 | 727 | if(length <= 0) { |
mbed_official | 119:3921aeca8633 | 728 | return 0; |
mbed_official | 119:3921aeca8633 | 729 | } |
mbed_official | 119:3921aeca8633 | 730 | |
mbed_official | 119:3921aeca8633 | 731 | while ((count < length) && (status == 0)) { |
mbed_official | 119:3921aeca8633 | 732 | status = i2c_do_write(obj, data[count]); |
mbed_official | 119:3921aeca8633 | 733 | if(status == 0) { |
mbed_official | 119:3921aeca8633 | 734 | /* Wait send end */ |
mbed_official | 119:3921aeca8633 | 735 | status = i2c_wait_TEND(obj); |
mbed_official | 119:3921aeca8633 | 736 | if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) { |
mbed_official | 119:3921aeca8633 | 737 | /* NACK */ |
mbed_official | 119:3921aeca8633 | 738 | break; |
mbed_official | 119:3921aeca8633 | 739 | } |
mbed_official | 119:3921aeca8633 | 740 | } |
mbed_official | 119:3921aeca8633 | 741 | count++; |
mbed_official | 119:3921aeca8633 | 742 | } |
mbed_official | 119:3921aeca8633 | 743 | /* dummy read */ |
mbed_official | 119:3921aeca8633 | 744 | (void)REG(DRR.UINT32); |
mbed_official | 119:3921aeca8633 | 745 | (void)i2c_wait_STOP(obj); |
mbed_official | 119:3921aeca8633 | 746 | i2c_set_SR2_NACKF_STOP(obj); |
mbed_official | 119:3921aeca8633 | 747 | |
mbed_official | 119:3921aeca8633 | 748 | return count; |
mbed_official | 119:3921aeca8633 | 749 | } |
mbed_official | 119:3921aeca8633 | 750 | |
mbed_official | 119:3921aeca8633 | 751 | void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { |
mbed_official | 119:3921aeca8633 | 752 | REG(SAR0.UINT32) = (address & 0xfffffffe); |
mbed_official | 119:3921aeca8633 | 753 | } |