mbed library sources. Supersedes mbed-src.
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targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c@119:3921aeca8633, 2016-04-29 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Apr 29 01:15:11 2016 +0100
- Revision:
- 119:3921aeca8633
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270
Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/
[Renesas RZ/A1H] Enable asynchronous communications
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 119:3921aeca8633 | 1 | /* mbed Microcontroller Library |
mbed_official | 119:3921aeca8633 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 119:3921aeca8633 | 3 | * |
mbed_official | 119:3921aeca8633 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 119:3921aeca8633 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 119:3921aeca8633 | 6 | * You may obtain a copy of the License at |
mbed_official | 119:3921aeca8633 | 7 | * |
mbed_official | 119:3921aeca8633 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 119:3921aeca8633 | 9 | * |
mbed_official | 119:3921aeca8633 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 119:3921aeca8633 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 119:3921aeca8633 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 119:3921aeca8633 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 119:3921aeca8633 | 14 | * limitations under the License. |
mbed_official | 119:3921aeca8633 | 15 | */ |
mbed_official | 119:3921aeca8633 | 16 | #include <stddef.h> |
mbed_official | 119:3921aeca8633 | 17 | |
mbed_official | 119:3921aeca8633 | 18 | #include "gpio_irq_api.h" |
mbed_official | 119:3921aeca8633 | 19 | #include "intc_iodefine.h" |
mbed_official | 119:3921aeca8633 | 20 | #include "pinmap.h" |
mbed_official | 119:3921aeca8633 | 21 | #include "cmsis.h" |
mbed_official | 119:3921aeca8633 | 22 | #include "gpio_addrdefine.h" |
mbed_official | 119:3921aeca8633 | 23 | |
mbed_official | 119:3921aeca8633 | 24 | #define CHANNEL_NUM 8 |
mbed_official | 119:3921aeca8633 | 25 | |
mbed_official | 119:3921aeca8633 | 26 | static void gpio_irq0(void); |
mbed_official | 119:3921aeca8633 | 27 | static void gpio_irq1(void); |
mbed_official | 119:3921aeca8633 | 28 | static void gpio_irq2(void); |
mbed_official | 119:3921aeca8633 | 29 | static void gpio_irq3(void); |
mbed_official | 119:3921aeca8633 | 30 | static void gpio_irq4(void); |
mbed_official | 119:3921aeca8633 | 31 | static void gpio_irq5(void); |
mbed_official | 119:3921aeca8633 | 32 | static void gpio_irq6(void); |
mbed_official | 119:3921aeca8633 | 33 | static void gpio_irq7(void); |
mbed_official | 119:3921aeca8633 | 34 | |
mbed_official | 119:3921aeca8633 | 35 | static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL}; |
mbed_official | 119:3921aeca8633 | 36 | static gpio_irq_handler irq_handler; |
mbed_official | 119:3921aeca8633 | 37 | static const int nIRQn_h = 32; |
mbed_official | 119:3921aeca8633 | 38 | extern PinName gpio_multi_guard; |
mbed_official | 119:3921aeca8633 | 39 | |
mbed_official | 119:3921aeca8633 | 40 | enum { |
mbed_official | 119:3921aeca8633 | 41 | IRQ0,IRQ1, |
mbed_official | 119:3921aeca8633 | 42 | IRQ2,IRQ3, |
mbed_official | 119:3921aeca8633 | 43 | IRQ4,IRQ5, |
mbed_official | 119:3921aeca8633 | 44 | IRQ6,IRQ7, |
mbed_official | 119:3921aeca8633 | 45 | |
mbed_official | 119:3921aeca8633 | 46 | } IRQNo; |
mbed_official | 119:3921aeca8633 | 47 | |
mbed_official | 119:3921aeca8633 | 48 | static const IRQHandler irq_tbl[CHANNEL_NUM] = { |
mbed_official | 119:3921aeca8633 | 49 | &gpio_irq0, |
mbed_official | 119:3921aeca8633 | 50 | &gpio_irq1, |
mbed_official | 119:3921aeca8633 | 51 | &gpio_irq2, |
mbed_official | 119:3921aeca8633 | 52 | &gpio_irq3, |
mbed_official | 119:3921aeca8633 | 53 | &gpio_irq4, |
mbed_official | 119:3921aeca8633 | 54 | &gpio_irq5, |
mbed_official | 119:3921aeca8633 | 55 | &gpio_irq6, |
mbed_official | 119:3921aeca8633 | 56 | &gpio_irq7, |
mbed_official | 119:3921aeca8633 | 57 | }; |
mbed_official | 119:3921aeca8633 | 58 | |
mbed_official | 119:3921aeca8633 | 59 | #ifdef MAX_PERI |
mbed_official | 119:3921aeca8633 | 60 | static const PinMap PinMap_IRQ[] = { |
mbed_official | 119:3921aeca8633 | 61 | {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, |
mbed_official | 119:3921aeca8633 | 62 | {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, |
mbed_official | 119:3921aeca8633 | 63 | {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, |
mbed_official | 119:3921aeca8633 | 64 | {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, |
mbed_official | 119:3921aeca8633 | 65 | {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, |
mbed_official | 119:3921aeca8633 | 66 | {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, |
mbed_official | 119:3921aeca8633 | 67 | {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, |
mbed_official | 119:3921aeca8633 | 68 | {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, |
mbed_official | 119:3921aeca8633 | 69 | {NC, NC, 0} |
mbed_official | 119:3921aeca8633 | 70 | }; |
mbed_official | 119:3921aeca8633 | 71 | #else |
mbed_official | 119:3921aeca8633 | 72 | static const PinMap PinMap_IRQ[] = { |
mbed_official | 119:3921aeca8633 | 73 | {P9_1, IRQ0, 4}, |
mbed_official | 119:3921aeca8633 | 74 | {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, |
mbed_official | 119:3921aeca8633 | 75 | {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, |
mbed_official | 119:3921aeca8633 | 76 | {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, |
mbed_official | 119:3921aeca8633 | 77 | {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, |
mbed_official | 119:3921aeca8633 | 78 | {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, |
mbed_official | 119:3921aeca8633 | 79 | {NC, NC, 0} |
mbed_official | 119:3921aeca8633 | 80 | }; |
mbed_official | 119:3921aeca8633 | 81 | #endif |
mbed_official | 119:3921aeca8633 | 82 | |
mbed_official | 119:3921aeca8633 | 83 | static void handle_interrupt_in(int irq_num) { |
mbed_official | 119:3921aeca8633 | 84 | uint16_t irqs; |
mbed_official | 119:3921aeca8633 | 85 | uint16_t edge_req; |
mbed_official | 119:3921aeca8633 | 86 | gpio_irq_t *obj; |
mbed_official | 119:3921aeca8633 | 87 | gpio_irq_event irq_event; |
mbed_official | 119:3921aeca8633 | 88 | |
mbed_official | 119:3921aeca8633 | 89 | irqs = INTCIRQRR; |
mbed_official | 119:3921aeca8633 | 90 | if (irqs & (1 << irq_num)) { |
mbed_official | 119:3921aeca8633 | 91 | obj = channel_obj[irq_num]; |
mbed_official | 119:3921aeca8633 | 92 | if (obj != NULL) { |
mbed_official | 119:3921aeca8633 | 93 | edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3); |
mbed_official | 119:3921aeca8633 | 94 | if (edge_req == 1) { |
mbed_official | 119:3921aeca8633 | 95 | irq_event = IRQ_FALL; |
mbed_official | 119:3921aeca8633 | 96 | } else if (edge_req == 2) { |
mbed_official | 119:3921aeca8633 | 97 | irq_event = IRQ_RISE; |
mbed_official | 119:3921aeca8633 | 98 | } else { |
mbed_official | 119:3921aeca8633 | 99 | uint32_t mask = (1 << (obj->pin & 0x0F)); |
mbed_official | 119:3921aeca8633 | 100 | __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin)); |
mbed_official | 119:3921aeca8633 | 101 | |
mbed_official | 119:3921aeca8633 | 102 | if ((*reg_in & mask) == 0) { |
mbed_official | 119:3921aeca8633 | 103 | irq_event = IRQ_FALL; |
mbed_official | 119:3921aeca8633 | 104 | } else { |
mbed_official | 119:3921aeca8633 | 105 | irq_event = IRQ_RISE; |
mbed_official | 119:3921aeca8633 | 106 | } |
mbed_official | 119:3921aeca8633 | 107 | } |
mbed_official | 119:3921aeca8633 | 108 | irq_handler(obj->port, irq_event); |
mbed_official | 119:3921aeca8633 | 109 | } |
mbed_official | 119:3921aeca8633 | 110 | INTCIRQRR &= ~(1 << irq_num); |
mbed_official | 119:3921aeca8633 | 111 | } |
mbed_official | 119:3921aeca8633 | 112 | } |
mbed_official | 119:3921aeca8633 | 113 | |
mbed_official | 119:3921aeca8633 | 114 | static void gpio_irq0(void) { |
mbed_official | 119:3921aeca8633 | 115 | handle_interrupt_in(0); |
mbed_official | 119:3921aeca8633 | 116 | } |
mbed_official | 119:3921aeca8633 | 117 | |
mbed_official | 119:3921aeca8633 | 118 | static void gpio_irq1(void) { |
mbed_official | 119:3921aeca8633 | 119 | handle_interrupt_in(1); |
mbed_official | 119:3921aeca8633 | 120 | } |
mbed_official | 119:3921aeca8633 | 121 | |
mbed_official | 119:3921aeca8633 | 122 | static void gpio_irq2(void) { |
mbed_official | 119:3921aeca8633 | 123 | handle_interrupt_in(2); |
mbed_official | 119:3921aeca8633 | 124 | } |
mbed_official | 119:3921aeca8633 | 125 | |
mbed_official | 119:3921aeca8633 | 126 | static void gpio_irq3(void) { |
mbed_official | 119:3921aeca8633 | 127 | handle_interrupt_in(3); |
mbed_official | 119:3921aeca8633 | 128 | } |
mbed_official | 119:3921aeca8633 | 129 | |
mbed_official | 119:3921aeca8633 | 130 | static void gpio_irq4(void) { |
mbed_official | 119:3921aeca8633 | 131 | handle_interrupt_in(4); |
mbed_official | 119:3921aeca8633 | 132 | } |
mbed_official | 119:3921aeca8633 | 133 | |
mbed_official | 119:3921aeca8633 | 134 | static void gpio_irq5(void) { |
mbed_official | 119:3921aeca8633 | 135 | handle_interrupt_in(5); |
mbed_official | 119:3921aeca8633 | 136 | } |
mbed_official | 119:3921aeca8633 | 137 | |
mbed_official | 119:3921aeca8633 | 138 | static void gpio_irq6(void) { |
mbed_official | 119:3921aeca8633 | 139 | handle_interrupt_in(6); |
mbed_official | 119:3921aeca8633 | 140 | } |
mbed_official | 119:3921aeca8633 | 141 | |
mbed_official | 119:3921aeca8633 | 142 | static void gpio_irq7(void) { |
mbed_official | 119:3921aeca8633 | 143 | handle_interrupt_in(7); |
mbed_official | 119:3921aeca8633 | 144 | } |
mbed_official | 119:3921aeca8633 | 145 | |
mbed_official | 119:3921aeca8633 | 146 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
mbed_official | 119:3921aeca8633 | 147 | int shift; |
mbed_official | 119:3921aeca8633 | 148 | if (pin == NC) return -1; |
mbed_official | 119:3921aeca8633 | 149 | |
mbed_official | 119:3921aeca8633 | 150 | obj->ch = pinmap_peripheral(pin, PinMap_IRQ); |
mbed_official | 119:3921aeca8633 | 151 | obj->pin = (int)pin ; |
mbed_official | 119:3921aeca8633 | 152 | obj->port = (int)id ; |
mbed_official | 119:3921aeca8633 | 153 | |
mbed_official | 119:3921aeca8633 | 154 | shift = obj->ch*2; |
mbed_official | 119:3921aeca8633 | 155 | channel_obj[obj->ch] = obj; |
mbed_official | 119:3921aeca8633 | 156 | irq_handler = handler; |
mbed_official | 119:3921aeca8633 | 157 | |
mbed_official | 119:3921aeca8633 | 158 | pinmap_pinout(pin, PinMap_IRQ); |
mbed_official | 119:3921aeca8633 | 159 | gpio_multi_guard = pin; /* Set multi guard */ |
mbed_official | 119:3921aeca8633 | 160 | |
mbed_official | 119:3921aeca8633 | 161 | // INTC settings |
mbed_official | 119:3921aeca8633 | 162 | InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]); |
mbed_official | 119:3921aeca8633 | 163 | INTCICR1 &= ~(0x3 << shift); |
mbed_official | 119:3921aeca8633 | 164 | INTCICR1 |= (0x3 << shift); |
mbed_official | 119:3921aeca8633 | 165 | GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); |
mbed_official | 119:3921aeca8633 | 166 | GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); |
mbed_official | 119:3921aeca8633 | 167 | obj->int_enable = 1; |
mbed_official | 119:3921aeca8633 | 168 | __enable_irq(); |
mbed_official | 119:3921aeca8633 | 169 | |
mbed_official | 119:3921aeca8633 | 170 | return 0; |
mbed_official | 119:3921aeca8633 | 171 | } |
mbed_official | 119:3921aeca8633 | 172 | |
mbed_official | 119:3921aeca8633 | 173 | void gpio_irq_free(gpio_irq_t *obj) { |
mbed_official | 119:3921aeca8633 | 174 | channel_obj[obj->ch] = NULL; |
mbed_official | 119:3921aeca8633 | 175 | } |
mbed_official | 119:3921aeca8633 | 176 | |
mbed_official | 119:3921aeca8633 | 177 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
mbed_official | 119:3921aeca8633 | 178 | int shift = obj->ch*2; |
mbed_official | 119:3921aeca8633 | 179 | uint16_t val = event == IRQ_RISE ? 2 : |
mbed_official | 119:3921aeca8633 | 180 | event == IRQ_FALL ? 1 : 0; |
mbed_official | 119:3921aeca8633 | 181 | uint16_t work_icr_val; |
mbed_official | 119:3921aeca8633 | 182 | |
mbed_official | 119:3921aeca8633 | 183 | /* check edge interrupt setting */ |
mbed_official | 119:3921aeca8633 | 184 | work_icr_val = INTCICR1; |
mbed_official | 119:3921aeca8633 | 185 | if (enable == 1) { |
mbed_official | 119:3921aeca8633 | 186 | /* Set interrupt serect */ |
mbed_official | 119:3921aeca8633 | 187 | work_icr_val |= (val << shift); |
mbed_official | 119:3921aeca8633 | 188 | } else { |
mbed_official | 119:3921aeca8633 | 189 | /* Clear interrupt serect */ |
mbed_official | 119:3921aeca8633 | 190 | work_icr_val &= ~(val << shift); |
mbed_official | 119:3921aeca8633 | 191 | } |
mbed_official | 119:3921aeca8633 | 192 | |
mbed_official | 119:3921aeca8633 | 193 | if ((work_icr_val & (3 << shift)) == 0) { |
mbed_official | 119:3921aeca8633 | 194 | /* No edge interrupt setting */ |
mbed_official | 119:3921aeca8633 | 195 | GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); |
mbed_official | 119:3921aeca8633 | 196 | /* Clear Interrupt flags */ |
mbed_official | 119:3921aeca8633 | 197 | INTCIRQRR &= ~(1 << obj->ch); |
mbed_official | 119:3921aeca8633 | 198 | INTCICR1 = work_icr_val; |
mbed_official | 119:3921aeca8633 | 199 | } else if (obj->int_enable == 1) { |
mbed_official | 119:3921aeca8633 | 200 | INTCICR1 = work_icr_val; |
mbed_official | 119:3921aeca8633 | 201 | GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); |
mbed_official | 119:3921aeca8633 | 202 | } else { |
mbed_official | 119:3921aeca8633 | 203 | INTCICR1 = work_icr_val; |
mbed_official | 119:3921aeca8633 | 204 | } |
mbed_official | 119:3921aeca8633 | 205 | } |
mbed_official | 119:3921aeca8633 | 206 | |
mbed_official | 119:3921aeca8633 | 207 | void gpio_irq_enable(gpio_irq_t *obj) { |
mbed_official | 119:3921aeca8633 | 208 | int shift = obj->ch*2; |
mbed_official | 119:3921aeca8633 | 209 | uint16_t work_icr_val = INTCICR1; |
mbed_official | 119:3921aeca8633 | 210 | |
mbed_official | 119:3921aeca8633 | 211 | /* check edge interrupt setting */ |
mbed_official | 119:3921aeca8633 | 212 | if ((work_icr_val & (3 << shift)) != 0) { |
mbed_official | 119:3921aeca8633 | 213 | GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); |
mbed_official | 119:3921aeca8633 | 214 | } |
mbed_official | 119:3921aeca8633 | 215 | obj->int_enable = 1; |
mbed_official | 119:3921aeca8633 | 216 | } |
mbed_official | 119:3921aeca8633 | 217 | |
mbed_official | 119:3921aeca8633 | 218 | void gpio_irq_disable(gpio_irq_t *obj) { |
mbed_official | 119:3921aeca8633 | 219 | GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); |
mbed_official | 119:3921aeca8633 | 220 | obj->int_enable = 0; |
mbed_official | 119:3921aeca8633 | 221 | } |
mbed_official | 119:3921aeca8633 | 222 |