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mbed library sources. Supersedes mbed-src.

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targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c@119:3921aeca8633, 2016-04-29 (annotated)

Committer:
mbed_official
Date:
Fri Apr 29 01:15:11 2016 +0100
Revision:
119:3921aeca8633
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270



Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/



[Renesas RZ/A1H] Enable asynchronous communications

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 119:3921aeca8633 1 /* mbed Microcontroller Library
mbed_official 119:3921aeca8633 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 119:3921aeca8633 3 *
mbed_official 119:3921aeca8633 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 119:3921aeca8633 5 * you may not use this file except in compliance with the License.
mbed_official 119:3921aeca8633 6 * You may obtain a copy of the License at
mbed_official 119:3921aeca8633 7 *
mbed_official 119:3921aeca8633 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 119:3921aeca8633 9 *
mbed_official 119:3921aeca8633 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 119:3921aeca8633 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 119:3921aeca8633 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 119:3921aeca8633 13 * See the License for the specific language governing permissions and
mbed_official 119:3921aeca8633 14 * limitations under the License.
mbed_official 119:3921aeca8633 15 */
mbed_official 119:3921aeca8633 16 #include <string.h>
mbed_official 119:3921aeca8633 17 #include "mbed_assert.h"
mbed_official 119:3921aeca8633 18 #include "can_api.h"
mbed_official 119:3921aeca8633 19 #include "RZ_A1_Init.h"
mbed_official 119:3921aeca8633 20 #include "cmsis.h"
mbed_official 119:3921aeca8633 21 #include "pinmap.h"
mbed_official 119:3921aeca8633 22 #include "rscan0_iodefine.h"
mbed_official 119:3921aeca8633 23 #include "r_typedefs.h"
mbed_official 119:3921aeca8633 24 #include "VKRZA1H.h"
mbed_official 119:3921aeca8633 25
mbed_official 119:3921aeca8633 26 #define CAN_NUM 5
mbed_official 119:3921aeca8633 27 #define CAN_SND_RCV 2
mbed_official 119:3921aeca8633 28 #define IRQ_NUM 8
mbed_official 119:3921aeca8633 29
mbed_official 119:3921aeca8633 30 static void can_rec_irq(uint32_t ch);
mbed_official 119:3921aeca8633 31 static void can_trx_irq(uint32_t ch);
mbed_official 119:3921aeca8633 32 static void can_err_irq(uint32_t ch, CanIrqType type);
mbed_official 119:3921aeca8633 33 static void can0_rec_irq(void);
mbed_official 119:3921aeca8633 34 static void can1_rec_irq(void);
mbed_official 119:3921aeca8633 35 static void can2_rec_irq(void);
mbed_official 119:3921aeca8633 36 static void can3_rec_irq(void);
mbed_official 119:3921aeca8633 37 static void can4_rec_irq(void);
mbed_official 119:3921aeca8633 38 static void can0_trx_irq(void);
mbed_official 119:3921aeca8633 39 static void can1_trx_irq(void);
mbed_official 119:3921aeca8633 40 static void can2_trx_irq(void);
mbed_official 119:3921aeca8633 41 static void can3_trx_irq(void);
mbed_official 119:3921aeca8633 42 static void can4_trx_irq(void);
mbed_official 119:3921aeca8633 43 static void can0_err_warning_irq(void);
mbed_official 119:3921aeca8633 44 static void can1_err_warning_irq(void);
mbed_official 119:3921aeca8633 45 static void can2_err_warning_irq(void);
mbed_official 119:3921aeca8633 46 static void can3_err_warning_irq(void);
mbed_official 119:3921aeca8633 47 static void can4_err_warning_irq(void);
mbed_official 119:3921aeca8633 48 static void can0_overrun_irq(void);
mbed_official 119:3921aeca8633 49 static void can1_overrun_irq(void);
mbed_official 119:3921aeca8633 50 static void can2_overrun_irq(void);
mbed_official 119:3921aeca8633 51 static void can3_overrun_irq(void);
mbed_official 119:3921aeca8633 52 static void can4_overrun_irq(void);
mbed_official 119:3921aeca8633 53 static void can0_passive_irq(void);
mbed_official 119:3921aeca8633 54 static void can1_passive_irq(void);
mbed_official 119:3921aeca8633 55 static void can2_passive_irq(void);
mbed_official 119:3921aeca8633 56 static void can3_passive_irq(void);
mbed_official 119:3921aeca8633 57 static void can4_passive_irq(void);
mbed_official 119:3921aeca8633 58 static void can0_arb_lost_irq(void);
mbed_official 119:3921aeca8633 59 static void can1_arb_lost_irq(void);
mbed_official 119:3921aeca8633 60 static void can2_arb_lost_irq(void);
mbed_official 119:3921aeca8633 61 static void can3_arb_lost_irq(void);
mbed_official 119:3921aeca8633 62 static void can4_arb_lost_irq(void);
mbed_official 119:3921aeca8633 63 static void can0_bus_err_irq(void);
mbed_official 119:3921aeca8633 64 static void can1_bus_err_irq(void);
mbed_official 119:3921aeca8633 65 static void can2_bus_err_irq(void);
mbed_official 119:3921aeca8633 66 static void can3_bus_err_irq(void);
mbed_official 119:3921aeca8633 67 static void can4_bus_err_irq(void);
mbed_official 119:3921aeca8633 68 static void can_reset_reg(can_t *obj);
mbed_official 119:3921aeca8633 69 static void can_reset_recv_rule(can_t *obj);
mbed_official 119:3921aeca8633 70 static void can_reset_buffer(can_t *obj);
mbed_official 119:3921aeca8633 71 static void can_reconfigure_channel(void);
mbed_official 119:3921aeca8633 72 static void can_set_frequency(can_t *obj, int f);
mbed_official 119:3921aeca8633 73 static void can_set_global_mode(int mode);
mbed_official 119:3921aeca8633 74 static void can_set_channel_mode(uint32_t ch, int mode);
mbed_official 119:3921aeca8633 75
mbed_official 119:3921aeca8633 76 typedef enum {
mbed_official 119:3921aeca8633 77 CAN_SEND = 0,
mbed_official 119:3921aeca8633 78 CAN_RECV
mbed_official 119:3921aeca8633 79 } CANfunc;
mbed_official 119:3921aeca8633 80
mbed_official 119:3921aeca8633 81 typedef enum {
mbed_official 119:3921aeca8633 82 GL_OPE = 0,
mbed_official 119:3921aeca8633 83 GL_RESET,
mbed_official 119:3921aeca8633 84 GL_TEST
mbed_official 119:3921aeca8633 85 } Globalmode;
mbed_official 119:3921aeca8633 86
mbed_official 119:3921aeca8633 87 typedef enum {
mbed_official 119:3921aeca8633 88 CH_COMM = 0,
mbed_official 119:3921aeca8633 89 CH_RESET,
mbed_official 119:3921aeca8633 90 CH_HOLD
mbed_official 119:3921aeca8633 91 } Channelmode;
mbed_official 119:3921aeca8633 92
mbed_official 119:3921aeca8633 93 typedef struct {
mbed_official 119:3921aeca8633 94 IRQn_Type int_num; /* Interrupt number */
mbed_official 119:3921aeca8633 95 IRQHandler handler; /* Interrupt handler */
mbed_official 119:3921aeca8633 96 } can_info_int_t;
mbed_official 119:3921aeca8633 97
mbed_official 119:3921aeca8633 98 static can_irq_handler irq_handler;
mbed_official 119:3921aeca8633 99 static uint32_t can_irq_id[CAN_NUM];
mbed_official 119:3921aeca8633 100 static int can_initialized[CAN_NUM] = {0};
mbed_official 119:3921aeca8633 101
mbed_official 119:3921aeca8633 102 #ifdef MAX_PERI
mbed_official 119:3921aeca8633 103 static const PinMap PinMap_CAN_RD[] = {
mbed_official 119:3921aeca8633 104 {P7_8 , CAN_0, 4},
mbed_official 119:3921aeca8633 105 {P9_1 , CAN_0, 3},
mbed_official 119:3921aeca8633 106 {P1_4 , CAN_1, 3},
mbed_official 119:3921aeca8633 107 {P5_9 , CAN_1, 5},
mbed_official 119:3921aeca8633 108 {P7_11 , CAN_1, 4},
mbed_official 119:3921aeca8633 109 {P4_9 , CAN_2, 6},
mbed_official 119:3921aeca8633 110 {P6_4 , CAN_2, 3},
mbed_official 119:3921aeca8633 111 {P7_2 , CAN_2, 5},
mbed_official 119:3921aeca8633 112 {P2_12 , CAN_3, 5},
mbed_official 119:3921aeca8633 113 {P4_2 , CAN_3, 4},
mbed_official 119:3921aeca8633 114 {P1_5 , CAN_4, 3},
mbed_official 119:3921aeca8633 115 {P2_14 , CAN_4, 5},
mbed_official 119:3921aeca8633 116 {NC , NC , 0}
mbed_official 119:3921aeca8633 117 };
mbed_official 119:3921aeca8633 118
mbed_official 119:3921aeca8633 119 static const PinMap PinMap_CAN_TD[] = {
mbed_official 119:3921aeca8633 120 {P7_9 , CAN_0, 4},
mbed_official 119:3921aeca8633 121 {P9_0 , CAN_0, 3},
mbed_official 119:3921aeca8633 122 {P5_10 , CAN_1, 5},
mbed_official 119:3921aeca8633 123 {P7_10 , CAN_1, 4},
mbed_official 119:3921aeca8633 124 {P4_8 , CAN_2, 6},
mbed_official 119:3921aeca8633 125 {P6_5 , CAN_2, 3},
mbed_official 119:3921aeca8633 126 {P7_3 , CAN_2, 5},
mbed_official 119:3921aeca8633 127 {P2_13 , CAN_3, 5},
mbed_official 119:3921aeca8633 128 {P4_3 , CAN_3, 4},
mbed_official 119:3921aeca8633 129 {P4_11 , CAN_4, 6},
mbed_official 119:3921aeca8633 130 {P8_10 , CAN_4, 5},
mbed_official 119:3921aeca8633 131 {NC , NC , 0}
mbed_official 119:3921aeca8633 132 };
mbed_official 119:3921aeca8633 133 #else
mbed_official 119:3921aeca8633 134 static const PinMap PinMap_CAN_RD[] = {
mbed_official 119:3921aeca8633 135 {P9_1 , CAN_0, 3},
mbed_official 119:3921aeca8633 136 {P1_4 , CAN_1, 3},
mbed_official 119:3921aeca8633 137 {P5_9 , CAN_1, 5},
mbed_official 119:3921aeca8633 138 {P4_2 , CAN_3, 4},
mbed_official 119:3921aeca8633 139 {P1_5 , CAN_4, 3},
mbed_official 119:3921aeca8633 140 {NC , NC , 0}
mbed_official 119:3921aeca8633 141 };
mbed_official 119:3921aeca8633 142
mbed_official 119:3921aeca8633 143 static const PinMap PinMap_CAN_TD[] = {
mbed_official 119:3921aeca8633 144 {P9_0 , CAN_0, 3},
mbed_official 119:3921aeca8633 145 {P5_10 , CAN_1, 5},
mbed_official 119:3921aeca8633 146 {P4_3 , CAN_3, 4},
mbed_official 119:3921aeca8633 147 {P8_10 , CAN_4, 5},
mbed_official 119:3921aeca8633 148 {NC , NC , 0}
mbed_official 119:3921aeca8633 149 };
mbed_official 119:3921aeca8633 150 #endif
mbed_official 119:3921aeca8633 151
mbed_official 119:3921aeca8633 152 static __IO uint32_t *CTR_MATCH[] = {
mbed_official 119:3921aeca8633 153 &RSCAN0C0CTR,
mbed_official 119:3921aeca8633 154 &RSCAN0C1CTR,
mbed_official 119:3921aeca8633 155 &RSCAN0C2CTR,
mbed_official 119:3921aeca8633 156 &RSCAN0C3CTR,
mbed_official 119:3921aeca8633 157 &RSCAN0C4CTR,
mbed_official 119:3921aeca8633 158 };
mbed_official 119:3921aeca8633 159
mbed_official 119:3921aeca8633 160 static __IO uint32_t *CFG_MATCH[] = {
mbed_official 119:3921aeca8633 161 &RSCAN0C0CFG,
mbed_official 119:3921aeca8633 162 &RSCAN0C1CFG,
mbed_official 119:3921aeca8633 163 &RSCAN0C2CFG,
mbed_official 119:3921aeca8633 164 &RSCAN0C3CFG,
mbed_official 119:3921aeca8633 165 &RSCAN0C4CFG,
mbed_official 119:3921aeca8633 166 };
mbed_official 119:3921aeca8633 167
mbed_official 119:3921aeca8633 168 static __IO uint32_t *RFCC_MATCH[] = {
mbed_official 119:3921aeca8633 169 &RSCAN0RFCC0,
mbed_official 119:3921aeca8633 170 &RSCAN0RFCC1,
mbed_official 119:3921aeca8633 171 &RSCAN0RFCC2,
mbed_official 119:3921aeca8633 172 &RSCAN0RFCC3,
mbed_official 119:3921aeca8633 173 &RSCAN0RFCC4,
mbed_official 119:3921aeca8633 174 &RSCAN0RFCC5,
mbed_official 119:3921aeca8633 175 &RSCAN0RFCC6,
mbed_official 119:3921aeca8633 176 &RSCAN0RFCC7
mbed_official 119:3921aeca8633 177 };
mbed_official 119:3921aeca8633 178
mbed_official 119:3921aeca8633 179 static __IO uint32_t *TXQCC_MATCH[] = {
mbed_official 119:3921aeca8633 180 &RSCAN0TXQCC0,
mbed_official 119:3921aeca8633 181 &RSCAN0TXQCC1,
mbed_official 119:3921aeca8633 182 &RSCAN0TXQCC2,
mbed_official 119:3921aeca8633 183 &RSCAN0TXQCC3,
mbed_official 119:3921aeca8633 184 &RSCAN0TXQCC4,
mbed_official 119:3921aeca8633 185 };
mbed_official 119:3921aeca8633 186
mbed_official 119:3921aeca8633 187 static __IO uint32_t *THLCC_MATCH[] = {
mbed_official 119:3921aeca8633 188 &RSCAN0THLCC0,
mbed_official 119:3921aeca8633 189 &RSCAN0THLCC1,
mbed_official 119:3921aeca8633 190 &RSCAN0THLCC2,
mbed_official 119:3921aeca8633 191 &RSCAN0THLCC3,
mbed_official 119:3921aeca8633 192 &RSCAN0THLCC4,
mbed_official 119:3921aeca8633 193 };
mbed_official 119:3921aeca8633 194
mbed_official 119:3921aeca8633 195 static __IO uint32_t *STS_MATCH[] = {
mbed_official 119:3921aeca8633 196 &RSCAN0C0STS,
mbed_official 119:3921aeca8633 197 &RSCAN0C1STS,
mbed_official 119:3921aeca8633 198 &RSCAN0C2STS,
mbed_official 119:3921aeca8633 199 &RSCAN0C3STS,
mbed_official 119:3921aeca8633 200 &RSCAN0C4STS,
mbed_official 119:3921aeca8633 201 };
mbed_official 119:3921aeca8633 202
mbed_official 119:3921aeca8633 203 static __IO uint32_t *ERFL_MATCH[] = {
mbed_official 119:3921aeca8633 204 &RSCAN0C0ERFL,
mbed_official 119:3921aeca8633 205 &RSCAN0C1ERFL,
mbed_official 119:3921aeca8633 206 &RSCAN0C2ERFL,
mbed_official 119:3921aeca8633 207 &RSCAN0C3ERFL,
mbed_official 119:3921aeca8633 208 &RSCAN0C4ERFL,
mbed_official 119:3921aeca8633 209 };
mbed_official 119:3921aeca8633 210
mbed_official 119:3921aeca8633 211 static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 212 { &RSCAN0CFCC0 , &RSCAN0CFCC1 },
mbed_official 119:3921aeca8633 213 { &RSCAN0CFCC3 , &RSCAN0CFCC4 },
mbed_official 119:3921aeca8633 214 { &RSCAN0CFCC6 , &RSCAN0CFCC7 },
mbed_official 119:3921aeca8633 215 { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
mbed_official 119:3921aeca8633 216 { &RSCAN0CFCC12, &RSCAN0CFCC13 }
mbed_official 119:3921aeca8633 217 };
mbed_official 119:3921aeca8633 218
mbed_official 119:3921aeca8633 219 static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 220 { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 },
mbed_official 119:3921aeca8633 221 { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 },
mbed_official 119:3921aeca8633 222 { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 },
mbed_official 119:3921aeca8633 223 { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
mbed_official 119:3921aeca8633 224 { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }
mbed_official 119:3921aeca8633 225 };
mbed_official 119:3921aeca8633 226
mbed_official 119:3921aeca8633 227 static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 228 { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 },
mbed_official 119:3921aeca8633 229 { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 },
mbed_official 119:3921aeca8633 230 { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 },
mbed_official 119:3921aeca8633 231 { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
mbed_official 119:3921aeca8633 232 { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }
mbed_official 119:3921aeca8633 233 };
mbed_official 119:3921aeca8633 234
mbed_official 119:3921aeca8633 235 static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 236 { &RSCAN0CFID0 , &RSCAN0CFID1 },
mbed_official 119:3921aeca8633 237 { &RSCAN0CFID3 , &RSCAN0CFID4 },
mbed_official 119:3921aeca8633 238 { &RSCAN0CFID6 , &RSCAN0CFID7 },
mbed_official 119:3921aeca8633 239 { &RSCAN0CFID9 , &RSCAN0CFID10 },
mbed_official 119:3921aeca8633 240 { &RSCAN0CFID12, &RSCAN0CFID13 }
mbed_official 119:3921aeca8633 241 };
mbed_official 119:3921aeca8633 242
mbed_official 119:3921aeca8633 243 static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 244 { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 },
mbed_official 119:3921aeca8633 245 { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 },
mbed_official 119:3921aeca8633 246 { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 },
mbed_official 119:3921aeca8633 247 { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
mbed_official 119:3921aeca8633 248 { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
mbed_official 119:3921aeca8633 249 };
mbed_official 119:3921aeca8633 250
mbed_official 119:3921aeca8633 251 static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 252 { &RSCAN0CFDF00 , &RSCAN0CFDF01 },
mbed_official 119:3921aeca8633 253 { &RSCAN0CFDF03 , &RSCAN0CFDF04 },
mbed_official 119:3921aeca8633 254 { &RSCAN0CFDF06 , &RSCAN0CFDF07 },
mbed_official 119:3921aeca8633 255 { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
mbed_official 119:3921aeca8633 256 { &RSCAN0CFDF012, &RSCAN0CFDF013 }
mbed_official 119:3921aeca8633 257 };
mbed_official 119:3921aeca8633 258
mbed_official 119:3921aeca8633 259 static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
mbed_official 119:3921aeca8633 260 { &RSCAN0CFDF10 , &RSCAN0CFDF11 },
mbed_official 119:3921aeca8633 261 { &RSCAN0CFDF13 , &RSCAN0CFDF14 },
mbed_official 119:3921aeca8633 262 { &RSCAN0CFDF16 , &RSCAN0CFDF17 },
mbed_official 119:3921aeca8633 263 { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
mbed_official 119:3921aeca8633 264 { &RSCAN0CFDF112, &RSCAN0CFDF113 }
mbed_official 119:3921aeca8633 265 };
mbed_official 119:3921aeca8633 266
mbed_official 119:3921aeca8633 267 static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
mbed_official 119:3921aeca8633 268 {
mbed_official 119:3921aeca8633 269 { /* ch0 */
mbed_official 119:3921aeca8633 270 { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */
mbed_official 119:3921aeca8633 271 { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */
mbed_official 119:3921aeca8633 272 { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
mbed_official 119:3921aeca8633 273 { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */
mbed_official 119:3921aeca8633 274 { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */
mbed_official 119:3921aeca8633 275 { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */
mbed_official 119:3921aeca8633 276 { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */
mbed_official 119:3921aeca8633 277 { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */
mbed_official 119:3921aeca8633 278 },
mbed_official 119:3921aeca8633 279 { /* ch1 */
mbed_official 119:3921aeca8633 280 { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */
mbed_official 119:3921aeca8633 281 { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */
mbed_official 119:3921aeca8633 282 { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
mbed_official 119:3921aeca8633 283 { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */
mbed_official 119:3921aeca8633 284 { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */
mbed_official 119:3921aeca8633 285 { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */
mbed_official 119:3921aeca8633 286 { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */
mbed_official 119:3921aeca8633 287 { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */
mbed_official 119:3921aeca8633 288 },
mbed_official 119:3921aeca8633 289 { /* ch2 */
mbed_official 119:3921aeca8633 290 { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */
mbed_official 119:3921aeca8633 291 { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */
mbed_official 119:3921aeca8633 292 { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
mbed_official 119:3921aeca8633 293 { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */
mbed_official 119:3921aeca8633 294 { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */
mbed_official 119:3921aeca8633 295 { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */
mbed_official 119:3921aeca8633 296 { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */
mbed_official 119:3921aeca8633 297 { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */
mbed_official 119:3921aeca8633 298 },
mbed_official 119:3921aeca8633 299 { /* ch3 */
mbed_official 119:3921aeca8633 300 { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */
mbed_official 119:3921aeca8633 301 { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */
mbed_official 119:3921aeca8633 302 { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
mbed_official 119:3921aeca8633 303 { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */
mbed_official 119:3921aeca8633 304 { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */
mbed_official 119:3921aeca8633 305 { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */
mbed_official 119:3921aeca8633 306 { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */
mbed_official 119:3921aeca8633 307 { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */
mbed_official 119:3921aeca8633 308 },
mbed_official 119:3921aeca8633 309 { /* ch4 */
mbed_official 119:3921aeca8633 310 { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */
mbed_official 119:3921aeca8633 311 { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */
mbed_official 119:3921aeca8633 312 { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
mbed_official 119:3921aeca8633 313 { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */
mbed_official 119:3921aeca8633 314 { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */
mbed_official 119:3921aeca8633 315 { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */
mbed_official 119:3921aeca8633 316 { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */
mbed_official 119:3921aeca8633 317 { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */
mbed_official 119:3921aeca8633 318 }
mbed_official 119:3921aeca8633 319 };
mbed_official 119:3921aeca8633 320
mbed_official 119:3921aeca8633 321 static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
mbed_official 119:3921aeca8633 322 static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0;
mbed_official 119:3921aeca8633 323 static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
mbed_official 119:3921aeca8633 324 static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
mbed_official 119:3921aeca8633 325
mbed_official 119:3921aeca8633 326 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
mbed_official 119:3921aeca8633 327 irq_handler = handler;
mbed_official 119:3921aeca8633 328 can_irq_id[obj->ch] = id;
mbed_official 119:3921aeca8633 329 }
mbed_official 119:3921aeca8633 330
mbed_official 119:3921aeca8633 331 void can_irq_free(can_t *obj) {
mbed_official 119:3921aeca8633 332 can_irq_id[obj->ch] = 0;
mbed_official 119:3921aeca8633 333 }
mbed_official 119:3921aeca8633 334
mbed_official 119:3921aeca8633 335 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
mbed_official 119:3921aeca8633 336 __IO uint32_t *dmy_ctr;
mbed_official 119:3921aeca8633 337
mbed_official 119:3921aeca8633 338 /* Wake-up Irq is not supported */
mbed_official 119:3921aeca8633 339 if (type != IRQ_WAKEUP) {
mbed_official 119:3921aeca8633 340 if (enable) {
mbed_official 119:3921aeca8633 341 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 342 if (type == IRQ_ERROR) {
mbed_official 119:3921aeca8633 343 /* EWIE interrupts is enable */
mbed_official 119:3921aeca8633 344 *dmy_ctr |= 0x00000200;
mbed_official 119:3921aeca8633 345 } else if (type == IRQ_OVERRUN) {
mbed_official 119:3921aeca8633 346 /* OLIE interrupts is enable */
mbed_official 119:3921aeca8633 347 *dmy_ctr |= 0x00002000;
mbed_official 119:3921aeca8633 348 } else if (type == IRQ_PASSIVE) {
mbed_official 119:3921aeca8633 349 /* EPIE interrupts is enable */
mbed_official 119:3921aeca8633 350 *dmy_ctr |= 0x00000400;
mbed_official 119:3921aeca8633 351 } else if (type == IRQ_ARB) {
mbed_official 119:3921aeca8633 352 /* ALIE interrupts is enable */
mbed_official 119:3921aeca8633 353 *dmy_ctr |= 0x00008000;
mbed_official 119:3921aeca8633 354 } else if (type == IRQ_BUS) {
mbed_official 119:3921aeca8633 355 /* BEIE interrupts is enable */
mbed_official 119:3921aeca8633 356 *dmy_ctr |= 0x00000100;
mbed_official 119:3921aeca8633 357 }
mbed_official 119:3921aeca8633 358 InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
mbed_official 119:3921aeca8633 359 GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
mbed_official 119:3921aeca8633 360 GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
mbed_official 119:3921aeca8633 361 } else {
mbed_official 119:3921aeca8633 362 GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
mbed_official 119:3921aeca8633 363 }
mbed_official 119:3921aeca8633 364 }
mbed_official 119:3921aeca8633 365 }
mbed_official 119:3921aeca8633 366
mbed_official 119:3921aeca8633 367 static void can_rec_irq(uint32_t ch) {
mbed_official 119:3921aeca8633 368 __IO uint32_t *dmy_cfsts;
mbed_official 119:3921aeca8633 369
mbed_official 119:3921aeca8633 370 dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
mbed_official 119:3921aeca8633 371 *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF
mbed_official 119:3921aeca8633 372
mbed_official 119:3921aeca8633 373 irq_handler(can_irq_id[ch], IRQ_RX);
mbed_official 119:3921aeca8633 374 }
mbed_official 119:3921aeca8633 375
mbed_official 119:3921aeca8633 376 static void can_trx_irq(uint32_t ch) {
mbed_official 119:3921aeca8633 377 __IO uint32_t *dmy_cfsts;
mbed_official 119:3921aeca8633 378
mbed_official 119:3921aeca8633 379 dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
mbed_official 119:3921aeca8633 380 *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF
mbed_official 119:3921aeca8633 381
mbed_official 119:3921aeca8633 382 irq_handler(can_irq_id[ch], IRQ_TX);
mbed_official 119:3921aeca8633 383 }
mbed_official 119:3921aeca8633 384
mbed_official 119:3921aeca8633 385 static void can_err_irq(uint32_t ch, CanIrqType type) {
mbed_official 119:3921aeca8633 386 __IO uint32_t *dmy_erfl;
mbed_official 119:3921aeca8633 387 int val = 1;
mbed_official 119:3921aeca8633 388
mbed_official 119:3921aeca8633 389 dmy_erfl = ERFL_MATCH[ch];
mbed_official 119:3921aeca8633 390 switch (type) {
mbed_official 119:3921aeca8633 391 case IRQ_ERROR:
mbed_official 119:3921aeca8633 392 *dmy_erfl &= 0xFFFFFFFD; // Clear EWF
mbed_official 119:3921aeca8633 393 break;
mbed_official 119:3921aeca8633 394 case IRQ_OVERRUN:
mbed_official 119:3921aeca8633 395 *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF
mbed_official 119:3921aeca8633 396 break;
mbed_official 119:3921aeca8633 397 case IRQ_PASSIVE:
mbed_official 119:3921aeca8633 398 *dmy_erfl &= 0xFFFFFFFB; // Clear EPF
mbed_official 119:3921aeca8633 399 break;
mbed_official 119:3921aeca8633 400 case IRQ_ARB:
mbed_official 119:3921aeca8633 401 *dmy_erfl &= 0xFFFFFF7F; // Clear ALF
mbed_official 119:3921aeca8633 402 break;
mbed_official 119:3921aeca8633 403 case IRQ_BUS:
mbed_official 119:3921aeca8633 404 *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR
mbed_official 119:3921aeca8633 405 *dmy_erfl &= 0xFFFFFFFE; // Clear BEF
mbed_official 119:3921aeca8633 406 break;
mbed_official 119:3921aeca8633 407 case IRQ_WAKEUP:
mbed_official 119:3921aeca8633 408 /* not supported */
mbed_official 119:3921aeca8633 409 /* fall through */
mbed_official 119:3921aeca8633 410 default:
mbed_official 119:3921aeca8633 411 val = 0;
mbed_official 119:3921aeca8633 412 break;
mbed_official 119:3921aeca8633 413 }
mbed_official 119:3921aeca8633 414 if (val == 1) {
mbed_official 119:3921aeca8633 415 irq_handler(can_irq_id[ch], type);
mbed_official 119:3921aeca8633 416 }
mbed_official 119:3921aeca8633 417 }
mbed_official 119:3921aeca8633 418
mbed_official 119:3921aeca8633 419 static void can0_rec_irq(void) {
mbed_official 119:3921aeca8633 420 can_rec_irq(CAN_0);
mbed_official 119:3921aeca8633 421 }
mbed_official 119:3921aeca8633 422
mbed_official 119:3921aeca8633 423 static void can1_rec_irq(void) {
mbed_official 119:3921aeca8633 424 can_rec_irq(CAN_1);
mbed_official 119:3921aeca8633 425 }
mbed_official 119:3921aeca8633 426
mbed_official 119:3921aeca8633 427 static void can2_rec_irq(void) {
mbed_official 119:3921aeca8633 428 can_rec_irq(CAN_2);
mbed_official 119:3921aeca8633 429 }
mbed_official 119:3921aeca8633 430
mbed_official 119:3921aeca8633 431 static void can3_rec_irq(void) {
mbed_official 119:3921aeca8633 432 can_rec_irq(CAN_3);
mbed_official 119:3921aeca8633 433 }
mbed_official 119:3921aeca8633 434
mbed_official 119:3921aeca8633 435 static void can4_rec_irq(void) {
mbed_official 119:3921aeca8633 436 can_rec_irq(CAN_4);
mbed_official 119:3921aeca8633 437 }
mbed_official 119:3921aeca8633 438
mbed_official 119:3921aeca8633 439 static void can0_trx_irq(void) {
mbed_official 119:3921aeca8633 440 can_trx_irq(CAN_0);
mbed_official 119:3921aeca8633 441 }
mbed_official 119:3921aeca8633 442
mbed_official 119:3921aeca8633 443 static void can1_trx_irq(void) {
mbed_official 119:3921aeca8633 444 can_trx_irq(CAN_1);
mbed_official 119:3921aeca8633 445 }
mbed_official 119:3921aeca8633 446
mbed_official 119:3921aeca8633 447 static void can2_trx_irq(void) {
mbed_official 119:3921aeca8633 448 can_trx_irq(CAN_2);
mbed_official 119:3921aeca8633 449 }
mbed_official 119:3921aeca8633 450
mbed_official 119:3921aeca8633 451 static void can3_trx_irq(void) {
mbed_official 119:3921aeca8633 452 can_trx_irq(CAN_3);
mbed_official 119:3921aeca8633 453 }
mbed_official 119:3921aeca8633 454
mbed_official 119:3921aeca8633 455 static void can4_trx_irq(void) {
mbed_official 119:3921aeca8633 456 can_trx_irq(CAN_4);
mbed_official 119:3921aeca8633 457 }
mbed_official 119:3921aeca8633 458
mbed_official 119:3921aeca8633 459 static void can0_err_warning_irq(void) {
mbed_official 119:3921aeca8633 460 can_err_irq(CAN_0, IRQ_ERROR);
mbed_official 119:3921aeca8633 461 }
mbed_official 119:3921aeca8633 462
mbed_official 119:3921aeca8633 463 static void can1_err_warning_irq(void) {
mbed_official 119:3921aeca8633 464 can_err_irq(CAN_1, IRQ_ERROR);
mbed_official 119:3921aeca8633 465 }
mbed_official 119:3921aeca8633 466
mbed_official 119:3921aeca8633 467 static void can2_err_warning_irq(void) {
mbed_official 119:3921aeca8633 468 can_err_irq(CAN_2, IRQ_ERROR);
mbed_official 119:3921aeca8633 469 }
mbed_official 119:3921aeca8633 470
mbed_official 119:3921aeca8633 471 static void can3_err_warning_irq(void) {
mbed_official 119:3921aeca8633 472 can_err_irq(CAN_3, IRQ_ERROR);
mbed_official 119:3921aeca8633 473 }
mbed_official 119:3921aeca8633 474
mbed_official 119:3921aeca8633 475 static void can4_err_warning_irq(void) {
mbed_official 119:3921aeca8633 476 can_err_irq(CAN_4, IRQ_ERROR);
mbed_official 119:3921aeca8633 477 }
mbed_official 119:3921aeca8633 478
mbed_official 119:3921aeca8633 479 static void can0_overrun_irq(void) {
mbed_official 119:3921aeca8633 480 can_err_irq(CAN_0, IRQ_OVERRUN);
mbed_official 119:3921aeca8633 481 }
mbed_official 119:3921aeca8633 482
mbed_official 119:3921aeca8633 483 static void can1_overrun_irq(void) {
mbed_official 119:3921aeca8633 484 can_err_irq(CAN_1, IRQ_OVERRUN);
mbed_official 119:3921aeca8633 485 }
mbed_official 119:3921aeca8633 486
mbed_official 119:3921aeca8633 487 static void can2_overrun_irq(void) {
mbed_official 119:3921aeca8633 488 can_err_irq(CAN_2, IRQ_OVERRUN);
mbed_official 119:3921aeca8633 489 }
mbed_official 119:3921aeca8633 490
mbed_official 119:3921aeca8633 491 static void can3_overrun_irq(void) {
mbed_official 119:3921aeca8633 492 can_err_irq(CAN_3, IRQ_OVERRUN);
mbed_official 119:3921aeca8633 493 }
mbed_official 119:3921aeca8633 494
mbed_official 119:3921aeca8633 495 static void can4_overrun_irq(void) {
mbed_official 119:3921aeca8633 496 can_err_irq(CAN_4, IRQ_OVERRUN);
mbed_official 119:3921aeca8633 497 }
mbed_official 119:3921aeca8633 498
mbed_official 119:3921aeca8633 499 static void can0_passive_irq(void) {
mbed_official 119:3921aeca8633 500 can_err_irq(CAN_0, IRQ_PASSIVE);
mbed_official 119:3921aeca8633 501 }
mbed_official 119:3921aeca8633 502
mbed_official 119:3921aeca8633 503 static void can1_passive_irq(void) {
mbed_official 119:3921aeca8633 504 can_err_irq(CAN_1, IRQ_PASSIVE);
mbed_official 119:3921aeca8633 505 }
mbed_official 119:3921aeca8633 506
mbed_official 119:3921aeca8633 507 static void can2_passive_irq(void) {
mbed_official 119:3921aeca8633 508 can_err_irq(CAN_2, IRQ_PASSIVE);
mbed_official 119:3921aeca8633 509 }
mbed_official 119:3921aeca8633 510
mbed_official 119:3921aeca8633 511 static void can3_passive_irq(void) {
mbed_official 119:3921aeca8633 512 can_err_irq(CAN_3, IRQ_PASSIVE);
mbed_official 119:3921aeca8633 513 }
mbed_official 119:3921aeca8633 514
mbed_official 119:3921aeca8633 515 static void can4_passive_irq(void) {
mbed_official 119:3921aeca8633 516 can_err_irq(CAN_4, IRQ_PASSIVE);
mbed_official 119:3921aeca8633 517 }
mbed_official 119:3921aeca8633 518
mbed_official 119:3921aeca8633 519 static void can0_arb_lost_irq(void) {
mbed_official 119:3921aeca8633 520 can_err_irq(CAN_0, IRQ_ARB);
mbed_official 119:3921aeca8633 521 }
mbed_official 119:3921aeca8633 522
mbed_official 119:3921aeca8633 523 static void can1_arb_lost_irq(void) {
mbed_official 119:3921aeca8633 524 can_err_irq(CAN_1, IRQ_ARB);
mbed_official 119:3921aeca8633 525 }
mbed_official 119:3921aeca8633 526
mbed_official 119:3921aeca8633 527 static void can2_arb_lost_irq(void) {
mbed_official 119:3921aeca8633 528 can_err_irq(CAN_2, IRQ_ARB);
mbed_official 119:3921aeca8633 529 }
mbed_official 119:3921aeca8633 530
mbed_official 119:3921aeca8633 531 static void can3_arb_lost_irq(void) {
mbed_official 119:3921aeca8633 532 can_err_irq(CAN_3, IRQ_ARB);
mbed_official 119:3921aeca8633 533 }
mbed_official 119:3921aeca8633 534
mbed_official 119:3921aeca8633 535 static void can4_arb_lost_irq(void) {
mbed_official 119:3921aeca8633 536 can_err_irq(CAN_4, IRQ_ARB);
mbed_official 119:3921aeca8633 537 }
mbed_official 119:3921aeca8633 538
mbed_official 119:3921aeca8633 539 static void can0_bus_err_irq(void) {
mbed_official 119:3921aeca8633 540 can_err_irq(CAN_0, IRQ_BUS);
mbed_official 119:3921aeca8633 541 }
mbed_official 119:3921aeca8633 542
mbed_official 119:3921aeca8633 543 static void can1_bus_err_irq(void) {
mbed_official 119:3921aeca8633 544 can_err_irq(CAN_1, IRQ_BUS);
mbed_official 119:3921aeca8633 545 }
mbed_official 119:3921aeca8633 546
mbed_official 119:3921aeca8633 547 static void can2_bus_err_irq(void) {
mbed_official 119:3921aeca8633 548 can_err_irq(CAN_2, IRQ_BUS);
mbed_official 119:3921aeca8633 549 }
mbed_official 119:3921aeca8633 550
mbed_official 119:3921aeca8633 551 static void can3_bus_err_irq(void) {
mbed_official 119:3921aeca8633 552 can_err_irq(CAN_3, IRQ_BUS);
mbed_official 119:3921aeca8633 553 }
mbed_official 119:3921aeca8633 554
mbed_official 119:3921aeca8633 555 static void can4_bus_err_irq(void) {
mbed_official 119:3921aeca8633 556 can_err_irq(CAN_4, IRQ_BUS);
mbed_official 119:3921aeca8633 557 }
mbed_official 119:3921aeca8633 558
mbed_official 119:3921aeca8633 559 void can_init(can_t *obj, PinName rd, PinName td) {
mbed_official 119:3921aeca8633 560 __IO uint32_t *dmy_ctr;
mbed_official 119:3921aeca8633 561
mbed_official 119:3921aeca8633 562 /* determine the CAN to use */
mbed_official 119:3921aeca8633 563 uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
mbed_official 119:3921aeca8633 564 uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
mbed_official 119:3921aeca8633 565 obj->ch = pinmap_merge(can_tx, can_rx);
mbed_official 119:3921aeca8633 566 MBED_ASSERT((int)obj->ch != NC);
mbed_official 119:3921aeca8633 567
mbed_official 119:3921aeca8633 568 /* enable CAN clock */
mbed_official 119:3921aeca8633 569 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
mbed_official 119:3921aeca8633 570 /* Has CAN RAM initialisation completed ? */
mbed_official 119:3921aeca8633 571 while ((RSCAN0GSTS & 0x08) == 0x08) {
mbed_official 119:3921aeca8633 572 __NOP();
mbed_official 119:3921aeca8633 573 }
mbed_official 119:3921aeca8633 574 /* clear Global Stop mode bit */
mbed_official 119:3921aeca8633 575 RSCAN0GCTR &= 0xFFFFFFFB;
mbed_official 119:3921aeca8633 576 /* clear Channel Stop mode bit */
mbed_official 119:3921aeca8633 577 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 578 *dmy_ctr &= 0xFFFFFFFB;
mbed_official 119:3921aeca8633 579 /* Enter global reset mode */
mbed_official 119:3921aeca8633 580 can_set_global_mode(GL_RESET);
mbed_official 119:3921aeca8633 581 /* Enter channel reset mode */
mbed_official 119:3921aeca8633 582 can_set_channel_mode(obj->ch, CH_RESET);
mbed_official 119:3921aeca8633 583 /* reset register */
mbed_official 119:3921aeca8633 584 can_reset_reg(obj);
mbed_official 119:3921aeca8633 585
mbed_official 119:3921aeca8633 586 can_initialized[obj->ch] = 1;
mbed_official 119:3921aeca8633 587 /* reconfigure channel which is already initialized */
mbed_official 119:3921aeca8633 588 can_reconfigure_channel();
mbed_official 119:3921aeca8633 589
mbed_official 119:3921aeca8633 590 /* pin out the can pins */
mbed_official 119:3921aeca8633 591 pinmap_pinout(rd, PinMap_CAN_RD);
mbed_official 119:3921aeca8633 592 pinmap_pinout(td, PinMap_CAN_TD);
mbed_official 119:3921aeca8633 593 }
mbed_official 119:3921aeca8633 594
mbed_official 119:3921aeca8633 595 void can_free(can_t *obj) {
mbed_official 119:3921aeca8633 596 /* disable CAN clock */
mbed_official 119:3921aeca8633 597 CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
mbed_official 119:3921aeca8633 598 }
mbed_official 119:3921aeca8633 599
mbed_official 119:3921aeca8633 600 int can_frequency(can_t *obj, int f) {
mbed_official 119:3921aeca8633 601 int retval = 0;
mbed_official 119:3921aeca8633 602
mbed_official 119:3921aeca8633 603 if (f <= 1000000) {
mbed_official 119:3921aeca8633 604 /* less than 1Mhz */
mbed_official 119:3921aeca8633 605 /* set Channel Reset mode */
mbed_official 119:3921aeca8633 606 can_set_channel_mode(obj->ch, CH_RESET);
mbed_official 119:3921aeca8633 607 can_set_frequency(obj, f);
mbed_official 119:3921aeca8633 608 /* set Channel Communication mode */
mbed_official 119:3921aeca8633 609 can_set_channel_mode(obj->ch, CH_COMM);
mbed_official 119:3921aeca8633 610 retval = 1;
mbed_official 119:3921aeca8633 611 }
mbed_official 119:3921aeca8633 612
mbed_official 119:3921aeca8633 613 return retval;
mbed_official 119:3921aeca8633 614 }
mbed_official 119:3921aeca8633 615
mbed_official 119:3921aeca8633 616 void can_reset(can_t *obj) {
mbed_official 119:3921aeca8633 617 /* Enter global reset mode */
mbed_official 119:3921aeca8633 618 can_set_global_mode(GL_RESET);
mbed_official 119:3921aeca8633 619 /* Enter channel reset mode */
mbed_official 119:3921aeca8633 620 can_set_channel_mode(obj->ch, CH_RESET);
mbed_official 119:3921aeca8633 621 /* reset register */
mbed_official 119:3921aeca8633 622 can_reset_reg(obj);
mbed_official 119:3921aeca8633 623 /* reconfigure channel which is already initialized */
mbed_official 119:3921aeca8633 624 can_reconfigure_channel();
mbed_official 119:3921aeca8633 625 }
mbed_official 119:3921aeca8633 626
mbed_official 119:3921aeca8633 627 int can_write(can_t *obj, CAN_Message msg, int cc) {
mbed_official 119:3921aeca8633 628 __IO uint32_t *dmy_sts;
mbed_official 119:3921aeca8633 629 __IO uint32_t *dmy_cfsts;
mbed_official 119:3921aeca8633 630 __IO uint32_t *dmy_cfid;
mbed_official 119:3921aeca8633 631 __IO uint32_t *dmy_cfptr;
mbed_official 119:3921aeca8633 632 __IO uint32_t *dmy_cfdf0;
mbed_official 119:3921aeca8633 633 __IO uint32_t *dmy_cfdf1;
mbed_official 119:3921aeca8633 634 __IO uint32_t *dmy_cfpctr;
mbed_official 119:3921aeca8633 635 int retval = 0;
mbed_official 119:3921aeca8633 636
mbed_official 119:3921aeca8633 637 /* Wait to become channel communication mode */
mbed_official 119:3921aeca8633 638 dmy_sts = STS_MATCH[obj->ch];
mbed_official 119:3921aeca8633 639 while ((*dmy_sts & 0x07) != 0) {
mbed_official 119:3921aeca8633 640 __NOP();
mbed_official 119:3921aeca8633 641 }
mbed_official 119:3921aeca8633 642
mbed_official 119:3921aeca8633 643 if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
mbed_official 119:3921aeca8633 644 /* send/receive FIFO buffer isn't full */
mbed_official 119:3921aeca8633 645 dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 646 if ((*dmy_cfsts & 0x02) != 0x02) {
mbed_official 119:3921aeca8633 647 /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
mbed_official 119:3921aeca8633 648 dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 649 *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
mbed_official 119:3921aeca8633 650 if (msg.format == CANStandard) {
mbed_official 119:3921aeca8633 651 *dmy_cfid |= (msg.id & 0x07FF);
mbed_official 119:3921aeca8633 652 } else {
mbed_official 119:3921aeca8633 653 *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
mbed_official 119:3921aeca8633 654 }
mbed_official 119:3921aeca8633 655 /* set length */
mbed_official 119:3921aeca8633 656 dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 657 *dmy_cfptr = msg.len << 28;
mbed_official 119:3921aeca8633 658 /* set data */
mbed_official 119:3921aeca8633 659 dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 660 memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
mbed_official 119:3921aeca8633 661 dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 662 memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
mbed_official 119:3921aeca8633 663 /* send request */
mbed_official 119:3921aeca8633 664 dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 665 *dmy_cfpctr = 0xFF;
mbed_official 119:3921aeca8633 666 retval = 1;
mbed_official 119:3921aeca8633 667 }
mbed_official 119:3921aeca8633 668 }
mbed_official 119:3921aeca8633 669
mbed_official 119:3921aeca8633 670 return retval;
mbed_official 119:3921aeca8633 671 }
mbed_official 119:3921aeca8633 672
mbed_official 119:3921aeca8633 673 int can_read(can_t *obj, CAN_Message *msg, int handle) {
mbed_official 119:3921aeca8633 674 __IO uint32_t *dmy_sts;
mbed_official 119:3921aeca8633 675 __IO uint32_t *dmy_cfsts;
mbed_official 119:3921aeca8633 676 __IO uint32_t *dmy_cfid;
mbed_official 119:3921aeca8633 677 __IO uint32_t *dmy_cfptr;
mbed_official 119:3921aeca8633 678 __IO uint32_t *dmy_cfdf0;
mbed_official 119:3921aeca8633 679 __IO uint32_t *dmy_cfdf1;
mbed_official 119:3921aeca8633 680 __IO uint32_t *dmy_cfpctr;
mbed_official 119:3921aeca8633 681 int retval = 0;
mbed_official 119:3921aeca8633 682
mbed_official 119:3921aeca8633 683 /* Wait to become channel communication mode */
mbed_official 119:3921aeca8633 684 dmy_sts = STS_MATCH[obj->ch];
mbed_official 119:3921aeca8633 685 while ((*dmy_sts & 0x07) != 0) {
mbed_official 119:3921aeca8633 686 __NOP();
mbed_official 119:3921aeca8633 687 }
mbed_official 119:3921aeca8633 688
mbed_official 119:3921aeca8633 689 /* send/receive FIFO buffer isn't empty */
mbed_official 119:3921aeca8633 690 dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 691 while ((*dmy_cfsts & 0x01) != 0x01) {
mbed_official 119:3921aeca8633 692 /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
mbed_official 119:3921aeca8633 693 dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 694 msg->format = (CANFormat)(*dmy_cfid >> 31);
mbed_official 119:3921aeca8633 695 msg->type = (CANType)(*dmy_cfid >> 30);
mbed_official 119:3921aeca8633 696 if (msg->format == CANStandard) {
mbed_official 119:3921aeca8633 697 msg->id = (*dmy_cfid & 0x07FF);
mbed_official 119:3921aeca8633 698 } else {
mbed_official 119:3921aeca8633 699 msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
mbed_official 119:3921aeca8633 700 }
mbed_official 119:3921aeca8633 701 /* get length */
mbed_official 119:3921aeca8633 702 dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 703 msg->len = (unsigned char)(*dmy_cfptr >> 28);
mbed_official 119:3921aeca8633 704 /* get data */
mbed_official 119:3921aeca8633 705 dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 706 memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
mbed_official 119:3921aeca8633 707 dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 708 memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
mbed_official 119:3921aeca8633 709 /* receive(next data) request */
mbed_official 119:3921aeca8633 710 dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 711 *dmy_cfpctr = 0xFF;
mbed_official 119:3921aeca8633 712 retval = 1;
mbed_official 119:3921aeca8633 713 }
mbed_official 119:3921aeca8633 714
mbed_official 119:3921aeca8633 715 return retval;
mbed_official 119:3921aeca8633 716 }
mbed_official 119:3921aeca8633 717
mbed_official 119:3921aeca8633 718 unsigned char can_rderror(can_t *obj) {
mbed_official 119:3921aeca8633 719 __IO uint32_t *dmy_sts;
mbed_official 119:3921aeca8633 720
mbed_official 119:3921aeca8633 721 dmy_sts = STS_MATCH[obj->ch];
mbed_official 119:3921aeca8633 722 return (unsigned char)((*dmy_sts >> 16) & 0xFF);
mbed_official 119:3921aeca8633 723 }
mbed_official 119:3921aeca8633 724
mbed_official 119:3921aeca8633 725 unsigned char can_tderror(can_t *obj) {
mbed_official 119:3921aeca8633 726 __IO uint32_t *dmy_sts;
mbed_official 119:3921aeca8633 727
mbed_official 119:3921aeca8633 728 dmy_sts = STS_MATCH[obj->ch];
mbed_official 119:3921aeca8633 729 return (unsigned char)((*dmy_sts >> 24) & 0xFF);
mbed_official 119:3921aeca8633 730 }
mbed_official 119:3921aeca8633 731
mbed_official 119:3921aeca8633 732 int can_mode(can_t *obj, CanMode mode) {
mbed_official 119:3921aeca8633 733 __IO uint32_t *dmy_ctr;
mbed_official 119:3921aeca8633 734 __IO uint32_t *dmy_sts;
mbed_official 119:3921aeca8633 735 __IO uint32_t *dmy_cfcc;
mbed_official 119:3921aeca8633 736 int ch_cnt;
mbed_official 119:3921aeca8633 737 can_t *tmp_obj;
mbed_official 119:3921aeca8633 738 tmp_obj = obj;
mbed_official 119:3921aeca8633 739 int retval = 1;
mbed_official 119:3921aeca8633 740
mbed_official 119:3921aeca8633 741 switch (mode) {
mbed_official 119:3921aeca8633 742 case MODE_RESET:
mbed_official 119:3921aeca8633 743 can_set_global_mode(GL_RESET);
mbed_official 119:3921aeca8633 744 can_set_channel_mode(obj->ch, CH_RESET);
mbed_official 119:3921aeca8633 745 for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
mbed_official 119:3921aeca8633 746 can_initialized[ch_cnt] = 0;
mbed_official 119:3921aeca8633 747 }
mbed_official 119:3921aeca8633 748 break;
mbed_official 119:3921aeca8633 749 case MODE_NORMAL:
mbed_official 119:3921aeca8633 750 can_set_global_mode(GL_OPE);
mbed_official 119:3921aeca8633 751 can_set_channel_mode(obj->ch, CH_COMM);
mbed_official 119:3921aeca8633 752 break;
mbed_official 119:3921aeca8633 753 case MODE_SILENT:
mbed_official 119:3921aeca8633 754 can_set_channel_mode(obj->ch, CH_HOLD);
mbed_official 119:3921aeca8633 755 /* set listen only mode, enable communication test mode */
mbed_official 119:3921aeca8633 756 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 757 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
mbed_official 119:3921aeca8633 758 can_set_channel_mode(obj->ch, CH_COMM);
mbed_official 119:3921aeca8633 759 break;
mbed_official 119:3921aeca8633 760 case MODE_TEST_LOCAL:
mbed_official 119:3921aeca8633 761 can_set_channel_mode(obj->ch, CH_HOLD);
mbed_official 119:3921aeca8633 762 /* set self test mode 0, enable communication test mode */
mbed_official 119:3921aeca8633 763 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 764 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
mbed_official 119:3921aeca8633 765 can_set_channel_mode(obj->ch, CH_COMM);
mbed_official 119:3921aeca8633 766 break;
mbed_official 119:3921aeca8633 767 case MODE_TEST_GLOBAL:
mbed_official 119:3921aeca8633 768 /* set the channel between the communication test on channel 1 and channel 2 */
mbed_official 119:3921aeca8633 769 /* set Channel Hold mode */
mbed_official 119:3921aeca8633 770 for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
mbed_official 119:3921aeca8633 771 dmy_sts = STS_MATCH[tmp_obj->ch];
mbed_official 119:3921aeca8633 772 if ((*dmy_sts & 0x04) == 0x04) {
mbed_official 119:3921aeca8633 773 /* Channel Stop mode */
mbed_official 119:3921aeca8633 774 /* clear Channel Stop mode bit */
mbed_official 119:3921aeca8633 775 dmy_ctr = CTR_MATCH[tmp_obj->ch];
mbed_official 119:3921aeca8633 776 *dmy_ctr &= 0xFFFFFFFB;
mbed_official 119:3921aeca8633 777 can_set_channel_mode(tmp_obj->ch, CH_RESET);
mbed_official 119:3921aeca8633 778 }
mbed_official 119:3921aeca8633 779 can_set_channel_mode(tmp_obj->ch, CH_HOLD);
mbed_official 119:3921aeca8633 780 }
mbed_official 119:3921aeca8633 781 can_set_global_mode(GL_TEST);
mbed_official 119:3921aeca8633 782 /* enable communication test between channel1 and channel2 */
mbed_official 119:3921aeca8633 783 RSCAN0GTSTCFG = 0x06;
mbed_official 119:3921aeca8633 784 RSCAN0GTSTCTR = 0x01;
mbed_official 119:3921aeca8633 785 /* send and receive setting of channel1 and channel2 */
mbed_official 119:3921aeca8633 786 for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
mbed_official 119:3921aeca8633 787 can_reset_buffer(tmp_obj);
mbed_official 119:3921aeca8633 788 /* set global interrrupt */
mbed_official 119:3921aeca8633 789 /* THLEIE, MEIE and DEIE interrupts are disable */
mbed_official 119:3921aeca8633 790 RSCAN0GCTR &= 0xFFFFF8FF;
mbed_official 119:3921aeca8633 791 /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
mbed_official 119:3921aeca8633 792 /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
mbed_official 119:3921aeca8633 793 dmy_ctr = CTR_MATCH[tmp_obj->ch];
mbed_official 119:3921aeca8633 794 *dmy_ctr &= 0x00018700;
mbed_official 119:3921aeca8633 795 can_set_global_mode(GL_OPE);
mbed_official 119:3921aeca8633 796 can_set_channel_mode(tmp_obj->ch, CH_COMM);
mbed_official 119:3921aeca8633 797 /* Use send/receive FIFO buffer */
mbed_official 119:3921aeca8633 798 dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 799 *dmy_cfcc |= 0x01;
mbed_official 119:3921aeca8633 800 dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 801 *dmy_cfcc |= 0x01;
mbed_official 119:3921aeca8633 802 }
mbed_official 119:3921aeca8633 803 break;
mbed_official 119:3921aeca8633 804 case MODE_TEST_SILENT:
mbed_official 119:3921aeca8633 805 /* not supported */
mbed_official 119:3921aeca8633 806 /* fall through */
mbed_official 119:3921aeca8633 807 default:
mbed_official 119:3921aeca8633 808 retval = 0;
mbed_official 119:3921aeca8633 809 break;
mbed_official 119:3921aeca8633 810 }
mbed_official 119:3921aeca8633 811
mbed_official 119:3921aeca8633 812 return retval;
mbed_official 119:3921aeca8633 813 }
mbed_official 119:3921aeca8633 814
mbed_official 119:3921aeca8633 815 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
mbed_official 119:3921aeca8633 816 int retval = 0;
mbed_official 119:3921aeca8633 817
mbed_official 119:3921aeca8633 818 if ((format == CANStandard) || (format == CANExtended)) {
mbed_official 119:3921aeca8633 819 if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
mbed_official 119:3921aeca8633 820 /* set Global Reset mode and Channel Reset mode */
mbed_official 119:3921aeca8633 821 can_set_global_mode(GL_RESET);
mbed_official 119:3921aeca8633 822 can_set_channel_mode(obj->ch, CH_RESET);
mbed_official 119:3921aeca8633 823 /* enable receive rule table writing */
mbed_official 119:3921aeca8633 824 RSCAN0GAFLECTR = 0x00000100;
mbed_official 119:3921aeca8633 825 /* set the page number of receive rule table(page number = 0) */
mbed_official 119:3921aeca8633 826 RSCAN0GAFLECTR |= (obj->ch * 4);
mbed_official 119:3921aeca8633 827 /* set IDE format */
mbed_official 119:3921aeca8633 828 *dmy_gaflid = (format << 31);
mbed_official 119:3921aeca8633 829 if (format == CANExtended) {
mbed_official 119:3921aeca8633 830 /* set receive rule ID for bit28-11 */
mbed_official 119:3921aeca8633 831 *dmy_gaflid |= (id << 11);
mbed_official 119:3921aeca8633 832 } else {
mbed_official 119:3921aeca8633 833 /* set receive rule ID for bit10-0 */
mbed_official 119:3921aeca8633 834 *dmy_gaflid |= id;
mbed_official 119:3921aeca8633 835 }
mbed_official 119:3921aeca8633 836 /* set ID mask bit */
mbed_official 119:3921aeca8633 837 *dmy_gaflm = (0xC0000000 | mask);
mbed_official 119:3921aeca8633 838 /* disable receive rule table writing */
mbed_official 119:3921aeca8633 839 RSCAN0GAFLECTR &= 0xFFFFFEFF;
mbed_official 119:3921aeca8633 840 /* reconfigure channel which is already initialized */
mbed_official 119:3921aeca8633 841 can_reconfigure_channel();
mbed_official 119:3921aeca8633 842 retval = 1;
mbed_official 119:3921aeca8633 843 }
mbed_official 119:3921aeca8633 844 }
mbed_official 119:3921aeca8633 845
mbed_official 119:3921aeca8633 846 return retval;
mbed_official 119:3921aeca8633 847 }
mbed_official 119:3921aeca8633 848
mbed_official 119:3921aeca8633 849 void can_monitor(can_t *obj, int silent) {
mbed_official 119:3921aeca8633 850 __IO uint32_t *dmy_ctr;
mbed_official 119:3921aeca8633 851
mbed_official 119:3921aeca8633 852 /* set Channel Hold mode */
mbed_official 119:3921aeca8633 853 can_set_channel_mode(obj->ch, CH_HOLD);
mbed_official 119:3921aeca8633 854 if (silent) {
mbed_official 119:3921aeca8633 855 /* set listen only mode, enable communication test mode */
mbed_official 119:3921aeca8633 856 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 857 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
mbed_official 119:3921aeca8633 858 can_set_channel_mode(obj->ch, CH_COMM);
mbed_official 119:3921aeca8633 859 } else {
mbed_official 119:3921aeca8633 860 /* set normal test mode, disable communication test mode */
mbed_official 119:3921aeca8633 861 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 862 *dmy_ctr &= 0x00FFFFFF;
mbed_official 119:3921aeca8633 863 /* reset register */
mbed_official 119:3921aeca8633 864 can_reset_reg(obj);
mbed_official 119:3921aeca8633 865 /* reconfigure channel which is already initialized */
mbed_official 119:3921aeca8633 866 can_reconfigure_channel();
mbed_official 119:3921aeca8633 867 }
mbed_official 119:3921aeca8633 868 }
mbed_official 119:3921aeca8633 869
mbed_official 119:3921aeca8633 870 static void can_reset_reg(can_t *obj) {
mbed_official 119:3921aeca8633 871 __IO uint32_t *dmy_ctr;
mbed_official 119:3921aeca8633 872
mbed_official 119:3921aeca8633 873 /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */
mbed_official 119:3921aeca8633 874 /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
mbed_official 119:3921aeca8633 875 RSCAN0GCFG = 0x00000003;
mbed_official 119:3921aeca8633 876 /* set default frequency at 100k */
mbed_official 119:3921aeca8633 877 can_set_frequency(obj, 100000);
mbed_official 119:3921aeca8633 878 /* set receive rule */
mbed_official 119:3921aeca8633 879 can_reset_recv_rule(obj);
mbed_official 119:3921aeca8633 880 /* set buffer */
mbed_official 119:3921aeca8633 881 can_reset_buffer(obj);
mbed_official 119:3921aeca8633 882 /* set global interrrupt */
mbed_official 119:3921aeca8633 883 /* THLEIE, MEIE and DEIE interrupts are disable */
mbed_official 119:3921aeca8633 884 RSCAN0GCTR &= 0xFFFFF8FF;
mbed_official 119:3921aeca8633 885 /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
mbed_official 119:3921aeca8633 886 dmy_ctr = CTR_MATCH[obj->ch];
mbed_official 119:3921aeca8633 887 *dmy_ctr &= 0xFFFF00FF;
mbed_official 119:3921aeca8633 888 }
mbed_official 119:3921aeca8633 889
mbed_official 119:3921aeca8633 890 static void can_reset_recv_rule(can_t *obj) {
mbed_official 119:3921aeca8633 891 /* number of receive rules of each chanel = 64 */
mbed_official 119:3921aeca8633 892 RSCAN0GAFLCFG0 = 0x40404040;
mbed_official 119:3921aeca8633 893 RSCAN0GAFLCFG1 = 0x40000000;
mbed_official 119:3921aeca8633 894 /* enable receive rule table writing */
mbed_official 119:3921aeca8633 895 RSCAN0GAFLECTR = 0x00000100;
mbed_official 119:3921aeca8633 896 /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
mbed_official 119:3921aeca8633 897 RSCAN0GAFLECTR |= (obj->ch * 4);
mbed_official 119:3921aeca8633 898 /* set standard ID, data frame and receive rule ID */
mbed_official 119:3921aeca8633 899 *dmy_gaflid = 0x07FF;
mbed_official 119:3921aeca8633 900 /* IDE bit, RTR bit and ID bit(28-0) are not compared */
mbed_official 119:3921aeca8633 901 *dmy_gaflm = 0;
mbed_official 119:3921aeca8633 902 /* DLC check is 1 bytes, not use a receive buffer */
mbed_official 119:3921aeca8633 903 *dmy_gaflp0 = 0x10000000;
mbed_official 119:3921aeca8633 904 /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
mbed_official 119:3921aeca8633 905 *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
mbed_official 119:3921aeca8633 906 /* disable receive rule table writing */
mbed_official 119:3921aeca8633 907 RSCAN0GAFLECTR &= 0xFFFFFEFF;
mbed_official 119:3921aeca8633 908 }
mbed_official 119:3921aeca8633 909
mbed_official 119:3921aeca8633 910 static void can_reset_buffer(can_t *obj) {
mbed_official 119:3921aeca8633 911 __IO uint32_t *dmy_rfcc;
mbed_official 119:3921aeca8633 912 __IO uint32_t *dmy_cfcc;
mbed_official 119:3921aeca8633 913 __IO uint32_t *dmy_txqcc;
mbed_official 119:3921aeca8633 914 __IO uint32_t *dmy_thlcc;
mbed_official 119:3921aeca8633 915 int cnt;
mbed_official 119:3921aeca8633 916
mbed_official 119:3921aeca8633 917 /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
mbed_official 119:3921aeca8633 918 /* number of rows of send/receive FIFO buffer = 4 */
mbed_official 119:3921aeca8633 919 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 920 *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */
mbed_official 119:3921aeca8633 921 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 922 *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */
mbed_official 119:3921aeca8633 923 /* receive buffer is not used */
mbed_official 119:3921aeca8633 924 RSCAN0RMNB = 0;
mbed_official 119:3921aeca8633 925 /* receive FIFO buffer is not used */
mbed_official 119:3921aeca8633 926 for (cnt = 0; cnt < 8; cnt++) {
mbed_official 119:3921aeca8633 927 dmy_rfcc = RFCC_MATCH[cnt];
mbed_official 119:3921aeca8633 928 *dmy_rfcc = 0;
mbed_official 119:3921aeca8633 929 }
mbed_official 119:3921aeca8633 930 /* send queue is not used */
mbed_official 119:3921aeca8633 931 dmy_txqcc = TXQCC_MATCH[obj->ch];
mbed_official 119:3921aeca8633 932 *dmy_txqcc = 0;
mbed_official 119:3921aeca8633 933 /* send history is not used */
mbed_official 119:3921aeca8633 934 dmy_thlcc = THLCC_MATCH[obj->ch];
mbed_official 119:3921aeca8633 935 *dmy_thlcc = 0;
mbed_official 119:3921aeca8633 936
mbed_official 119:3921aeca8633 937 /* CFTXIE and CFRXIE interrupts are enable */
mbed_official 119:3921aeca8633 938 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
mbed_official 119:3921aeca8633 939 *dmy_cfcc |= 0x04;
mbed_official 119:3921aeca8633 940 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
mbed_official 119:3921aeca8633 941 *dmy_cfcc |= 0x02;
mbed_official 119:3921aeca8633 942 /* TMIEp interrupt is disable */
mbed_official 119:3921aeca8633 943 RSCAN0TMIEC0 = 0x00000000;
mbed_official 119:3921aeca8633 944 RSCAN0TMIEC1 = 0x00000000;
mbed_official 119:3921aeca8633 945 RSCAN0TMIEC2 = 0x00000000;
mbed_official 119:3921aeca8633 946 }
mbed_official 119:3921aeca8633 947
mbed_official 119:3921aeca8633 948 static void can_reconfigure_channel(void) {
mbed_official 119:3921aeca8633 949 __IO uint32_t *dmy_cfcc;
mbed_official 119:3921aeca8633 950 int ch_cnt;
mbed_official 119:3921aeca8633 951
mbed_official 119:3921aeca8633 952 for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
mbed_official 119:3921aeca8633 953 if (can_initialized[ch_cnt] == 1) {
mbed_official 119:3921aeca8633 954 /* set Global Operation mode and Channel Communication mode */
mbed_official 119:3921aeca8633 955 can_set_global_mode(GL_OPE);
mbed_official 119:3921aeca8633 956 can_set_channel_mode(ch_cnt, CH_COMM);
mbed_official 119:3921aeca8633 957 /* Use send/receive FIFO buffer */
mbed_official 119:3921aeca8633 958 dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
mbed_official 119:3921aeca8633 959 *dmy_cfcc |= 0x01;
mbed_official 119:3921aeca8633 960 dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
mbed_official 119:3921aeca8633 961 *dmy_cfcc |= 0x01;
mbed_official 119:3921aeca8633 962 }
mbed_official 119:3921aeca8633 963 }
mbed_official 119:3921aeca8633 964 }
mbed_official 119:3921aeca8633 965
mbed_official 119:3921aeca8633 966 static void can_set_frequency(can_t *obj, int f) {
mbed_official 119:3921aeca8633 967 __IO uint32_t *dmy_cfg;
mbed_official 119:3921aeca8633 968 int oldfreq = 0;
mbed_official 119:3921aeca8633 969 int newfreq = 0;
mbed_official 119:3921aeca8633 970 uint32_t clkc_val;
mbed_official 119:3921aeca8633 971 uint8_t tmp_tq;
mbed_official 119:3921aeca8633 972 uint8_t tq = 0;
mbed_official 119:3921aeca8633 973 uint8_t tmp_brp;
mbed_official 119:3921aeca8633 974 uint8_t brp = 0;
mbed_official 119:3921aeca8633 975 uint8_t tseg1 = 0;
mbed_official 119:3921aeca8633 976 uint8_t tseg2 = 0;
mbed_official 119:3921aeca8633 977
mbed_official 119:3921aeca8633 978 /* set clkc */
mbed_official 119:3921aeca8633 979 if (RZ_A1_IsClockMode0() == false) {
mbed_official 119:3921aeca8633 980 clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
mbed_official 119:3921aeca8633 981 } else {
mbed_official 119:3921aeca8633 982 clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
mbed_official 119:3921aeca8633 983 }
mbed_official 119:3921aeca8633 984 /* calculate BRP bit and Choose max value of calculated frequency */
mbed_official 119:3921aeca8633 985 for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
mbed_official 119:3921aeca8633 986 /* f = fCAN / ((BRP+1) * Tq) */
mbed_official 119:3921aeca8633 987 /* BRP = (fCAN / (f * Tq)) - 1 */
mbed_official 119:3921aeca8633 988 tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry)
mbed_official 119:3921aeca8633 989 newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
mbed_official 119:3921aeca8633 990 if (newfreq >= oldfreq) {
mbed_official 119:3921aeca8633 991 oldfreq = newfreq;
mbed_official 119:3921aeca8633 992 tq = tmp_tq;
mbed_official 119:3921aeca8633 993 brp = tmp_brp;
mbed_official 119:3921aeca8633 994 }
mbed_official 119:3921aeca8633 995 }
mbed_official 119:3921aeca8633 996 /* calculate TSEG1 bit and TSEG2 bit */
mbed_official 119:3921aeca8633 997 tseg1 = (tq - 1) * 0.666666667;
mbed_official 119:3921aeca8633 998 tseg2 = (tq - 1) - tseg1;
mbed_official 119:3921aeca8633 999 /* set RSCAN0CmCFG register */
mbed_official 119:3921aeca8633 1000 dmy_cfg = CFG_MATCH[obj->ch];
mbed_official 119:3921aeca8633 1001 *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
mbed_official 119:3921aeca8633 1002 }
mbed_official 119:3921aeca8633 1003
mbed_official 119:3921aeca8633 1004 static void can_set_global_mode(int mode) {
mbed_official 119:3921aeca8633 1005 /* set Global mode */
mbed_official 119:3921aeca8633 1006 RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode);
mbed_official 119:3921aeca8633 1007 /* Wait to cahnge into Global XXXX mode */
mbed_official 119:3921aeca8633 1008 while ((RSCAN0GSTS & 0x07) != mode) {
mbed_official 119:3921aeca8633 1009 __NOP();
mbed_official 119:3921aeca8633 1010 }
mbed_official 119:3921aeca8633 1011 }
mbed_official 119:3921aeca8633 1012
mbed_official 119:3921aeca8633 1013 static void can_set_channel_mode(uint32_t ch, int mode) {
mbed_official 119:3921aeca8633 1014 __IO uint32_t *dmy_ctr;
mbed_official 119:3921aeca8633 1015 __IO uint32_t *dmy_sts;
mbed_official 119:3921aeca8633 1016
mbed_official 119:3921aeca8633 1017 /* set Channel mode */
mbed_official 119:3921aeca8633 1018 dmy_ctr = CTR_MATCH[ch];
mbed_official 119:3921aeca8633 1019 *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode);
mbed_official 119:3921aeca8633 1020 /* Wait to cahnge into Channel XXXX mode */
mbed_official 119:3921aeca8633 1021 dmy_sts = STS_MATCH[ch];
mbed_official 119:3921aeca8633 1022 while ((*dmy_sts & 0x07) != mode) {
mbed_official 119:3921aeca8633 1023 __NOP();
mbed_official 119:3921aeca8633 1024 }
mbed_official 119:3921aeca8633 1025 }
mbed_official 119:3921aeca8633 1026