teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Child:
147:30b64687e01f
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ***************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file ncs36510_init.c
<> 144:ef7eb2e8f9f7 4 * @brief Initialization of Orion SoC
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev:
<> 144:ef7eb2e8f9f7 8 * $Date: $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup main
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 27 * *
<> 144:ef7eb2e8f9f7 28 * Header files *
<> 144:ef7eb2e8f9f7 29 * *
<> 144:ef7eb2e8f9f7 30 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 31 #include "NCS36510Init.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 void fPmuInit(void);
<> 144:ef7eb2e8f9f7 34 /**
<> 144:ef7eb2e8f9f7 35 * @brief
<> 144:ef7eb2e8f9f7 36 * Hardware trimming function
<> 144:ef7eb2e8f9f7 37 * This function copies trim codes from specific flash location
<> 144:ef7eb2e8f9f7 38 * where they are stored to proper hw registers.
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40 boolean fTrim()
<> 144:ef7eb2e8f9f7 41 {
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**- Check if trim values are present */
<> 144:ef7eb2e8f9f7 44 /**- If Trim data is present. Only trim if valid trim values are present. */
<> 144:ef7eb2e8f9f7 45 /**- Copy trims in registers */
<> 144:ef7eb2e8f9f7 46 if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /**- board specific clock trims may only be done when present, writing all 1's is not good */
<> 144:ef7eb2e8f9f7 49 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 50 CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
<> 144:ef7eb2e8f9f7 51 }
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 54 CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
<> 144:ef7eb2e8f9f7 55 }
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 RFANATRIMREG->TX_CHAIN_TRIM = TRIMREG->TX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 60 RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
<> 144:ef7eb2e8f9f7 61 RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**- board specific RSSI trims may only be done when present, writing all 1's is not good */
<> 144:ef7eb2e8f9f7 64 if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 65 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 69 RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
<> 144:ef7eb2e8f9f7 70 RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** REVD boards are trimmed (in flash) with rx vco trims specific for high side injection,
<> 144:ef7eb2e8f9f7 73 * */
<> 144:ef7eb2e8f9f7 74 RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
<> 144:ef7eb2e8f9f7 75 RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
<> 144:ef7eb2e8f9f7 78 RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 return True;
<> 144:ef7eb2e8f9f7 82 } else {
<> 144:ef7eb2e8f9f7 83 /**- If no trim values are present, update the global status variable. */
<> 144:ef7eb2e8f9f7 84 return False;
<> 144:ef7eb2e8f9f7 85 }
<> 144:ef7eb2e8f9f7 86 }
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* See clock.h for documentation. */
<> 144:ef7eb2e8f9f7 89 void fClockInit()
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** Enable external 32MHz oscillator */
<> 144:ef7eb2e8f9f7 93 CLOCKREG->CCR.BITS.OSC_SEL = 1;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** - Wait external 32MHz oscillator to be ready */
<> 144:ef7eb2e8f9f7 96 while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
<> 144:ef7eb2e8f9f7 99 PMUREG->CONTROL.BITS.INT32M = 0;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** - Wait 5 uSec for clock to stabilize */
<> 144:ef7eb2e8f9f7 102 volatile uint8_t Timer;
<> 144:ef7eb2e8f9f7 103 for(Timer = 0; Timer < 10; Timer++);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** - Enable calibration */
<> 144:ef7eb2e8f9f7 106 CLOCKREG->CCR.BITS.CAL32M = True;
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** - Wait calibration to be completed */
<> 144:ef7eb2e8f9f7 109 while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** - Check calibration status */
<> 144:ef7eb2e8f9f7 112 while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** - Power down internal 32MHz osc */
<> 144:ef7eb2e8f9f7 115 PMUREG->CONTROL.BITS.INT32M = 1;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
<> 144:ef7eb2e8f9f7 118 PMUREG->CONTROL.BITS.INT32K = 0;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** - Wait 5 uSec for clock to stabilize */
<> 144:ef7eb2e8f9f7 121 for(Timer = 0; Timer < 10; Timer++);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** - Enable calibration */
<> 144:ef7eb2e8f9f7 124 CLOCKREG->CCR.BITS.CAL32K = True;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** - Wait calibration to be completed */
<> 144:ef7eb2e8f9f7 127 while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** - Check calibration status */
<> 144:ef7eb2e8f9f7 130 while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** - Power down external 32KHz osc */
<> 144:ef7eb2e8f9f7 133 PMUREG->CONTROL.BITS.EXT32K = 1;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** Disable all peripheral clocks by default */
<> 144:ef7eb2e8f9f7 136 CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** Set core frequency */
<> 144:ef7eb2e8f9f7 139 CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Initializes PMU module */
<> 144:ef7eb2e8f9f7 143 void fPmuInit()
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 /** Enable the clock for PMU peripheral device */
<> 144:ef7eb2e8f9f7 146 CLOCK_ENABLE(CLOCK_PMU);
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** Unset wakeup on pending (only enabled irq can wakeup) */
<> 144:ef7eb2e8f9f7 149 SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** Unset auto sleep when returning from wakeup irq */
<> 144:ef7eb2e8f9f7 152 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /** Set regulator timings */
<> 144:ef7eb2e8f9f7 155 PMUREG->FVDD_TSETTLE = 160;
<> 144:ef7eb2e8f9f7 156 PMUREG->FVDD_TSTARTUP = 400;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** Keep SRAMA & SRAMB powered in coma mode */
<> 144:ef7eb2e8f9f7 159 PMUREG->CONTROL.BITS.SRAMA = False;
<> 144:ef7eb2e8f9f7 160 PMUREG->CONTROL.BITS.SRAMB = False;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
<> 144:ef7eb2e8f9f7 163 PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** Disable the clock for PMU peripheral device, all settings are done */
<> 144:ef7eb2e8f9f7 166 CLOCK_DISABLE(CLOCK_PMU);
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* See clock.h for documentation. */
<> 144:ef7eb2e8f9f7 170 uint32_t fClockGetPeriphClockfrequency()
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @brief
<> 144:ef7eb2e8f9f7 178 * Hardware initialization function
<> 144:ef7eb2e8f9f7 179 * This function initializes hardware at application start up prior
<> 144:ef7eb2e8f9f7 180 * to other initializations or OS operations.
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 static void fHwInit(void)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Trim register settings */
<> 144:ef7eb2e8f9f7 186 fTrim();
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Clock setting */
<> 144:ef7eb2e8f9f7 189 /** - Initialize clock */
<> 144:ef7eb2e8f9f7 190 fClockInit();
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** - Initialize pmu */
<> 144:ef7eb2e8f9f7 193 fPmuInit();
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /** Orion has 4 interrupt bits in interrupt priority register
<> 144:ef7eb2e8f9f7 196 * The lowest 4 bits are not used.
<> 144:ef7eb2e8f9f7 197 *
<> 144:ef7eb2e8f9f7 198 @verbatim
<> 144:ef7eb2e8f9f7 199 +-----+-----+-----+-----+-----+-----+-----+-----+
<> 144:ef7eb2e8f9f7 200 |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|
<> 144:ef7eb2e8f9f7 201 | | | | | 0 | 0 | 0 | 0 |
<> 144:ef7eb2e8f9f7 202 +-----+-----+-----+-----+-----+-----+-----+-----+
<> 144:ef7eb2e8f9f7 203 |
<> 144:ef7eb2e8f9f7 204 INTERRUPT PRIORITY | NOT IMPLEMENTED,
<> 144:ef7eb2e8f9f7 205 | read as 0
<> 144:ef7eb2e8f9f7 206 Valid priorities are 0x00, 0x10, 0x20, 0x30
<> 144:ef7eb2e8f9f7 207 0x40, 0x50, 0x60, 0x70
<> 144:ef7eb2e8f9f7 208 0x80, 0x90, 0xA0, 0xB0
<> 144:ef7eb2e8f9f7 209 0xC0, 0xD0, 0xE0, 0xF0
<> 144:ef7eb2e8f9f7 210 @endverbatim
<> 144:ef7eb2e8f9f7 211 * Lowest number is highest priority
<> 144:ef7eb2e8f9f7 212 *
<> 144:ef7eb2e8f9f7 213 *
<> 144:ef7eb2e8f9f7 214 * This range is defined by
<> 144:ef7eb2e8f9f7 215 * configKERNEL_INTERRUPT_PRIORITY (lowest)
<> 144:ef7eb2e8f9f7 216 * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt
<> 144:ef7eb2e8f9f7 217 * priorities need to fall in that range.
<> 144:ef7eb2e8f9f7 218 *
<> 144:ef7eb2e8f9f7 219 * To be future safe, the LSbits of the priority are set to 0xF.
<> 144:ef7eb2e8f9f7 220 * This wil lmake sure that if more interrupt bits are used, the
<> 144:ef7eb2e8f9f7 221 * priority is maintained.
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /** - Set IRQs priorities */
<> 144:ef7eb2e8f9f7 225 NVIC_SetPriority(Tim0_IRQn, 14);
<> 144:ef7eb2e8f9f7 226 NVIC_SetPriority(Tim1_IRQn, 14);
<> 144:ef7eb2e8f9f7 227 NVIC_SetPriority(Tim2_IRQn, 14);
<> 144:ef7eb2e8f9f7 228 NVIC_SetPriority(Uart1_IRQn,14);
<> 144:ef7eb2e8f9f7 229 NVIC_SetPriority(Spi_IRQn, 14);
<> 144:ef7eb2e8f9f7 230 NVIC_SetPriority(I2C_IRQn, 14);
<> 144:ef7eb2e8f9f7 231 NVIC_SetPriority(Gpio_IRQn, 14);
<> 144:ef7eb2e8f9f7 232 NVIC_SetPriority(Rtc_IRQn, 14);
<> 144:ef7eb2e8f9f7 233 NVIC_SetPriority(MacHw_IRQn, 13);
<> 144:ef7eb2e8f9f7 234 NVIC_SetPriority(Aes_IRQn, 13);
<> 144:ef7eb2e8f9f7 235 NVIC_SetPriority(Adc_IRQn, 14);
<> 144:ef7eb2e8f9f7 236 NVIC_SetPriority(ClockCal_IRQn, 14);
<> 144:ef7eb2e8f9f7 237 NVIC_SetPriority(Uart2_IRQn, 14);
<> 144:ef7eb2e8f9f7 238 NVIC_SetPriority(Dma_IRQn, 14);
<> 144:ef7eb2e8f9f7 239 NVIC_SetPriority(Uvi_IRQn, 14);
<> 144:ef7eb2e8f9f7 240 NVIC_SetPriority(DbgPwrUp_IRQn, 14);
<> 144:ef7eb2e8f9f7 241 NVIC_SetPriority(Spi2_IRQn, 14);
<> 144:ef7eb2e8f9f7 242 NVIC_SetPriority(I2C2_IRQn, 14);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 extern void __Vectors;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 void fNcs36510Init(void)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /** Setting this register is helping to debug imprecise bus access faults
<> 144:ef7eb2e8f9f7 250 * making them precise bus access faults. It has an impact on application
<> 144:ef7eb2e8f9f7 251 * performance. */
<> 144:ef7eb2e8f9f7 252 // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /** This main function implements: */
<> 144:ef7eb2e8f9f7 255 /**- Disable all interrupts */
<> 144:ef7eb2e8f9f7 256 NVIC->ICER[0] = 0x1F;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /**- Clear all Pending interrupts */
<> 144:ef7eb2e8f9f7 259 NVIC->ICPR[0] = 0x1F;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**- Clear all pending SV and systick */
<> 144:ef7eb2e8f9f7 262 SCB->ICSR = (uint32_t)0x0A000000;
<> 144:ef7eb2e8f9f7 263 SCB->VTOR = (uint32_t) (&__Vectors);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**- Initialize hardware */
<> 144:ef7eb2e8f9f7 266 fHwInit();
<> 144:ef7eb2e8f9f7 267 }