teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**********************************************************************
bogdanm 0:9b334a45a8ff 2 * $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
bogdanm 0:9b334a45a8ff 3 *//**
bogdanm 0:9b334a45a8ff 4 * @file system_LPC407x_8x_177x_8x.c
bogdanm 0:9b334a45a8ff 5 * @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
bogdanm 0:9b334a45a8ff 6 * for the NXP LPC407x_8x_177x_8x Device Series
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * ARM Limited (ARM) is supplying this software for use with
bogdanm 0:9b334a45a8ff 9 * Cortex-M processor based microcontrollers. This file can be
bogdanm 0:9b334a45a8ff 10 * freely distributed within development tools that are supporting
bogdanm 0:9b334a45a8ff 11 * such ARM based processors.
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * @version 1.2
bogdanm 0:9b334a45a8ff 14 * @date 20. June. 2012
bogdanm 0:9b334a45a8ff 15 * @author NXP MCU SW Application Team
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * Copyright(C) 2012, NXP Semiconductor
bogdanm 0:9b334a45a8ff 18 * All rights reserved.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 ***********************************************************************
bogdanm 0:9b334a45a8ff 21 * Software that is described herein is for illustrative purposes only
bogdanm 0:9b334a45a8ff 22 * which provides customers with programming information regarding the
bogdanm 0:9b334a45a8ff 23 * products. This software is supplied "AS IS" without any warranties.
bogdanm 0:9b334a45a8ff 24 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 0:9b334a45a8ff 25 * use of the software, conveys no license or title under any patent,
bogdanm 0:9b334a45a8ff 26 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 0:9b334a45a8ff 27 * reserves the right to make changes in the software without
bogdanm 0:9b334a45a8ff 28 * notification. NXP Semiconductors also make no representation or
bogdanm 0:9b334a45a8ff 29 * warranty that such application will be suitable for the specified
bogdanm 0:9b334a45a8ff 30 * use without further testing or modification.
bogdanm 0:9b334a45a8ff 31 **********************************************************************/
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 #include <stdint.h>
bogdanm 0:9b334a45a8ff 34 #include "LPC407x_8x_177x_8x.h"
bogdanm 0:9b334a45a8ff 35 #include "system_LPC407x_8x_177x_8x.h"
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 /*
bogdanm 0:9b334a45a8ff 40 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42 /*--------------------- Clock Configuration ----------------------------------
bogdanm 0:9b334a45a8ff 43 //
bogdanm 0:9b334a45a8ff 44 // <e> Clock Configuration
bogdanm 0:9b334a45a8ff 45 // <h> System Controls and Status Register (SCS - address 0x400F C1A0)
bogdanm 0:9b334a45a8ff 46 // <o1.0> EMC Shift Control Bit
bogdanm 0:9b334a45a8ff 47 // <i> Controls how addresses are output on the EMC address pins for static memories
bogdanm 0:9b334a45a8ff 48 // <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
bogdanm 0:9b334a45a8ff 49 // <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
bogdanm 0:9b334a45a8ff 50 //
bogdanm 0:9b334a45a8ff 51 // <o1.1> EMC Reset Disable Bit
bogdanm 0:9b334a45a8ff 52 // <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
bogdanm 0:9b334a45a8ff 53 // <i> If 1, EMC is still retained its state through a warm reset
bogdanm 0:9b334a45a8ff 54 // <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
bogdanm 0:9b334a45a8ff 55 // <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
bogdanm 0:9b334a45a8ff 56 //
bogdanm 0:9b334a45a8ff 57 // <o1.2> EMC Burst Control
bogdanm 0:9b334a45a8ff 58 // <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
bogdanm 0:9b334a45a8ff 59 // <0=> Burst enabled (Bit 2 is 0)
bogdanm 0:9b334a45a8ff 60 // <1=> Bust disbled (Bit 2 is 1)
bogdanm 0:9b334a45a8ff 61 //
bogdanm 0:9b334a45a8ff 62 // <o1.3> MCIPWR Active Level
bogdanm 0:9b334a45a8ff 63 // <i> Selects the active level for the SD card interface signal SD_PWR
bogdanm 0:9b334a45a8ff 64 // <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
bogdanm 0:9b334a45a8ff 65 // <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
bogdanm 0:9b334a45a8ff 66 //
bogdanm 0:9b334a45a8ff 67 // <o1.4> Main Oscillator Range Select
bogdanm 0:9b334a45a8ff 68 // <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
bogdanm 0:9b334a45a8ff 69 // <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
bogdanm 0:9b334a45a8ff 70 //
bogdanm 0:9b334a45a8ff 71 // <o1.5> Main Oscillator enable
bogdanm 0:9b334a45a8ff 72 // <i> 0 (zero) means disabled, 1 means enable
bogdanm 0:9b334a45a8ff 73 //
bogdanm 0:9b334a45a8ff 74 // <o1.6> Main Oscillator status (Read-Only)
bogdanm 0:9b334a45a8ff 75 // </h>
bogdanm 0:9b334a45a8ff 76 //
bogdanm 0:9b334a45a8ff 77 // <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
bogdanm 0:9b334a45a8ff 78 // <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
bogdanm 0:9b334a45a8ff 79 // <0=> Internal RC oscillator (Bit 0 is 0)
bogdanm 0:9b334a45a8ff 80 // <1=> Main oscillator (Bit 0 is 1)
bogdanm 0:9b334a45a8ff 81 // </h>
bogdanm 0:9b334a45a8ff 82 //
bogdanm 0:9b334a45a8ff 83 // <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
bogdanm 0:9b334a45a8ff 84 // <i> F_in is in the range of 1 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 85 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 86 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
bogdanm 0:9b334a45a8ff 87 //
bogdanm 0:9b334a45a8ff 88 // <o4.0..4> MSEL: PLL Multiplier Value
bogdanm 0:9b334a45a8ff 89 // <i> M Value
bogdanm 0:9b334a45a8ff 90 // <1-32><#-1>
bogdanm 0:9b334a45a8ff 91 //
bogdanm 0:9b334a45a8ff 92 // <o4.5..6> PSEL: PLL Divider Value
bogdanm 0:9b334a45a8ff 93 // <i> P Value
bogdanm 0:9b334a45a8ff 94 // <0=> 1
bogdanm 0:9b334a45a8ff 95 // <1=> 2
bogdanm 0:9b334a45a8ff 96 // <2=> 4
bogdanm 0:9b334a45a8ff 97 // <3=> 8
bogdanm 0:9b334a45a8ff 98 // </e>
bogdanm 0:9b334a45a8ff 99 //
bogdanm 0:9b334a45a8ff 100 // <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
bogdanm 0:9b334a45a8ff 101 // <i> F_in is in the range of 1 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 102 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 103 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
bogdanm 0:9b334a45a8ff 104 //
bogdanm 0:9b334a45a8ff 105 // <o6.0..4> MSEL: PLL Multiplier Value
bogdanm 0:9b334a45a8ff 106 // <i> M Value
bogdanm 0:9b334a45a8ff 107 // <1-32><#-1>
bogdanm 0:9b334a45a8ff 108 //
bogdanm 0:9b334a45a8ff 109 // <o6.5..6> PSEL: PLL Divider Value
bogdanm 0:9b334a45a8ff 110 // <i> P Value
bogdanm 0:9b334a45a8ff 111 // <0=> 1
bogdanm 0:9b334a45a8ff 112 // <1=> 2
bogdanm 0:9b334a45a8ff 113 // <2=> 4
bogdanm 0:9b334a45a8ff 114 // <3=> 8
bogdanm 0:9b334a45a8ff 115 // </e>
bogdanm 0:9b334a45a8ff 116 //
bogdanm 0:9b334a45a8ff 117 // <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
bogdanm 0:9b334a45a8ff 118 // <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
bogdanm 0:9b334a45a8ff 119 // <i> 0: The divider is turned off. No clock will be provided to the CPU
bogdanm 0:9b334a45a8ff 120 // <i> n: The input clock is divided by n to produce the CPU clock
bogdanm 0:9b334a45a8ff 121 // <0-31>
bogdanm 0:9b334a45a8ff 122 //
bogdanm 0:9b334a45a8ff 123 // <o7.8> CCLKSEL: Select the input to the divider of CPU clock
bogdanm 0:9b334a45a8ff 124 // <0=> sysclk clock is used
bogdanm 0:9b334a45a8ff 125 // <1=> Main PLL0 clock is used
bogdanm 0:9b334a45a8ff 126 // </h>
bogdanm 0:9b334a45a8ff 127 //
bogdanm 0:9b334a45a8ff 128 // <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
bogdanm 0:9b334a45a8ff 129 // <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
bogdanm 0:9b334a45a8ff 130 // <0=> Divider is off and no clock provides to USB subsystem
bogdanm 0:9b334a45a8ff 131 // <4=> Divider value is 4 (The source clock is divided by 4)
bogdanm 0:9b334a45a8ff 132 // <6=> Divider value is 6 (The source clock is divided by 6)
bogdanm 0:9b334a45a8ff 133 //
bogdanm 0:9b334a45a8ff 134 // <o8.8..9> USBSEL: Select the source for USB clock divider
bogdanm 0:9b334a45a8ff 135 // <i> When CPU clock is selected, the USB can be accessed
bogdanm 0:9b334a45a8ff 136 // <i> by software but cannot perform USB functions
bogdanm 0:9b334a45a8ff 137 // <0=> sysclk clock (the clock input to PLL0)
bogdanm 0:9b334a45a8ff 138 // <1=> The clock output from PLL0
bogdanm 0:9b334a45a8ff 139 // <2=> The clock output from PLL1
bogdanm 0:9b334a45a8ff 140 // </h>
bogdanm 0:9b334a45a8ff 141 //
bogdanm 0:9b334a45a8ff 142 // <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
bogdanm 0:9b334a45a8ff 143 // <o9.0> EMCDIV: Set the divider for EMC clock
bogdanm 0:9b334a45a8ff 144 // <0=> Divider value is 1
bogdanm 0:9b334a45a8ff 145 // <1=> Divider value is 2 (EMC clock is equal a half of input clock)
bogdanm 0:9b334a45a8ff 146 // </h>
bogdanm 0:9b334a45a8ff 147 //
bogdanm 0:9b334a45a8ff 148 // <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
bogdanm 0:9b334a45a8ff 149 // <o10.0..4> PCLKDIV: APB Peripheral clock divider
bogdanm 0:9b334a45a8ff 150 // <i> 0: The divider is turned off. No clock will be provided to APB peripherals
bogdanm 0:9b334a45a8ff 151 // <i> n: The input clock is divided by n to produce the APB peripheral clock
bogdanm 0:9b334a45a8ff 152 // <0-31>
bogdanm 0:9b334a45a8ff 153 // </h>
bogdanm 0:9b334a45a8ff 154 //
bogdanm 0:9b334a45a8ff 155 // <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
bogdanm 0:9b334a45a8ff 156 // <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
bogdanm 0:9b334a45a8ff 157 // <i> 0: The divider is turned off. No clock will be provided to the SPIFI
bogdanm 0:9b334a45a8ff 158 // <i> n: The input clock is divided by n to produce the SPIFI clock
bogdanm 0:9b334a45a8ff 159 // <0-31>
bogdanm 0:9b334a45a8ff 160 //
bogdanm 0:9b334a45a8ff 161 // <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
bogdanm 0:9b334a45a8ff 162 // <0=> sysclk clock (the clock input to PLL0)
bogdanm 0:9b334a45a8ff 163 // <1=> The clock output from PLL0
bogdanm 0:9b334a45a8ff 164 // <2=> The clock output from PLL1
bogdanm 0:9b334a45a8ff 165 // </h>
bogdanm 0:9b334a45a8ff 166 //
bogdanm 0:9b334a45a8ff 167 // <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
bogdanm 0:9b334a45a8ff 168 // <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
bogdanm 0:9b334a45a8ff 169 // <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
bogdanm 0:9b334a45a8ff 170 // <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
bogdanm 0:9b334a45a8ff 171 // <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
bogdanm 0:9b334a45a8ff 172 // <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
bogdanm 0:9b334a45a8ff 173 // <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
bogdanm 0:9b334a45a8ff 174 // <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
bogdanm 0:9b334a45a8ff 175 // <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
bogdanm 0:9b334a45a8ff 176 // <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
bogdanm 0:9b334a45a8ff 177 // <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
bogdanm 0:9b334a45a8ff 178 // <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
bogdanm 0:9b334a45a8ff 179 // <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
bogdanm 0:9b334a45a8ff 180 // <o12.12> PCADC: A/D converter power/clock enable (bit 12)
bogdanm 0:9b334a45a8ff 181 // <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
bogdanm 0:9b334a45a8ff 182 // <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
bogdanm 0:9b334a45a8ff 183 // <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
bogdanm 0:9b334a45a8ff 184 // <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
bogdanm 0:9b334a45a8ff 185 // <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
bogdanm 0:9b334a45a8ff 186 // <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
bogdanm 0:9b334a45a8ff 187 // <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
bogdanm 0:9b334a45a8ff 188 // <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
bogdanm 0:9b334a45a8ff 189 // <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
bogdanm 0:9b334a45a8ff 190 // <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
bogdanm 0:9b334a45a8ff 191 // <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
bogdanm 0:9b334a45a8ff 192 // <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
bogdanm 0:9b334a45a8ff 193 // <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
bogdanm 0:9b334a45a8ff 194 // <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
bogdanm 0:9b334a45a8ff 195 // <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
bogdanm 0:9b334a45a8ff 196 // <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
bogdanm 0:9b334a45a8ff 197 // <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
bogdanm 0:9b334a45a8ff 198 // <o12.31> PCUSB: USB interface power/clock enable (bit 31)
bogdanm 0:9b334a45a8ff 199 // </h>
bogdanm 0:9b334a45a8ff 200 //
bogdanm 0:9b334a45a8ff 201 // <h> Clock Output Configuration Register (CLKOUTCFG)
bogdanm 0:9b334a45a8ff 202 // <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
bogdanm 0:9b334a45a8ff 203 // <0=> CPU clock
bogdanm 0:9b334a45a8ff 204 // <1=> Main Oscillator
bogdanm 0:9b334a45a8ff 205 // <2=> Internal RC Oscillator
bogdanm 0:9b334a45a8ff 206 // <3=> USB clock
bogdanm 0:9b334a45a8ff 207 // <4=> RTC Oscillator
bogdanm 0:9b334a45a8ff 208 // <5=> unused
bogdanm 0:9b334a45a8ff 209 // <6=> Watchdog Oscillator
bogdanm 0:9b334a45a8ff 210 //
bogdanm 0:9b334a45a8ff 211 // <o13.4..7> CLKOUTDIV: Output Clock Divider
bogdanm 0:9b334a45a8ff 212 // <1-16><#-1>
bogdanm 0:9b334a45a8ff 213 //
bogdanm 0:9b334a45a8ff 214 // <o13.8> CLKOUT_EN: CLKOUT enable
bogdanm 0:9b334a45a8ff 215 // </h>
bogdanm 0:9b334a45a8ff 216 //
bogdanm 0:9b334a45a8ff 217 // </e>
bogdanm 0:9b334a45a8ff 218 */
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 221 #define SCS_Val 0x00000020
bogdanm 0:9b334a45a8ff 222 #define CLKSRCSEL_Val 0x00000001
bogdanm 0:9b334a45a8ff 223 #define PLL0_SETUP 1
bogdanm 0:9b334a45a8ff 224 #define PLL0CFG_Val 0x00000009
bogdanm 0:9b334a45a8ff 225 #define PLL1_SETUP 1
bogdanm 0:9b334a45a8ff 226 #define PLL1CFG_Val 0x00000023
bogdanm 0:9b334a45a8ff 227 #define CCLKSEL_Val 0x00000101
bogdanm 0:9b334a45a8ff 228 #define USBCLKSEL_Val 0x00000201
bogdanm 0:9b334a45a8ff 229 #define EMCCLKSEL_Val 0x00000001
bogdanm 0:9b334a45a8ff 230 #define PCLKSEL_Val 0x00000002
bogdanm 0:9b334a45a8ff 231 #define SPIFICLKSEL_Val 0x00000002
bogdanm 0:9b334a45a8ff 232 #define PCONP_Val 0x042887DE
bogdanm 0:9b334a45a8ff 233 #define CLKOUTCFG_Val 0x00000100
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 #ifdef CORE_M4
bogdanm 0:9b334a45a8ff 236 #define LPC_CPACR 0xE000ED88
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 #define SCB_MVFR0 0xE000EF40
bogdanm 0:9b334a45a8ff 239 #define SCB_MVFR0_RESET 0x10110021
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 #define SCB_MVFR1 0xE000EF44
bogdanm 0:9b334a45a8ff 242 #define SCB_MVFR1_RESET 0x11000011
bogdanm 0:9b334a45a8ff 243 #endif
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 /*--------------------- Flash Accelerator Configuration ----------------------
bogdanm 0:9b334a45a8ff 247 //
bogdanm 0:9b334a45a8ff 248 // <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
bogdanm 0:9b334a45a8ff 249 // <o1.12..15> FLASHTIM: Flash Access Time
bogdanm 0:9b334a45a8ff 250 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
bogdanm 0:9b334a45a8ff 251 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
bogdanm 0:9b334a45a8ff 252 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
bogdanm 0:9b334a45a8ff 253 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
bogdanm 0:9b334a45a8ff 254 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
bogdanm 0:9b334a45a8ff 255 // <5=> 6 CPU clocks (for any CPU clock)
bogdanm 0:9b334a45a8ff 256 // </e>
bogdanm 0:9b334a45a8ff 257 */
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 #define FLASH_SETUP 1
bogdanm 0:9b334a45a8ff 260 #define FLASHCFG_Val 0x00005000
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 263 Check the register settings
bogdanm 0:9b334a45a8ff 264 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 265 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 266 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /* Clock Configuration -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 269 #if (CHECK_RSVD((SCS_Val), ~0x0000003F))
bogdanm 0:9b334a45a8ff 270 #error "SCS: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 271 #endif
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 274 #error "CLKSRCSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 275 #endif
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 #if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
bogdanm 0:9b334a45a8ff 278 #error "PLL0CFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 279 #endif
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
bogdanm 0:9b334a45a8ff 282 #error "PLL1CFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 283 #endif
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 #if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
bogdanm 0:9b334a45a8ff 286 #error "CCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 287 #endif
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 #if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
bogdanm 0:9b334a45a8ff 290 #error "USBCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 291 #endif
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 #if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
bogdanm 0:9b334a45a8ff 294 #error "EMCCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 295 #endif
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 #if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
bogdanm 0:9b334a45a8ff 298 #error "PCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 299 #endif
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 #if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
bogdanm 0:9b334a45a8ff 302 #error "PCONP: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 303 #endif
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 306 #error "CLKOUTCFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 307 #endif
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* Flash Accelerator Configuration -------------------------------------------*/
bogdanm 0:9b334a45a8ff 310 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
bogdanm 0:9b334a45a8ff 311 #warning "FLASHCFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 312 #endif
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 316 DEFINES
bogdanm 0:9b334a45a8ff 317 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 318 /* pll_out_clk = F_cco / (2 � P)
bogdanm 0:9b334a45a8ff 319 F_cco = pll_in_clk � M � 2 � P */
bogdanm 0:9b334a45a8ff 320 #define __M ((PLL0CFG_Val & 0x1F) + 1)
bogdanm 0:9b334a45a8ff 321 #define __PLL0_CLK(__F_IN) (__F_IN * __M)
bogdanm 0:9b334a45a8ff 322 #define __CCLK_DIV (CCLKSEL_Val & 0x1F)
bogdanm 0:9b334a45a8ff 323 #define __PCLK_DIV (PCLKSEL_Val & 0x1F)
bogdanm 0:9b334a45a8ff 324 #define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /* Determine core clock frequency according to settings */
bogdanm 0:9b334a45a8ff 327 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
bogdanm 0:9b334a45a8ff 330 #error "Main Oscillator is selected as clock source but is not enabled!"
bogdanm 0:9b334a45a8ff 331 #endif
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
bogdanm 0:9b334a45a8ff 334 #error "Main PLL is selected as clock source but is not enabled!"
bogdanm 0:9b334a45a8ff 335 #endif
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
bogdanm 0:9b334a45a8ff 338 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
bogdanm 0:9b334a45a8ff 339 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 340 #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
bogdanm 0:9b334a45a8ff 341 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
bogdanm 0:9b334a45a8ff 342 #else /* sysclk = osc_clk */
bogdanm 0:9b334a45a8ff 343 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 344 #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
bogdanm 0:9b334a45a8ff 345 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
bogdanm 0:9b334a45a8ff 346 #endif
bogdanm 0:9b334a45a8ff 347 #else /* cclk = pll_clk */
bogdanm 0:9b334a45a8ff 348 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
bogdanm 0:9b334a45a8ff 349 #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 350 #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
bogdanm 0:9b334a45a8ff 351 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
bogdanm 0:9b334a45a8ff 352 #else /* sysclk = osc_clk */
bogdanm 0:9b334a45a8ff 353 #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 354 #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
bogdanm 0:9b334a45a8ff 355 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
bogdanm 0:9b334a45a8ff 356 #endif
bogdanm 0:9b334a45a8ff 357 #endif
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 #else
bogdanm 0:9b334a45a8ff 360 #define __CORE_CLK (IRC_OSC)
bogdanm 0:9b334a45a8ff 361 #define __PER_CLK (IRC_OSC)
bogdanm 0:9b334a45a8ff 362 #define __EMC_CLK (__CORE_CLK)
bogdanm 0:9b334a45a8ff 363 #endif
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 366 Clock Variable definitions
bogdanm 0:9b334a45a8ff 367 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 368 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 0:9b334a45a8ff 369 uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
bogdanm 0:9b334a45a8ff 370 uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
bogdanm 0:9b334a45a8ff 371 uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
bogdanm 0:9b334a45a8ff 372 be updated after call SystemCoreClockUpdate, should be 48MHz*/
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 376 Clock functions
bogdanm 0:9b334a45a8ff 377 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 378 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 379 {
bogdanm 0:9b334a45a8ff 380 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 381 if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
bogdanm 0:9b334a45a8ff 382 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
bogdanm 0:9b334a45a8ff 383 SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
bogdanm 0:9b334a45a8ff 384 PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
bogdanm 0:9b334a45a8ff 385 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387 else { /* sysclk = osc_clk */
bogdanm 0:9b334a45a8ff 388 if ((LPC_SC->SCS & 0x40) == 0) {
bogdanm 0:9b334a45a8ff 389 SystemCoreClock = 0; /* this should never happen! */
bogdanm 0:9b334a45a8ff 390 PeripheralClock = 0;
bogdanm 0:9b334a45a8ff 391 EMCClock = 0;
bogdanm 0:9b334a45a8ff 392 }
bogdanm 0:9b334a45a8ff 393 else {
bogdanm 0:9b334a45a8ff 394 SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
bogdanm 0:9b334a45a8ff 395 PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
bogdanm 0:9b334a45a8ff 396 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398 }
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400 else { /* cclk = pll_clk */
bogdanm 0:9b334a45a8ff 401 if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
bogdanm 0:9b334a45a8ff 402 SystemCoreClock = 0; /* this should never happen! */
bogdanm 0:9b334a45a8ff 403 PeripheralClock = 0;
bogdanm 0:9b334a45a8ff 404 EMCClock = 0;
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406 else {
bogdanm 0:9b334a45a8ff 407 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
bogdanm 0:9b334a45a8ff 408 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
bogdanm 0:9b334a45a8ff 409 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
bogdanm 0:9b334a45a8ff 410 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
bogdanm 0:9b334a45a8ff 411 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
bogdanm 0:9b334a45a8ff 412 SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
bogdanm 0:9b334a45a8ff 413 PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
bogdanm 0:9b334a45a8ff 414 EMCClock = SystemCoreClock / emc_div;
bogdanm 0:9b334a45a8ff 415 }
bogdanm 0:9b334a45a8ff 416 else { /* sysclk = osc_clk */
bogdanm 0:9b334a45a8ff 417 if ((LPC_SC->SCS & 0x40) == 0) {
bogdanm 0:9b334a45a8ff 418 SystemCoreClock = 0; /* this should never happen! */
bogdanm 0:9b334a45a8ff 419 PeripheralClock = 0;
bogdanm 0:9b334a45a8ff 420 EMCClock = 0;
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 else {
bogdanm 0:9b334a45a8ff 423 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
bogdanm 0:9b334a45a8ff 424 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
bogdanm 0:9b334a45a8ff 425 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
bogdanm 0:9b334a45a8ff 426 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
bogdanm 0:9b334a45a8ff 427 SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
bogdanm 0:9b334a45a8ff 428 PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
bogdanm 0:9b334a45a8ff 429 EMCClock = SystemCoreClock / emc_div;
bogdanm 0:9b334a45a8ff 430 }
bogdanm 0:9b334a45a8ff 431 }
bogdanm 0:9b334a45a8ff 432 }
bogdanm 0:9b334a45a8ff 433 }
bogdanm 0:9b334a45a8ff 434 /* ---update USBClock------------------*/
bogdanm 0:9b334a45a8ff 435 if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
bogdanm 0:9b334a45a8ff 436 {
bogdanm 0:9b334a45a8ff 437 switch (LPC_SC->USBCLKSEL & 0x1F)
bogdanm 0:9b334a45a8ff 438 {
bogdanm 0:9b334a45a8ff 439 case 0:
bogdanm 0:9b334a45a8ff 440 USBClock = 0; //no clock will be provided to the USB subsystem
bogdanm 0:9b334a45a8ff 441 break;
bogdanm 0:9b334a45a8ff 442 case 4:
bogdanm 0:9b334a45a8ff 443 case 6:
bogdanm 0:9b334a45a8ff 444 {
bogdanm 0:9b334a45a8ff 445 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
bogdanm 0:9b334a45a8ff 446 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
bogdanm 0:9b334a45a8ff 447 if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
bogdanm 0:9b334a45a8ff 448 USBClock = OSC_CLK * mul / usb_div;
bogdanm 0:9b334a45a8ff 449 else //pll_clk_in = irc_clk
bogdanm 0:9b334a45a8ff 450 USBClock = IRC_OSC * mul / usb_div;
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452 break;
bogdanm 0:9b334a45a8ff 453 default:
bogdanm 0:9b334a45a8ff 454 USBClock = 0; /* this should never happen! */
bogdanm 0:9b334a45a8ff 455 }
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457 else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
bogdanm 0:9b334a45a8ff 460 USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
bogdanm 0:9b334a45a8ff 461 else //pll1_clk_in = irc_clk
bogdanm 0:9b334a45a8ff 462 USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464 else
bogdanm 0:9b334a45a8ff 465 USBClock = 0; /* this should never happen! */
bogdanm 0:9b334a45a8ff 466 }
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 #ifdef CORE_M4
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 void fpu_init(void)
bogdanm 0:9b334a45a8ff 473 {
bogdanm 0:9b334a45a8ff 474 // from arm trm manual:
bogdanm 0:9b334a45a8ff 475 // ; CPACR is located at address 0xE000ED88
bogdanm 0:9b334a45a8ff 476 // LDR.W R0, =0xE000ED88
bogdanm 0:9b334a45a8ff 477 // ; Read CPACR
bogdanm 0:9b334a45a8ff 478 // LDR R1, [R0]
bogdanm 0:9b334a45a8ff 479 // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
bogdanm 0:9b334a45a8ff 480 // ORR R1, R1, #(0xF << 20)
bogdanm 0:9b334a45a8ff 481 // ; Write back the modified value to the CPACR
bogdanm 0:9b334a45a8ff 482 // STR R1, [R0]
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
bogdanm 0:9b334a45a8ff 486 volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
bogdanm 0:9b334a45a8ff 487 volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
bogdanm 0:9b334a45a8ff 488 volatile uint32_t Cpacr;
bogdanm 0:9b334a45a8ff 489 volatile uint32_t Mvfr0;
bogdanm 0:9b334a45a8ff 490 volatile uint32_t Mvfr1;
bogdanm 0:9b334a45a8ff 491 char vfpPresent = 0;
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 Mvfr0 = *regMvfr0;
bogdanm 0:9b334a45a8ff 494 Mvfr1 = *regMvfr1;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 if(vfpPresent)
bogdanm 0:9b334a45a8ff 499 {
bogdanm 0:9b334a45a8ff 500 Cpacr = *regCpacr;
bogdanm 0:9b334a45a8ff 501 Cpacr |= (0xF << 20);
bogdanm 0:9b334a45a8ff 502 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506 #endif
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /**
bogdanm 0:9b334a45a8ff 509 * Initialize the system
bogdanm 0:9b334a45a8ff 510 *
bogdanm 0:9b334a45a8ff 511 * @param none
bogdanm 0:9b334a45a8ff 512 * @return none
bogdanm 0:9b334a45a8ff 513 *
bogdanm 0:9b334a45a8ff 514 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 515 * Initialize the System.
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 void SystemInit (void)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 #ifndef __CODE_RED
bogdanm 0:9b334a45a8ff 520 #ifdef CORE_M4
bogdanm 0:9b334a45a8ff 521 fpu_init();
bogdanm 0:9b334a45a8ff 522 #endif
bogdanm 0:9b334a45a8ff 523 #endif
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 526 LPC_SC->SCS = SCS_Val;
bogdanm 0:9b334a45a8ff 527 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
bogdanm 0:9b334a45a8ff 528 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
bogdanm 0:9b334a45a8ff 529 }
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 #if (PLL0_SETUP)
bogdanm 0:9b334a45a8ff 534 LPC_SC->PLL0CFG = PLL0CFG_Val;
bogdanm 0:9b334a45a8ff 535 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
bogdanm 0:9b334a45a8ff 536 LPC_SC->PLL0FEED = 0xAA;
bogdanm 0:9b334a45a8ff 537 LPC_SC->PLL0FEED = 0x55;
bogdanm 0:9b334a45a8ff 538 while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
bogdanm 0:9b334a45a8ff 539 #endif
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 #if (PLL1_SETUP)
bogdanm 0:9b334a45a8ff 542 LPC_SC->PLL1CFG = PLL1CFG_Val;
bogdanm 0:9b334a45a8ff 543 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
bogdanm 0:9b334a45a8ff 544 LPC_SC->PLL1FEED = 0xAA;
bogdanm 0:9b334a45a8ff 545 LPC_SC->PLL1FEED = 0x55;
bogdanm 0:9b334a45a8ff 546 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
bogdanm 0:9b334a45a8ff 547 #endif
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
bogdanm 0:9b334a45a8ff 550 LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
bogdanm 0:9b334a45a8ff 551 LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
bogdanm 0:9b334a45a8ff 552 LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
bogdanm 0:9b334a45a8ff 553 LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
bogdanm 0:9b334a45a8ff 554 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
bogdanm 0:9b334a45a8ff 555 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
bogdanm 0:9b334a45a8ff 556 #endif
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 LPC_SC->PBOOST |= 0x03; /* Power Boost control */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
bogdanm 0:9b334a45a8ff 561 LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
bogdanm 0:9b334a45a8ff 562 #endif
bogdanm 0:9b334a45a8ff 563 #ifndef __CODE_RED
bogdanm 0:9b334a45a8ff 564 #ifdef __RAM_MODE__
bogdanm 0:9b334a45a8ff 565 SCB->VTOR = 0x10000000 & 0x3FFFFF80;
bogdanm 0:9b334a45a8ff 566 #else
bogdanm 0:9b334a45a8ff 567 SCB->VTOR = 0x00000000 & 0x3FFFFF80;
bogdanm 0:9b334a45a8ff 568 #endif
bogdanm 0:9b334a45a8ff 569 #endif
bogdanm 0:9b334a45a8ff 570 SystemCoreClockUpdate();
bogdanm 0:9b334a45a8ff 571 }