teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file system_LPC17xx.c
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M3 Device System Source File for
bogdanm 0:9b334a45a8ff 4 * NXP LPC17xx Device Series
bogdanm 0:9b334a45a8ff 5 * @version V1.11
bogdanm 0:9b334a45a8ff 6 * @date 21. June 2011
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #include <stdint.h>
bogdanm 0:9b334a45a8ff 27 #include "LPC17xx.h"
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 /** @addtogroup LPC17xx_System
bogdanm 0:9b334a45a8ff 31 * @{
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 /*
bogdanm 0:9b334a45a8ff 35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /*--------------------- Clock Configuration ----------------------------------
bogdanm 0:9b334a45a8ff 39 //
bogdanm 0:9b334a45a8ff 40 // <e> Clock Configuration
bogdanm 0:9b334a45a8ff 41 // <h> System Controls and Status Register (SCS)
bogdanm 0:9b334a45a8ff 42 // <o1.4> OSCRANGE: Main Oscillator Range Select
bogdanm 0:9b334a45a8ff 43 // <0=> 1 MHz to 20 MHz
bogdanm 0:9b334a45a8ff 44 // <1=> 15 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 45 // <e1.5> OSCEN: Main Oscillator Enable
bogdanm 0:9b334a45a8ff 46 // </e>
bogdanm 0:9b334a45a8ff 47 // </h>
bogdanm 0:9b334a45a8ff 48 //
bogdanm 0:9b334a45a8ff 49 // <h> Clock Source Select Register (CLKSRCSEL)
bogdanm 0:9b334a45a8ff 50 // <o2.0..1> CLKSRC: PLL Clock Source Selection
bogdanm 0:9b334a45a8ff 51 // <0=> Internal RC oscillator
bogdanm 0:9b334a45a8ff 52 // <1=> Main oscillator
bogdanm 0:9b334a45a8ff 53 // <2=> RTC oscillator
bogdanm 0:9b334a45a8ff 54 // </h>
bogdanm 0:9b334a45a8ff 55 //
bogdanm 0:9b334a45a8ff 56 // <e3> PLL0 Configuration (Main PLL)
bogdanm 0:9b334a45a8ff 57 // <h> PLL0 Configuration Register (PLL0CFG)
bogdanm 0:9b334a45a8ff 58 // <i> F_cco0 = (2 * M * F_in) / N
bogdanm 0:9b334a45a8ff 59 // <i> F_in must be in the range of 32 kHz to 50 MHz
bogdanm 0:9b334a45a8ff 60 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
bogdanm 0:9b334a45a8ff 61 // <o4.0..14> MSEL: PLL Multiplier Selection
bogdanm 0:9b334a45a8ff 62 // <6-32768><#-1>
bogdanm 0:9b334a45a8ff 63 // <i> M Value
bogdanm 0:9b334a45a8ff 64 // <o4.16..23> NSEL: PLL Divider Selection
bogdanm 0:9b334a45a8ff 65 // <1-256><#-1>
bogdanm 0:9b334a45a8ff 66 // <i> N Value
bogdanm 0:9b334a45a8ff 67 // </h>
bogdanm 0:9b334a45a8ff 68 // </e>
bogdanm 0:9b334a45a8ff 69 //
bogdanm 0:9b334a45a8ff 70 // <e5> PLL1 Configuration (USB PLL)
bogdanm 0:9b334a45a8ff 71 // <h> PLL1 Configuration Register (PLL1CFG)
bogdanm 0:9b334a45a8ff 72 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
bogdanm 0:9b334a45a8ff 73 // <i> F_cco1 = F_osc * M * 2 * P
bogdanm 0:9b334a45a8ff 74 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 75 // <o6.0..4> MSEL: PLL Multiplier Selection
bogdanm 0:9b334a45a8ff 76 // <1-32><#-1>
bogdanm 0:9b334a45a8ff 77 // <i> M Value (for USB maximum value is 4)
bogdanm 0:9b334a45a8ff 78 // <o6.5..6> PSEL: PLL Divider Selection
bogdanm 0:9b334a45a8ff 79 // <0=> 1
bogdanm 0:9b334a45a8ff 80 // <1=> 2
bogdanm 0:9b334a45a8ff 81 // <2=> 4
bogdanm 0:9b334a45a8ff 82 // <3=> 8
bogdanm 0:9b334a45a8ff 83 // <i> P Value
bogdanm 0:9b334a45a8ff 84 // </h>
bogdanm 0:9b334a45a8ff 85 // </e>
bogdanm 0:9b334a45a8ff 86 //
bogdanm 0:9b334a45a8ff 87 // <h> CPU Clock Configuration Register (CCLKCFG)
bogdanm 0:9b334a45a8ff 88 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
bogdanm 0:9b334a45a8ff 89 // <1-256><#-1>
bogdanm 0:9b334a45a8ff 90 // </h>
bogdanm 0:9b334a45a8ff 91 //
bogdanm 0:9b334a45a8ff 92 // <h> USB Clock Configuration Register (USBCLKCFG)
bogdanm 0:9b334a45a8ff 93 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
bogdanm 0:9b334a45a8ff 94 // <0-15>
bogdanm 0:9b334a45a8ff 95 // <i> Divide is USBSEL + 1
bogdanm 0:9b334a45a8ff 96 // </h>
bogdanm 0:9b334a45a8ff 97 //
bogdanm 0:9b334a45a8ff 98 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
bogdanm 0:9b334a45a8ff 99 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
bogdanm 0:9b334a45a8ff 100 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 101 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 102 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 103 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 104 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
bogdanm 0:9b334a45a8ff 105 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 106 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 107 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 108 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 109 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
bogdanm 0:9b334a45a8ff 110 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 111 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 112 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 113 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 114 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
bogdanm 0:9b334a45a8ff 115 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 116 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 117 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 118 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 119 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
bogdanm 0:9b334a45a8ff 120 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 121 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 122 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 123 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 124 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
bogdanm 0:9b334a45a8ff 125 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 126 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 127 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 128 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 129 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
bogdanm 0:9b334a45a8ff 130 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 131 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 132 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 133 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 134 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
bogdanm 0:9b334a45a8ff 135 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 136 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 137 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 138 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 139 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
bogdanm 0:9b334a45a8ff 140 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 141 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 142 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 143 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 144 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
bogdanm 0:9b334a45a8ff 145 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 146 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 147 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 148 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 149 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
bogdanm 0:9b334a45a8ff 150 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 151 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 152 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 153 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 154 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
bogdanm 0:9b334a45a8ff 155 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 156 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 157 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 158 // <3=> Pclk = Hclk / 6
bogdanm 0:9b334a45a8ff 159 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
bogdanm 0:9b334a45a8ff 160 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 161 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 162 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 163 // <3=> Pclk = Hclk / 6
bogdanm 0:9b334a45a8ff 164 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
bogdanm 0:9b334a45a8ff 165 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 166 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 167 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 168 // <3=> Pclk = Hclk / 6
bogdanm 0:9b334a45a8ff 169 // </h>
bogdanm 0:9b334a45a8ff 170 //
bogdanm 0:9b334a45a8ff 171 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
bogdanm 0:9b334a45a8ff 172 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
bogdanm 0:9b334a45a8ff 173 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 174 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 175 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 176 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 177 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
bogdanm 0:9b334a45a8ff 178 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 179 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 180 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 181 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 182 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
bogdanm 0:9b334a45a8ff 183 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 184 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 185 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 186 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 187 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
bogdanm 0:9b334a45a8ff 188 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 189 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 190 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 191 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 192 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
bogdanm 0:9b334a45a8ff 193 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 194 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 195 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 196 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 197 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
bogdanm 0:9b334a45a8ff 198 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 199 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 200 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 201 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 202 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
bogdanm 0:9b334a45a8ff 203 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 204 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 205 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 206 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 207 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
bogdanm 0:9b334a45a8ff 208 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 209 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 210 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 211 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 212 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
bogdanm 0:9b334a45a8ff 213 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 214 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 215 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 216 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 217 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
bogdanm 0:9b334a45a8ff 218 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 219 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 220 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 221 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 222 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
bogdanm 0:9b334a45a8ff 223 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 224 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 225 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 226 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 227 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
bogdanm 0:9b334a45a8ff 228 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 229 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 230 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 231 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 232 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
bogdanm 0:9b334a45a8ff 233 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 234 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 235 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 236 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 237 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
bogdanm 0:9b334a45a8ff 238 // <0=> Pclk = Cclk / 4
bogdanm 0:9b334a45a8ff 239 // <1=> Pclk = Cclk
bogdanm 0:9b334a45a8ff 240 // <2=> Pclk = Cclk / 2
bogdanm 0:9b334a45a8ff 241 // <3=> Pclk = Hclk / 8
bogdanm 0:9b334a45a8ff 242 // </h>
bogdanm 0:9b334a45a8ff 243 //
bogdanm 0:9b334a45a8ff 244 // <h> Power Control for Peripherals Register (PCONP)
bogdanm 0:9b334a45a8ff 245 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
bogdanm 0:9b334a45a8ff 246 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
bogdanm 0:9b334a45a8ff 247 // <o11.3> PCUART0: UART 0 power/clock enable
bogdanm 0:9b334a45a8ff 248 // <o11.4> PCUART1: UART 1 power/clock enable
bogdanm 0:9b334a45a8ff 249 // <o11.6> PCPWM1: PWM 1 power/clock enable
bogdanm 0:9b334a45a8ff 250 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
bogdanm 0:9b334a45a8ff 251 // <o11.8> PCSPI: SPI interface power/clock enable
bogdanm 0:9b334a45a8ff 252 // <o11.9> PCRTC: RTC power/clock enable
bogdanm 0:9b334a45a8ff 253 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
bogdanm 0:9b334a45a8ff 254 // <o11.12> PCAD: A/D converter power/clock enable
bogdanm 0:9b334a45a8ff 255 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
bogdanm 0:9b334a45a8ff 256 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
bogdanm 0:9b334a45a8ff 257 // <o11.15> PCGPIO: GPIOs power/clock enable
bogdanm 0:9b334a45a8ff 258 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
bogdanm 0:9b334a45a8ff 259 // <o11.17> PCMC: Motor control PWM power/clock enable
bogdanm 0:9b334a45a8ff 260 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
bogdanm 0:9b334a45a8ff 261 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
bogdanm 0:9b334a45a8ff 262 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
bogdanm 0:9b334a45a8ff 263 // <o11.22> PCTIM2: Timer 2 power/clock enable
bogdanm 0:9b334a45a8ff 264 // <o11.23> PCTIM3: Timer 3 power/clock enable
bogdanm 0:9b334a45a8ff 265 // <o11.24> PCUART2: UART 2 power/clock enable
bogdanm 0:9b334a45a8ff 266 // <o11.25> PCUART3: UART 3 power/clock enable
bogdanm 0:9b334a45a8ff 267 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
bogdanm 0:9b334a45a8ff 268 // <o11.27> PCI2S: I2S interface power/clock enable
bogdanm 0:9b334a45a8ff 269 // <o11.29> PCGPDMA: GP DMA function power/clock enable
bogdanm 0:9b334a45a8ff 270 // <o11.30> PCENET: Ethernet block power/clock enable
bogdanm 0:9b334a45a8ff 271 // <o11.31> PCUSB: USB interface power/clock enable
bogdanm 0:9b334a45a8ff 272 // </h>
bogdanm 0:9b334a45a8ff 273 //
bogdanm 0:9b334a45a8ff 274 // <h> Clock Output Configuration Register (CLKOUTCFG)
bogdanm 0:9b334a45a8ff 275 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
bogdanm 0:9b334a45a8ff 276 // <0=> CPU clock
bogdanm 0:9b334a45a8ff 277 // <1=> Main oscillator
bogdanm 0:9b334a45a8ff 278 // <2=> Internal RC oscillator
bogdanm 0:9b334a45a8ff 279 // <3=> USB clock
bogdanm 0:9b334a45a8ff 280 // <4=> RTC oscillator
bogdanm 0:9b334a45a8ff 281 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
bogdanm 0:9b334a45a8ff 282 // <1-16><#-1>
bogdanm 0:9b334a45a8ff 283 // <o12.8> CLKOUT_EN: CLKOUT enable control
bogdanm 0:9b334a45a8ff 284 // </h>
bogdanm 0:9b334a45a8ff 285 //
bogdanm 0:9b334a45a8ff 286 // </e>
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
bogdanm 0:9b334a45a8ff 292 @{
bogdanm 0:9b334a45a8ff 293 */
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 296 #define SCS_Val 0x00000020
bogdanm 0:9b334a45a8ff 297 #define CLKSRCSEL_Val 0x00000001
bogdanm 0:9b334a45a8ff 298 #define PLL0_SETUP 1
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 #ifdef MCB1700
bogdanm 0:9b334a45a8ff 301 # define PLL0CFG_Val 0x00050063
bogdanm 0:9b334a45a8ff 302 # define PLL1_SETUP 1
bogdanm 0:9b334a45a8ff 303 # define PLL1CFG_Val 0x00000023
bogdanm 0:9b334a45a8ff 304 # define CCLKCFG_Val 0x00000003
bogdanm 0:9b334a45a8ff 305 # define USBCLKCFG_Val 0x00000000
bogdanm 0:9b334a45a8ff 306 #else
bogdanm 0:9b334a45a8ff 307 # define PLL0CFG_Val 0x0000000B
bogdanm 0:9b334a45a8ff 308 # define PLL1_SETUP 0
bogdanm 0:9b334a45a8ff 309 # define PLL1CFG_Val 0x00000000
bogdanm 0:9b334a45a8ff 310 # define CCLKCFG_Val 0x00000002
bogdanm 0:9b334a45a8ff 311 # define USBCLKCFG_Val 0x00000005
bogdanm 0:9b334a45a8ff 312 #endif
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 #define PCLKSEL0_Val 0x00000000
bogdanm 0:9b334a45a8ff 315 #define PCLKSEL1_Val 0x00000000
bogdanm 0:9b334a45a8ff 316 #define PCONP_Val 0x042887DE
bogdanm 0:9b334a45a8ff 317 #define CLKOUTCFG_Val 0x00000000
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /*--------------------- Flash Accelerator Configuration ----------------------
bogdanm 0:9b334a45a8ff 321 //
bogdanm 0:9b334a45a8ff 322 // <e> Flash Accelerator Configuration
bogdanm 0:9b334a45a8ff 323 // <o1.12..15> FLASHTIM: Flash Access Time
bogdanm 0:9b334a45a8ff 324 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
bogdanm 0:9b334a45a8ff 325 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
bogdanm 0:9b334a45a8ff 326 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
bogdanm 0:9b334a45a8ff 327 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
bogdanm 0:9b334a45a8ff 328 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
bogdanm 0:9b334a45a8ff 329 // <5=> 6 CPU clocks (for any CPU clock)
bogdanm 0:9b334a45a8ff 330 // </e>
bogdanm 0:9b334a45a8ff 331 */
bogdanm 0:9b334a45a8ff 332 #define FLASH_SETUP 1
bogdanm 0:9b334a45a8ff 333 #define FLASHCFG_Val 0x0000303A
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /*
bogdanm 0:9b334a45a8ff 336 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 0:9b334a45a8ff 337 */
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 340 Check the register settings
bogdanm 0:9b334a45a8ff 341 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 342 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 343 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /* Clock Configuration -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 346 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
bogdanm 0:9b334a45a8ff 347 #error "SCS: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 348 #endif
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
bogdanm 0:9b334a45a8ff 351 #error "CLKSRCSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 352 #endif
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
bogdanm 0:9b334a45a8ff 355 #error "PLL0CFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 356 #endif
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
bogdanm 0:9b334a45a8ff 359 #error "PLL1CFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 360 #endif
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 #if (PLL0_SETUP) /* if PLL0 is used */
bogdanm 0:9b334a45a8ff 363 #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
bogdanm 0:9b334a45a8ff 364 #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
bogdanm 0:9b334a45a8ff 365 #endif
bogdanm 0:9b334a45a8ff 366 #endif
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 #if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
bogdanm 0:9b334a45a8ff 369 #error "CCLKCFG: Value out of range!"
bogdanm 0:9b334a45a8ff 370 #endif
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
bogdanm 0:9b334a45a8ff 373 #error "USBCLKCFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 374 #endif
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
bogdanm 0:9b334a45a8ff 377 #error "PCLKSEL0: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 378 #endif
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
bogdanm 0:9b334a45a8ff 381 #error "PCLKSEL1: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 382 #endif
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
bogdanm 0:9b334a45a8ff 385 #error "PCONP: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 386 #endif
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 389 #error "CLKOUTCFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 390 #endif
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /* Flash Accelerator Configuration -------------------------------------------*/
bogdanm 0:9b334a45a8ff 393 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
bogdanm 0:9b334a45a8ff 394 #error "FLASHCFG: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 395 #endif
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 399 DEFINES
bogdanm 0:9b334a45a8ff 400 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 403 Define clocks
bogdanm 0:9b334a45a8ff 404 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 405 #define XTAL (12000000UL) /* Oscillator frequency */
bogdanm 0:9b334a45a8ff 406 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
bogdanm 0:9b334a45a8ff 407 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
bogdanm 0:9b334a45a8ff 408 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* F_cco0 = (2 * M * F_in) / N */
bogdanm 0:9b334a45a8ff 412 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
bogdanm 0:9b334a45a8ff 413 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
bogdanm 0:9b334a45a8ff 414 #define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
bogdanm 0:9b334a45a8ff 415 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Determine core clock frequency according to settings */
bogdanm 0:9b334a45a8ff 418 #if (PLL0_SETUP)
bogdanm 0:9b334a45a8ff 419 #if ((CLKSRCSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 420 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 421 #elif ((CLKSRCSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 422 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 423 #else
bogdanm 0:9b334a45a8ff 424 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 425 #endif
bogdanm 0:9b334a45a8ff 426 #else
bogdanm 0:9b334a45a8ff 427 #if ((CLKSRCSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 428 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 429 #elif ((CLKSRCSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 430 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 431 #else
bogdanm 0:9b334a45a8ff 432 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
bogdanm 0:9b334a45a8ff 433 #endif
bogdanm 0:9b334a45a8ff 434 #endif
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /**
bogdanm 0:9b334a45a8ff 437 * @}
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
bogdanm 0:9b334a45a8ff 442 @{
bogdanm 0:9b334a45a8ff 443 */
bogdanm 0:9b334a45a8ff 444 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 445 Clock Variable definitions
bogdanm 0:9b334a45a8ff 446 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 447 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /**
bogdanm 0:9b334a45a8ff 450 * @}
bogdanm 0:9b334a45a8ff 451 */
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
bogdanm 0:9b334a45a8ff 455 @{
bogdanm 0:9b334a45a8ff 456 */
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /**
bogdanm 0:9b334a45a8ff 459 * Update SystemCoreClock variable
bogdanm 0:9b334a45a8ff 460 *
bogdanm 0:9b334a45a8ff 461 * @param none
bogdanm 0:9b334a45a8ff 462 * @return none
bogdanm 0:9b334a45a8ff 463 *
bogdanm 0:9b334a45a8ff 464 * @brief Updates the SystemCoreClock with current core Clock
bogdanm 0:9b334a45a8ff 465 * retrieved from cpu registers.
bogdanm 0:9b334a45a8ff 466 */void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 467 {
bogdanm 0:9b334a45a8ff 468 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 469 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
bogdanm 0:9b334a45a8ff 470 switch (LPC_SC->CLKSRCSEL & 0x03) {
bogdanm 0:9b334a45a8ff 471 case 0: /* Int. RC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 472 case 3: /* Reserved, default to Int. RC */
bogdanm 0:9b334a45a8ff 473 SystemCoreClock = (IRC_OSC *
bogdanm 0:9b334a45a8ff 474 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
bogdanm 0:9b334a45a8ff 475 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
bogdanm 0:9b334a45a8ff 476 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
bogdanm 0:9b334a45a8ff 477 break;
bogdanm 0:9b334a45a8ff 478 case 1: /* Main oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 479 SystemCoreClock = (OSC_CLK *
bogdanm 0:9b334a45a8ff 480 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
bogdanm 0:9b334a45a8ff 481 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
bogdanm 0:9b334a45a8ff 482 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
bogdanm 0:9b334a45a8ff 483 break;
bogdanm 0:9b334a45a8ff 484 case 2: /* RTC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 485 SystemCoreClock = (RTC_CLK *
bogdanm 0:9b334a45a8ff 486 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
bogdanm 0:9b334a45a8ff 487 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
bogdanm 0:9b334a45a8ff 488 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
bogdanm 0:9b334a45a8ff 489 break;
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491 } else {
bogdanm 0:9b334a45a8ff 492 switch (LPC_SC->CLKSRCSEL & 0x03) {
bogdanm 0:9b334a45a8ff 493 case 0: /* Int. RC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 494 case 3: /* Reserved, default to Int. RC */
bogdanm 0:9b334a45a8ff 495 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
bogdanm 0:9b334a45a8ff 496 break;
bogdanm 0:9b334a45a8ff 497 case 1: /* Main oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 498 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
bogdanm 0:9b334a45a8ff 499 break;
bogdanm 0:9b334a45a8ff 500 case 2: /* RTC oscillator => PLL0 */
bogdanm 0:9b334a45a8ff 501 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
bogdanm 0:9b334a45a8ff 502 break;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /**
bogdanm 0:9b334a45a8ff 509 * Initialize the system
bogdanm 0:9b334a45a8ff 510 *
bogdanm 0:9b334a45a8ff 511 * @param none
bogdanm 0:9b334a45a8ff 512 * @return none
bogdanm 0:9b334a45a8ff 513 *
bogdanm 0:9b334a45a8ff 514 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 515 * Initialize the System.
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 void SystemInit (void)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 520 LPC_SC->SCS = SCS_Val;
bogdanm 0:9b334a45a8ff 521 if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
bogdanm 0:9b334a45a8ff 522 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
bogdanm 0:9b334a45a8ff 523 }
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
bogdanm 0:9b334a45a8ff 526 /* Periphral clock must be selected before PLL0 enabling and connecting
bogdanm 0:9b334a45a8ff 527 * - according errata.lpc1768-16.March.2010 -
bogdanm 0:9b334a45a8ff 528 */
bogdanm 0:9b334a45a8ff 529 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
bogdanm 0:9b334a45a8ff 530 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 #if (PLL0_SETUP)
bogdanm 0:9b334a45a8ff 533 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
bogdanm 0:9b334a45a8ff 536 LPC_SC->PLL0FEED = 0xAA;
bogdanm 0:9b334a45a8ff 537 LPC_SC->PLL0FEED = 0x55;
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
bogdanm 0:9b334a45a8ff 540 LPC_SC->PLL0FEED = 0xAA;
bogdanm 0:9b334a45a8ff 541 LPC_SC->PLL0FEED = 0x55;
bogdanm 0:9b334a45a8ff 542 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
bogdanm 0:9b334a45a8ff 545 LPC_SC->PLL0FEED = 0xAA;
bogdanm 0:9b334a45a8ff 546 LPC_SC->PLL0FEED = 0x55;
bogdanm 0:9b334a45a8ff 547 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
bogdanm 0:9b334a45a8ff 548 #endif
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 #if (PLL1_SETUP)
bogdanm 0:9b334a45a8ff 551 LPC_SC->PLL1CFG = PLL1CFG_Val;
bogdanm 0:9b334a45a8ff 552 LPC_SC->PLL1FEED = 0xAA;
bogdanm 0:9b334a45a8ff 553 LPC_SC->PLL1FEED = 0x55;
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
bogdanm 0:9b334a45a8ff 556 LPC_SC->PLL1FEED = 0xAA;
bogdanm 0:9b334a45a8ff 557 LPC_SC->PLL1FEED = 0x55;
bogdanm 0:9b334a45a8ff 558 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
bogdanm 0:9b334a45a8ff 561 LPC_SC->PLL1FEED = 0xAA;
bogdanm 0:9b334a45a8ff 562 LPC_SC->PLL1FEED = 0x55;
bogdanm 0:9b334a45a8ff 563 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
bogdanm 0:9b334a45a8ff 564 #else
bogdanm 0:9b334a45a8ff 565 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
bogdanm 0:9b334a45a8ff 566 #endif
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
bogdanm 0:9b334a45a8ff 571 #endif
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
bogdanm 0:9b334a45a8ff 574 LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
bogdanm 0:9b334a45a8ff 575 #endif
bogdanm 0:9b334a45a8ff 576 }
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 /**
bogdanm 0:9b334a45a8ff 579 * @}
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 /**
bogdanm 0:9b334a45a8ff 583 * @}
bogdanm 0:9b334a45a8ff 584 */