teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file system_LPC11xx.c
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
bogdanm 0:9b334a45a8ff 4 * for the NXP LPC11xx/LPC11Cxx Devices
bogdanm 0:9b334a45a8ff 5 * @version V1.10
bogdanm 0:9b334a45a8ff 6 * @date 24. November 2010
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #include <stdint.h>
bogdanm 0:9b334a45a8ff 27 #include "LPC11xx.h"
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 /*
bogdanm 0:9b334a45a8ff 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 31 */
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /*--------------------- Clock Configuration ----------------------------------
bogdanm 0:9b334a45a8ff 34 //
bogdanm 0:9b334a45a8ff 35 // <e> Clock Configuration
bogdanm 0:9b334a45a8ff 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
bogdanm 0:9b334a45a8ff 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
bogdanm 0:9b334a45a8ff 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 0:9b334a45a8ff 39 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 0:9b334a45a8ff 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
bogdanm 0:9b334a45a8ff 41 // <i> Determines frequency range for Low-power oscillator.
bogdanm 0:9b334a45a8ff 42 // <0=> 1 - 20 MHz
bogdanm 0:9b334a45a8ff 43 // <1=> 15 - 25 MHz
bogdanm 0:9b334a45a8ff 44 // </h>
bogdanm 0:9b334a45a8ff 45 //
bogdanm 0:9b334a45a8ff 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
bogdanm 0:9b334a45a8ff 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 0:9b334a45a8ff 48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
bogdanm 0:9b334a45a8ff 49 // <0-31>
bogdanm 0:9b334a45a8ff 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
bogdanm 0:9b334a45a8ff 51 // <0=> Undefined
bogdanm 0:9b334a45a8ff 52 // <1=> 0.5 MHz
bogdanm 0:9b334a45a8ff 53 // <2=> 0.8 MHz
bogdanm 0:9b334a45a8ff 54 // <3=> 1.1 MHz
bogdanm 0:9b334a45a8ff 55 // <4=> 1.4 MHz
bogdanm 0:9b334a45a8ff 56 // <5=> 1.6 MHz
bogdanm 0:9b334a45a8ff 57 // <6=> 1.8 MHz
bogdanm 0:9b334a45a8ff 58 // <7=> 2.0 MHz
bogdanm 0:9b334a45a8ff 59 // <8=> 2.2 MHz
bogdanm 0:9b334a45a8ff 60 // <9=> 2.4 MHz
bogdanm 0:9b334a45a8ff 61 // <10=> 2.6 MHz
bogdanm 0:9b334a45a8ff 62 // <11=> 2.7 MHz
bogdanm 0:9b334a45a8ff 63 // <12=> 2.9 MHz
bogdanm 0:9b334a45a8ff 64 // <13=> 3.1 MHz
bogdanm 0:9b334a45a8ff 65 // <14=> 3.2 MHz
bogdanm 0:9b334a45a8ff 66 // <15=> 3.4 MHz
bogdanm 0:9b334a45a8ff 67 // </h>
bogdanm 0:9b334a45a8ff 68 //
bogdanm 0:9b334a45a8ff 69 // <h> System PLL Control Register (SYSPLLCTRL)
bogdanm 0:9b334a45a8ff 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 73 // <o3.0..4> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 74 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 75 // <0-31>
bogdanm 0:9b334a45a8ff 76 // <o3.5..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 77 // <0=> P = 1
bogdanm 0:9b334a45a8ff 78 // <1=> P = 2
bogdanm 0:9b334a45a8ff 79 // <2=> P = 4
bogdanm 0:9b334a45a8ff 80 // <3=> P = 8
bogdanm 0:9b334a45a8ff 81 // </h>
bogdanm 0:9b334a45a8ff 82 //
bogdanm 0:9b334a45a8ff 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
bogdanm 0:9b334a45a8ff 84 // <o4.0..1> SEL: System PLL Clock Source
bogdanm 0:9b334a45a8ff 85 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 86 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 87 // <2=> Reserved
bogdanm 0:9b334a45a8ff 88 // <3=> Reserved
bogdanm 0:9b334a45a8ff 89 // </h>
bogdanm 0:9b334a45a8ff 90 //
bogdanm 0:9b334a45a8ff 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
bogdanm 0:9b334a45a8ff 92 // <o5.0..1> SEL: Clock Source for Main Clock
bogdanm 0:9b334a45a8ff 93 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 94 // <1=> Input Clock to System PLL
bogdanm 0:9b334a45a8ff 95 // <2=> WDT Oscillator
bogdanm 0:9b334a45a8ff 96 // <3=> System PLL Clock Out
bogdanm 0:9b334a45a8ff 97 // </h>
bogdanm 0:9b334a45a8ff 98 //
bogdanm 0:9b334a45a8ff 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
bogdanm 0:9b334a45a8ff 100 // <o6.0..7> DIV: System AHB Clock Divider
bogdanm 0:9b334a45a8ff 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 0:9b334a45a8ff 102 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 103 // <0-255>
bogdanm 0:9b334a45a8ff 104 // </h>
bogdanm 0:9b334a45a8ff 105 // </e>
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 108 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 109 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 110 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
bogdanm 0:9b334a45a8ff 111 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 0:9b334a45a8ff 112 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
bogdanm 0:9b334a45a8ff 113 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /*
bogdanm 0:9b334a45a8ff 116 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 120 Check the register settings
bogdanm 0:9b334a45a8ff 121 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 122 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 123 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /* Clock Configuration -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 126 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 127 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 128 #endif
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 131 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 132 #endif
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
bogdanm 0:9b334a45a8ff 135 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 136 #endif
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 139 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 140 #endif
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 143 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 144 #endif
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 147 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 148 #endif
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 152 DEFINES
bogdanm 0:9b334a45a8ff 153 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 156 Define clocks
bogdanm 0:9b334a45a8ff 157 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 158 #define __XTAL (12000000UL) /* Oscillator frequency */
bogdanm 0:9b334a45a8ff 159 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
bogdanm 0:9b334a45a8ff 160 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 0:9b334a45a8ff 164 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 167 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 168 #define __WDT_OSC_CLK ( 0) /* undefined */
bogdanm 0:9b334a45a8ff 169 #elif (__FREQSEL == 1)
bogdanm 0:9b334a45a8ff 170 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 171 #elif (__FREQSEL == 2)
bogdanm 0:9b334a45a8ff 172 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 173 #elif (__FREQSEL == 3)
bogdanm 0:9b334a45a8ff 174 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 175 #elif (__FREQSEL == 4)
bogdanm 0:9b334a45a8ff 176 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 177 #elif (__FREQSEL == 5)
bogdanm 0:9b334a45a8ff 178 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 179 #elif (__FREQSEL == 6)
bogdanm 0:9b334a45a8ff 180 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 181 #elif (__FREQSEL == 7)
bogdanm 0:9b334a45a8ff 182 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 183 #elif (__FREQSEL == 8)
bogdanm 0:9b334a45a8ff 184 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 185 #elif (__FREQSEL == 9)
bogdanm 0:9b334a45a8ff 186 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 187 #elif (__FREQSEL == 10)
bogdanm 0:9b334a45a8ff 188 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 189 #elif (__FREQSEL == 11)
bogdanm 0:9b334a45a8ff 190 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 191 #elif (__FREQSEL == 12)
bogdanm 0:9b334a45a8ff 192 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 193 #elif (__FREQSEL == 13)
bogdanm 0:9b334a45a8ff 194 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 195 #elif (__FREQSEL == 14)
bogdanm 0:9b334a45a8ff 196 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 197 #else
bogdanm 0:9b334a45a8ff 198 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 199 #endif
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 /* sys_pllclkin calculation */
bogdanm 0:9b334a45a8ff 202 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 203 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 204 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 205 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 0:9b334a45a8ff 206 #else
bogdanm 0:9b334a45a8ff 207 #define __SYS_PLLCLKIN (0)
bogdanm 0:9b334a45a8ff 208 #endif
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* main clock calculation */
bogdanm 0:9b334a45a8ff 213 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 214 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 215 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 216 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 0:9b334a45a8ff 217 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 218 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 219 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
bogdanm 0:9b334a45a8ff 220 #else
bogdanm 0:9b334a45a8ff 221 #define __MAIN_CLOCK (__WDT_OSC_CLK)
bogdanm 0:9b334a45a8ff 222 #endif
bogdanm 0:9b334a45a8ff 223 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 224 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 0:9b334a45a8ff 225 #else
bogdanm 0:9b334a45a8ff 226 #define __MAIN_CLOCK (0)
bogdanm 0:9b334a45a8ff 227 #endif
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 #else
bogdanm 0:9b334a45a8ff 232 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 233 #endif // CLOCK_SETUP
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 237 Clock Variable definitions
bogdanm 0:9b334a45a8ff 238 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 239 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 243 Clock functions
bogdanm 0:9b334a45a8ff 244 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 245 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 246 {
bogdanm 0:9b334a45a8ff 247 uint32_t wdt_osc = 0;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 250 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 0:9b334a45a8ff 251 case 0: wdt_osc = 0; break;
bogdanm 0:9b334a45a8ff 252 case 1: wdt_osc = 500000; break;
bogdanm 0:9b334a45a8ff 253 case 2: wdt_osc = 800000; break;
bogdanm 0:9b334a45a8ff 254 case 3: wdt_osc = 1100000; break;
bogdanm 0:9b334a45a8ff 255 case 4: wdt_osc = 1400000; break;
bogdanm 0:9b334a45a8ff 256 case 5: wdt_osc = 1600000; break;
bogdanm 0:9b334a45a8ff 257 case 6: wdt_osc = 1800000; break;
bogdanm 0:9b334a45a8ff 258 case 7: wdt_osc = 2000000; break;
bogdanm 0:9b334a45a8ff 259 case 8: wdt_osc = 2200000; break;
bogdanm 0:9b334a45a8ff 260 case 9: wdt_osc = 2400000; break;
bogdanm 0:9b334a45a8ff 261 case 10: wdt_osc = 2600000; break;
bogdanm 0:9b334a45a8ff 262 case 11: wdt_osc = 2700000; break;
bogdanm 0:9b334a45a8ff 263 case 12: wdt_osc = 2900000; break;
bogdanm 0:9b334a45a8ff 264 case 13: wdt_osc = 3100000; break;
bogdanm 0:9b334a45a8ff 265 case 14: wdt_osc = 3200000; break;
bogdanm 0:9b334a45a8ff 266 case 15: wdt_osc = 3400000; break;
bogdanm 0:9b334a45a8ff 267 }
bogdanm 0:9b334a45a8ff 268 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 271 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 272 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 273 break;
bogdanm 0:9b334a45a8ff 274 case 1: /* Input Clock to System PLL */
bogdanm 0:9b334a45a8ff 275 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 276 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 277 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 278 break;
bogdanm 0:9b334a45a8ff 279 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 280 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 281 break;
bogdanm 0:9b334a45a8ff 282 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 283 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 284 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 285 break;
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287 break;
bogdanm 0:9b334a45a8ff 288 case 2: /* WDT Oscillator */
bogdanm 0:9b334a45a8ff 289 SystemCoreClock = wdt_osc;
bogdanm 0:9b334a45a8ff 290 break;
bogdanm 0:9b334a45a8ff 291 case 3: /* System PLL Clock Out */
bogdanm 0:9b334a45a8ff 292 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 293 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 294 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 0:9b334a45a8ff 295 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 296 } else {
bogdanm 0:9b334a45a8ff 297 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 298 }
bogdanm 0:9b334a45a8ff 299 break;
bogdanm 0:9b334a45a8ff 300 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 301 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 0:9b334a45a8ff 302 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 303 } else {
bogdanm 0:9b334a45a8ff 304 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306 break;
bogdanm 0:9b334a45a8ff 307 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 308 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 309 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 310 break;
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312 break;
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 }
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /**
bogdanm 0:9b334a45a8ff 320 * Initialize the system
bogdanm 0:9b334a45a8ff 321 *
bogdanm 0:9b334a45a8ff 322 * @param none
bogdanm 0:9b334a45a8ff 323 * @return none
bogdanm 0:9b334a45a8ff 324 *
bogdanm 0:9b334a45a8ff 325 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 326 * Initialize the System.
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 329 volatile uint32_t i;
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 334 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
bogdanm 0:9b334a45a8ff 335 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 336 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 337 #endif
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 340 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
bogdanm 0:9b334a45a8ff 341 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 342 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 343 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 344 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 0:9b334a45a8ff 345 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 346 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
bogdanm 0:9b334a45a8ff 347 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 348 #endif
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 0:9b334a45a8ff 351 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 352 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
bogdanm 0:9b334a45a8ff 353 for (i = 0; i < 200; i++) __NOP();
bogdanm 0:9b334a45a8ff 354 #endif
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
bogdanm 0:9b334a45a8ff 357 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
bogdanm 0:9b334a45a8ff 358 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 359 LPC_SYSCON->MAINCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 360 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 0:9b334a45a8ff 363 #endif
bogdanm 0:9b334a45a8ff 364 /* System clock to the IOCON needs to be enabled or
bogdanm 0:9b334a45a8ff 365 most of the I/O related peripherals won't work. */
bogdanm 0:9b334a45a8ff 366 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
bogdanm 0:9b334a45a8ff 367 }